AW9961
2015 年 11 月 V1.1.2
集成灵活的一线数字调光和 PWM 调光的串联 WLED 驱动器
特性
概要
2.7V 至 5.5V 的输入电压范围
AW9961 是 一 款 高 效 率 的 电 感 升 压 型 白 光
38V 过压保护（OVP）电压支持最多 10 颗串联 LED
LED 驱动器。AW9961 内部集成了 40V 的功
采用创新的 CDC(Classification Drive Control)输出驱
动技术，显著提升 EMI 性能
率开关，可支持单串最多 10 颗 LED 应用。
AW9961 的 600kHz 固定工作频率减小了输出
电压纹波，提高了转换效率，而且允许使用封
200mV 反馈电压
集成灵活的一线数字调光和 PWM 调光
支持 EMI 性能一线/PWM 模式下可调
PWM 调光频率范围 10k~100kHz，调光最小占空比：1%
AW9961 同时支持两种调光方式，LED 的电流
600kHz 开关频率
可通过 CTRL 引脚的一线数字接口控制，也可
内置过流保护和过温保护功能
通过加在 CTRL 引脚的 PWM 调光信号的占空
内置软启动功能，限制启动时的浪涌电流
比来控制。无论采用哪种调光方式，AW9961
纤小的 TDFN2×2-6L 封装
装更小的外围器件。
AW9961 的反馈电压为 200mV，如典型应用
图所示，LED 的电流通过外置设定电阻确定。
都尽可能降低输出电压及电流的纹波，避免产
生人耳可听见的噪声。
应用
AW9961 内置 EMI 配置寄存器，可在一线或
PWM 模式下进行配置。
移动电话
便携式多媒体播放器
PDA
LED 开路过压保护（OVP）及过温保护，防止
GPS 接收器
芯片进入异常工作状态。
AW9961 内置软启动功能，最大限度地减小电
源的浪涌电流。AW9961 还内置过流保护、
典型应用图
Schottky Diode
L
VIN
22μH
*optional
CIN2
100nF
6
VIN
CIN1
10μF
4
COUT1
SW 1μF/50V
*
COUT2 optional
33pF/50V
D1
D2
D3
D4
AW9961DNR
ON/OFF
DIMMING CONTROL
5
2
CCOMP
220nF
CTRL
FB
COMP
GND
1
D5
D6
RSET
10Ω
D7
3,7
D8
D9
D10
20mA
图1
AW9961 典型应用图
手册中提到的全部商标所有权归各自拥有者所有。
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AW9961
November 2015 V1.1.2
White LED Driver with Flexible Digital and PWM Brightness
Control in Small Package
FEATURES
GENERAL DESCRIPTION
2.7 to 5.5V Input Voltage Range
38V Over-voltage Protection for up to 10 LEDs in
Series
Innovative CDC Output Drive Technology,
Significantly Improve EMI Performance
200mV Reference Voltage
The AW9961 is a white LED driver with integrated
boost converter. With an internal 40V switch FET,
the AW9961 drives up a string of up to 10 LEDs in
series. The boost converter runs at 600kHz fixed
switching frequency to reduce output ripple,
improve conversion efficiency, and allows for the
use of small external components.
Flexible Digital and
Brightness Control
Support EMI performance programmable
under 1-wire/PWM mode
PWM Dimming Frequency Range: 10kHz ~
100kHz, Minimum Duty Cycle:1%
600kHz Switching Frequency
Over-current and Over-temperature Protection
Built-in Soft-start Limits Inrush Current
Ultra Small 2mm*2mm TDFN-6L package
PWM
White
LED
The default white LED current is set with the
external sense resistor RSET, and the feedback
voltage is regulated to 200mV, as shown in the
typical application. During the operation, the LED
current can be controlled by using the 1-wire
digital interface through the CTRL pin. Alternately,
a pulse width modulation (PWM) signal can be
applied to the CTRL pin through which the duty
cycle determines the feedback reference voltage.
In either digital or PWM mode, the AW9961 does
not generate audible noises on the output
capacitor. For maximum protection, the device
features integrated open LED over-voltage
protection that disables the AW9961 to prevent the
output from exceeding the absolute maximum
ratings during open LED conditions.
APPLICATIONS
Mobile Phones
Portable Media Players
GPS Receivers
AW9961 sets a built-in EMI performance register,
which can be configured under either 1-wire or
PWM mode.
TYPICAL APPLICATION CIRCUIT
Schottky Diode
L
VIN
*
CIN2 optional
100nF
22μH
6
VIN
CIN1
10μF
4
COUT1
SW 1μF/50V
*
COUT2 optional
33pF/50V
D1
D2
D3
D4
AW9961DNR
5
ON/OFF
DIMMING CONTROL
2
CCOMP
220nF
CTRL
FB
COMP
GND
1
D5
D6
RSET
10Ω
D7
3,7
D8
D9
D10
20mA
Figure 1
Typical Application Circuit of AW9961
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1
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
PIN CONFIGURATION AND TOP MARK
AW9961DNR TOP VIEW
（TDFN2x2-6L）
FB 1
AW9961DNR MARKING
（TDFN2x2-6L）
6 VIN
7
GND
COMP 2
5 CTRL
GND 3
AL61
XY
4 SW
AL61——AW9961DNR
XY——Manufacture Data Code
Figure 2
Pin Configuration and Top Mark
PIN DEFINITION
No.
NAME
DESCRIPTION
1
FB
Feedback pin for current. Connect the sense resistor from FB to GND.
2
COMP
Output of the transconductance error amplifier. Connect an external
capacitor to this pin to compensate the regulator.
3
GND
4
SW
This is the switching node of the IC. Connect the inductor between the
VIN and SW pin. This pin is also used to sense the output voltage for
open LED protection.
5
CTRL
Control pin of the boost regulator. It is a multi-functional pin which can
be used for enable control, PWM and digital dimming.
6
VIN
The input supply pin for the IC. Connect VIN to a supply voltage
between 2.7 and 5.5V.
7
GND
Exposed pad should be soldered to PCB board and Connected to
GND.
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Ground.
2
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
FUNCTIONAL BLOCK DIAGRAM
1
2
FB
6
COMP
4
VIN
SW
UVLO
Input Logic
and DAC
5
Reference
Control
Error
Amp
+
Thermal
Shutdown
OVP
PWM Control
and
Gate Drive
Soft-Start
CTRL
Oscillator
Ramp
Generator
Current
Amp
+
GND
7
Figure 3
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GND
3
FUNCTIONAL BLOCK DIAGRAM
3
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
TYPICAL APPLICATION CIRCUITS
Schottky Diode
L
VIN
22μH
*optional
CIN2
100nF
6
VIN
CIN1
10μF
4
COUT1
SW 1μF/50V
*
COUT2 optional
33pF/50V
D1
D2
D3
D4
AW9961DNR
5
ON/OFF
DIMMING CONTROL
2
CCOMP
220nF
CTRL
1
FB
D5
D6
RSET
10Ω
COMP
GND
D7
3,7
D8
D9
D10
20mA
Figure 4
Typical Application of AW9961
Schottky Diode
L
VIN
22μH
*optional
CIN2
100nF
6
VIN
CIN1
10μF
4
COUT1
SW 1μF/50V
*
COUT2 optional
33pF/50V
D1
D2
AW9961DNR
ON/OFF
DIMMING CONTROL
5
2
CCOMP
220nF
D10
CTRL
COMP
FB
20mA
1
GND
10kΩ
3,7
80kΩ
RSET
10Ω
PWM Signal
100kΩ
0.1μF
PWM Signal:1.8 V, 200 Hz
LED Current = 1.8Vx(1-d)/(8 x RSET)
Figure 5
Additional Typical Application for 10 LEDs with External PWM Dimming Network
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
L
VIN
Schottky Diode
3p6s
22μH
*optional
CIN2
100nF
COUT1
4
SW 1μF/50V
6
VIN
CIN1
10μF
COUT2*optional
33pF/50V
AW9961DNR
ON/OFF
DIMMING CONTROL
5
CTRL
2
FB
COMP
CCOMP
220nF
Figure 6
GND
1
RSET
3.3Ω
60mA
3,7
Drive 18 White LEDs for Big Screen Display
Notice for Typical Application Circuits:
1：Recommended device for AW9961:
L:TDK VLCF5020T-220MR75-1
CIN1: Murata GRM188R61C106MA73
CIN2: Murata GRM155R61C104K
COUT1: Murata GRM21BR71H105KA
COUT2: Murata GRM1555C1H330GA
Schottky Diode: ONsemi MBR0540T1
2：CIN2 and COUT2 are recommended to use in parallel with the input capacitor and output capacitor to
suppress high frequency noise.
3：Red lines are high current paths, reference to the section APPLICATION INFORMATION.
4：The capacitors (CIN1, CIN2, COUT1, COUT2 and CCOMP) should be placed as close to the pins of the IC as
possible.
5：Minimize trace lengths between the IC and the inductor, the Schottky diode and the output capacitor, keep
these traces short, direct, and wide.
6：Minimize the length and area of all traces connected to the SW pin and always use a ground plane under
the switching regulator to minimize inter-plane coupling.
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
ORDERING INFORMATION
Part Number
Temperature
Package
Marking
Delivery Form
AW9961DNR
-40℃～85℃
TDFN2x2-6L
AL61
3000 units/
Tape and Reel
AW9961
Shipping
R: Tape & Reel
Package Type
DN:TDFN2x2-6L
ABSOLUTE MAXIMUM RATINGS(NOTE1)
PARAMETERS
Supply voltage range VIN
RANGE
(NOTE 2)
Voltage on FB,CTRL and COMP
Voltage on SW
-0.3V to 6V
(NOTE 2)
-0.3V to 6V
(NOTE 2)
-0.3V to 40V
Junction-to-ambient thermal resistance θJA
65℃/W
Operating free-air temperature range
-40℃ to 85℃
Maximum Junction temperature TJMAX
160℃
Storage temperature TSTG
-65℃ to 150℃
Lead Temperature (Soldering 10 Seconds)
ESD
ALL PINS HBM (human body model)
(NOTE 4)
ALL PINS CDM (charge device model)
ALL PINS MM (machine model)
260℃
(NOTE 3)
±6000V
(NOTE 5)
(NOTE 6)
±2500V
±300V
(NOTE 7)
Latch-up
Latch-up current maximum rating per JEDEC standard
+IT：250mA
-IT：-250mA
NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent damages
to the device. In spite of the limits above, functional operation conditions of the device should within the
ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated conditions for
prolonged periods may affect device reliability.
NOTE2: All voltage values are with respect to network ground terminal.
NOTE3: This integrated circuit can be damaged by ESD if you don’t pay attention to ESD protection. AWINIC
recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper
handling and installation procedures can cause damage. ESD damage can range from subtle performance
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications.
NOTE4: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test
method: MIL-STD-883H Method 3015.8.
NOTE5: Test Condition: JEDEC EIA/JESD22-C101E.
NOTE6: Test Condition: JEDEC EIA/JESD22-A115.
NOTE7: Test Condition: JEDEC STANDARD NO.78D NOVEMBER 2011.
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AW9961
November 2015 V1.1.2
ELECTRICAL CHARACTERISTICS
Test Condition: TA = 25℃, VIN = 3.6V, VCTRL = VIN (Unless otherwise specified).
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
5.5
V
SUPPLY VOLTAGE AND CURRENT
VIN
Input voltage range
2.7
IQ
Operating quiescent current
VFB = 1V
0.9
1.4
mA
ISD
Shutdown current
VCTRL = GND,
VIN=4.2V
0.1
1
A
Under-voltage lockout threshold
VIN falling
2.45
2.75
V
UVLO
Vhys
Under-voltage lockout
hysteresis
250
mV
ENABLE AND REFERENCE CONTROL
V(CTRLh)
CTRL logic high voltage
VIN = 2.7V to 5.5V
V(CTRLl)
CTRL logic low voltage
VIN = 2.7V to 5.5V
R(CTRL)
CTRL pull down resistor
toff
1.5
V
0.3
V
kΩ
600
CTRL pulse width to shutdown
CTRL high to low
2.5
ms
t1w_det
Digital 1-wire brightness
(NOTE 1)
detection time
CTRL pin low
260
s
t1w_delay
Digital 1-wire brightness
detection delay
100
s
t1w_win
Digital 1-wire brightness
detection window time
1
ms
Measured from CTRL
pin
VOLTAGE AND CURRENT CONTROL
VREF
Voltage feedback regulation
voltage
V(REF_PWM)
Voltage feedback regulation
voltage under brightness
control
195
200
205
mV
fPWM = 10 kHz, duty
cycle = 25%
46
50
54
mV
fPWM = 10 kHz, duty
cycle = 10%
16
20
24
mV
0.1
1
A
700
kHz
0.65
Ω
IFB
Voltage feedback input bias
current
fS
Oscillator frequency
500
600
Dmax
Maximum duty cycle
90%
95%
POWER SWITCH
N-channel MOSFET
on-resistance
VIN = 3.6V
RDS(on)
VIN = 3.0V
0.7
Ω
ILN_NFET
N-channel leakage current
VSW = 35V, TA = 25℃
1
A
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8
0.36
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AW9961
November 2015 V1.1.2
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
0.6
1.1
1.7
A
36
38
40
V
OCP AND OVP
ILIM
N-channel MOSFET current
limit
VOVP
Open LED overvoltage
protection threshold
tREF
VREF filter time constant
Measured on the SW
pin
s
480
DIGITAL 1-WIRE COMMAND TIMING
s
tstart
Start time of program stream
2
tEOS
End time of program stream
2
360
s
tH_LB
High time low bit
Logic 0
2
180
s
tL_LB
Low time low bit
Logic 0
2×tH_LB
360
s
tH_HB
High time high bit
Logic 1
2×tL_HB
360
s
tL_HB
Low time high bit
Logic 1
2
180
s
VACKNL
Acknowledge output voltage
low
Open drain, Rpullup =
15kΩ to VIN
tvalACKN
Acknowledge valid time
See
tACKN
Duration of acknowledge
condition
See
0.1
V
(NOTE 2)
2
s
(NOTE 2)
512
s
100
kHz
PWM DIMMING TIMING
fPWM
Frequency of PWM dimming
tH_PWM
High time of PWM dimming
signal
10
fPWM=10kHz
1
μs
fPWM=100kHz
100
ns
THERMAL SHUTDOWN
TOTP
Thermal shutdown threshold
165
℃
Thys
Thermal shutdown threshold
hysteresis
16
℃
NOTE1: To select 1-wire digital interface mode, the CTRL pin has to be low for more than t1w_det during t1w_win.
NOTE2: Acknowledge condition active 0, this condition will only be applied in case the RFA bit is set. Open
drain output, line needs to be pulled high by the host with resistor load.
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AW9961
November 2015 V1.1.2
TYPICAL CHARACTERISTICS
Table 1 TABLE OF FIGURES
INDEX
FIGURE No.
Efficiency 1
VIN=3.6V; 4,6,8,10 LEDs;
L=22
FIGURE 7
Efficiency 2
VIN=4.2/3.6/3.0V; 10 LEDs,
L=22
FIGURE 8
Efficiency 3
VIN=2.5~5.5V; 1P10S,
2P8S,3P8S LEDs, L=22
FIGURE 9
VIN=2.5~5.5V, 10 LEDs,
L=22
FIGURE 10
Switching frequency
1-wire dimming step
FIGURE 11
PWM dimming linearity
PWM Freq = 20 kHz
FIGURE 12
Feedback voltage line regulation
VIN=2.5~5.5V
FIGURE 13
Soft-start waveform
VIN=3.8V, 10 LEDs, L=22
FIGURE 14
Switching waveform
VIN=3.8V, 10 LEDs, L=10
FIGURE 15
Open LED protection
VIN=3.6V, 10 LEDs, L=22
FIGURE 16
EFFICIENCY
Vs.
OUTPUT CURRENT
EFFICIENCY
Vs.
OUTPUT CURRENT
100
100
Efficiency (%)
80
8 LEDs
6 LEDs
VIN=4.2V
90
Efficiency (%)
4 LEDs
90
10 LEDs
70
60
50
VIN=3.6V
80
VIN=3.0V
70
60
50
VIN=3.6V
40
0
10
20
10 LEDs
30
40
Output Current (mA)
Figure 7.
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40
0
10
20
30
40
Output Current (mA)
Figure 8.
10
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AW9961
November 2015 V1.1.2
EFFICIENCY
Vs.
INPUT VOLTAGE
FREQUENCY
Vs.
INPUT VOLTAGE
100
750
700
Frequency (kHz)
Efficiency (%)
3P8S
2P8S
90
1P10S
80
70
60
2.5
3.0
3.5
4.0
4.5
5.0
500
5.5
3.5
4.0
4.5
5.0
FEEDBACK VOLTAGE
Vs.
1-WIRE DIMMING STEP
FEEDBACK VOLTAGE
Vs.
PWM DUTY CYCLE
200
160
160
120
80
40
0
3.0
Input Voltage (V)
Figure 10.
200
0
2.5
Input Voltage (V)
Figure 9.
Feedback Voltage (mV)
Feedback Voltage (mV)
600
550
50
40
650
4
8
12
16
20
24
28
1-wire Dimming Step (Step)
Figure 11.
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11
32
5.5
120
80
40
0
0
20
40
60
80
100
PWM Duty Cycle (%)
Figure 12.
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
FEEDBACK VOLTAGE
Vs.
INPUT VOLTAGE
SOFT-START
WAVEFORM
Feedback Voltage (mV)
210
CTRL
DC Coupled
2.0V/div
205
200
VOUT
DC Coupled
10.0V/div
195
190
185
IL
DC Coupled
200mA/div
2.5
3.1
3.7
4.3
4.9
5.5
Input Voltage (V)
Time (5ms/div)
Figure
Figure
13.
SWITCHING
WAVEFORM
14.
OPEN LED
PROTECTION
VOUT
DC Coupled
10.0V/div
VOUT
AC Coupled
100mV/div
VOUT
DC Coupled
10.0V/div
IL
DC Coupled
200mA/div
IL
DC Coupled
200mA/div
Time (2μs/div)
Figure
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Time (2μs/div)
15.
Figure
12
16.
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
DETAILED FUNCTIONAL DESCRIPTION
The AW9961 is a high efficiency, high output voltage boost converter in small package size. The device is
ideal for driving up to 10 white LED in series. The serial LED connection provides even illumination by
sourcing the same output current through all LEDs, eliminating the need for expensive factory calibration. The
device integrates 40V/1.0A switch FET and operates in pulse width modulation (PWM) with 600kHz fixed
switching frequency. For operation see the block diagram. The duty cycle of the converter is set by the error
amplifier output and the current signal applied to the PWM control comparator. The control architecture is
based on traditional current-mode control. Therefore, slope compensation is added to the current signal to
allow stable operation for duty cycle larger than 50%. The feedback loop regulates the FB pin to a low
reference voltage (200mV typical), reducing the power dissipation in the current sense resistor.
SOFT START-UP
Soft-start circuitry is integrated into the IC to avoid a high inrush current during start-up. After the device is
enabled, the voltage at FB pin ramps up to the reference voltage. This ensures that the output voltage rises
slowly to reduce the input current. See the start-up waveform of a typical example.
OPEN LED OVER-VOLTAGE PROTECTION
Open LED over-voltage protection circuitry prevents IC damage as the result of white LED disconnection. The
AW9961 monitors the voltage at the SW pin during each switching cycle. The circuitry turns off the switch FET
as soon as the SW voltage exceeds the VOVP threshold for 8 clock cycles. The switch will switch after about
50ms. When the above condition is met, the protection circuitry will work again.
SHUTDOWN
The CTRL input is used to enable or disable the AW9961. Pulling the CTRL pin higher than 1.5V will enable
the device. The AW9961 has an internal shutdown delay circuitry, when the CTRL pin is held low for an
amount of time longer than 3.0ms, the AW9961 will enter shutdown mode and the input supply current for the
device is less than 1μA. Although the internal FET does not switch in shutdown, there is still a DC current path
between the input and the LEDs through the inductor and Schottky diode. The minimum forward voltage of
the LED array must exceed the maximum input voltage to ensure that the LEDs remain off in shutdown.
However, in the typical application with two or more LEDs, the forward voltage is large enough to reverse bias
the Schottky and keep leakage current low.
UNDER-VOLTAGE LOCKOUT
An under-voltage lockout prevents operation of the device at input voltage below typical 2.45V. When the
input voltage is below the under-voltage threshold, the device is shutdown and the internal switch FET is
turned off. If the input voltage rises by under-voltage lockout hysteresis, the IC restarts.
CURRENT PROGRAM
The FB voltage is regulated by a low 200mV reference voltage. The LED current is programmed externally
using a current sense resistor in series with the LED string. The value of the RSET can be calculated by the
following equation:
ILED =
VFB
RSET
(1)
Where:
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AW9961
November 2015 V1.1.2
ILED = output current of LEDs
VFB = regulated voltage of FB
RSET = current sense resistor
LED BRIGHTNESS DIMMING MODE SELECTION
The CTRL pin is used for the control input for both dimming modes, PWM dimming and the 1-wire dimming.
The dimming mode for the AW9961 is selected each time the device is enabled. The default dimming mode is
PWM dimming. To enter 1-wire mode, the following digital pattern on the CTRL pin must be recognized by the
IC every time that the IC starts from the shutdown mode.
1.
Pull the CTRL pin high to enable the AW9961, and to start the 1-wire detection window.
2.
After the digital 1-wire brightness detection delay (t1w_dealy, 100μs) expires, drive the CTRL pin low for
more than the digital 1-wire brightness detection time (t1w_det, 260μs).
3.
The CTRL pin has to be low for more than digital 1-wire brightness detection time before the digital 1-wire
brightness detection window (t1w_win, 1ms) expires. Digital 1-wire brightness detection window starts from
the first CTRL pin low to high transition.
The IC immediately enters 1-wire mode once the above three conditions are met. The 1-wire mode
communication can start before the detection window expires. Once the dimming mode is programmed, it
cannot be changed without another start up. This means the IC needs to be shut down by pulling the CTRL
pin low for 2.5ms and restarts. See the Dimming Mode Detection and Soft-start (See FIGURE 17) for a
graphical explanation.
PWM signal
high
CTRL
low
PWM
mode
Startup
delay
Shutdown
delay
200mV x duty cycle
FB ramp
FB
Enter 1-wire mode
timing window
t
Programming code
Programming code
Enter 1-wire mode
high
t1w_det
CTRL
low
1-wire
mode
t1w_delay
FB
Figure 17
FB ramp
Programmed value1
(if not programmed
200mV default)
Shutdown
delay
Programmed
value2
Startup delay
FB ramp
IC
shutdown
Startup delay
Dimming Mode Detection and Soft Start PWM Brightness Dimming
PWM BRIGHTNESS DIMMING
When the CTRL pin is constantly high, the FB voltage is regulated to 200mV typically. However, the CTRL pin
allows a PWM signal to reduce this regulation voltage, it achieves LED brightness dimming. The relationship
between the duty cycle and the FB voltage is given by the following equation:
VFB = Duty x 200mV
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14
(2)
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
Where:
Duty = duty cycle of the PWM signal
200mV = internal reference voltage
As shown in the FIGURE 18, the IC chops up the internal 200mV reference voltage at the duty cycle of the
PWM signal. The pulse signal is then filtered by an internal low pass filter. The output of the filter is connected
to the error amplifier as the reference voltage for the FB pin regulation. Therefore, although a PWM signal is
used for brightness dimming, only the WLED DC current is modulated, which is often referred as analog
dimming. This eliminates the audible noise which often occurs when the LED current is pulsed in replica of the
frequency and duty cycle of PWM control. Unlike other scheme which filters the PWM signal for analog
dimming, AW9661 regulation voltage is independent of the PWM logic voltage level which often has large
variations.
For optimum performance, use the PWM dimming frequency in the range of 10kHz to 100kHz. The
requirement of minimum dimming frequency comes from the digital 1-wire brightness detection delay and
detection time specification in the dimming mode selection. Since the CTRL pin is logic only pin, adding
external RC filter applied to the pin does not work.
To use lower PWM dimming, add an external RC network connected to the FB pin as shown in the additional
typical application, FIGURE 5.
Reference
200mV
CTRL
+
Error
Amp
EA out
FB
Figure 18
Block Diagram of Programmable FB Voltage Using PWM Signal
DIGITAL 1-WIRE BRIGHTNESS DIMMING
The CTRL pin features a simple digital interface to allow digital brightness control. The digital dimming can
save the processor power and battery life as it does not require a PWM signal all the time, and the processor
can enter idle mode if available.
The AW9961 adopts the 1-wire digital interface for the digital dimming, which can program the FB voltage to
any of the 32 steps with single command. The step increment increases with the voltage to produce pseudo
logarithmic curve for the brightness step. See TABLE 2 for the FB pin voltage steps. The default step is full
scale when the device is first enabled (VFB = 200mV). The programmed reference voltage is stored in an
internal register. The shutdown mode clears the register value and reset it to default.
1-wire digital interface is a simple but flexible single pin interface to configure the FB voltage. The interface is
based on a master-slave structure, where the master is typically a microcontroller or application processor.
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15
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
TABLE 3 and FIGURE 19 give an overview of the protocol. The protocol consists of a device specific address
byte and a data byte. The device specific address byte is fixed to 72H. The data byte consists of five bits for
information, two address bits, and the RFA bit. The RFA bit set to high indicates the ―Request for
Acknowledge‖ condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of 1-wire digital interface compared with other single pin interface is that its bit detection is in a
large extent independent from the bit transmission rate.
Table 2 Selectable FB Voltage
FB voltage
(mV)
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
1
5
0
0
0
0
1
2
8
0
0
0
1
0
3
11
0
0
0
1
1
4
14
0
0
1
0
0
5
17
0
0
1
0
1
6
20
0
0
1
1
0
7
23
0
0
1
1
1
8
26
0
1
0
0
0
9
29
0
1
0
0
1
10
32
0
1
0
1
0
11
35
0
1
0
1
1
12
38
0
1
1
0
0
13
44
0
1
1
0
1
14
50
0
1
1
1
0
15
56
0
1
1
1
1
16
62
1
0
0
0
0
17
68
1
0
0
0
1
18
74
1
0
0
1
0
19
80
1
0
0
1
1
20
86
1
0
1
0
0
21
92
1
0
1
0
1
22
98
1
0
1
1
0
23
104
1
0
1
1
1
24
116
1
1
0
0
0
25
128
1
1
0
0
1
26
140
1
1
0
1
0
27
152
1
1
0
1
1
28
164
1
1
1
0
0
29
176
1
1
1
0
1
30
188
1
1
1
1
0
31
200
1
1
1
1
1
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16
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
Table 3 1-wire Digital Interface Bit Description
Byte
Device Address
Byte(72 hex)
Bit
Number
Name
Transmission
Direction
7
DA7
0 MSB device address
6
DA6
1
5
DA5
1
4
DA4
Description
1
IN
Data Byte
3
DA3
0
2
DA2
0
1
DA1
1
0
DA0
0 LSB device address
7 (MSB)
RFA
Request for acknowledge. If high,
acknowledge is applied by device
6
A1
0 Address bit 1
5
A0
0 Address bit 0
4
D4
3
D3
Data bit 3
2
D2
Data bit 2
1
D1
Data bit 1
0 (LSB)
D0
Data bit 0
Data bit 4
IN
ACK
Acknowledge condition active 0, this condition
will only be applied in case RFA bit is set.
Open drain output, line needs to be pulled high
by the host with a pull-up resistor. This feature
can only be used if the master has an open
drain output stage. In case of a push-pull
output stage acknowledge condition may not
be requested.
OUT
DATAIN
Device Adress Byte
Start
DA7
0
DA6
1
DA5
1
DA4
1
DA3
0
Data Byte
DA2
0
DA1
1
DA0
0
EOS
Start
RFA
A1
A0
D4
D3
D2
D1
D0
EOS
DATAOUT
Figure 19
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ACK
Digital 1-wire Interface Protocol Overview
17
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
Digital 1-wire Brightness Timing, without Acknowledge RFA = 0
tStart
DATA IN
Address Byte
tStart
Data Byte
Static High
Static High
DA7
0
DA0
0
tEOS
RFA
0
D0
1
tEOS
Digital 1-wire Brightness Timing, with Acknowledge RFA = 1
tStart
DATA IN
Address Byte
tStart
Data Byte
Static High
DA7
0
DA0
0
tEOS
RFA
1
D0
1
tvalACK
ACKN
Acknowledge True
Data line pulled down by device
tACKN
Controller needs to pull up data line
via a resistor to detect ACKN
DATA OUT
Acknowledge False
No pull down
tLow
tHigh
Low Bit
Logic 0
Figure 20
tLow
tHigh
High Bit
Logic 1
Digital 1-wire Interface Bit Coding
All bits are transmitted MSB first and LSB last. FIGURE 20 shows the protocol without acknowledge request
(Bit RFA = 0), and the protocol with acknowledge (Bit RFA = 1) request. Prior to both bytes, device address
byte and data byte, a start condition must be applied. For this, the CTRL pin must be pulled high for at least
tstart (2μs) before the bit transmission starts with the falling edge. If the CTRL pin is already at high level, no
start condition is needed prior to the device address byte. The transmission of each byte is closed with an End
of Stream condition for at least tEOS (2μs).
The bit detection is based on a logic detection scheme, where the criterion is the relation between t Low and tHigh.
It can be simplified to:
High Bit: tHigh > tLow, but with tHigh at least 2 x tLow, see FIGURE 20.
Low Bit: tLow > tHigh, but with tLow at least 2 x tHigh, see FIGURE 20.
The bit detection starts with a falling edge on the CTRL pin and ends with the next falling edge. Depending on
the relation between tHigh and tLow, the logic 0 or 1 is detected.
The acknowledge condition is only applied if:
Acknowledge is requested by a set RFA bit.
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18
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
The transmitted device address matches with the device address of the device.
16 bits is received correctly.
If the device turns on the internal ACKN-MOSFET and pulls the CTRL pin low for the time tACKN, which is
512μs maximum then the Acknowledge condition is valid after an internal delay time t valACK. This means that
the internal ACKN-MOSFET is turned on after tvalACK, when the last falling edge of the protocol was detected.
The master controller keeps the line low in this period. The master device can detect the acknowledge
condition with its input by releasing the CTRL pin after t valACK and read back a logic 0. The CTRL pin can be
used again after the acknowledge condition ends.
Note that the acknowledge condition may only be requested in case the master device has an open drain
output. For a push-pull output stage, the use a series resistor in the CTRL line to limit the current to 500μA is
recommended to for such cases as:
an accidentally requested acknowledge, or
to protect the internal ACKN-MOSFET.
EMI CONTROL BITS
To adjust the EMI(electromagnetic interference) issue arisen by the periodic change of inductor current,
AW9961 sets an EMI control register EMI_CTL, of which default value is 00. By configuring the EMI bits,
the EMI performance can be adjusted. EMI control register is detailed in the table below.
Table 4 EMI Control Register Description
Register
A1
A0
D4
D3
D2
D1
D0
Default
PROTECT
1
1
0
1
0
1
0
0
EMI_CTL
1
0
-
-
-
EMI_CTL
EMI_CTL
00
Note that the EMI_CTL register cannot be written unless the PROTECT register has been written firstly. And
the PROTECT bits sequence which needs to be followed is fixed to ―1101010‖, from A1 to D0. The PROTECT
register would be cleared automatically when the next write operation happens.
Among all of the EMI bits configuration, ―00‖ has been set for default condition. The other three conditions
would be described in terms of EMI performance/ efficiency compared to default status as follows: 01(EMI
worst, efficiency best), 10(EMI best, efficiency worst), 11(EMI better, efficiency worse).
AW9961 supports the EMI adjustment under either 1-wire or PWM brightness dimming mode, and the register
should be configured by means of 1-wire interface protocol in both modes. While there are still some
differences between the two configure methods, below are more details:
1-wire Mode
Under 1-wire mode, EMI_CTL register can be configured in the same way as dimming register. FIGURE 21
shows a timing diagram for EMI adjustment under 1-wire mode.
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19
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
No ACK if
RFA=0
tStart
tStart
high
t1w_det
CTRL
0 1
1
0
1
0 1
0
1
RFA
0 1
1
0
0 1
low
t1w_delay
tvalACK
or
tEOS
tACKN
tEOS
Enter 1-wire mode
timing window
Device Address Byte
Data Byte
72H
Write PROTECT Register
No ACK if
RFA=0
tStart
0 1
1
1
0
0 1
0
RFA
1
0 0
0
0
Data Byte
72H
Write EMI_CTL Register
Figure 21
ACKN
1-wire Brightness
Dimming Command
tvalACK
or
tEOS
Device Address Byte
ACK if
RFA=1
tStart
EMI EMI
_CTL _CTL
tEOS
tStart
tACKN
ACK if
RFA=1
ACKN
EMI_CTL Register Configuration Timing under 1-wire Mode
PWM Mode
In PWM mode, EMI_CTL register configuration would be implemented with the 1-wire interface protocol, while
there are some different timing requirements from those under 1-wire mode at the CTRL pin: Firstly, Host
should pull the CTRL pin high for 2~3ms when enabling the chip, to avoid making confusion with the mode
detection window. On the other hand, no ACK would be applied at the CTRL pin unless the following
sequence is satisfied:
a) PROTECT register be configured correctly only one time (non-repetitive)
b) EMI_CTL bits be configured correctly
c) the RFA bit of EMI_CTL Data Byte has been set to request an acknowledge. See FIGURE 22.
tStart
tStart
tStart
high
CTRL
0 1
1
1
0
0
0 1
RFA
1
1
0 1
0 1
0
low
tEOS
tEOS
last high for 2~3ms, longer
than the Enter 1-wire mode
timing window
Device Address Byte
Data Byte
72H
Write PROTECT Register
No ACK if
RFA=0
tStart
0 1
1
1
0
0 1
0
RFA
1
0
0 0
0
Brightness Dimming Data
tvalACK
or
tEOS
ACK if
RFA=1
tACKN
Data Byte
Device Address Byte
72H
Figure 22
tStart
EMI EMI
_CTL _CTL
tEOS
No ACK
here
Write EMI_CTL Register
ACKN
EMI_CTL Register Configuration Timing under PWM Mode
THERMAL SHUTDOWN
An internal thermal shutdown turns off the device when the typical junction temperature of is exceeded 165℃.
The device is released from shutdown automatically when the junction temperature decreases by 16℃.
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20
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
APPLICATION INFORMATION
MAXIMUM OUTPUT CURRENT
The over-current limit in a boost converter limits the maximum input current and thus maximum input power
for a given input voltage. Maximum output power is less than maximum input power due to power conversion
losses. Therefore, the current limit setting, input voltage, output voltage and efficiency can all change
maximum current output. The current limit clamps the peak inductor current. Therefore, the ripple has to be
subtracted to derive maximum DC current. The ripple current is a function of switching frequency, inductor
value and duty cycle. The following equations take into account of all the above factors for maximum output
current calculation.
IP =
[L ×Fs ×(
VOUT
(3)
1
1
1
+
)]
+ VF - VIN VIN
Where:
IP = inductor peak to peak ripple
L= inductor value
VF = Schottky diode forward voltage
FS = switching frequency
VOUT = output voltage of the boost converter. It is equal to the sum of VFB and the voltage drop across
LEDs.
Iout _ max =
VIN ×(Ilim - IP / 2) ×η
VOUT
(4)
Where:
Iout_max = maximum output current of the boost converter
Ilim = over-current limit, for worst case calculation the minimum value has to be chosen.
η = efficiency
INDUCTOR SELECTION
The selection of the inductor affects steady state operation as well as transient behavior and loop stability.
These factors make it the most important component in power regulator design. There are three important
inductor specifications, inductor value, DC resistance and saturation current. Considering inductor value
alone is not enough.
The inductor value determines the inductor ripple current. Choose an inductor that can handle the necessary
peak current without saturating, according to half of the peak-to-peak ripple current given by equation 3,
pause the inductor DC current given by:
IIN _ DC =
VOUT ×Iout
VIN ×η
(5)
Inductor values can have ±20% tolerance with no current bias. When the inductor current approaches
saturation level, its inductance can decrease 20% to 35% from the 0A value depending on how the inductor
vendor defines saturation current. Using an inductor with a smaller inductance value forces discontinuous
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21
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
PWM when the inductor current ramps down to zero before the end of each switching cycle. This reduces the
boost converter’s maximum output current, causes large input voltage ripple and reduces efficiency. Large
inductance value provides much more output current and higher conversion efficiency. For these reasons, a
10μH to 22μH inductor value range is recommended. A 22μH inductor optimized the efficiency for most
application while maintaining low inductor peak to peak ripple. TABLE 5 lists the recommended inductor for
the AW9961. When recommending inductor value, the factory has considered –40% and +20% tolerance
from its nominal value.
AW9961 has built-in slope compensation to avoid sub-harmonic oscillation associated with current mode
control. If the inductor value is lower than 10μH, the slope compensation may not be adequate, and the loop
can be unstable. Therefore, customers need to verify the inductor in their application if it is different from the
recommended values.
Table 5 Recommended Inductors for AW9961
Part
Number
L
(μH)
DCR Max
(Ω )
Saturation Current
(mA)
Size
(L x W x H mm)
Vendor
VLCF5020T-220MR75-1
22
0.4
750
5 x 5 x 2.0
TDK
LQH3NPN100NM0
10
0.3
750
3 x 3 x 1.5
Murata
A997AS-220M
22
0.4
510
4 x 4 x 1.8
TOKO
CDH3809/SLD
10
0.3
570
4 x 4 x 1.0
Sumida
SCHOTTKY DIODE SELECTION
The high switching frequency of the AW9961 demands a high-speed rectification for optimum efficiency.
Ensure that the diode average and peak current rating exceeds the average output current and peak inductor
current. In addition, the diode’s reverse breakdown voltage must exceed the open LED over-voltage
protection voltage. The ONSemi MBR0540 and the ZETEX ZHCS400 are recommended for AW9961.
COMPENSATION CAPACITOR SELECTION
For most applications, ceramic capacitors with X7R or X5R temperature characteristic are preferred for use
with the AW9961. These capacitors have tight capacitance tolerance (as good as ±10%) and hold their value
over temperature (X7R: ±15% over -55°C to 125°C; X5R: ±15% over -55°C to 85°C).
Capacitors with Y5V or Z5U temperature characteristic are generally not recommended for use with the
AW9961. Capacitors with these temperature characteristics typically have wide capacitance tolerance (+80%,
-20%) and vary significantly over temperature (Y5V: +22%, -82% over -30°C to +85°C range; Z5U: +22%, -56%
over +10°C to +85°C range). Under some conditions, a nominal 1μF Y5V or Z5U capacitor could have a
capacitance of only 0.1μF. Such detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to
meet the minimum capacitance requirements of the AW9961.
The compensation capacitor CCOMP (see the application circuit), connected from COMP pin to GND, is used to
stabilize the feedback loop of the AW9961. Use 220nF X5R or X7R ceramic capacitor for CCOMP.
INPUT AND OUTPUT CAPCCITORS SELECTION
The output capacitor is mainly selected to meet the requirements for the output ripple and loop stability. This
ripple voltage is related to the capacitor’s capacitance and its equivalent series resistance (ESR). Assuming a
capacitor with zero ESR, the minimum capacitance needed for a given ripple can be calculated by：
C OUT =
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22
( VOUT - VIN) ×Iout
VOUT ×FS ×Vripple
(6)
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
Where, Vripple = peak-to-peak output ripple. The additional output ripple component caused by ESR is
calculated using:
Vripple _ ESR Iout RESR
(7)
Due to its low ESR, Vripple_ESR can be neglected for ceramic capacitors, but must be considered if tantalum or
electrolytic capacitors are used.
Care must be taken when evaluating a ceramic capacitor’s derating under dc bias, aging and AC signal. For
example, larger form factor capacitors (in 1206 size) have a resonant frequency in the range of the switching
frequency. So the effective capacitance is significantly lower. The DC bias can also significantly reduce
capacitance. Ceramic capacitors can loss as much as 50% of its capacitance at its rated voltage. Therefore,
leave the margin on the voltage rating to ensure adequate capacitance at the required output voltage.
An X5R or X7R capacitor of 10μF is recommended for input side. The output requires a X5R or X7R capacitor
in the range of 0.47μF to 4.7μF. A 100nF capacitor and a 33 pF capacitor are recommended to use in parallel
with the input capacitor and the output capacitor to suppress high frequency noise.
The output capacitor affects the loop stability of the boost regulator. If the output capacitor is below the range,
the boost regulator can potentially become unstable. For example, if use the output capacitor of 0.1μF, a
470nF compensation capacitor has to be used for the loop stable.
Note that capacitor degradation increases the ripple much. Select the capacitor with 50V rated voltage to
reduce the degradation at the output voltage. If the output ripple is too large, change a capacitor with less
degradation effect or with higher rated voltage could be helpful.
POWER DISSIPATION
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. This
restriction limits the power dissipation of the AW9961. Calculate the maximum allowable dissipation, P D(max),
and keep the actual dissipation less than or equal to P D(max). The maximum-power-dissipation limit is
determined by using the following equation:
PD(max) =
TJ max - TA
θ ja
Where, TJmax is the Maximum Junction Temperature, TA is the maximum ambient temperature for the
application. θja is the thermal resistance junction-to-ambient given in Power Dissipation Table.
The AW9961 comes in a thermally enhanced TDFN package. Compared with the TSOT package, the TDFN
package has better heat dissipation. This package includes a thermal pad that improves the thermal
capabilities of the package. The θja of the TDFN package greatly depends on the PCB layout and thermal pad
connection. The thermal pad must be soldered directly to the analog ground on the PCB. After soldering, the
PCB can be used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached
directly to the appropriate copper plane, or alternatively, can be attached to a special heatsink structure
designed into the PCB. This design optimizes the heat transfer from the integrated circuit(IC).
Using thermal vias underneath the thermal pad as illustrated in the layout example.
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
PCB LAYOUT CONSIDERATION
As for all switching power supplies, especially those high frequency and high current ones, layout is an
important design step. If layout is not carefully done, the regulator could suffer from instability as well as noise
problems. To reduce switching losses, the SW pin rise and fall times are made as short as possible. To
prevent radiation of high frequency resonance problems, proper layout of the high frequency switching path is
essential. Minimize the length and area of all traces connected to the SW pin and always use a ground plane
under the switching regulator to minimize inter-plane coupling. The loop including the PWM switch, Schottky
diode, and output capacitor, contains high current rising and falling in nanosecond and should be kept as
short as possible. The input capacitor needs not only to be close to the VIN pin, but also to the GND pin in
order to reduce the IC supply ripple.
Connect the exposed paddle to the PCB ground plane using at least two vias. The input and the output
bypass capacitors should be placed as close to the IC as possible. Minimize trace lengths between the IC and
the inductor, the diode and the output capacitor; keep these traces short, direct, and wide.
A recommended PCB Layout is shown in FIGURE 23. In order to dissipate the package heat, the package
thermal pad must be connected to a large copper area on the ground plane underneath using multiple vias.
Figure 23
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Recommended PCB Layout
24
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
TAPE AND REEL INFORMATION
Carrier Tape
Reel
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25
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
PACKAGE DESCRIPTION
D
K
COMMON DIMENSIIONS
(UNITS OF MEASURE=MILLIMETER
1
LASER MARK
PIN 1 I.D.
H
E2
E
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A3
e
D2
b
TOP VIEW
Symbol
L
BOTTOM VIEW
0.25
0.30
0.35
D
1.90
2.00
2.10
E
1.90
2.00
2.10
D2
0.90
1.00
1.10
E2
1.50
1.60
1.70
e
0.55
0.65
0.75
K
0.15
0.25
0.35
L
0.20
0.25
0.30
H
A
0.20REF
b
0.20REF
A1
A3
SIDE VIEW
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NOTES:
ALL DIMENSIONS REFER TO JEDEC STANDARD MO-229
DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
26
Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
LAND PATTERN DATA
NOTE A: All linear dimensions are in millimeters.
NOTE B: This drawing is subject to change without notice.
NOTE C: Publication IPC-7351 is recommended for alternate designs.
NOTE D: This land pattern is designed to be soldered to a thermal pad on the board.
NOTE E: Laser cutting aperture with trapezoidal walls and also rounding corners will offer better paste release.
Customers should contact their board assembly site for stencil design recommendations. Refer to IPC-7525
for stencil design considerations.
NOTE F: Customers should contact their board fabrication site for solder mask tolerances.
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
REFLOW
Figure 24
Package Reflow Oven Thermal Profile
Reflow Note
Spec
Average ramp-up rate (217℃c to Peak)
Max. 3℃/sec
Time of Preheat temp.(from 150℃ to 200℃)
60-120sec
Time to be maintained above 217℃
60-150sec
Peak Temperature
>260℃
Time within 5℃ of actual peak temp
20-40sec.
Ramp-down rate
Max. 6℃/sec
Time from 25℃ to peak temp
Max. 8min.
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
REVISION HISTORY
Vision
Date
Change Record
V0.9
August 2014
Datasheet V0.9 Released
V1.0
March 2015
Datasheet V1.0 Released
V1.1
May 2015
1、 Refreshed CIN information;
2、 Refreshed Figure 5;
3、 Added EMI_CTL register and configuration description.
V1.1.1
June 2015
1、 Added Figure 6;
2、 Corrected some literal mistakes.
V1.1.2
November 2015
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1、 Added PWM DIMMING TIMING information in the Electrical
Characteristics
2、 Corrected some literal mistakes.
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Copyright © 2015 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW9961
November 2015 V1.1.2
DISCLAIMER
Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology
Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and shall have no liability for the consequences of use of
such information.
AWINIC Technology reserves the right to make changes to information published in this document, including
without limitation specifications and product descriptions, at any time and without notice. Customers shall
obtain the latest relevant information before placing orders and shall verify that such information is current and
complete. This document supersedes and replaces all information supplied prior to the publication hereof.
AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,
military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an
AWINIC Technology product can reasonably be expected to result in personal injury, death or severe property
or environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC
Technology products in such equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications that are described herein for any of these products are for illustrative purposes only. AWINIC
Technology makes no representation or warranty that such applications will be suitable for the specified use
without further testing or modification.
All products are sold subject to the general terms and conditions of commercial sale supplied at the time of
order acknowledgement.
Nothing in this document may be interpreted or construed as an offer to sell products that is open for
acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other
industrial or intellectual property rights.
Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction
is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
AWINIC is not responsible or liable for such altered documentation. Information of third parties may be subject
to additional restrictions.
Resale of AWINIC components or services with statements different from or beyond the parameters stated by
AWINIC for that component or service voids all express and any implied warranties for the associated
AWINIC component or service and is an unfair and deceptive business practice. AWINIC is not responsible or
liable for any such statements.
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