NUC980DK61YC

NUC980 ARM926EJ-S Based 32-bit Microprocessor NUC980 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microprocessor based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Oct., 02, 2019 Page 1 of 246 Rev 1.11 NUC980 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. NUC980 Table of Contents 1 GENERAL DESCRIPTION .............................................................................. 9 2 FEATURES DESCRIPTION .......................................................................... 10 3 PARTS INFORMATION................................................................................. 17 3.1 Package Type............................................................................................................... 17 3.2 NUC980 Series Part Selection Guide ...................................................................... 18 3.3 NUC980 Series Naming Rule .................................................................................... 19 4 PIN CONFIGURATION .................................................................................. 20 4.1 Pin Configuration ......................................................................................................... 20 4.1.1 NUC980DRxxYx LQFP64-EP Pin Diagram ............................................................... 20 4.1.2 NUC980DKxxYx LQFP128 Pin Diagram ................................................................... 21 4.1.3 NUC980DFxxYx LQFP216 Pin Diagram .................................................................... 22 4.2 Pin Description ............................................................................................................. 23 4.2.1 NUC980 Pin Description ............................................................................................... 23 4.2.2 NUC980 Multi-function Summary Table ..................................................................... 47 4.2.3 NUC980 Multi-function Summary Table Sorted by GPIO ........................................ 64 5 BLOCK DIAGRAM ........................................................................................ 84 5.1 NUC980 Series Block Diagram ................................................................................. 84 6 FUNCTIONAL DESCRIPTION ...................................................................... 85 6.1 ARM® ARM926EJ-S CPU Core ................................................................................. 85 NUC980 SERIES DATASHEET 6.1.1 Overview ......................................................................................................................... 85 6.2 System Manager.......................................................................................................... 86 6.2.1 Overview ......................................................................................................................... 86 6.2.2 System Reset ................................................................................................................. 86 6.2.3 System Power Distribution ........................................................................................... 86 6.2.4 System Memory Map .................................................................................................... 87 6.2.5 Power-On Setting .......................................................................................................... 91 6.2.6 Register Map .................................................................................................................. 93 6.2.7 Register Description ...................................................................................................... 95 6.3 Clock Controller ......................................................................................................... 142 6.3.1 Overview ....................................................................................................................... 142 6.3.2 Features ........................................................................................................................ 142 6.3.3 Block Diagram .............................................................................................................. 143 6.3.4 Functional Description................................................................................................. 150 6.3.5 Registers Map .............................................................................................................. 152 6.3.6 Register Description .................................................................................................... 153 6.4 Advanced Interrpt Controller .................................................................................... 180 6.4.1 Overview ....................................................................................................................... 180 Oct., 02, 2019 Page 2 of 246 Rev 1.11 NUC980 6.4.2 Features ........................................................................................................................ 180 6.5 SDRAM Interface Controller .................................................................................... 181 6.5.1 Overview ....................................................................................................................... 181 6.5.2 Features ........................................................................................................................ 181 6.6 External Bus Interface .............................................................................................. 182 6.6.1 Overview ....................................................................................................................... 182 6.6.2 Features ........................................................................................................................ 182 6.7 General Purpose I/O ................................................................................................. 183 6.7.1 Overview ....................................................................................................................... 183 6.7.2 Features ........................................................................................................................ 183 6.8 Peripheral DMA Controller ....................................................................................... 184 6.8.1 Overview ....................................................................................................................... 184 6.8.2 Features ........................................................................................................................ 184 6.9 Timer Controller (TMR) ............................................................................................. 185 6.9.1 Overview ....................................................................................................................... 185 6.9.2 Features ........................................................................................................................ 185 6.10 Pulse Width Modulation (PWM) ........................................................................ 186 6.10.1 Overview ....................................................................................................................... 186 6.10.2 Features ........................................................................................................................ 186 6.11 Watchdog Timer ................................................................................................... 187 6.11.1 Overview ....................................................................................................................... 187 6.11.2 Features ........................................................................................................................ 187 Windowed Watchdog Timer (WWDT)............................................................... 188 6.12.1 Overview ....................................................................................................................... 188 6.12.2 Features ........................................................................................................................ 188 6.13 Real Time Clock (RTC) ....................................................................................... 189 6.13.1 Overview ....................................................................................................................... 189 6.13.2 Features ........................................................................................................................ 189 6.14 UART Interface Controller (UART).................................................................... 190 6.14.1 Overview ....................................................................................................................... 190 6.14.2 Features ........................................................................................................................ 190 6.15 Smart Card Host Interface.................................................................................. 191 6.15.1 Overview ....................................................................................................................... 191 6.15.2 Features ........................................................................................................................ 191 6.16 I²C Serial Interface Controller ............................................................................ 192 6.16.1 Overview ....................................................................................................................... 192 6.16.2 Features ........................................................................................................................ 192 6.17 Serial Peripheral Interface (SPI)........................................................................ 193 6.17.1 Overview ....................................................................................................................... 193 Oct., 02, 2019 Page 3 of 246 Rev 1.11 NUC980 SERIES DATASHEET 6.12 NUC980 6.17.2 Features ........................................................................................................................ 193 6.18 Quad Serial Peripheral Interface (QSPI).......................................................... 194 6.18.1 Overview ....................................................................................................................... 194 6.18.2 Features ........................................................................................................................ 194 6.19 I²S Controller (I²S) ............................................................................................... 195 6.19.1 Overview ....................................................................................................................... 195 6.19.2 Features ........................................................................................................................ 195 6.20 Ethernet MAC Controller (EMAC) ..................................................................... 196 6.20.1 Overview ....................................................................................................................... 196 6.20.2 Features ........................................................................................................................ 196 6.21 High Speed USB 2.0 Device Controller (HSUSBD) ....................................... 197 6.21.1 Overview ....................................................................................................................... 197 6.21.2 Features ........................................................................................................................ 197 6.22 USB 2.0 Host Controller (USBH) ...................................................................... 198 6.22.1 Overview ....................................................................................................................... 198 6.22.2 Features ........................................................................................................................ 198 6.23 Controller Area Network (CAN) ......................................................................... 199 6.23.1 Overview ....................................................................................................................... 199 6.23.2 Features ........................................................................................................................ 199 6.24 Flash Memory Interface (FMI) ........................................................................... 200 6.24.1 Overview ....................................................................................................................... 200 6.24.2 Features ........................................................................................................................ 200 NUC980 SERIES DATASHEET 6.25 Secure Digital Host Controller (SDH) ............................................................... 201 6.25.1 Overview ....................................................................................................................... 201 6.25.2 Features ........................................................................................................................ 201 6.26 Cryptographic Accelerator (CRYPTO) .............................................................. 202 6.26.1 Overview ....................................................................................................................... 202 6.26.2 Features ........................................................................................................................ 202 6.27 Capture Sensor Interface Controller (CAP) ..................................................... 204 6.27.1 Overview ....................................................................................................................... 204 6.27.2 Features ........................................................................................................................ 204 6.28 Analog to Digitial Converter (ADC) ................................................................... 205 6.28.1 Overview ....................................................................................................................... 205 6.28.2 Features ........................................................................................................................ 205 7 ELECTRICAL CHARACTERISTICS ........................................................... 206 7.1 Absolute Maximum Ratings ..................................................................................... 206 7.2 DC Electrical Characteristics ................................................................................... 207 7.2.1 NUC980 Series DC Electrical Characteristics ......................................................... 207 7.2.2 NUC980 Series GPIO Characteristics ...................................................................... 209 Oct., 02, 2019 Page 4 of 246 Rev 1.11 NUC980 7.3 AC Electrical Characteristics ................................................................................... 210 7.3.1 External 12MHz High Speed Crystal ........................................................................ 210 7.3.2 External 32.768 kHz Low Speed Crystal .................................................................. 211 7.3.3 Power Sequence & nRESET Timing......................................................................... 212 7.3.4 nRESET PIN characteristics ...................................................................................... 214 7.3.5 PLL characteristics ...................................................................................................... 214 7.3.6 EBI Timing..................................................................................................................... 215 7.3.7 I2C Interface Timing .................................................................................................... 216 7.3.8 SPI Interface Timing .................................................................................................... 217 7.3.9 QSPI Interface Timing ................................................................................................. 220 7.3.10 I2S Interface Timing..................................................................................................... 223 7.3.11 Ethernet Interface Timing ........................................................................................... 224 7.3.12 NAND Interface Timing ............................................................................................... 226 7.3.13 SD Interface Timing ..................................................................................................... 227 7.3.14 Capture Sensor Interface Timing ............................................................................... 229 7.4 Analog Characteristics .............................................................................................. 230 7.4.1 12-bit SARADC ............................................................................................................ 230 7.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR) ................................ 231 7.4.3 3.3V Power-On Reset (POR33) ................................................................................ 231 7.4.4 1.2V Power-On Reset (POR12) ................................................................................ 231 7.4.5 USB 2.0 PHY ................................................................................................................ 232 8 PACKAGE DIMENSIONS ........................................................................... 234 8.1 LQFP216 (24x24x1.4mm footprint 2.0mm) ........................................................... 234 8.3 LQFP64-EP (10x10x1.4mm footprint 2.0 mm)...................................................... 236 8.4 Thermal Characteristics............................................................................................ 238 8.4.1 Thermal Performance of LQFP under Forced Convection .................................... 238 8.4.2 Thermal Performance Terminology ........................................................................... 238 8.4.3 Simulation Conditions ................................................................................................. 239 8.5 PCB Reflow Profile Suggestion ............................................................................... 240 8.5.1 Profile Setting Consideration ................................................................................. 240 8.5.2 Profile Suggestion ..................................................................................................... 241 8.6 PKG Baking and Vacuumed .................................................................................... 242 9 ABBREVIATIONS ....................................................................................... 243 10 REVISION HISTORY ................................................................................... 245 Oct., 02, 2019 Page 5 of 246 Rev 1.11 NUC980 SERIES DATASHEET 8.2 LQFP128 (14x14x1.4mm footprint 2.0mm) ........................................................... 235 NUC980 LIST OF FIGURES Figure 3-1 NUC980 Series Package Type ..................................................................................... 17 Figure 3.3-1 NUC980 Series Selection Code ................................................................................ 19 Figure 4.1-1 NUC980DRxxY LQFP 64-pin with EX-PAD Diagram ................................................ 20 Figure 4.1-2 NUC980DKxxYx LQFP 128-pin Diagram .................................................................. 21 Figure 4.1-3 NUC980DFxxYx LQFP 216-pin Diagram .................................................................. 22 Figure 5.1-1 NUC980 Series Block Diagram ................................................................................. 84 Figure 6.2-1 NUC980 Series Power Distribution Diagram ............................................................. 87 Figure 6.2-2 NUC980 System Memory Map Diagram ................................................................... 88 Figure 6.3-1 Clock Controller Block Diagram ............................................................................... 143 Figure 6.3-2 ADC Controller Clock Divider Block Diagram .......................................................... 144 Figure 6.3-3 SD Card Host Controller Clock Divider Block Diagram ........................................... 144 Figure 6.3-4 Timer Clock Divider Clock Diagram ......................................................................... 145 Figure 6.3-5 Ethernet MAC Controller Clock Divider Block Diagram ........................................... 145 2 Figure 6.3-6 I S Controller Clock Divider Block Diagram ............................................................. 145 Figure 6.3-7 Reference Clock Output Divider Block Diagram...................................................... 146 Figure 6.3-8 Smart Card Host Controller Clock Divider Block Diagram ...................................... 146 Figure 6.3-9 CMOS Sensor Controller Divider Block Diagram .................................................... 146 Figure 6.3-10 UART Clock Divider Block Diagram ...................................................................... 147 Figure 6.3-11 USB 1.1 Host Controller 48 MHz Clock Divider Block Diagram ............................ 147 Figure 6.3-12 Watchdog Timer Clock Divider Block Diagram...................................................... 147 NUC980 SERIES DATASHEET Figure 6.3-13 Windowed Watchdog Timer Clock Divider Block Diagram .................................... 148 Figure 6.3-14 CPU_HCLK Clock Generator Block Diagram ........................................................ 149 Figure 7.3-1 Typical HXT Crystal Application Circuit ................................................................... 210 Figure 7.3-2 Typical LXT Crystal Application Circuit .................................................................... 211 Figure 7.3-3 Power up Sequence & nRESET timing Case 1 ....................................................... 212 Figure 7.3-4 Power up Sequence & nRESET timing Case 2 ....................................................... 213 Figure 7.3-5 External Bus Interface Timing Diagram ................................................................... 215 Figure 7.3-6 I2C Interface Timing Diagram .................................................................................. 216 Figure 7.3-7 SPI Master Mode Timing Diagram .......................................................................... 217 Figure 7.3-8 SPI Slave Mode Timing Diagram ............................................................................ 219 Figure 7.3-9 QSPI Master Mode Timing Diagram ........................................................................ 220 Figure 7.3-10 QSPI Slave Mode Timing Diagram ........................................................................ 222 Figure 7.3-11 I2S Interface Timing Diagram ................................................................................ 223 Figure 7.3-12 RMII Interface Timing Diagram .............................................................................. 224 Figure 7.3-13 Ethernet PHY Management Interface Timing Diagram ......................................... 225 Figure 7.3-14 NAND Interface Timing Diagram ........................................................................... 226 Oct., 02, 2019 Page 6 of 246 Rev 1.11 NUC980 Figure 7.3-15 SD Interface Default Mode Timing Diagram .......................................................... 227 Figure 7.3-16 SD Interface High-Speed Mode Timing Diagram .................................................. 228 Figure 7.3-17 Capture Sensor Interface Timing Diagram ............................................................ 229 Figure 8.4-1 Junction to Ambient Thermal Resistance ................................................................ 238 Figure 8.4-2 Junction to Case Thermal Resistance ..................................................................... 239 Figure 8.5-1 PCB Reflow Profile Diagram.................................................................................... 240 Figure 8.5-2 Profile Suggestion for NUC980 series ..................................................................... 241 Figure 8.6-1 Cautions for PKG Baking ......................................................................................... 242 NUC980 SERIES DATASHEET Oct., 02, 2019 Page 7 of 246 Rev 1.11 NUC980 LIST OF TABLES Table 3.2-1 NUC980 Series Part Selection Guide ......................................................................... 18 Table 6.2-1 Address Space Assignments for On-Chip Controllers ................................................ 90 Table 6.2-2 Power-On Setting Bit Description ............................................................................... 92 Table 6.3-1 The Mapping of N and Fpfd Range ............................................................................ 178 Table 7.3-1 EBI Characteristics ................................................................................................... 215 2 Table 7.3-2 I C Interface Characteristics ..................................................................................... 216 Table 7.3-3 SPI Master Mode Characteristics ............................................................................. 217 Table 7.3-4 SPI Slave Mode Characteristics ............................................................................... 218 Table 7.3-5 QSPI Master Mode Characteristics .......................................................................... 220 Table 7.3-6 QSPI Slave Mode Characteristics ............................................................................ 221 2 Table 7.3-7 I S Interface Characteristics ..................................................................................... 223 Table 7.3-8 RMII Interface Characteristics................................................................................... 224 Table 7.3-9 Ethernet PHY Management Interface Characteristics .............................................. 225 Table 7.3-10 NAND Interface Characteristics .............................................................................. 226 Table 7.3-11 SD Interface Default Mode Characteristics............................................................. 227 Table 7.3-12 SD Interface High-Speed Mode Characteristics ..................................................... 228 Table 7.3-13 Capture Sensor Interface Characteristics ............................................................... 229 Table 8.4-1 Thermal Performance of LQFP ................................................................................. 238 Table 8.4-2 Thermal Characteristics Simulation Conditions ........................................................ 239 Table 8.5-1 PCB Reflow Profile Parameters ................................................................................ 240 NUC980 SERIES DATASHEET Table 8.5-2 Profile Parameters for NUC980 Series ..................................................................... 241 Table 9‑1 List of Abbreviations .................................................................................................... 244 Oct., 02, 2019 Page 8 of 246 Rev 1.11 NUC980 1 GENERAL DESCRIPTION The NUC980 series 32-bit microprocessor is powered by the Arm926EJ-S™ processor core with 16 KB I-cache, 16 KB D-cache and MMU running up to 300 MHz. Its SDRAM interface supports SDR/DDR/DDR2/LPDDR type SDRAM running up to 150 MHz. The NUC980 series supports built-in 16KB embedded SRAM and 16.5 KB IBR (Internal Boot ROM) for booting from USB, NAND, SD/eMMC and SPI Flash, and industrial operating temperature from -40°C to 85°C. In addition, the NUC980 series provides built-in SDRAM in LQFP package to ease PCB design and reduce the BOM cost. The NUC980 series is equipped with a large number of high speed digital peripherals, such as two 10/100 Mbps Ethernet MAC supporting RMII, a USB 2.0 high speed host/device, a USB 2.0 high speed host controller, up to six USB 1.1 host lite interfaces, two CMOS sensor interfaces supporting CCIR601 and CCIR656 type sensor, two SD interfaces supporting SD/SDHC/SDIO card, a NAND Flash interface supporting SLC and MLC type NAND Flash, an I2S interface supporting I2S and PCM protocol, Also the NUC980 series offers a built-in hardware cryptography accelerator that supports RSA, ECC, AES, SHA, HMAC and a random number generator (RNG). The NUC980 series provides up to ten UART interfaces, two ISO-7816-3 interfaces, a Quad-SPI interface, two SPI interfaces, up to four I2C interfaces, four CAN 2.0B interfaces, eight channels PWM output, eight channels 12-bit SAR ADC, six 32-bit timers, WDT (Watchdog Timer), WWDT( Window Watchdog Timer), 32.768 kHz XTL and RTC (Real Time Clock). The NUC980 series also supports two 10-channel peripheral DMA (PDMA) for automatic data transfer between memories and peripherals. Key Features Applications - 300 MHz ARM ARM926EJ-S™ MPU with ® - Smart Home gateway - Fingerprint Machine. 16 KB I-cache, 16 KB D-cache - Memory Manager Unit (MMU) - Power concentrator - Built-in 128 MB/64MB/16MB SDRAM Memory in LQFP package - Data Collector - Supports booting from SPI ROM/SPI NAND Flash/NAND/eMMC/SD Card and USB device - Serial server - Smart Home Appliance - 2D/1D Barcode reader - Dual Ethernet MAC - Barcode printer - Four CAN 2.0B interfaces - Power Distribution Unit - Six USB FS Lite hosts - Ethernet Industrial Control - Two USB High speed hosts - SNMP Card - One USB High speed device - Ethernet RTU/ DTU NUC980 SERIES DATASHEET - Supports up to 100MHz Quad-SPI - Two CCIR656/601 Camera interfaces - Supports PRNG, AES256, SHA, ECC, and RAS2048 Oct., 02, 2019 Page 9 of 246 Rev 1.11 NUC980 2 FEATURES DESCRIPTION Core And System  Factory pre-loaded 16.5 KB mask ROM supporting four booting modes – Boot from USB Boot Loader – Boot from SD/eMMC – Boot from NAND Flash – Boot from SPI Flash (SPI-NOR/SPI-NAND)  Arm926EJ-S™ processor core running up to 300 MHz  Built-in 16 KB instruction cache and 16 KB data cache  Built-in Memory Management Unit (MMU)  Supports JTAG debug interface  Up to 64 interrupt sources including 4 external interrupts.  Configurable normal (IRQ) or fast interrupt mode (FIQ).  Configurable 8-level interrupt priority scheme. Low Voltage Detect (LVD)  Two-level LVD with low voltage detect interrupt. (2.8V/2.6V) Low Voltage Reset (LVR)  LVR with 2.4V threshold voltage level.  Built-in 128MB/ 64MB/16MB SDRAM Memory in LQFP package  Clock speed up to 150 MHz  Supports 16-bit data width  Up to 16 KB on-chip SRAM  Byte-, half-word- and word-access  PDMA operation  Two sets of PDMA with ten independent and configurable channels for automatic data transfer between memories and peripherals  Basic and Scatter-Gather transfer modes  Each channel supports circular buffer management using Scatter-Gather Transfer mode  Stride function for rectangle image data movement  Fixed-priority and Round-robin priorities modes  Single and burst transfer types  Byte-, half-word- and word tranfer unit with count up to 65536  Incremental or fixed source and destination address  12 MHz High-speed eXternal crystal oscillator (HXT) for precise timing operation  32.7688 kHz Low-speed eXternal crystal oscillator (LXT) for RTC function and low-power system operation Arm926EJ-S™ Advanced Interrupt Controller Memories SDRAM NUC980 SERIES DATASHEET SRAM Peripheral DMA (PDMA) Clocks External Clock Source Oct., 02, 2019 Page 10 of 246 Rev 1.11 NUC980  Two on-chip PLL up to 500 MHz on-chip PLL, sourced from HXT, allows CPU operation up to the maximim CPU frequency without the need for a highfrequency crystal  Real-Time Clock with a separate power domain (VBAT33)  The RTC clock source includes Low-speed external crystal oscillator (LXT)  The RTC block includes 64 bytes backup registers  Able to wake up CPU  Supports ±5ppm within 5 seconds software clock accuracy compensation  Supports Alarm registers (second, minute, hour, day, month, year)  Supports RTC Time Tick and Alarm Match interrupt  Selectable 12-hour or 24-hour mode  Automatic leap year recognition  Supports 1 Hz clock to be Timer capture source for calibration  Six sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter from independent clock source  One-shot, Periodic, Toggle and Continuous Counting operation modes  Supports event counting function to count the event from external pins  Supports external capture pin for interval measurement and resetting 24-bit up counter  Supports internal capture source from RTC 1 Hz clock for interval measurement resetting 24-bit up counter  Supports chip wake-up function, if a timer interrupt signal is generated  Eight 16-bit down-count counters with four 8-bit prescalar for eight PWM output channels.  Supports complementary mode for 4 complementary paired PWM output channels  18-bit free running up counter for WDT time-out interval  Supports multiple clock sources from HXT, HXT/512 (default selection), PCLK2/4096 or LXT with 8 selectable time-out period  Able to wake up system from Power-down or Idle mode  Time-out event to trigger interrupt or reset system  Supports four WDT reset delay periods, including 1026, 130, 18 or 3 WDT_CLK reset delay period  Configured to force WDT enabled on chip power-on or reset.  Clock sourced from HXT, HXT/512 (default selection), PCLK2/4096 or LXT; the window set by 6-bit counter with 11-bit prescale  Suspended in Idle/Power-down mode  One 12-bit, 9-ch 200k SPS SAR ADC with up to 8 single-ended input channels; 10-bit accuracy is guaranteed.  One internal channels for band-gap VBG input.  Supports external VREF pin. Internal Clock Source Real-Time Clock (RTC) Timers 32-bit Timer Watchdog Window Watchdog Analog Interfaces Analog-to-Digital Converter (ADC) Oct., 02, 2019 Page 11 of 246 Rev 1.11 NUC980 SERIES DATASHEET PWM (PWM) NUC980 Communication Interfaces Low-power UART  10 sets of UARTs with up to 17.45 MHz baud rate.  Auto-Baud Rate measurement and baud rate compensation function.  Supports low power UART (LPUART): baud rate clock from LXT(32.768 kHz) with 9600bps in Power-down mode even system clock is stopped.  16-byte FIFOs with programmable level trigger  Auto flow control ( nCTS and nRTS)  Supports IrDA (SIR) function  Supports LIN function on UART0 and UART1  Supports RS-485 9-bit mode and direction control  Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function in idle mode.  Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction  Supports wake-up function  8-bit receiver FIFO time-out detection function  Supports break error, frame error, parity error and receive/transmit FIFO overflow detection function  PDMA operation.  Two sets of ISO-7816-3 which are compliant with ISO-7816-3 T=0, T=1  Supports full duplex UART function.  4-byte FIFOs with programmable level trigger  Programmable guard time selection (11 ETU ~ 266 ETU)  One 24-bit and two 8 bit time-out counters for Answer to Request (ATR) and waiting times processing  Auto inverse convention function  Stop clock level and clock stop (clock keep) function  Transmitter and receiver error retry function  Supports hardware activation, deactivation and warm reset sequence process  Supports hardware auto deactivation sequence after card removal.  Four sets of I2C devices with Master/Slave mode.  Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)  Supports 10 bits mode  Programmable clocks allowing for versatile rate control  Supports multiple address recognition (four slave address with mask option)  Supports SMBus and PMBus  Supports multi-address power-down wake-up function  PDMA operation  One set of SPI Quad controller with Master/Slave mode, up to 96 MHz at 2.7V~3.6V stsyem voltage.  Supports Dual and Quad I/O Transfer mode  Supports one/two data channel half-duplex transfer Smart Card Interface NUC980 SERIES DATASHEET I2C Quad SPI Oct., 02, 2019 Page 12 of 246 Rev 1.11 NUC980 SPI Supports receive-only mode  Configurable bit length of a transfer word from 8 to 32-bit  Provides separate 8-level depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports the byte reorder function  Supports Byte or Word Suspend mode  Supports 3-wired, no slave select signal, bi-direction interface  PDMA operation.  Up to two sets of SPI controllers with Master/Slave mode.  SPI provides separate 4-level of 32-bit (or 8-level of 16-bit) transmit and receive FIFO buffers.  Able to communicate at up to 96 Mbit/s  Configurable bit length of a transfer word from 8 to 32-bit.  MSB first or LSB first transfer sequence.  Byte reorder function.  Supports Byte or Word Suspend mode.  Supports one data channel half-duplex transfer.  Supports receive-only mode.  PDMA operation.  One set of I2S controller with I2S protocol and PCM protocol.  Supports mono and stereo audio data with 8-, 16- and 24-bit word sizes.  Four 8-level 24-bit FIFO data buffers for left/right channel record and left/right playback.  Built-in DMA function  Supports 2 buffer address for left/right channel and 2 slots data transfer. I2S Mode 2 IS  Supports record and playback.  Supports master and slave mode.  Supports Philips standard and MSB-justified data format. PCM Mode Controller Area Network (CAN) Secure Digital Host Controller (SDHC) Oct., 02, 2019  Supports record and playback.  Supports master mode.  Supports PCM standard data format.  Four CAN 2.0B interfaces  Each supports 32 Message Objects; each Message Object has its own identifier mask.  Programmable FIFO mode (concatenation of Message Object).  Disabled Automatic Re-transmission mode for Time Triggered CAN applications.  Supports power-down wake-up function.  Two sets of Secure Digital Host Controllers, compliant with SD Memory Card Specification Version 2.0.  Supports 50 MHz to achieve 200 Mbps at 3.3V operation. Page 13 of 246 Rev 1.11 NUC980 SERIES DATASHEET  NUC980 NAND Flash Controller External Bus Interface (EBI) GPIO NUC980 SERIES DATASHEET  Supports dedicated DMA master with Scatter-Gather function to accelerate the data transfer between system memory and SD/SDHC/SDIO card.  Supports SLC and MLC type NAND Flash device.  Supports 2KB, 4KB and 8KB page size NAND Flash device.  8-bit data width.  Supports ECC8, ECC12 and ECC24 BCH algorithm with ECC code generation, error detection and error correction.  Supports dedicated DMA master with Scatter-Gather function to accelerate the data transfer between system memory and NAND Flash.  Supports up to three memory banks with individual adjustment of timing parameter.  Each bank supports dedicated external chip select pin with polarity control and up to 1 MB addressing space.  8-/16-bit data width.  Configurable idle cycle for different access condition: Idle of Write command finish (W2X) and Idle of Read-to-Read (R2R).  Supports address bus and data bus separate mode.  Supports LCD interface i80 mode.  PDMA operation.  Supports four I/O modes: Bi-direction, Push-Pull output, Open-Drain output and Input only with high impendence mode.  Selectable TTL/Schmitt trigger input.  Configured as interrupt source with edge/level trigger setting.  Supports independent pull-up/pull-down control.  Supports 5V-tolerance function except analog I/O. (Except PB.0 ~ 7; All USB High Speed PIN.)  Compliant with USB Revision 2.0 Specification.  Compatible with OHCI (Open Host Controller Interface) Revision 1.0.  Supports full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.  Supports Control, Bulk, Interrupt, Isochronous and Split transfers.  Supports an integrated Root Hub.  Up to six USB Host Lite ports.  Built-in DMA.  Apply to USB dongle devices or USB cable length is limited to less than 1 meter. Advanced Connectivity USB 1.1 Host Lite USB 2.0 High Speed Host/Device USB 2.0 High Speed with on-chip transceiver Oct., 02, 2019  One set of on-chip USB 2.0 high speed dual role transceiver configurable as host, device or ID-dependent.  One set of on-chip USB 2.0 high speed transceiver with host only. USB 2.0 High Speed Host Controller  Compliant with USB Revision 2.0 Specification.  Compatible with EHCI (Enhanced Host Controller Interface) Revision 1.0.  Compatible with OHCI (Open Host Controller Interface) Revision 1.0. Page 14 of 246 Rev 1.11 NUC980  Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.  Integrated with a port routing logic to route full/low speed device to OHCI controller.  Supports an integrated Root Hub.  Built-in DMA. USB 2.0 High Speed Device Controller Ethernet MAC Compliant with USB Revision 2.0 Specification.  Supports one dedicate control endpoint and 12 configurable endpoints; each can be Isochronous, Bulk or Interrupt and either IN or OUT direction.  4096 bytes configurable RAM for endpoint buffer and up to 1024 bytes packet size.  Three different operation modes of an in-endpoint: Auto Validation mode, Manual Validation mode and Fly mode.  Suspend, resume and remote wake-up capability.  Built-in DMA.  IEEE Std. 802.3 CSMA/CD protocol.  Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol.  Two sets of Ethernet MAC.  Supports both half and full duplex for 10 Mbps or 100 Mbps operation.  RMII (Reduced Media Independent Interface) and serial management interface (MDC/MDIO).  Pause and remote pause function for flow control.  Long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception.  CAM function for Ethernet MAC address recognition.  Supports Magic Packet recognition to wake system up from Power-down mode.  Built-in DMA.  Two sets of CMOS sensor interfaces supporting CCIR601 and CCIR656 type sensor.  Resolution up to 3M pixels.  Supports YUV422 and RGB565 color format for data output by CMOS image sensor.  Supports YUV422, RGB565, RGB555 and Y-only color format with planar and packet data format for data storing to system memory.  Supports image cropping and cropping window up to 4096x2048.  Supports vertical and horizontal scaling-down with N/M scaling factor.  Supports Negative, Sepia and Posterization color effects Cryptography Accelerator Rivest、Shamir and Adleman Cryptography (RSA) Elliptic Curve Cryptography (ECC) Oct., 02, 2019  Hardware RSA accelerator.  Supports both encryption and decryption.  Supports up to 2048 bits.  Hardware ECC accelerator.  Supports 192-bit and 256-bit key length. Page 15 of 246 Rev 1.11 NUC980 SERIES DATASHEET CMOS Sensor Interface  NUC980 Advanced Encryption Standard (AES) Secure Hash Algorithm (SHA) keyed-Hash Message Authentication Code (HMAC) PRNG  Supports both prime field GF(p) and binary field GF(2m).  Supports NIST P-192, P-224, P-256, P-384 and P-521 curve sizes.  Supports NIST B-163, B-233, B-283, B-409 and B-571 curve sizes.  Supports NIST K-163, K-233, K-283, K-409 and K-571 curve sizes.  Supports point multiplication, addition and doubling operations in GF(p) and GF(2m).  Supports modulus division, multiplication, addition and subtraction operations in GF(p).  Hardware AES accelerator.  Supports 128-bit, 192-bit and 256-bit key length and key expander, and compliant with FIPS 197.  Supports ECB, CBC, CFB, OFB, CTR, CBC-CS1, CBC-CS2 and CBC-CS3 block cipher modes  Compliant with NIST SP800-38A and addendum.  Hardware SHA accelerator.  Supports SHA-160, SHA-224, SHA-256, SHA-384 and SHA-512.  Compliant with FIPS 180/180-2.  Hardware HMAC accelerator.  Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA384, and HMAC-SHA-512.  Compliant with FIPS 180/180-2.  Supports 64-/128-/192-/256-bit random number generator. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 16 of 246 Rev 1.11 NUC980 3 PARTS INFORMATION 3.1 Package Type Part No. NUC980 LQFP64-EP LQFP128 LQFP216 NUC980DRxxYC NUC980DKxxYC NUC980DFxxYC NUC980DRxxY NUC980DKxxY NUC980DFxxY Figure 3-1 NUC980 Series Package Type NUC980 SERIES DATASHEET Oct., 02, 2019 Page 17 of 246 Rev 1.11 NUC980 3.2 NUC980 Series Part Selection Guide NUC980 Part Number DF71YC DF71Y DF61YC DK71YC DK71Y DK61YC DK61Y DK41Y DR61YC DR61Y DR41YC DR41Y DDR Siz e(MB) 128 128 64 128 128 64 64 16 64 64 16 16 I/O 104 104 104 92 92 92 92 92 40 40 40 40 NAND NAND NAND NAND NAND NAND NAND NAND SPI NOR SPI NOR SPI NOR SPI NOR QSPI NAND QSPI NAND QSPI NAND QSPI NAND QSPI NAND QSPI NAND QSPI NAND QSPI NAND Boot Sourc e QSPI NOR QSPI NOR QSPI NOR QSPI NOR QSPI NOR QSPI NOR QSPI NOR QSPI NOR SPI NOR SPI NOR SPI NOR SPI NOR SPI NOR SPI NOR SPI NOR SPI NOR eMMC eMMC eMMC eMMC eMMC eMMC eMMC eMMC SD Card SD Card SD Card SD Card SD Card SD Card SD Card SD Card RTC √ √ √ √ √ √ √ √ - - - - UART 10 10 10 10 10 10 10 10 8 8 8 8 ISO-7816 2 2 2 2 2 2 2 2 2 2 2 2 SPI 3 3 3 3 3 3 3 3 2 2 2 2 I2S 1 1 1 1 1 1 1 1 1 1 1 1 I2C 4 4 4 4 4 4 4 4 2 2 2 2 CAN 4 - 4 4 - 4 - - 2 - 2 - SDHC/SDIO/eMMC 2 2 2 2 2 2 2 2 1 1 1 1 Cry pto √ √ √ √ √ √ √ √ √ √ √ √ Ex ternal Bus Interfac e √ √ √ √ √ √ √ √ - - - - Camera Interfac e 2 2 2 2 2 2 2 2 1 1 1 1 16-bit PWM 10/100Mb Ethernet MAC USB 1.1 FS Hos t Lite USB 2.0 HS Hos t 8 2 6 1 8 2 6 1 8 2 6 1 8 2 6 1 8 2 1 8 2 6 1 8 2 1 8 2 1 5 1 - 5 1 - 5 1 - 5 1 - USB 2.0 HS Hos t / Dev ic e 1 1 1 1 1 1 1 1 1 1 1 1 12-bit ADC 8 8 8 8 8 8 8 8 2 2 2 2 Pac k age LQF P216 LQF P216 LQF P216 LQF P 128 LQF P 128 LQF P 128 LQF P 128 LQF P 128 LQF P 64 - EP LQF P 64 - EP LQF P 64 - EP LQF P 64 - EP Table 3.2-1 NUC980 Series Part Selection Guide NUC980 SERIES DATASHEET Oct., 02, 2019 Page 18 of 246 Rev 1.11 NUC980 3.3 NUC980 Series Naming Rule NUC 9 80 D K 6 1 Y C Nuvoton MCU Core Series Package Pin count DDR Size DDR Vonder ID PB Free Support CAN D: LQFP K:128 pin 7:128MB C: CAN F:216 pin 6: 64MB N/A : Non CAN R:64 pin 4: 16MB ARM 926 Figure 3.3-1 NUC980 Series Selection Code NUC980 SERIES DATASHEET Oct., 02, 2019 Page 19 of 246 Rev 1.11 NUC980 4 PIN CONFIGURATION 4.1 Pin Configuration VDD12 PF.6 PF.5 PF.4 PF.3 PF.2 PF.1 PF.0 VDD33 MVDD VDD12 nRESET PD.5 PD.4 PD.3 PD.2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 NUC980DRxxYx LQFP64-EP Pin Diagram 49 32 VDD33 PF.8 50 31 VDD12 PF.9 51 30 PC.15 PF.11 52 29 PC.14 PF.12 53 28 PC.13 VDD33 54 27 PC.12 XT_IN 55 26 PC.11 XT_OUT 56 25 PC.10 PE.11 57 24 PC.9 VDD12 58 23 PC.8 VUSB1_VDD33 59 22 PC.6 VUSB0_VDD12 60 21 PC.5 USB0_DM 61 20 PC.4 USB0_DP 62 19 PC.3 VUSB0_VDD33 63 18 AVDD33 USB0_REXT 64 17 PB.4 Top transparent view LQFP64-EP 8 9 10 11 12 13 14 15 16 VDD33 VDD12 MVDD VDD12 VDD33 PG.1 PG.0 PB.6 PA.3 PA.6 5 PA.2 PA.5 4 PA.1 7 3 6 2 PA.4 1 VSS PA.0 NUC980 SERIES DATASHEET PF.7 USB0_ID 4.1.1 Figure 4.1-1 NUC980DRxxYx LQFP 64-pin with EX-PAD Diagram Oct., 02, 2019 Page 20 of 246 Rev 1.11 NUC980 PF.7 PLL_VSS VDD PB.13 PF.6 PF.5 PF.4 PF.3 PF.2 PF.1 PF.0 VDDIO MVDD MVDD VDD nRESET PG.15 PG.14 PG.13 PG.12 PG.11 PD.15 PD.14 PD.13 PD.12 PD.11 PD.10 PD.9 PD.8 PD.7 PD.6 PD.5 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 NUC980DKxxYx LQFP128 Pin Diagram 97 64 VSS PF.9 98 63 PD.4 PF.10 99 62 PD.3 PF.11 100 61 PD.2 PF.12 101 60 VDDIO VDDIO 102 59 PC.15 XT_IN 103 58 PC.14 XT_OUT 104 57 PC.13 PE.0 105 56 PC.12 PE.1 106 55 PC.11 PE.2 107 54 PC.10 PE.3 108 53 PC.9 PE.4 109 52 PC.8 PE.5 110 51 PC.7 PE.6 111 50 PC.6 PE.7 112 49 PC.5 PE.8 113 48 PC.4 PE.9 114 47 PC.3 PE.10 115 46 PC.2 PE.11 116 45 PC.1 PE.12 117 44 PC.0 VDD 118 43 VDD USB1_DM 119 42 PB.8 USB1_DP 120 41 X32_OUT USB1_VDD33 121 40 X32_IN USB1_REXT 122 39 VBAT33 USB0_VDD 123 38 PB.2 USB0_DM 124 37 PB.3 USB0_DP 125 36 PB.1 USB0_VDD33 126 35 PB.5 USB0_REXT 127 34 PB.7 VSS 128 33 AVDDADC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PA.6 VDDIO VDD MVDD MVDD VDD PA.7 PA.8 PA.9 PA.10 PA.11 PA.12 VDDIO PG.9 PG.8 PG.7 PG.6 PG.5 PG.3 PG.1 PG.0 PB.0 PB.6 PB.4 AVSSADC LQFP128 Figure 4.1-2 NUC980DKxxYx LQFP 128-pin Diagram Oct., 02, 2019 Page 21 of 246 Rev 1.11 NUC980 SERIES DATASHEET PF.8 USB0_ID 4.1.2 NUC980 NUC980DFxxYx LQFP216 Pin Diagram 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 163 108 164 107 165 106 166 105 167 104 168 103 169 102 170 101 171 100 172 99 173 98 174 97 175 96 176 95 177 94 178 93 179 92 180 91 181 90 182 89 183 88 184 87 185 86 186 85 187 84 188 83 189 82 LQFP216 190 81 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 55 26 56 216 25 57 215 24 58 214 23 59 213 22 60 212 21 61 211 20 62 210 19 63 209 18 64 208 17 65 207 16 66 206 15 67 205 14 68 204 13 69 203 12 70 202 11 71 201 10 72 200 9 73 199 8 74 198 7 75 197 6 76 196 5 77 195 4 78 194 3 79 193 2 80 192 1 191 USER_ID.3 USER_ID.2 USER_ID.1 USER_ID.0 VSS DRAM_SIZE.2 DRAM_SIZE.1 DRAM_SIZE.0 CRPT_EN VDDIO CAN_EN VSS VSS VDD PC.15 PC.14 PC.13 PC.12 PC.11 PC.10 VSS PC.9 VSS PC.8 PC.7 PC.6 VSS PC.5 VSS PC.4 PC.3 PC.2 PC.1 PC.0 VDD VSS VSS PB.8 VSS BAT_VSS33 X32_OUT X32_IN nWAKEUP PWREN VBAT33 AVDDADC VREF PB.2 PB.3 PB.1 PB.5 PB.7 AVDDADC AVSSADC VSS USB0_ID PA.0 PA.1 PA.2 PA.3 PA.4 PA.5 PA.6 VDDIO VSS VDD VSS VDD VSS MVDD VSS MVDD VSS MVDD VSS MVDD VSS MVDD VSS VSS VSS VDD PA.7 PA.8 PA.9 PA.10 PA.11 PA.12 PA.13 PA.14 PA.15 PG.10 VDDIO PG.9 PG.8 PG.7 PG.6 PG.5 PG.4 PG.3 PG.2 PG.1 PG.0 VSS VSS PB.0 PB.6 PB.4 NUC980 SERIES DATASHEET PLL_VSS VSS PF.7 PF.8 PF.9 VDD PF.10 PF.11 VSS PF.12 VDDIO XT_IN XT_OUT VSS PE.0 PE.1 PE.2 VDD PE.3 PE.4 PE.5 PE.6 PE.7 VDDIO PE.8 PE.9 PE.10 PE.11 PE.12 VSS VDD VSS VDD VDD USB1_VSS USB1_XTALOUT_U1 USB1_XTALIN_U1 USB1_VSS USB1_DM USB1_DP USB1_VDD33 USB1_VDD33 USB1_REXT USB0_VDD USB0_VDD USB0_VSS USB0_XTALOUT_U0 USB0_XTALIN_U0 USB0_VSS USB0_DM USB0_DP USB0_VDD33 USB0_VDD33 USB0_REXT 161 162 PLL_VDD VDD PB.13 PF.6 PF.5 PF.4 PF.3 PF.2 PF.1 PF.0 VDDIO VSS VSS VSS MVDD VSS MVDD VSS MVDD VSS MVDD VDD VSS VSS VDDIO nRESET PG.15 PG.14 PG.13 PG.12 PG.11 PD.15 PD.14 PD.13 VSS PD.12 PD.11 PD.10 PD.9 PD.8 PD.7 PD.6 PD.5 PD.4 PD.3 PD.2 PB.12 PB.11 PB.10 PB.9 PD.1 PD.0 VSS USER_ID.4 4.1.3 Figure 4.1-3 NUC980DFxxYx LQFP 216-pin Diagram Oct., 02, 2019 Page 22 of 246 Rev 1.11 NUC980 4.2 Pin Description 4.2.1 NUC980 Pin Description 64 128 216 Pin Name Pin Pin Pin 1 1 Type MFP Description Ground pin for digital circuit 1 VSS P MFP0 2 USB0_ID IU - USB0 Host/Device identification with an internal pull-up 1: Device (default) 0: Host 2 3 5 3 4 5 Oct., 02, 2019 3 4 5 6 PA.0 I/O MFP0 General purpose digital I/O pin QSPI0_SS1 I/O MFP1 Quad SPI0 slave select 1 pin I2C0_SDA I/O MFP3 I2C0 data input/output pin UART1_RXD I MFP4 UART1 data receiver input pin EINT0 I MFP5 External interrupt 0 input pin TM0_ECNT I/O MFP6 Timer0 event counter input/toggle output pin CAN3_RXD I MFP7 CAN3 bus receiver input PA.1 I/O MFP0 General purpose digital I/O pin EBI_nCS2 O MFP1 EBI chip select 2 output pin EBI_MCLK O MFP2 EBI external clock output pin I2C0_SCL I/O MFP3 I2C0 clock pin UART1_TXD O MFP4 UART1 data transmitter output pin EINT1 I MFP5 External interrupt 1 input pin TM1_ECNT I/O MFP6 Timer1 event counter input/toggle output pin CAN3_TXD O MFP7 CAN3 bus transmitter output PA.2 I/O MFP0 General purpose digital I/O pin UART6_CTS I MFP1 UART6 clear to Send input pin I2S_LRCK O MFP2 I2S left right channel clock output pin SC0_CD I MFP3 Smart Card 0 card detect pin JTAG1_TDO O MFP4 JTAG1 data output pin TM2_ECNT I/O MFP6 Timer2 event counter input/toggle output pin PA.3 I/O MFP0 General purpose digital I/O pin UART6_RTS O MFP1 UART6 request to Send output pin I2S_BCLK O MFP2 I2S bit clock output pin SC0_PWR O MFP3 Smart Card 0 power pin JTAG1_TCK I MFP4 JTAG1 clock input pin Page 23 of 246 NUC980 SERIES DATASHEET 4 2 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 6 Type MFP Description TM3_ECNT I/O MFP6 Timer3 event counter input/toggle output pin PA.4 I/O MFP0 General purpose digital I/O pin UART6_RXD I MFP1 UART6 data receiver input pin I2S_DI I MFP2 I2S data input pin I/O MFP3 Smart Card 0 data pin JTAG1_TMS I MFP4 JTAG1 test mode selection input pin TM4_ECNT I/O MFP6 Timer4 event counter input/toggle output pin PA.5 I/O MFP0 General purpose digital I/O pin UART6_TXD O MFP1 UART6 data transmitter output pin I2S_DO O MFP2 I2S data output pin SC0_CLK O MFP3 Smart Card 0 clock pin JTAG1_TDI I MFP4 JTAG1 data input pin TM5_ECNT I/O MFP6 Timer5 event counter input/toggle output pin PA.6 I/O MFP0 General purpose digital I/O pin EBI_nCS1 O MFP1 EBI chip select 1 output pin I2S_MCLK O MFP2 I2S master clock output pin SC0_RST O MFP3 Smart Card 0 reset pin JTAG1_nTRST I MFP4 JTAG1 reset input pin 10 VDD33 P MFP0 Power supply for I/O power pin 11 VSS P MFP0 Ground pin for digital circuit 12 VDD12 P MFP0 Power supply for Internal core power pin 13 VSS P MFP0 Ground pin for digital circuit 14 VDD12 P MFP0 Power supply for Internal core power pin 15 VSS P MFP0 Ground pin for digital circuit 16 MVDD P MFP0 Power supply for Memory ports 17 VSS P MFP0 Ground pin for digital circuit 18 MVDD P MFP0 Power supply for Memory ports 19 VSS P MFP0 Ground pin for digital circuit 20 MVDD P MFP0 Power supply for Memory ports 21 VSS P MFP0 Ground pin for digital circuit 22 MVDD P MFP0 Power supply for Memory ports 23 VSS P MFP0 Ground pin for digital circuit 24 MVDD P MFP0 Power supply for Memory ports 6 7 SC0_DAT 7 8 NUC980 SERIES DATASHEET 9 10 11 7 8 8 9 10 11 12 9 Oct., 02, 2019 Page 24 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 12 Type MFP Description VSS P MFP0 Ground pin for digital circuit 26 VSS P MFP0 Ground pin for digital circuit 27 VSS P MFP0 Ground pin for digital circuit 13 28 VDD12 P MFP0 Power supply for Internal core power pin 14 29 PA.7 I/O MFP0 General purpose digital I/O pin EBI_nWE O MFP1 EBI write enable output pin UART2_CTS I MFP2 UART2 clear to Send input pin TM3_EXT I/O MFP3 Timer3 external capture input/toggle output pin PA.8 I/O MFP0 General purpose digital I/O pin EBI_nRE O MFP1 EBI read enable output pin UART2_RTS O MFP2 UART2 request to Send output pin TM3_TGL I/O MFP3 Timer3 event counter input/toggle output pin PA.9 I/O MFP0 General purpose digital I/O pin EBI_nCS0 O MFP1 EBI chip select 0 output pin UART2_RXD I MFP2 UART2 data receiver input pin TM2_EXT I/O MFP3 Timer2 external capture input/toggle output pin PA.10 I/O MFP0 General purpose digital I/O pin EBI_ADDR10 O MFP1 EBI address bus bit 10 UART2_TXD O MFP2 UART2 data transmitter output pin TM2_TGL I/O MFP3 Timer2 event counter input/toggle output pin PA.11 I/O MFP0 General purpose digital I/O pin EBI_ADDR9 O MFP1 EBI address bus bit 9 UART8_RXD I MFP2 UART8 data receiver input pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin PA.12 I/O MFP0 General purpose digital I/O pin EBI_ADDR8 O MFP1 EBI address bus bit 8 UART8_TXD O MFP2 UART8 data transmitter output pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PA.13 I/O MFP0 General purpose digital I/O pin EBI_ADDR13 O MFP1 EBI address bus bit 13 I2C1_SDA I/O MFP2 I2C1 data input/output pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin A MFP4 USB 1.1 host lite port 5 differential signal D- 15 16 17 18 19 30 31 32 33 34 35 USBHL5_DM Oct., 02, 2019 Page 25 of 246 NUC980 SERIES DATASHEET 25 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 36 37 NUC980 SERIES DATASHEET 38 13 Type MFP Description CAN1_RXD I MFP5 CAN1 bus receiver input UART7_TXD O MFP6 UART7 data transmitter output pin PWM03 O MFP7 PWM03 counter synchronous trigger output pin EINT0 I MFP8 External interrupt 0 input pin PA.14 I/O MFP0 General purpose digital I/O pin EBI_ADDR14 O MFP1 EBI address bus bit 14 I2C1_SCL I/O MFP2 I2C1 clock pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin USBHL5_DP A MFP4 USB 1.1 host lite port 5 differential signal D+ CAN1_TXD O MFP5 CAN1 bus transmitter output UART7_RXD I MFP6 UART7 data receiver input pin PWM02 O MFP7 PWM02 counter synchronous trigger output pin EINT1 I MFP8 External interrupt 1 input pin PA.15 I/O MFP0 General purpose digital I/O pin EBI_ADDR19 O MFP1 EBI address bus bit 19 I2C0_SDA I/O MFP2 I2C0 data input/output pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin USBHL4_DM A MFP4 USB 1.1 host lite port 4 differential signal D- CAN2_RXD I MFP5 CAN2 bus receiver input SPI1_SS0 I/O MFP6 SPI1 slave select 0 pin PWM01 O MFP7 PWM01 counter synchronous trigger output pin I2S_LRCK O MFP8 I2S left right channel clock output pin PG.10 I/O MFP0 General purpose digital I/O pin EBI_DATA0 I/O MFP1 EBI data bus bit 0 I2C0_SCL I/O MFP2 I2C0 clock pin TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin USBHL4_DP A MFP4 USB 1.1 host lite port 4 differential signal D+ CAN2_TXD O MFP5 CAN2 bus transmitter output SPI1_CLK I/O MFP6 SPI1 serial clock pin PWM00 O MFP7 PWM00 counter synchronous trigger output pin I2S_BCLK O MFP8 I2S bit clock output pin 20 39 VDD33 P MFP0 Power supply for I/O power pin 21 40 PG.9 I/O MFP0 General purpose digital I/O pin Oct., 02, 2019 Page 26 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 22 23 24 42 43 44 45 26 46 Oct., 02, 2019 MFP Description EBI_ADDR7 O MFP1 EBI address bus bit 7 UART8_CTS I MFP2 UART8 clear to Send input pin PWM13 O MFP6 PWM13 counter synchronous trigger output pin CFG.9_PwrOnSet9 IU - PG.8 I/O MFP0 General purpose digital I/O pin EBI_ADDR6 O MFP1 EBI address bus bit 6 UART8_RTS O MFP2 UART8 request to Send output pin PWM12 O MFP6 PWM12 counter synchronous trigger output pin CFG.8_PwrOnSet8 IU - PG.7 I/O MFP0 General purpose digital I/O pin EBI_ADDR5 O MFP1 EBI address bus bit 5 UART5_TXD O MFP2 UART5 data transmitter output pin PWM11 O MFP6 PWM11 counter synchronous trigger output pin CFG.7_PwrOnSet7 IU - PG.6 I/O MFP0 General purpose digital I/O pin EBI_ADDR4 O MFP1 EBI address bus bit 4 UART5_RXD I MFP2 UART5 data receiver input pin PWM10 O MFP6 PWM10 counter synchronous trigger output pin CFG.6_PwrOnSet6 IU - PG.5 I/O MFP0 General purpose digital I/O pin EBI_ADDR12 O MFP1 EBI address bus bit 12 UART5_RTS O MFP2 UART5 request to Send output pin CFG.5_PwrOnSet5 IU - PG.4 I/O MFP0 General purpose digital I/O pin EBI_ADDR18 O MFP1 EBI address bus bit 18 UART5_CTS I MFP2 UART5 clear to Send input pin CFG.4_PwrOnSet4 IU - PG.3 I/O MFP0 General purpose digital I/O pin EBI_ADDR3 O MFP1 EBI address bus bit 3 UART2_RTS O MFP2 UART2 request to Send output pin System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. Page 27 of 246 Rev 1.11 NUC980 SERIES DATASHEET 25 41 Type NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin PWM03 O MFP6 PWM03 counter synchronous trigger output pin CFG.3_PwrOnSet3 IU - PG.2 I/O MFP0 General purpose digital I/O pin EBI_ADDR2 O MFP1 EBI address bus bit 2 UART2_CTS I MFP2 UART2 clear to Send input pin PWM02 O MFP6 PWM02 counter synchronous trigger output pin CFG.2_PwrOnSet2 IU - PG.1 I/O MFP0 General purpose digital I/O pin EBI_ADDR1 O MFP1 EBI address bus bit 1 UART2_TXD O MFP2 UART2 data transmitter output pin PWM01 O MFP6 PWM01 counter synchronous trigger output pin CFG.1_PwrOnSet1 IU - PG.0 I/O MFP0 General purpose digital I/O pin EBI_ADDR0 O MFP1 EBI address bus bit 0 UART2_RXD I MFP2 UART2 data receiver input pin CLK_OUT O MFP3 Internal clock selection output pin PWM00 O MFP6 PWM00 counter synchronous trigger output pin CFG.0_PwrOnSet0 IU - 50 VSS P MFP0 Ground pin for digital circuit 51 VSS P MFP0 Ground pin for digital circuit 52 PB.0 I/O MFP0 General purpose digital I/O pin EBI_ADDR12 O MFP1 EBI address bus bit 12 UART2_CTS I MFP2 UART2 clear to Send input pin ADC_AIN0 A MFP8 ADC channel 0 analog input PB.6 I/O MFP0 General purpose digital I/O pin EBI_ADDR13 O MFP1 EBI address bus bit 13 I2C1_SDA I/O MFP2 I2C1 data input/output pin I2S_LRCK O MFP3 I2S left right channel clock output pin USBHL0_DM A MFP4 USB 1.1 host lite port 0 differential signal D- UART7_TXD O MFP5 UART7 data transmitter output pin SPI1_SS0 I/O MFP6 SPI1 slave select 0 pin 47 14 15 27 28 NUC980 SERIES DATASHEET 29 16 30 48 49 53 Oct., 02, 2019 System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. Page 28 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin A MFP8 ADC channel 6 analog input PB.4 I/O MFP0 General purpose digital I/O pin EBI_ADDR14 O MFP1 EBI address bus bit 14 I2C1_SCL I/O MFP2 I2C1 clock pin I2S_BCLK O MFP3 I2S bit clock output pin USBHL0_DP A MFP4 USB 1.1 host lite port 0 differential signal D+ UART7_RXD I MFP5 UART7 data receiver input pin SPI1_CLK I/O MFP6 SPI1 serial clock pin ADC_AIN4 A MFP8 ADC channel 4 analog input ADC_AIN6 17 18 31 54 55 AVSS P MFP0 Ground pin for analog SAR-ADC 33 56 AVDD33 P MFP0 Power supply for analog SAR-ADC, DC3.3V 34 57 PB.7 I/O MFP0 General purpose digital I/O pin EBI_ADDR15 O MFP1 EBI address bus bit 15 I2C2_SDA I/O MFP2 I2C2 data input/output pin I2S_DI I MFP3 I2S data input pin USBHL0_DM A MFP4 USB 1.1 host lite port 0 differential signal D- UART7_CTS I MFP5 UART7 clear to Send input pin SPI1_MOSI I/O MFP6 SPI1 MOSI (Master Out, Slave In) pin ADC_AIN7 A MFP8 ADC channel 7 analog input PB.5 I/O MFP0 General purpose digital I/O pin EBI_ADDR16 O MFP1 EBI address bus bit 16 I2C2_SCL I/O MFP2 I2C2 clock pin I2S_DO O MFP3 I2S data output pin USBHL0_DP A MFP4 USB 1.1 host lite port 0 differential signal D+ UART7_RTS O MFP5 UART7 request to Send output pin SPI1_MISO I/O MFP6 SPI1 MISO (Master In, Slave Out) pin ADC_AIN5 A MFP8 ADC channel 5 analog input PB.1 I/O MFP0 General purpose digital I/O pin EBI_ADDR17 O MFP1 EBI address bus bit 17 I2C3_SDA I/O MFP2 I2C3 data input/output pin I2S_MCLK O MFP3 I2S master clock output pin CAN2_RXD I MFP4 CAN2 bus receiver input I/O MFP5 Timer0 external capture input/toggle output pin 35 36 58 59 TM0_EXT Oct., 02, 2019 Page 29 of 246 NUC980 SERIES DATASHEET 32 Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin SPI1_SS1 I/O MFP6 SPI1 slave select 1 pin UART9_TXD O MFP7 UART9 data transmitter output pin ADC_AIN1 A MFP8 ADC channel 1 analog input PB.3 I/O MFP0 General purpose digital I/O pin EBI_ADDR18 O MFP1 EBI address bus bit 18 I2C3_SCL I/O MFP2 I2C3 clock pin EINT2 I MFP3 External interrupt 2 input pin CAN2_TXD O MFP4 CAN2 bus transmitter output TM0_TGL I/O MFP5 Timer0 event counter input/toggle output pin SPI0_SS1 I/O MFP6 SPI0 slave select 1 pin UART9_RXD I MFP7 UART9 data receiver input pin ADC_AIN3 A MFP8 ADC channel 3 analog input PB.2 I/O MFP0 General purpose digital I/O pin EBI_ADDR2 O MFP1 EBI address bus bit 2 UART9_RTS O MFP7 UART9 request to Send output pin ADC_AIN2 A MFP8 ADC channel 2 analog input 62 AVref A MFP0 ADC reference voltage input 63 AVDD33 P MFP0 Power supply for analog SAR-ADC, DC 3.3V 64 VBAT33 P MFP0 Power supply by batteries for RTC 65 NC - No connect 66 NC - No connect 40 67 X32_IN I MFP0 External 32.768 kHz crystal input pin 41 68 X32_OUT O MFP0 External 32.768 kHz crystal output pin 69 VSS P MFP0 Ground pin for digital circuit 70 VSS P MFP0 Ground pin for digital circuit 71 PB.8 I/O MFP0 General purpose digital I/O pin EBI_ADDR11 O MFP1 EBI address bus bit 11 I2C2_SCL I/O MFP2 I2C2 clock pin CAN2_RXD I MFP3 CAN2 bus receiver input UART8_TXD O MFP4 UART8 data transmitter output pin SD0_nCD I MFP6 SD0 card detect input pin TM0_EXT I/O MFP7 Timer0 external capture input/toggle output pin P MFP0 Ground pin for digital circuit 37 38 NUC980 SERIES DATASHEET 39 42 60 61 72 Oct., 02, 2019 VSS Page 30 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin Description P MFP0 Ground pin for digital circuit 43 74 VDD12 P MFP0 Power supply Internal core power pin 44 75 PC.0 I/O MFP0 General purpose digital I/O pin EBI_DATA0 I/O MFP1 EBI data bus bit 0 I2C2_SDA I/O MFP2 I2C2 data input/output pin CAN2_TXD O MFP3 CAN2 bus transmitter output UART8_RXD I MFP4 UART8 data receiver input pin SPI0_SS1 I/O MFP5 SPI0 slave select 1 pin TM0_TGL I/O MFP7 Timer0 event counter input/toggle output pin PC.1 I/O MFP0 General purpose digital I/O pin EBI_DATA1 I/O MFP1 EBI data bus bit 1 NAND_nCS0 O MFP3 NAND flash chip enable input UART7_TXD O MFP4 UART7 data transmitter output pin PC.2 I/O MFP0 General purpose digital I/O pin EBI_DATA2 I/O MFP1 EBI data bus bit 2 NAND_nWP O MFP3 NAND flash write protect input UART7_RXD I MFP4 UART7 data receiver input pin PC.3 I/O MFP0 General purpose digital I/O pin EBI_DATA3 I/O MFP1 EBI data bus bit 3 VCAP0_CLKO O MFP2 Video image interface 0 sensor clock pin NAND_ALE O MFP3 NAND flash address latch enable I2C1_SCL I/O MFP4 I2C1 clock pin UART3_TXD O MFP5 UART3 data transmitter output pin CAN0_RXD I MFP7 CAN0 bus receiver input PC.4 I/O MFP0 General purpose digital I/O pin EBI_DATA4 I/O MFP1 EBI data bus bit 4 VCAP0_PCLK I MFP2 Video image interface 0 pixel clock pin NAND_CLE O MFP3 NAND flash command latch enable I2C1_SDA I/O MFP4 I2C1 data input/output pin I MFP5 UART3 data receiver input pin SPI0_MOSI I/O MFP6 SPI0 MOSI (Master Out, Slave In) pin CAN0_TXD O MFP7 CAN0 bus transmitter outpu VSS P MFP0 Ground pin for digital circuit 47 48 76 77 78 79 UART3_RXD 80 Oct., 02, 2019 Page 31 of 246 NUC980 SERIES DATASHEET VSS 46 20 MFP 73 45 19 Type Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin 21 49 81 PC.5 I/O MFP0 General purpose digital I/O pin EBI_DATA5 I/O MFP1 EBI data bus bit 5 VCAP0_HSYNC I MFP2 Video image interface 0 horizontal sync. Pin NAND_nWE O MFP3 NAND flash write enable SPI0_SS0 I/O MFP5 SPI0 slave select 0 pin SD0_CMD/ I/O MFP6 SD0 command/response pin eMMC0_CMD 22 50 eMMC0 command/response pin UART1_TXD O MFP7 UART1 data transmitter output pin 82 VSS P MFP0 Ground pin for digital circuit 83 PC.6 I/O MFP0 General purpose digital I/O pin EBI_DATA6 I/O MFP1 EBI data bus bit 6 VCAP0_VSYNC I MFP2 Video image interface 0 vertical sync. Pin NAND_nRE O MFP3 NAND flash read enable SC1_RST O MFP4 Smart Card 1 reset pin SPI0_CLK I/O MFP5 SPI0 serial clock pin SD0_CLK/ O MFP6 SD0 clock output pin eMMC0_CLK UART1_RXD NUC980 SERIES DATASHEET 51 84 eMMC0 clock output pin I MFP7 UART1 data receiver input pin PC.7 I/O MFP0 General purpose digital I/O pin EBI_DATA7 I/O MFP1 EBI data bus bit 7 VCAP0_FIELD I MFP2 Video image interface 0 frame sync. Pin NAND_RDY0 I MFP3 NAND flash ready/busy input SC1_CLK O MFP4 Smart Card 1 clock pin SPI0_MOSI I/O MFP5 SPI0 MOSI (Master Out, Slave In) pin SD0_DATA0/ I/O MFP6 SD0 data line bit 0 eMMC0_DATA0 23 52 85 Oct., 02, 2019 eMMC0 data line bit 0 UART1_RTS O MFP7 UART1 request to Send output pin PC.8 I/O MFP0 General purpose digital I/O pin EBI_DATA8 I/O MFP1 EBI data bus bit 8 VCAP0_DATA0 I MFP2 Video image interface 0 data 0 pin NAND_DATA0 I/O MFP3 NAND flash data bus bit 0 SC1_DAT I/O MFP4 Smart Card 1 data pin SPI0_MISO I/O MFP5 SPI0 MISO (Master In, Slave Out) pin Page 32 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin SD0_DATA1/ Type MFP Description I/O MFP6 SD0 data line bit 1 eMMC0_DATA1 24 53 eMMC0 data line bit 1 UART1_CTS I MFP7 UART1 clear to Send input pin 86 VSS P MFP0 Ground pin for digital circuit 87 PC.9 I/O MFP0 General purpose digital I/O pin EBI_DATA9 I/O MFP1 EBI data bus bit 9 VCAP0_DATA1 I MFP2 Video image interface 0 data 1 pin NAND_DATA1 I/O MFP3 NAND flash data bus bit 1 SC1_PWR O MFP4 Smart Card 1 power pin SD0_DATA2/ I/O MFP6 SD0 data line bit 2 eMMC0_DATA2 25 54 eMMC0 data line bit 2 O MFP7 UART4 data transmitter output pin 88 VSS P MFP0 Ground pin for digital circuit 89 PC.10 I/O MFP0 General purpose digital I/O pin EBI_DATA10 I/O MFP1 EBI data bus bit 10 VCAP0_DATA2 I MFP2 Video image interface 0 data 2 pin NAND_DATA2 I/O MFP3 NAND flash data bus bit 2 I MFP4 Smart Card 1 card detect pin I/O MFP6 SD0 data line bit 3 SC1_CD SD0_DATA3/ eMMC0_DATA3 UART4_RXD 26 27 55 56 90 91 Oct., 02, 2019 NUC980 SERIES DATASHEET UART4_TXD eMMC0 data line bit 3 I MFP7 UART4 data receiver input pin PC.11 I/O MFP0 General purpose digital I/O pin EBI_DATA11 I/O MFP1 EBI data bus bit 11 VCAP0_DATA3 I MFP2 Video image interface 0 data 3 pin NAND_DATA3 I/O MFP3 NAND flash data bus bit 3 SC0_RST O MFP4 Smart Card 0 reset pin PC.12 I/O MFP0 General purpose digital I/O pin EBI_DATA12 I/O MFP1 EBI data bus bit 12 VCAP0_DATA4 I MFP2 Video image interface 0 data 4 pin NAND_DATA4 I/O MFP3 NAND flash data bus bit 4 SC0_CLK O MFP4 Smart Card 0 clock pin SD0_nCD I MFP6 SD0 card detect input pin UART8_TXD O MFP7 UART8 data transmitter output pin Page 33 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin 28 57 92 PC.13 I/O MFP0 General purpose digital I/O pin EBI_DATA13 I/O MFP1 EBI data bus bit 13 VCAP0_DATA5 I MFP2 Video image interface 0 data 5 pin NAND_DATA5 I/O MFP3 NAND flash data bus bit 5 SC0_DAT I/O MFP4 Smart Card 0 data pin I MFP7 UART8 data receiver input pin PC.14 I/O MFP0 General purpose digital I/O pin EBI_DATA14 I/O MFP1 EBI data bus bit 14 VCAP0_DATA6 I MFP2 Video image interface 0 data 6 pin NAND_DATA6 I/O MFP3 NAND flash data bus bit 6 SC0_PWR O MFP4 Smart Card 0 power pin SPI0_MOSI I/O MFP5 SPI0 MOSI (Master Out, Slave In) pin UART8_RTS O MFP7 UART8 request to Send output pin PC.15 I/O MFP0 General purpose digital I/O pin EBI_DATA15 I/O MFP1 EBI data bus bit 15 VCAP0_DATA7 I MFP2 Video image interface 0 data 7 pin NAND_DATA7 I/O MFP3 NAND flash date bus bit 7 SC0_CD I MFP4 Smart Card 0 card detect pin UART8_CTS I MFP7 UART8 clear to Send input pin 95 VDD12 P MFP0 Power supply for Internal core power pin 96 VSS P MFP0 Ground pin for digital circuit 97 VSS P MFP0 Ground pin for digital circuit 98 NC - 99 VDD33 P 100 NC - No connect 101 NC - No connect 102 NC - No connect 103 NC - No connect 104 VSS P 105 NC - No connect 106 NC - No connect 107 NC - No connect 108 NC - No connect UART8_RXD 29 30 58 59 NUC980 SERIES DATASHEET 31 32 60 93 94 Oct., 02, 2019 No connect MFP0 MFP0 Power supply for I/O power pin Ground pin for digital circuit Page 34 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin Type MFP Description NC - 110 VSS P MFP0 Ground pin for digital circuit 111 PD.0 I/O MFP0 General purpose digital I/O pin QSPI0_SS1 I/O MFP1 Quad SPI0 slave select 1 pin UART5_TXD O MFP2 UART5 data transmitter output pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin I MFP4 External interrupt 2 input pin PD.1 I/O MFP0 General purpose digital I/O pin SPI0_SS1 I/O MFP1 SPI0 slave select 1 pin I MFP2 UART5 data receiver input pin I/O MFP3 Timer1 external capture input/toggle output pin I MFP4 External interrupt 3 input pin PB.9 I/O MFP0 General purpose digital I/O pin UART3_TXD O MFP1 UART3 data transmitter output pin PWM13 O MFP2 PWM13 counter synchronous trigger output pin TM0_TGL I/O MFP3 Timer0 event counter input/toggle output pin A MFP4 USB 1.1 host lite port 0 differential signal D- SPI1_SS0 I/O MFP5 SPI1 slave select 0 pin PB.10 I/O MFP0 General purpose digital I/O pin UART3_RXD I MFP1 UART3 data receiver input pin PWM12 O MFP2 PWM12 counter synchronous trigger output pin TM0_EXT I/O MFP3 Timer0 external capture input/toggle output pin A MFP4 USB 1.1 host lite port 0 differential signal D+ SPI1_CLK I/O MFP5 SPI1 serial clock pin PB.11 I/O MFP0 General purpose digital I/O pin UART3_RTS O MFP1 UART3 request to Send output pin PWM11 O MFP2 PWM11 counter synchronous trigger output pin TM2_EXT I/O MFP3 Timer2 external capture input/toggle output pin A MFP4 USB 1.1 host lite port 5 differential signal D- SPI1_MOSI I/O MFP5 SPI1 MOSI (Master Out, Slave In) pin PB.12 I/O MFP0 General purpose digital I/O pin UART3_CTS I MFP1 UART3 clear to Send input pin PWM10 O MFP2 PWM10 counter synchronous trigger output pin EINT2 112 UART5_RXD TM1_EXT EINT3 113 USBHL0_DM 114 USBHL0_DP 115 USBHL5_DM 116 Oct., 02, 2019 No connect Page 35 of 246 NUC980 SERIES DATASHEET 109 Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin I/O MFP3 Timer2 event counter input/toggle output pin USBHL5_DP A MFP4 USB 1.1 host lite port 5 differential signal D+ SPI1_MISO I/O MFP5 SPI1 MISO (Master In, Slave Out) pin PD.2 I/O MFP0 General purpose digital I/O pin QSPI0_SS0 I/O MFP1 Quad SPI0 slave select 0 pin.(booting) UART3_TXD O MFP2 UART3 data transmitter output pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin PD.3 I/O MFP0 General purpose digital I/O pin QSPI0_CLK I/O MFP1 Quad SPI0 serial clock pin.(booting) UART3_RXD I MFP2 UART3 data receiver input pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PD.4 I/O MFP0 General purpose digital I/O pin QSPI0_MOSI0 I/O MFP1 Quad SPI0 MOSI0 (Master Out, Slave In) pin. Data 0 of quad mode.(booting) UART3_RTS O MFP2 UART3 request to Send output pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin P MFP0 Ground pin for digital circuit PD.5 I/O MFP0 General purpose digital I/O pin QSPI0_MISO0 I/O MFP1 Quad SPI0 MISO0 (Master In, Slave Out) pin. Data 1 of quad mode.(booting) I MFP2 UART3 clear to Send input pin TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin PD.6 I/O MFP0 General purpose digital I/O pin QSPI0_MOSI1 I/O MFP1 Quad SPI0 MOSI1 (Master Out, Slave In) pin. Data 2 of quad mode.(booting) UART2_TXD O MFP2 UART2 data transmitter output pin TM0_ECNT I/O MFP3 Timer0 event counter input/toggle output pin CAN0_RXD I MFP4 CAN0 bus receiver input PD.7 I/O MFP0 General purpose digital I/O pin QSPI0_MISO1 I/O MFP1 Quad SPI0 MISO1 (Master In, Slave Out) pin. Data 3 of quad mode.(booting) I MFP2 UART2 data receiver input pin TM1_ECNT I/O MFP3 Timer1 event counter input/toggle output pin CAN0_TXD O MFP4 CAN0 bus transmitter output PD.8 I/O MFP0 General purpose digital I/O pin TM2_TGL 33 34 35 61 62 63 117 118 119 64 36 65 VSS 120 NUC980 SERIES DATASHEET UART3_CTS 66 67 121 122 UART2_RXD 68 123 Oct., 02, 2019 Page 36 of 246 Rev 1.11 NUC980 64 128 216 Pin Name MFP Description Pin Pin Pin I/O MFP1 SPI0 slave select 0 pin UART6_CTS I MFP2 UART6 clear to Send input pin TM2_ECNT I/O MFP3 Timer2 event counter input/toggle output pin PD.9 I/O MFP0 General purpose digital I/O pin SPI0_CLK I/O MFP1 SPI0 serial clock pin UART6_RTS O MFP2 UART6 request to Send output pin TM3_ECNT I/O MFP3 Timer3 event counter input/toggle output pin PD.10 I/O MFP0 General purpose digital I/O pin SPI0_MOSI I/O MFP1 SPI0 MOSI (Master Out, Slave In) pin UART6_TXD O MFP2 UART6 data transmitter output pin TM4_ECNT I/O MFP3 Timer4 event counter input/toggle output pin PD.11 I/O MFP0 General purpose digital I/O pin SPI0_MISO I/O MFP1 SPI0 MISO (Master In, Slave Out) pin I MFP2 UART6 data receiver input pin TM5_ECNT I/O MFP3 Timer5 event counter input/toggle output pin PD.12 I/O MFP0 General purpose digital I/O pin UART4_TXD O MFP1 UART4 data transmitter output pin TM2_TGL I/O MFP2 Timer2 event counter input/toggle output pin CAN2_RXD I MFP4 CAN2 bus receiver input PWM00 O MFP6 PWM00 counter synchronous trigger output pin EBI_DATA1 I/O MFP8 EBI data bus bit 1 P MFP0 Ground pin for digital circuit I/O MFP0 General purpose digital I/O pin I MFP1 UART4 data receiver input pin TM2_EXT I/O MFP2 Timer2 external capture input/toggle output pin CAN2_TXD O MFP4 CAN2 bus transmitter output PWM01 O MFP6 PWM01 counter synchronous trigger output pin EBI_DATA2 I/O MFP8 EBI data bus bit 2 PD.14 I/O MFP0 General purpose digital I/O pin UART4_RTS O MFP1 UART4 request to Send output pin TM3_TGL I/O MFP2 Timer3 event counter input/toggle output pin I2C3_SCL I/O MFP3 I2C3 clock pin I MFP4 CAN1 bus receiver input SPI0_SS0 69 70 71 124 125 126 UART6_RXD 72 73 127 128 VSS 129 PD.13 UART4_RXD 74 130 CAN1_RXD Oct., 02, 2019 Page 37 of 246 NUC980 SERIES DATASHEET Type Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 75 131 Type MFP Description USBHL0_DM A MFP5 USB 1.1 host lite port 0 differential signal D- PWM02 O MFP6 PWM02 counter synchronous trigger output pin EBI_DATA3 I/O MFP8 EBI data bus bit 3 PD.15 I/O MFP0 General purpose digital I/O pin I MFP1 UART4 clear to Send input pin TM3_EXT I/O MFP2 Timer3 external capture input/toggle output pin I2C3_SDA I/O MFP3 I2C3 data input/output pin CAN1_TXD O MFP4 CAN1 bus transmitter output USBHL0_DP A MFP5 USB 1.1 host lite port 0 differential signal D+ PWM03 O MFP6 PWM03 counter synchronous trigger output pin EBI_DATA4 I/O MFP8 EBI data bus bit 4 PG.11 I/O MFP0 General purpose digital I/O pin SPI1_SS0 I/O MFP2 SPI1 slave select 0 pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin CAN0_RXD I MFP4 CAN0 bus receiver input UART5_CTS I MFP5 UART5 clear to Send input pin PWM10 O MFP6 PWM10 counter synchronous trigger output pin JTAG0_TDO O MFP7 JTAG0 data output pin PG.12 I/O MFP0 General purpose digital I/O pin SPI1_CLK I/O MFP2 SPI1 serial clock pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin CAN0_TXD O MFP4 CAN0 bus transmitter output UART5_RTS O MFP5 UART5 request to Send output pin PWM11 O MFP6 PWM11 counter synchronous trigger output pin JTAG0_TCK I MFP7 JTAG0 clock input pin PG.13 I/O MFP0 General purpose digital I/O pin SPI1_MOSI I/O MFP2 SPI1 MOSI (Master Out, Slave In) pin CAN1_RXD I MFP4 CAN1 bus receiver input UART5_RXD I MFP5 UART5 data receiver input pin PWM12 O MFP6 PWM12 counter synchronous trigger output pin JTAG0_TMS I MFP7 JTAG0 test mode selection input pin PG.14 I/O MFP0 General purpose digital I/O pin SPI1_MISO I/O MFP2 SPI1 MISO (Master In, Slave Out) pin UART4_CTS 76 NUC980 SERIES DATASHEET 77 78 79 132 133 134 135 Oct., 02, 2019 Page 38 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 80 37 81 Type MFP Description CAN1_TXD O MFP4 CAN1 bus transmitter output UART5_TXD O MFP5 UART5 data transmitter output pin PWM13 O MFP6 PWM13 counter synchronous trigger output pin JTAG0_TDI I MFP7 JTAG0 data input pin PG.15 I/O MFP0 General purpose digital I/O pin SPI0_SS1 I/O MFP1 SPI0 slave select 1 pin SPI1_SS1 I/O MFP2 SPI1 slave select 1 pin EINT3 I MFP4 External interrupt 3 input pin JTAG0_nTRST I MFP7 JTAG0 reset input pin nRESET IU MFP0 External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state WDT_nRST O MFP1 Watch dog timer reset trigger output 138 VDD33 P MFP0 Power supply for I/O power pin 139 VSS P MFP0 Ground pin for digital circuit 140 VSS P MFP0 Ground pin for digital circuit 136 137 82 141 VDD12 P MFP0 Power supply for internal core power pin 39 83 142 MVDD P MFP0 Power supply for Memory ports 143 VSS P MFP0 Ground pin for digital circuit 144 MVDD P MFP0 Power supply for Memory ports 145 VSS P MFP0 Ground pin for digital circuit 146 MVDD P MFP0 Power supply for Memory ports 147 VSS P MFP0 Ground pin for digital circuit 148 MVDD P MFP0 Power supply for Memory ports 149 VSS P MFP0 Ground pin for digital circuit 150 VSS P MFP0 Ground pin for digital circuit 151 VSS P MFP0 Ground pin for digital circuit 84 40 85 152 VDD33 P MFP0 Power supply for I/O power pin 41 86 153 PF.0 I/O MFP0 General purpose digital I/O pin I MFP1 RMII1 Receive Data Error input pin I/O MFP2 SD1 command/response pin RMII1_RXERR SD1_CMD/ eMMC1_CMD Oct., 02, 2019 NUC980 SERIES DATASHEET 38 eMMC1 command/response pin TM0_ECNT I/O MFP3 Timer0 event counter input/toggle output pin SC1_RST O MFP4 Smart Card 1 reset pin Page 39 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 42 87 154 Type MFP Description UART7_CTS I MFP5 UART7 clear to Send input pin USBHL1_DM A MFP6 USB 1.1 host lite port 1 differential signal D- EBI_DATA5 I/O MFP8 EBI data bus bit 5 PF.1 I/O MFP0 General purpose digital I/O pin RMII1_CRSDV I MFP1 RMII1 Carrier Sense/Receive Data input pin SD1_CLK/ O MFP2 SD1 clock output pin eMMC1_CLK 43 88 155 eMMC1 clock output pin TM1_ECNT I/O MFP3 Timer1 event counter input/toggle output pin SC1_CLK O MFP4 Smart Card 1 clock pin UART7_RTS O MFP5 UART7 request to Send output pin USBHL1_DP A MFP6 USB 1.1 host lite port 1 differential signal D+ EBI_DATA6 I/O MFP8 EBI data bus bit 6 PF.2 I/O MFP0 General purpose digital I/O pin RMII1_RXD1 I MFP1 RMII1 Receive Data bus bit 1 SD1_DATA0/ I/O MFP2 SD1 data line bit 0 eMMC1_DATA0 NUC980 SERIES DATASHEET 44 89 156 eMMC1 data line bit 0 TM2_ECNT I/O MFP3 Timer2 event counter input/toggle output pin SC1_DAT I/O MFP4 Smart Card 1 data pin UART7_RXD I MFP5 UART7 data receiver input pin USBHL2_DM A MFP6 USB 1.1 host lite port 2 differential signal D- EBI_DATA7 I/O MFP8 EBI data bus bit 7 PF.3 I/O MFP0 General purpose digital I/O pin RMII1_RXD0 I MFP1 RMII1 Receive Data bus bit 0 SD1_DATA1/ I/O MFP2 SD1 data line bit 1 eMMC1_DATA1 45 90 157 Oct., 02, 2019 eMMC1 data line bit 1 TM3_ECNT I/O MFP3 Timer3 event counter input/toggle output pin SC1_PWR O MFP4 Smart Card 1 power pin UART7_TXD O MFP5 UART7 data transmitter output pin USBHL2_DP A MFP6 USB 1.1 host lite port 2 differential signal D+ EBI_DATA8 I/O MFP8 EBI data bus bit 8 PF.4 I/O MFP0 General purpose digital I/O pin RMII1_REFCLK I MFP1 RMII1 mode clock input pin SD1_DATA2/ eMMC1_DATA2 I/O MFP2 SD1 data line bit 2 Page 40 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin Type MFP Description eMMC1 data line bit 2 TM4_ECNT 46 91 158 I/O MFP3 Timer4 event counter input/toggle output pin SC1_CD I MFP4 Smart Card 1 card detect pin UART3_CTS I MFP5 UART3 clear to Send input pin USBHL3_DM A MFP6 USB 1.1 host lite port 3 differential signal D- EBI_DATA9 I/O MFP8 EBI data bus bit 9 PF.5 I/O MFP0 General purpose digital I/O pin RMII1_TXEN O MFP1 RMII1 Transmit Enable output pin SD1_DATA3/ I/O MFP2 SD1 data line bit 3 eMMC1_DATA3 47 92 48 94 160 TM5_ECNT I/O MFP3 Timer5 event counter input/toggle output pin PWM00 O MFP4 PWM00 counter synchronous trigger output pin UART3_RTS O MFP5 UART3 request to Send output pin USBHL3_DP A MFP6 USB 1.1 host lite port 3 differential signal D+ EBI_DATA10 I/O MFP8 EBI data bus bit 10 PF.6 I/O MFP0 General purpose digital I/O pin RMII1_TXD1 O MFP1 RMII1 Transmit Data bus bit 1 SD1_nCD I MFP2 SD1 card detect input pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin. PWM01 O MFP4 PWM01 counter synchronous trigger output pin UART3_RXD I MFP5 UART3 data receiver input pin USBHL4_DM A MFP6 USB 1.1 host lite port 4 differential signal D- EBI_DATA11 I/O MFP8 EBI data bus bit 11 PB.13 I/O MFP0 General purpose digital I/O pin EINT2 I MFP2 External interrupt 2 input pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PWM02 O MFP4 PWM02 counter synchronous trigger output pin UART3_TXD O MFP5 UART3 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 host lite port 4 differential signal D+ EBI_DATA0 I/O MFP8 EBI data bus bit 0 161 VDD12 P MFP0 Power supply for internal core power pin 162 VDD12 P MFP0 Power supply for internal core power pin 163 VSS P MFP0 Ground pin for digital circuit Oct., 02, 2019 Page 41 of 246 NUC980 SERIES DATASHEET 93 159 eMMC1 data line bit 3 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 95 164 VSS 96 165 49 50 51 97 98 NUC980 SERIES DATASHEET 99 52 100 166 167 Type MFP Description P MFP0 Ground pin for digital circuit PF.7 I/O MFP0 General purpose digital I/O pin RMII1_TXD0 O MFP1 RMII1 Transmit Data bus bit 0 UART1_CTS I MFP2 UART1 clear to Send input pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin PWM02 O MFP4 PWM02 counter synchronous trigger output pin UART3_TXD O MFP5 UART3 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 host lite port 4 differential signal D+ EBI_DATA12 I/O MFP8 EBI data bus bit 12 PF.8 I/O MFP0 General purpose digital I/O pin RMII1_MDIO I/O MFP1 RMII1 PHY Management Data pin UART1_RTS O MFP2 UART1 request to Send output pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin PWM03 O MFP4 PWM03 counter synchronous trigger output pin USBHL5_DM A MFP6 USB 1.1 host lite port 5 differential signal D- EBI_DATA13 I/O MFP8 EBI data bus bit 13 PF.9 I/O MFP0 General purpose digital I/O pin RMII1_MDC O MFP1 RMII1 PHY Management Clock output pin UART1_RXD I MFP2 UART1 data receiver input pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin PWM10 O MFP4 PWM10 counter synchronous trigger output pin USBHL5_DP A MFP6 USB 1.1 host lite port 5 differential signal D+ EBI_DATA14 I/O MFP8 EBI data bus bit 14 168 VDD12 P MFP0 Power supply for internal core power pin 169 PF.10 I/O MFP0 General purpose digital I/O pin UART1_TXD O MFP2 UART1 data transmitter output pin TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin PWM11 O MFP4 PWM11 counter synchronous trigger output pin VCAP1_PCLK I MFP7 Video image interface 1 pixel clock pin EBI_DATA15 I/O MFP8 EBI data bus bit 15 PF.11 I/O MFP0 General purpose digital I/O pin UART0_RXD I MFP1 UART0 data receiver input pin VSS P MFP0 Ground pin for digital circuit 170 171 Oct., 02, 2019 Page 42 of 246 Rev 1.11 NUC980 64 128 216 Pin Name Type MFP Description Pin Pin Pin 53 101 172 PF.12 I/O MFP0 General purpose digital I/O pin UART0_TXD O MFP1 UART0 data transmitter output pin 102 173 VDD33 P MFP0 Power supply for I/O power pin 55 103 174 XT_IN I MFP0 External 12 MHz crystal input pin 56 104 175 XT_OUT O MFP0 External 12 MHz crystal output pin 176 VSS P MFP0 Ground pin for digital circuit 177 PE.0 I/O MFP0 General purpose digital I/O pin RMII0_RXERR I MFP1 RMII0 Receive Data Error input pin CAN0_RXD I MFP2 CAN0 bus receiver input UART4_CTS I MFP5 UART4 clear to Send input pin USBHL1_DM A MFP6 USB 1.1 host lite port 1 differential signal D- VCAP1_HSYNC I MFP7 Video image interface 1 horizontal sync. Pin I/O MFP0 General purpose digital I/O pin RMII0_CRSDV I MFP1 RMII0 Carrier Sense/Receive Data input pin CAN0_TXD O MFP2 CAN0 bus transmitter output UART4_RTS O MFP5 UART4 request to Send output pin USBHL1_DP A MFP6 USB 1.1 host lite port 1 differential signal D+ VCAP1_VSYNC I MFP7 Video image interface 1 vertical sync. Pin I/O MFP0 General purpose digital I/O pin RMII0_RXD1 I MFP1 RMII0 Receive Data bus bit 1 CAN1_RXD I MFP2 CAN1 bus receiver input UART4_RXD I MFP5 UART4 data receiver input pin USBHL2_DM A MFP6 USB 1.1 host lite port 2 differential signal D- VCAP1_DATA0 I MFP7 Video image interface 1 data 0 pin 180 VDD12 P MFP0 Power supply for internal core power pin 181 PE.3 I/O MFP0 General purpose digital I/O pin RMII0_RXD0 I MFP1 RMII0 Receive Data bus bit 0 CAN1_TXD O MFP2 CAN1 bus transmitter output UART4_TXD O MFP5 UART4 data transmitter output pin USBHL2_DP A MFP6 USB 1.1 host lite port 2 differential signal D+ VCAP1_DATA1 I MFP7 Video image interface 1 data 1 pin I/O MFP0 General purpose digital I/O pin I MFP1 RMII0 mode clock input pin 105 106 107 108 109 178 179 182 PE.1 PE.2 PE.4 RMII0_REFCLK Oct., 02, 2019 Page 43 of 246 NUC980 SERIES DATASHEET 54 Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin 110 111 112 NUC980 SERIES DATASHEET 113 114 Type MFP Description CAN2_RXD I MFP2 CAN2 bus receiver input UART9_CTS I MFP5 UART9 clear to Send input pin USBHL3_DM A MFP6 USB 1.1 host lite port 3 differential signal D- VCAP1_DATA2 I MFP7 Video image interface 1 data 2 pin PE.5 I/O MFP0 General purpose digital I/O pin RMII0_TXEN O MFP1 RMII0 Transmit Enable output pin CAN2_TXD O MFP2 CAN2 bus transmitter output UART9_RTS O MFP5 UART9 request to Send output pin USBHL3_DP A MFP6 USB 1.1 host lite port 3 differential signal D+ VCAP1_DATA3 I MFP7 Video image interface 1 data 3 pin PE.6 I/O MFP0 General purpose digital I/O pin RMII0_TXD1 O MFP1 RMII0 Transmit Data bus bit 1 CAN3_RXD I MFP2 CAN3 bus receiver input UART9_RXD I MFP5 UART9 data receiver input pin USBHL4_DM A MFP6 USB 1.1 host lite port 4 differential signal D- VCAP1_DATA4 I MFP7 Video image interface 1 data 4 pin PE.7 I/O MFP0 General purpose digital I/O pin RMII0_TXD0 O MFP1 RMII0 Transmit Data bus bit 0 CAN3_TXD O MFP2 CAN3 bus transmitter output. UART9_TXD O MFP5 UART9 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 host lite port 4 differential signal D+ VCAP1_DATA5 I MFP7 Video image interface 1 data 5 pin 186 VDD33 P MFP0 Power supply for I/O power pin 187 PE.8 I/O MFP0 General purpose digital I/O pin RMII0_MDIO I/O MFP1 RMII0 PHY Management Data pin UART6_RXD I MFP5 UART6 data receiver input pin USBHL5_DM A MFP6 USB 1.1 host lite port 5 differential signal D- VCAP1_DATA6 I MFP7 Video image interface 1 data 6 pin PE.9 I/O MFP0 General purpose digital I/O pin RMII0_MDC O MFP1 RMII0 PHY Management Clock output pin UART6_TXD O MFP5 UART6 data transmitter output pin USBHL5_DP A MFP6 USB 1.1 host lite port 5 differential signal D+ VCAP1_DATA7 I MFP7 Video image interface 1 data 7 pin 183 184 185 188 Oct., 02, 2019 Page 44 of 246 Rev 1.11 NUC980 64 128 216 Pin Name MFP Description Pin Pin Pin 115 189 I/O MFP0 General purpose digital I/O pin USB_OVC I MFP1 HSUSB host bus power over voltage detector CAN3_RXD I MFP2 CAN3 bus receiver input UART9_RXD I MFP3 UART9 data receiver input pin PWM12 O MFP4 PWM12 counter synchronous trigger output pin EINT2 I MFP5 External interrupt 2 input pin I/O MFP6 I2C0 data input/output pin I MFP7 Video image interface 1 frame sync. Pin I/O MFP0 General purpose digital I/O pin I MFP1 USB0 VBUS vaild indication pin PE.12 I/O MFP0 General purpose digital I/O pin USBH_PWREN O MFP1 HSUSB host power control pin CAN3_TXD O MFP2 CAN3 bus transmitter output UART9_TXD O MFP3 UART9 data transmitter output pin PWM13 O MFP4 PWM13 counter synchronous trigger output pin EINT3 I MFP5 External interrupt 3 input pin I2C0_SCL I/O MFP6 I2C0 clock pin VCAP1_CLKO O MFP7 Video image interface sensor 1 clock pin 192 VSS P MFP0 Ground pin for digital circuit 193 VDD12 P MFP0 Power supply for internal core power pin 194 VSS P MFP0 Ground pin for digital circuit 195 VUSB1_VDD12 P MFP0 Power supply for USB1 VDD12 196 VUSB1_VDD12 P MFP0 Power supply for USB1 VDD12 197 VUSB1_VSS P MFP0 Ground pin for USB1 198 NC No connect 199 NC No connect 200 VUSB1_VSS P MFP0 Ground pin for USB1 119 201 USB1_DM A MFP0 USB1 differential signal D- 120 202 USB1_DP A MFP0 USB1 differential signal D+ 121 203 VUSB1_VDD33 P MFP0 Power supply for USB1 VDD33 204 VUSB1_VDD33 P MFP0 Power supply for USB1 VDD33 122 205 USB1_REXT A MFP0 USB1 module reference resister (external 12.1K to GND) 123 206 VUSB0_VDD12 P MFP0 Power supply for USB0 VDD12 PE.10 I2C0_SDA VCAP1_FIELD 57 116 190 PE.11 USB0_VBUSVLD 117 58 59 60 118 191 Oct., 02, 2019 Page 45 of 246 NUC980 SERIES DATASHEET Type Rev 1.11 NUC980 64 128 216 Pin Name Pin Pin Pin Type MFP Description 207 VUSB0_VDD12 P MFP0 Power supply for USB0 VDD12 208 VUSB0_VSS P MFP0 Ground pin for USB0 209 NC No connect 210 NC No connect 211 VUSB0_VSS P MFP0 Ground pin for USB0. 61 124 212 USB0_DM A MFP0 USB0 differential signal D- 62 125 213 USB0_DP A MFP0 USB0 differential signal D+ 63 126 214 VUSB0_VDD33 P MFP0 Power supply for USB0 VDD33 215 VUSB0_VDD33 P MFP0 Power supply for USB0 VDD33 216 USB0_REXT A MFP0 USB0 module reference resister (external 12.1K to GND) VSS P MFP0 Ground pin for digital circuit 64 127 EPAD 128 Note: Pin Type: 1. I = Digital Input; 2. IU= Digital Input with internal pull high; (Rpu value please refer the GPIO Characteristics of DC Electrical Characteristics) 3. O= Digital Output; 4. I/O= Bi-direction; 5. A = Analog; 6. P = Power Pin; 7. AP = Analog Power NUC980 SERIES DATASHEET Oct., 02, 2019 Page 46 of 246 Rev 1.11 NUC980 4.2.2 Group NUC980 Multi-function Summary Table Pin Name GPIO MFP Type Description ADC_AIN0 PB.0 MFP8 A ADC channel 0 analog input ADC_AIN1 PB.1 MFP8 A ADC channel 1 analog input ADC_AIN2 PB.2 MFP8 A ADC channel 2 analog input ADC_AIN3 PB.3 MFP8 A ADC channel 3 analog input ADC_AIN4 PB.4 MFP8 A ADC channel 4 analog input ADC_AIN5 PB.5 MFP8 A ADC channel 5 analog input ADC_AIN6 PB.6 MFP8 A ADC channel 6 analog input ADC_AIN7 PB.7 MFP8 A ADC channel 7 analog input PC.3 MFP7 I PD.6 MFP4 I PG.11 MFP4 I PE.0 MFP2 I PC.4 MFP7 O PD.7 MFP4 O PG.12 MFP4 O PE.1 MFP2 O PA.13 MFP5 I PD.14 MFP4 I PG.13 MFP4 I PE.2 MFP2 I PA.14 MFP5 O PD.15 MFP4 O PG.14 MFP4 O PE.3 MFP2 O PA.15 MFP5 I PB.1 MFP4 I PB.8 MFP3 I PD.12 MFP4 I PE.4 MFP2 I PG.10 MFP5 O PB.3 MFP4 O ADC CAN0_RXD CAN0 bus receiver input CAN0 CAN0_TXD CAN0 bus transmitter output NUC980 SERIES DATASHEET CAN1_RXD CAN1 bus receiver input CAN1 CAN1_TXD CAN2_RXD CAN2 CAN1 bus transmitter output CAN2_TXD Oct., 02, 2019 CAN2 bus receiver input CAN2 bus transmitter output Page 47 of 246 Rev 1.11 NUC980 Group Pin Name CAN3_RXD GPIO MFP Type PC.0 MFP3 O PD.13 MFP4 O PE.5 MFP2 O PA.0 MFP7 I PE.6 MFP2 I PE.10 MFP2 I PA.1 MFP7 O PE.7 MFP2 O PE.12 MFP2 O Description CAN3 bus receiver input CAN3 CAN3_TXD CAN3 bus transmitter output NUC980 SERIES DATASHEET CFG.0 CFG.0_PwrOnSet0 PG.0 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.1 CFG.1_PwrOnSet1 PG.1 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.2 CFG.2_PwrOnSet2 PG.2 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.3 CFG.3_PwrOnSet3 PG.3 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.4 CFG.4_PwrOnSet4 PG.4 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.5 CFG.5_PwrOnSet5 PG.5 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.6 CFG.6_PwrOnSet6 PG.6 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.7 CFG.7_PwrOnSet7 PG.7 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.8 CFG.8_PwrOnSet8 PG.8 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CFG.9 CFG.9_PwrOnSet9 PG.9 - IU System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset. CLK CLK_OUT PG.0 MFP3 O Internal clock selection output pin EBI_ADDR0 PG.0 MFP1 O EBI address bus bit 0 EBI_ADDR1 PG.1 MFP1 O EBI address bus bit 1 PG.2 MFP1 O PB.2 MFP1 O EBI EBI_ADDR2 Oct., 02, 2019 EBI address bus bit 2 Page 48 of 246 Rev 1.11 NUC980 Group Pin Name GPIO MFP Type Description EBI_ADDR3 PG.3 MFP1 O EBI address bus bit 3 EBI_ADDR4 PG.6 MFP1 O EBI address bus bit 4 EBI_ADDR5 PG.7 MFP1 O EBI address bus bit 5 EBI_ADDR6 PG.8 MFP1 O EBI address bus bit 6 EBI_ADDR7 PG.9 MFP1 O EBI address bus bit 7 EBI_ADDR8 PA.12 MFP1 O EBI address bus bit 8 EBI_ADDR9 PA.11 MFP1 O EBI address bus bit 9 EBI_ADDR10 PA.10 MFP1 O EBI address bus bit 10 EBI_ADDR11 PB.8 MFP1 O EBI address bus bit 11 PG.5 MFP1 O PB.0 MFP1 O PA.13 MFP1 O PB.6 MFP1 O PA.14 MFP1 O PB.4 MFP1 O EBI_ADDR15 PB.7 MFP1 O EBI address bus bit 15 EBI_ADDR16 PB.5 MFP1 O EBI address bus bit 16 EBI_ADDR17 PB.1 MFP1 O EBI address bus bit 17 PG.4 MFP1 O PB.3 MFP1 O PA.15 MFP1 O PG.10 MFP1 I/O PC.0 MFP1 I/O PB.13 MFP8 I/O PC.1 MFP1 I/O PD.12 MFP8 I/O PC.2 MFP1 I/O PD.13 MFP8 I/O PC.3 MFP1 I/O PD.14 MFP8 I/O PC.4 MFP1 I/O PD.15 MFP8 I/O PC.5 MFP1 I/O PF.0 MFP8 I/O EBI_ADDR12 EBI address bus bit 12 EBI_ADDR13 EBI address bus bit 13 EBI_ADDR14 EBI address bus bit 14 EBI_ADDR19 EBI_DATA0 EBI address bus bit 18 EBI_DATA1 EBI address bus bit 19 EBI data bus bit 0 EBI data bus bit 1 EBI_DATA2 EBI data bus bit 2 EBI_DATA3 EBI data bus bit 3 EBI_DATA4 EBI data bus bit 4 EBI_DATA5 Oct., 02, 2019 NUC980 SERIES DATASHEET EBI_ADDR18 EBI data bus bit 5 Page 49 of 246 Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PC.6 MFP1 I/O PF.1 MFP8 I/O PC.7 MFP1 I/O PF.2 MFP8 I/O PC.8 MFP1 I/O PF.3 MFP8 I/O PC.9 MFP1 I/O PF.4 MFP8 I/O PC.10 MFP1 I/O PF.5 MFP8 I/O PC.11 MFP1 I/O PF.6 MFP8 I/O PC.12 MFP1 I/O PF.7 MFP8 I/O PC.13 MFP1 I/O PF.8 MFP8 I/O PC.14 MFP1 I/O PF.9 MFP8 I/O PC.15 MFP1 I/O PF.10 MFP8 I/O EBI_MCLK PA.1 MFP2 O EBI external clock output pin EBI_nCS0 PA.9 MFP1 O EBI chip select 0 output pin EBI_nCS1 PA.6 MFP1 O EBI chip select 1 output pin EBI_nCS2 PA.1 MFP1 O EBI chip select 2 output pin EBI_nRE PA.8 MFP1 O EBI read enable output pin EBI_nWE PA.7 MFP1 O EBI write enable output pin PA.0 MFP5 I PA.13 MFP8 I PA.1 MFP5 I PA.14 MFP8 I PB.3 MFP3 I PD.0 MFP4 I PB.13 MFP2 I PE.10 MFP5 I EBI_DATA6 EBI data bus bit 6 EBI_DATA7 EBI data bus bit 7 EBI_DATA8 EBI data bus bit 8 EBI_DATA9 EBI data bus bit 9 EBI_DATA10 EBI data bus bit 10 EBI_DATA11 EBI data bus bit 11 EBI_DATA12 EBI data bus bit 12 EBI_DATA13 EBI data bus bit 13 EBI_DATA14 EBI data bus bit 14 NUC980 SERIES DATASHEET EBI_DATA15 EINT0 EINT1 EINT2 EBI data bus bit 15 EINT0 External interrupt 0 input pin EINT1 External interrupt 1 input pin EINT2 Oct., 02, 2019 Description External interrupt 2 input pin Page 50 of 246 Rev 1.11 NUC980 Group EINT3 Pin Name EINT3 I2C0_SCL GPIO MFP Type PD.1 MFP4 I PG.15 MFP4 I PE.12 MFP5 I PA.1 MFP3 I/O PG.10 MFP2 I/O PE.12 MFP6 I/O PA.0 MFP3 I/O PA.15 MFP2 I/O PE.10 MFP6 I/O PA.14 MFP2 I/O PB.4 MFP2 I/O PC.3 MFP4 I/O PA.13 MFP2 I/O PB.6 MFP2 I/O PC.4 MFP4 I/O PB.5 MFP2 I/O PB.8 MFP2 I/O PB.7 MFP2 I/O PC.0 MFP2 I/O PB.3 MFP2 I/O PD.14 MFP3 I/O PB.1 MFP2 I/O PD.15 MFP3 I/O PA.3 MFP2 O PG.10 MFP8 O PB.4 MFP3 O PA.4 MFP2 I PB.7 MFP3 I PA.5 MFP2 O PB.5 MFP3 O PA.2 MFP2 O PA.15 MFP8 O PB.6 MFP3 O PA.6 MFP2 O Description External interrupt 3 input pin I2C0 clock pin I2C0 I2C0_SDA I2C1_SCL I2C0 data input/output pin I2C1 clock pin I2C1 I2C1_SDA I2C2_SCL I2C1 data input/output pin I2C2 clock pin I2C2 I2C2_SDA I2C2 data input/output pin NUC980 SERIES DATASHEET I2C3_SCL I2C3 clock pin I2C3 I2C3_SDA I2S_BCLK I2C3 data input/output pin I2S_DI I2S I2S_ data input pin I2S_DO I2S_LRCK I2S_MCLK Oct., 02, 2019 I2S_ bit clock output pin I2S_ data output pin Page 51 of 246 I2S_ left right channel clock output pin I2S_ master clock output pin Rev 1.11 NUC980 Group JTAG0 JTAG1 NAND Pin Name NUC980 SERIES DATASHEET GPIO MFP Type PB.1 MFP3 O JTAG0_TCK PG.12 MFP7 I JTAG0 clock input pin JTAG0_TDI PG.14 MFP7 I JTAG0 data input pin JTAG0_TDO PG.11 MFP7 O JTAG0 data output pin JTAG0_TMS PG.13 MFP7 I JTAG0 test mode selection input pin JTAG0_nTRST PG.15 MFP7 I JTAG0 reset input pin JTAG1_TCK PA.3 MFP4 I JTAG1 clock input pin JTAG1_TDI PA.5 MFP4 I JTAG1 data input pin JTAG1_TDO PA.2 MFP4 O JTAG1 data output pin JTAG1_TMS PA.4 MFP4 I JTAG1 test mode selection input pin JTAG1_nTRST PA.6 MFP4 I JTAG1 reset input pin NAND_ALE PC.3 MFP3 O NAND Flash address latch enable NAND_CLE PC.4 MFP3 O NAND Flash command latch enable NAND_DATA0 PC.8 MFP3 I/O NAND Flash data bus bit 0 NAND_DATA1 PC.9 MFP3 I/O NAND Flash data bus bit 1 NAND_DATA2 PC.10 MFP3 I/O NAND Flash data bus bit 2 NAND_DATA3 PC.11 MFP3 I/O NAND Flash data bus bit 3 NAND_DATA4 PC.12 MFP3 I/O NAND Flash data bus bit 4 NAND_DATA5 PC.13 MFP3 I/O NAND Flash data bus bit 5 NAND_DATA6 PC.14 MFP3 I/O NAND Flash data bus bit 6 NAND_DATA7 PC.15 MFP3 I/O NAND Flash data bus bit 7 NAND_RDY0 PC.7 MFP3 I NAND Flash ready/busy pin NAND_nCS0 PC.1 MFP3 O NAND Flash chip enable input NAND_nRE PC.6 MFP3 O NAND Flash read enable NAND_nWE PC.5 MFP3 O NAND Flash write enable NAND_nWP PC.2 MFP3 O NAND Flash write protect input. PG.10 MFP7 O PG.0 MFP6 O PD.12 MFP6 O PF.5 MFP4 O PA.15 MFP7 O PG.1 MFP6 O PD.13 MFP6 O PF.6 MFP4 O PWM00 Description PWM00 counter synchronous trigger output pin PWM0 PWM01 Oct., 02, 2019 PWM01 counter synchronous trigger output pin Page 52 of 246 Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PA.14 MFP7 O PG.2 MFP6 O PD.14 MFP6 O PB.13 MFP4 O PF.7 MFP4 O PA.13 MFP7 O PG.3 MFP6 O PD.15 MFP6 O PF.8 MFP4 O PG.6 MFP6 O PB.12 MFP2 O PG.11 MFP6 O PF.9 MFP4 O PG.7 MFP6 O PB.11 MFP2 O PG.12 MFP6 O PF.10 MFP4 O PG.8 MFP6 O PB.10 MFP2 O PG.13 MFP6 O PE.10 MFP4 O PG.9 MFP6 O PB.9 MFP2 O PG.14 MFP6 O PE.12 MFP4 O QSPI0_CLK PD.3 MFP1 I/O Quad SPI0 serial clock pin QSPI0_MISO0 PD.5 MFP1 I/O Quad SPI0 MISO0 (Master In, Slave Out) pin QSPI0_MISO1 PD.7 MFP1 I/O Quad SPI0 MISO1 (Master In, Slave Out) pin QSPI0_MOSI0 PD.4 MFP1 I/O Quad SPI0 MOSI0 (Master Out, Slave In) pin QSPI0_MOSI1 PD.6 MFP1 I/O Quad SPI0 MOSI1 (Master Out, Slave In) pin QSPI0_SS0 PD.2 MFP1 I/O Quad SPI0 slave select 0 pin PA.0 MFP1 I/O PD.0 MFP1 I/O PE.1 MFP1 I PWM02 PWM03 Description PWM02 counter synchronous trigger output pin PWM03 counter synchronous trigger output pin PWM10 PWM10 counter synchronous trigger output pin PWM11 PWM11 counter synchronous trigger output pin PWM1 PWM12 counter synchronous trigger output pin PWM13 PWM13 counter synchronous trigger output pin QSPI0 QSPI0_SS1 RMII0 RMII0_CRSDV Oct., 02, 2019 Quad SPI0 slave select 1 pin Page 53 of 246 RMII0 Carrier Sense/Receive Data input pin Rev 1.11 NUC980 SERIES DATASHEET PWM12 NUC980 Group Pin Name GPIO MFP Type Description RMII0_MDC PE.9 MFP1 O RMII0 PHY Management Clock output pin RMII0_MDIO PE.8 MFP1 I/O RMII0 PHY Management Data pin RMII0_REFCLK PE.4 MFP1 I RMII0 mode clock input pin RMII0_RXD0 PE.3 MFP1 I RMII0 Receive Data bus bit 0 RMII0_RXD1 PE.2 MFP1 I RMII0 Receive Data bus bit 1 RMII0_RXERR PE.0 MFP1 I RMII0 Receive Data Error input pin RMII0_TXD0 PE.7 MFP1 O RMII0 Transmit Data bus bit 0 RMII0_TXD1 PE.6 MFP1 O RMII0 Transmit Data bus bit 1 RMII0_TXEN PE.5 MFP1 O RMII0 Transmit Enable output pin RMII1_CRSDV PF.1 MFP1 I RMII1 Carrier Sense/Receive Data input pin RMII1_MDC PF.9 MFP1 O RMII1 PHY Management Clock output pin RMII1_MDIO PF.8 MFP1 I/O RMII1 PHY Management Data pin RMII1_REFCLK PF.4 MFP1 I RMII1 mode clock input pin RMII1_RXD0 PF.3 MFP1 I RMII1 Receive Data bus bit 0 RMII1_RXD1 PF.2 MFP1 I RMII1 Receive Data bus bit 1 RMII1_RXERR PF.0 MFP1 I RMII1 Receive Data Error input pin RMII1_TXD0 PF.7 MFP1 O RMII1 Transmit Data bus bit 0 RMII1_TXD1 PF.6 MFP1 O RMII1 Transmit Data bus bit 1 RMII1_TXEN PF.5 MFP1 O RMII1 Transmit Enable output pin PA.2 MFP3 I PC.15 MFP4 I PA.5 MFP3 O PC.12 MFP4 O PA.4 MFP3 I/O PC.13 MFP4 I/O PA.3 MFP3 O PC.14 MFP4 O PA.6 MFP3 O PC.11 MFP4 O PC.10 MFP4 I PF.4 MFP4 I PC.7 MFP4 O PF.1 MFP4 O PC.8 MFP4 I/O RMII1 NUC980 SERIES DATASHEET SC0_CD Smart Card 0 card detect pin SC0_CLK SC0 Smart Card 0 clock pin SC0_DAT Smart Card 0 data pin SC0_PWR Smart Card 0 power pin SC0_RST Smart Card 0 reset pin SC1_CD SC1 Smart Card 1 card detect pin SC1_CLK SC1_DAT Oct., 02, 2019 Smart Card 1 clock pin Page 54 of 246 Smart Card 1 data pin Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PF.2 MFP4 I/O PC.9 MFP4 O PF.3 MFP4 O PC.6 MFP4 O PF.0 MFP4 O SD0_CLK PC.6 MFP6 O SD0 clock output pin SD0_CMD PC.5 MFP6 I/O SD0 command/response pin SD0_DATA0 PC.7 MFP6 I/O SD0 data line bit 0 SD0_DATA1 PC.8 MFP6 I/O SD0 data line bit 1 SD0_DATA2 PC.9 MFP6 I/O SD0 data line bit 2 SD0_DATA3 PC.10 MFP6 I/O SD0 data line bit 3 PB.8 MFP6 I PC.12 MFP6 I SD1_CLK PF.1 MFP2 O SD1 clock output pin SD1_CMD PF.0 MFP2 I/O SD1 command/response pin SD1_DATA0 PF.2 MFP2 I/O SD1 data line bit 0 SD1_DATA1 PF.3 MFP2 I/O SD1 data line bit 1 SD1_DATA2 PF.4 MFP2 I/O SD1 data line bit 2 SD1_DATA3 PF.5 MFP2 I/O SD1 data line bit 3 SD1_nCD PF.6 MFP2 I SD1 card detect input pin PC.6 MFP5 I/O PD.9 MFP1 I/O PC.8 MFP5 I/O PD.11 MFP1 I/O PC.4 MFP6 I/O PC.7 MFP5 I/O PC.14 MFP5 I/O PD.10 MFP1 I/O PC.5 MFP5 I/O PD.8 MFP1 I/O PB.3 MFP6 I/O PC.0 MFP5 I/O PD.1 MFP1 I/O PG.15 MFP1 I/O SC1_PWR Description Smart Card 1 power pin SC1_RST Smart Card 1 reset pin SD0 SD0_nCD SD1 SD0 card detect input pin NUC980 SERIES DATASHEET SPI0_CLK SPI0 serial clock pin SPI0_MISO SPI0 MISO (Master In, Slave Out) pin SPI0_MOSI SPI0 MOSI (Master Out, Slave In) pin SPI0 SPI0_SS0 SPI0 slave select 0 pin SPI0_SS1 Oct., 02, 2019 SPI0 slave select 1 pin Page 55 of 246 Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PG.10 MFP6 I/O PB.4 MFP6 I/O PB.10 MFP5 I/O PG.12 MFP2 I/O PB.5 MFP6 I/O PB.12 MFP5 I/O PG.14 MFP2 I/O PB.7 MFP6 I/O PB.11 MFP5 I/O PG.13 MFP2 I/O PA.15 MFP6 I/O PB.6 MFP6 I/O PB.9 MFP5 I/O PG.11 MFP2 I/O PB.1 MFP6 I/O PG.15 MFP2 I/O PB.1 MFP5 I/O PB.8 MFP7 I/O PB.10 MFP3 I/O PA.0 MFP6 I/O PD.6 MFP3 I/O PF.0 MFP3 I/O PB.3 MFP5 I/O PC.0 MFP7 I/O PB.9 MFP3 I/O PA.13 MFP3 I/O PD.1 MFP3 I/O PG.12 MFP3 I/O PF.9 MFP3 I/O PA.1 MFP6 I/O PD.7 MFP3 I/O PF.1 MFP3 I/O PA.14 MFP3 I/O PD.0 MFP3 I/O SPI1_CLK SPI1_MISO Description SPI1 serial clock pin SPI1 MISO (Master In, Slave Out) pin SPI1 SPI1_MOSI SPI1_SS0 SPI1 slave select 0 pin SPI1_SS1 TM0_EXT NUC980 SERIES DATASHEET TM0 TM0_ECNT TM0_TGL SPI1 slave select 1 pin TM1_EXT TM1 TM1_ECNT Timer0 external capture input/toggle output pin Timer0 event counter input/toggle output pin Timer0 event counter input/toggle output pin Timer1 external capture input/toggle output pin TM1_TGL Oct., 02, 2019 SPI1 MOSI (Master Out, Slave In) pin Timer1 event counter input/toggle output pin Timer1 event counter input/toggle output pin Page 56 of 246 Rev 1.11 NUC980 Group Pin Name TM2_EXT TM2 TM2_ECNT TM2_TGL GPIO MFP Type PG.11 MFP3 I/O PF.8 MFP3 I/O PA.9 MFP3 I/O PB.11 MFP3 I/O PD.13 MFP2 I/O PA.2 MFP6 I/O PD.8 MFP3 I/O PF.2 MFP3 I/O PA.10 MFP3 I/O PB.12 MFP3 I/O PD.12 MFP2 I/O PA.7 MFP3 I/O PD.15 MFP2 I/O PA.3 MFP6 I/O PD.9 MFP3 I/O PF.3 MFP3 I/O PA.8 MFP3 I/O PD.14 MFP2 I/O PA.11 MFP3 I/O PD.2 MFP3 I/O PF.6 MFP3 I/O PA.4 MFP6 I/O PD.10 MFP3 I/O PF.4 MFP3 I/O PA.12 MFP3 I/O PD.3 MFP3 I/O PB.13 MFP3 I/O PA.15 MFP3 I/O PD.4 MFP3 I/O PF.7 MFP3 I/O PA.5 MFP6 I/O PD.11 MFP3 I/O PF.5 MFP3 I/O PG.10 MFP3 I/O TM3_EXT TM3 TM3_ECNT TM4_ECNT TM4_TGL TM5_EXT TM5 TM5_ECNT TM5_TGL Oct., 02, 2019 Timer2 event counter input/toggle output pin Timer2 event counter input/toggle output pin Timer3 event counter input/toggle output pin Timer3 event counter input/toggle output pin Page 57 of 246 Timer4 external capture input/toggle output pin Timer4 event counter input/toggle output pin Timer4 event counter input/toggle output pin Timer5 external capture input/toggle output pin Timer5 event counter input/toggle output pin Timer5 event counter input/toggle output pin Rev 1.11 NUC980 SERIES DATASHEET TM4 Timer2 external capture input/toggle output pin Timer3 external capture input/toggle output pin TM3_TGL TM4_EXT Description NUC980 Group Pin Name GPIO MFP Type Description PD.5 MFP3 I/O PF.10 MFP3 I/O UART0_RXD PF.11 MFP1 I UART0 data receiver input pin UART0_TXD PF.12 MFP1 O UART0 data transmitter output pin PC.8 MFP7 I PF.7 MFP2 I PC.7 MFP7 O PF.8 MFP2 O PA.0 MFP4 I PC.6 MFP7 I PF.9 MFP2 I PA.1 MFP4 O PC.5 MFP7 O PF.10 MFP2 O PA.7 MFP2 I PG.2 MFP2 I PB.0 MFP2 I PA.8 MFP2 O PG.3 MFP2 O PA.9 MFP2 I PG.0 MFP2 I PD.7 MFP2 I PA.10 MFP2 O PG.1 MFP2 O PD.6 MFP2 O PB.12 MFP1 I PD.5 MFP2 I PF.4 MFP5 I PB.11 MFP1 O PD.4 MFP2 O PF.5 MFP5 O PC.4 MFP5 I PB.10 MFP1 I PD.3 MFP2 I UART0 UART1_CTS UART1 clear to Send input pin UART1_RTS UART1 request to Send output pin UART1 UART1_RXD UART1_TXD UART2_CTS UART2_RTS NUC980 SERIES DATASHEET UART2 UART2_RXD UART2_TXD UART3_CTS UART3 UART3_RTS UART3_RXD Oct., 02, 2019 UART1 data receiver input pin UART1 data transmitter output pin UART2 clear to Send input pin UART2 request to Send output pin Page 58 of 246 UART2 data receiver input pin UART2 data transmitter output pin UART3 clear to Send input pin UART3 request to Send output pin UART3 data receiver input pin Rev 1.11 NUC980 Group Pin Name UART3_TXD GPIO MFP Type PF.6 MFP5 I PC.3 MFP5 O PB.9 MFP1 O PD.2 MFP2 O PB.13 MFP5 O PF.7 MFP5 O PD.15 MFP1 I PE.0 MFP5 I PD.14 MFP1 O PE.1 MFP5 O PC.10 MFP7 I PD.13 MFP1 I PE.2 MFP5 I PC.9 MFP7 O PD.12 MFP1 O PE.3 MFP5 O PG.4 MFP2 I PG.11 MFP5 I PG.5 MFP2 O PG.12 MFP5 O PG.6 MFP2 I PD.1 MFP2 I PG.13 MFP5 I PG.7 MFP2 O PD.0 MFP2 O PG.14 MFP5 O PA.2 MFP1 I PD.8 MFP2 I PA.3 MFP1 O PD.9 MFP2 O PA.4 MFP1 I PD.11 MFP2 I PE.8 MFP5 I PA.5 MFP1 O UART4_CTS Description UART3 data transmitter output pin UART4 clear to Send input pin UART4_RTS UART4 request to Send output pin UART4 UART4_RXD UART4_TXD UART5_CTS UART4 data receiver input pin UART4 data transmitter output pin UART5 clear to Send input pin UART5 request to Send output pin NUC980 SERIES DATASHEET UART5_RTS UART5 UART5_RXD UART5_TXD UART6_CTS UART5 data receiver input pin UART5 data transmitter output pin UART6 clear to Send input pin UART6_RTS UART6 request to Send output pin UART6 UART6_RXD UART6_TXD Oct., 02, 2019 Page 59 of 246 UART6 data receiver input pin UART6 data transmitter output pin Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PD.10 MFP2 O PE.9 MFP5 O PB.7 MFP5 I PF.0 MFP5 I PB.5 MFP5 O PF.1 MFP5 O PA.14 MFP6 I PB.4 MFP5 I PC.2 MFP4 I PF.2 MFP5 I PA.13 MFP6 O PB.6 MFP5 O PC.1 MFP4 O PF.3 MFP5 O PG.9 MFP2 I PC.15 MFP7 I PG.8 MFP2 O PC.14 MFP7 O PA.11 MFP2 I PC.0 MFP4 I PC.13 MFP7 I PA.12 MFP2 O PB.8 MFP4 O PC.12 MFP7 O PE.4 MFP5 I PB.2 MFP7 O PE.5 MFP5 O PB.3 MFP7 I PE.6 MFP5 I PE.10 MFP3 I PB.1 MFP7 O PE.7 MFP5 O PE.12 MFP3 O PE.11 MFP1 I UART7_CTS UART7 clear to Send input pin UART7_RTS UART7 Description UART7 request to Send output pin UART7_RXD UART7 data receiver input pin UART7_TXD UART7 data transmitter output pin UART8_CTS UART8 clear to Send input pin UART8_RTS UART8 request to Send output pin NUC980 SERIES DATASHEET UART8 UART8_RXD UART8_TXD UART9_CTS UART9_RTS UART9 UART9_RXD UART9_TXD USB0 USB0_VBUSVLD Oct., 02, 2019 UART8 data receiver input pin UART8 data transmitter output pin UART9 clear to Send input pin UART9 request to Send output pin Page 60 of 246 UART9 data receiver input pin UART9 data transmitter output pin USB0 VBUS vaild indication pin Rev 1.11 NUC980 Group Pin Name GPIO MFP Type PB.6 MFP4 A PB.7 MFP4 A PB.9 MFP4 A PD.14 MFP5 A PB.4 MFP4 A PB.5 MFP4 A PB.10 MFP4 A PD.15 MFP5 A PF.0 MFP6 A PE.0 MFP6 A PF.1 MFP6 A PE.1 MFP6 A PF.2 MFP6 A PE.2 MFP6 A PF.3 MFP6 A PE.3 MFP6 A PF.4 MFP6 A PE.4 MFP6 A PF.5 MFP6 A PE.5 MFP6 A PA.15 MFP4 A PF.6 MFP6 A PE.6 MFP6 A PG.10 MFP4 A PB.13 MFP6 A PF.7 MFP6 A PE.7 MFP6 A PA.13 MFP4 A PB.11 MFP4 A PF.8 MFP6 A PE.8 MFP6 A PA.14 MFP4 A PB.12 MFP4 A PF.9 MFP6 A USBHL0_DM Description USB 1.1 Host Lite port 0 differential signal D- USBHL0 USBHL0_DP USB 1.1 Host Lite port 0 differential signal D+ USBHL1_DM USB 1.1 Host Lite port 1 differential signal D- USBHL1 USBHL1_DP USB 1.1 Host Lite port 1 differential signal D+ USBHL2_DM USB 1.1 Host Lite port 2 differential signal D- USBHL2 USBHL2_DP USB 1.1 Host Lite port 2 differential signal D+ USBHL3_DM USB 1.1 Host Lite port 3 differential signal D- USBHL3 USBHL4_DM USBHL4 USB 1.1 Host Lite port 3 differential signal D+ USBHL4_DP USB 1.1 Host Lite port 4 differential signal D+ USBHL5_DM USBHL5 USBHL5_DP Oct., 02, 2019 USB 1.1 Host Lite port 4 differential signal D- USB 1.1 Host Lite port 5 differential signal D- Page 61 of 246 USB 1.1 Host Lite port 5 differential signal D+ Rev 1.11 NUC980 SERIES DATASHEET USBHL3_DP NUC980 Group Pin Name GPIO MFP Type PE.9 MFP6 A Description USBH USBH_PWREN PE.12 MFP1 O HSUSB host power control pin USB USB_OVC PE.10 MFP1 I USB host bus power over voltage detector VCAP0_CLKO PC.3 MFP2 O Video image interface 0 sensor clock pin VCAP0_DATA0 PC.8 MFP2 I Video image interface 0 data 0 pin VCAP0_DATA1 PC.9 MFP2 I Video image interface 0 data 1 pin VCAP0_DATA2 PC.10 MFP2 I Video image interface 0 data 2 pin VCAP0_DATA3 PC.11 MFP2 I Video image interface 0 data 3 pin VCAP0_DATA4 PC.12 MFP2 I Video image interface 0 data 4 pin VCAP0_DATA5 PC.13 MFP2 I Video image interface 0 data 5 pin VCAP0_DATA6 PC.14 MFP2 I Video image interface 0 data 6 pin VCAP0_DATA7 PC.15 MFP2 I Video image interface 0 data 7 pin VCAP0_FIELD PC.7 MFP2 I Video image interface 0 frame sync. Pin VCAP0_HSYNC PC.5 MFP2 I Video image interface 0 horizontal sync. Pin VCAP0_PCLK PC.4 MFP2 I Video image interface 0 pixel clock pin VCAP0_VSYNC PC.6 MFP2 I Video image interface 0 vertical sync. Pin VCAP1_CLKO PE.12 MFP7 O Video image interface 1 sensor clock pin VCAP1_DATA0 PE.2 MFP7 I Video image interface 1 data 0 pin VCAP1_DATA1 PE.3 MFP7 I Video image interface 1 data 1 pin VCAP1_DATA2 PE.4 MFP7 I Video image interface 1 data 2 pin VCAP1_DATA3 PE.5 MFP7 I Video image interface 1 data 3 pin VCAP1_DATA4 PE.6 MFP7 I Video image interface 1 data 4 pin VCAP1_DATA5 PE.7 MFP7 I Video image interface 1 data 5 pin VCAP1_DATA6 PE.8 MFP7 I Video image interface 1 data 6 pin VCAP1_DATA7 PE.9 MFP7 I Video image interface 1 data 7 pin VCAP1_FIELD PE.10 MFP7 I Video image interface 1 frame sync. Pin VCAP1_HSYNC PE.0 MFP7 I Video image interface 1 horizontal sync. Pin VCAP1_PCLK PF.10 MFP7 I Video image interface 1 pixel clock pin VCAP1_VSYNC PE.1 MFP7 I Video image interface 1 vertical sync. Pin WDT_nRST nRESET MFP1 O Watch dog timer reset trigger output eMMC0_CLK PC.6 MFP6 O eMMC0 clock output pin eMMC0_CMD PC.5 MFP6 I/O eMMC0 command/response pin eMMC0_DATA0 PC.7 MFP6 I/O eMMC0 data line bit 0 eMMC0_DATA1 PC.8 MFP6 I/O eMMC0 data line bit 1 VCAP0 NUC980 SERIES DATASHEET VCAP1 WDT eMMC0 Oct., 02, 2019 Page 62 of 246 Rev 1.11 NUC980 Group Pin Name GPIO MFP Type Description eMMC0_DATA2 PC.9 MFP6 I/O eMMC0 data line bit 2 eMMC0_DATA3 PC.10 MFP6 I/O eMMC0 data line bit 3 eMMC1_CLK PF.1 MFP2 O eMMC1 clock output pin eMMC1_CMD PF.0 MFP2 I/O eMMC1 command/response pin eMMC1_DATA0 PF.2 MFP2 I/O eMMC1 data line bit 0 eMMC1_DATA1 PF.3 MFP2 I/O eMMC1 data line bit 1 eMMC1_DATA2 PF.4 MFP2 I/O eMMC1 data line bit 2 eMMC1_DATA3 PF.5 MFP2 I/O eMMC1 data line bit 3 eMMC1 NUC980 SERIES DATASHEET Oct., 02, 2019 Page 63 of 246 Rev 1.11 NUC980 4.2.3 PA.0 NUC980 Multi-function Summary Table Sorted by GPIO Pin Name Type MFP Description PA.0 I/O MFP0 General purpose digital I/O pin QSPI0_SS1 I/O MFP1 Quad SPI0 slave select 1 pin I2C0_SDA I/O MFP3 I2C0 data input/output pin UART1_RXD I MFP4 UART1 data receiver input pin EINT0 I MFP5 External interrupt 0 input pin TM0_ECNT I/O MFP6 Timer0 event counter input/toggle output pin CAN3_RXD I MFP7 CAN3 bus receiver input PA.1 I/O MFP0 General purpose digital I/O pin EBI_nCS2 O MFP1 EBI chip select 2 output pin EBI_MCLK O MFP2 EBI external clock output pin I2C0_SCL I/O MFP3 I2C0 clock pin UART1_TXD O MFP4 UART1 data transmitter output pin EINT1 I MFP5 External interrupt 1 input pin TM1_ECNT I/O MFP6 Timer1 event counter input/toggle output pin CAN3_TXD O MFP7 CAN3 bus transmitter output PA.2 I/O MFP0 General purpose digital I/O pin UART6_CTS I MFP1 UART6 clear to Send input pin I2S_LRCK O MFP2 I2S_ left right channel clock output pin SC0_CD I MFP3 Smart Card 0 card detect pin JTAG1_TDO O MFP4 JTAG1 data output pin TM2_ECNT I/O MFP6 Timer2 event counter input/toggle output pin PA.3 I/O MFP0 General purpose digital I/O pin UART6_RTS O MFP1 UART6 request to Send output pin I2S_BCLK O MFP2 I2S_ bit clock output pin SC0_PWR O MFP3 Smart Card 0 power pin JTAG1_TCK I MFP4 JTAG1 clock input pin TM3_ECNT I/O MFP6 Timer3 event counter input/toggle output pin PA.4 I/O MFP0 General purpose digital I/O pin UART6_RXD I MFP1 UART6 data receiver input pin I2S_DI I MFP2 I2S_ data input pin SC0_DAT I/O MFP3 Smart Card 0 data pin JTAG1_TMS I MFP4 JTAG1 test mode selection input pin PA.1 NUC980 SERIES DATASHEET PA.2 PA.3 PA.4 Oct., 02, 2019 Page 64 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description TM4_ECNT I/O MFP6 Timer4 event counter input/toggle output pin PA.5 I/O MFP0 General purpose digital I/O pin UART6_TXD O MFP1 UART6 data transmitter output pin I2S_DO O MFP2 I2S_ data output pin SC0_CLK O MFP3 Smart Card 0 clock pin JTAG1_TDI I MFP4 JTAG1 data input pin TM5_ECNT I/O MFP6 Timer5 event counter input/toggle output pin PA.6 I/O MFP0 General purpose digital I/O pin EBI_nCS1 O MFP1 EBI chip select 1 output pin I2S_MCLK O MFP2 I2S_ master clock output pin SC0_RST O MFP3 Smart Card 0 reset pin JTAG1_nTRST I MFP4 JTAG1 reset input pin PA.7 I/O MFP0 General purpose digital I/O pin EBI_nWE O MFP1 EBI write enable output pin UART2_CTS I MFP2 UART2 clear to Send input pin TM3_EXT I/O MFP3 Timer3 external capture input/toggle output pin PA.8 I/O MFP0 General purpose digital I/O pin EBI_nRE O MFP1 EBI read enable output pin UART2_RTS O MFP2 UART2 request to Send output pin TM3_TGL I/O MFP3 Timer3 event counter input/toggle output pin PA.9 I/O MFP0 General purpose digital I/O pin EBI_nCS0 O MFP1 EBI chip select 0 output pin UART2_RXD I MFP2 UART2 data receiver input pin TM2_EXT I/O MFP3 Timer2 external capture input/toggle output pin PA.10 I/O MFP0 General purpose digital I/O pin EBI_ADDR10 O MFP1 EBI address bus bit 10 UART2_TXD O MFP2 UART2 data transmitter output pin TM2_TGL I/O MFP3 Timer2 event counter input/toggle output pin PA.11 I/O MFP0 General purpose digital I/O pin EBI_ADDR9 O MFP1 EBI address bus bit 9 UART8_RXD I MFP2 UART8 data receiver input pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin PA.12 I/O MFP0 General purpose digital I/O pin EBI_ADDR8 O MFP1 EBI address bus bit 8 PA.5 PA.6 PA.7 PA.8 NUC980 SERIES DATASHEET PA.9 PA.10 PA.11 PA.12 Oct., 02, 2019 Page 65 of 246 Rev 1.11 NUC980 PA.13 PA.14 NUC980 SERIES DATASHEET PA.15 Pin Name Type MFP Description UART8_TXD O MFP2 UART8 data transmitter output pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PA.13 I/O MFP0 General purpose digital I/O pin EBI_ADDR13 O MFP1 EBI address bus bit 13 I2C1_SDA I/O MFP2 I2C1 data input/output pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin USBHL5_DM A MFP4 USB 1.1 Host Lite port 5 differential signal D- CAN1_RXD I MFP5 CAN1 bus receiver input UART7_TXD O MFP6 UART7 data transmitter output pin PWM03 O MFP7 PWM03 counter synchronous trigger output pin EINT0 I MFP8 External interrupt 0 input pin PA.14 I/O MFP0 General purpose digital I/O pin EBI_ADDR14 O MFP1 EBI address bus bit 14 I2C1_SCL I/O MFP2 I2C1 clock pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin USBHL5_DP A MFP4 USB 1.1 Host Lite port 5 differential signal D+ CAN1_TXD O MFP5 CAN1 bus transmitter output UART7_RXD I MFP6 UART7 data receiver input pin PWM02 O MFP7 PWM02 counter synchronous trigger output pin EINT1 I MFP8 External interrupt 1 input pin PA.15 I/O MFP0 General purpose digital I/O pin EBI_ADDR19 O MFP1 EBI address bus bit 19 I2C0_SDA I/O MFP2 I2C0 data input/output pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin USBHL4_DM A MFP4 USB 1.1 Host Lite port 4 differential signal D- CAN2_RXD I MFP5 CAN2 bus receiver input SPI1_SS0 I/O MFP6 SPI1 slave select 0 pin PWM01 O MFP7 PWM01 counter synchronous trigger output pin I2S_LRCK O MFP8 I2S_ left right channel clock output pin PB.0 I/O MFP0 General purpose digital I/O pin EBI_ADDR12 O MFP1 EBI address bus bit 12 UART2_CTS I MFP2 UART2 clear to Send input pin ADC_AIN0 A MFP8 ADC channel 0 analog input PB.1 I/O MFP0 General purpose digital I/O pin PB.0 PB.1 Oct., 02, 2019 Page 66 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description EBI_ADDR17 O MFP1 EBI address bus bit 17 I2C3_SDA I/O MFP2 I2C3 data input/output pin I2S_MCLK O MFP3 I2S_ master clock output pin CAN2_RXD I MFP4 CAN2 bus receiver input TM0_EXT I/O MFP5 Timer0 external capture input/toggle output pin SPI1_SS1 I/O MFP6 SPI1 slave select 1 pin UART9_TXD O MFP7 UART9 data transmitter output pin ADC_AIN1 A MFP8 ADC channel 1 analog input PB.2 I/O MFP0 General purpose digital I/O pin EBI_ADDR2 O MFP1 EBI address bus bit 2 UART9_RTS O MFP7 UART9 request to Send output pin ADC_AIN2 A MFP8 ADC channel 2 analog input PB.3 I/O MFP0 General purpose digital I/O pin EBI_ADDR18 O MFP1 EBI address bus bit 18 I2C3_SCL I/O MFP2 I2C3 clock pin EINT2 I MFP3 External interrupt 2 input pin CAN2_TXD O MFP4 CAN2 bus transmitter output TM0_TGL I/O MFP5 Timer0 event counter input/toggle output pin SPI0_SS1 I/O MFP6 SPI0 slave select 1 pin UART9_RXD I MFP7 UART9 data receiver input pin ADC_AIN3 A MFP8 ADC channel 3 analog input PB.4 I/O MFP0 General purpose digital I/O pin EBI_ADDR14 O MFP1 EBI address bus bit 14 I2C1_SCL I/O MFP2 I2C1 clock pin I2S_BCLK O MFP3 I2S_ bit clock output pin USBHL0_DP A MFP4 USB 1.1 Host Lite port 0 differential signal D+ UART7_RXD I MFP5 UART7 data receiver input pin SPI1_CLK I/O MFP6 SPI1 serial clock pin ADC_AIN4 A MFP8 ADC channel 4 analog input PB.5 I/O MFP0 General purpose digital I/O pin EBI_ADDR16 O MFP1 EBI address bus bit 16 I2C2_SCL I/O MFP2 I2C2 clock pin I2S_DO O MFP3 I2S_ data output pin USBHL0_DP A MFP4 USB 1.1 Host Lite port 0 differential signal D+ PB.2 PB.3 NUC980 SERIES DATASHEET PB.4 PB.5 Oct., 02, 2019 Page 67 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description UART7_RTS O MFP5 UART7 request to Send output pin SPI1_MISO I/O MFP6 SPI1 MISO (Master In, Slave Out) pin ADC_AIN5 A MFP8 ADC channel 5 analog input PB.6 I/O MFP0 General purpose digital I/O pin EBI_ADDR13 O MFP1 EBI address bus bit 13 I2C1_SDA I/O MFP2 I2C1 data input/output pin I2S_LRCK O MFP3 I2S_ left right channel clock output pin USBHL0_DM A MFP4 USB 1.1 Host Lite port 0 differential signal D- UART7_TXD O MFP5 UART7 data transmitter output pin SPI1_SS0 I/O MFP6 SPI1 slave select 0 pin ADC_AIN6 A MFP8 ADC channel 6 analog input PB.7 I/O MFP0 General purpose digital I/O pin EBI_ADDR15 O MFP1 EBI address bus bit 15 I2C2_SDA I/O MFP2 I2C2 data input/output pin I2S_DI I MFP3 I2S_ data input pin USBHL0_DM A MFP4 USB 1.1 Host Lite port 0 differential signal D- UART7_CTS I MFP5 UART7 clear to Send input pin SPI1_MOSI I/O MFP6 SPI1 MOSI (Master Out, Slave In) pin ADC_AIN7 A MFP8 ADC channel 7 analog input PB.8 I/O MFP0 General purpose digital I/O pin EBI_ADDR11 O MFP1 EBI address bus bit 11 I2C2_SCL I/O MFP2 I2C2 clock pin CAN2_RXD I MFP3 CAN2 bus receiver input UART8_TXD O MFP4 UART8 data transmitter output pin SD0_nCD I MFP6 SD0 card detect input pin TM0_EXT I/O MFP7 Timer0 external capture input/toggle output pin PB.9 I/O MFP0 General purpose digital I/O pin UART3_TXD O MFP1 UART3 data transmitter output pin PWM13 O MFP2 PWM13 counter synchronous trigger output pin TM0_TGL I/O MFP3 Timer0 event counter input/toggle output pin USBHL0_DM A MFP4 USB 1.1 Host Lite port 0 differential signal D- SPI1_SS0 I/O MFP5 SPI1 slave select 0 pin PB.10 I/O MFP0 General purpose digital I/O pin UART3_RXD I MFP1 UART3 data receiver input pin PB.6 PB.7 NUC980 SERIES DATASHEET PB.8 PB.9 PB.10 Oct., 02, 2019 Page 68 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description PWM12 O MFP2 PWM12 counter synchronous trigger output pin TM0_EXT I/O MFP3 Timer0 external capture input/toggle output pin USBHL0_DP A MFP4 USB 1.1 Host Lite port 0 differential signal D+ SPI1_CLK I/O MFP5 SPI1 serial clock pin PB.11 I/O MFP0 General purpose digital I/O pin UART3_RTS O MFP1 UART3 request to Send output pin PWM11 O MFP2 PWM11 counter synchronous trigger output pin TM2_EXT I/O MFP3 Timer2 external capture input/toggle output pin USBHL5_DM A MFP4 USB 1.1 Host Lite port 5 differential signal D- SPI1_MOSI I/O MFP5 SPI1 MOSI (Master Out, Slave In) pin PB.12 I/O MFP0 General purpose digital I/O pin UART3_CTS I MFP1 UART3 clear to Send input pin PWM10 O MFP2 PWM10 counter synchronous trigger output pin TM2_TGL I/O MFP3 Timer2 event counter input/toggle output pin USBHL5_DP A MFP4 USB 1.1 Host Lite port 5 differential signal D+ SPI1_MISO I/O MFP5 SPI1 MISO (Master In, Slave Out) pin PB.13 I/O MFP0 General purpose digital I/O pin EINT2 I MFP2 External interrupt 2 input pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PWM02 O MFP4 PWM02 counter synchronous trigger output pin UART3_TXD O MFP5 UART3 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 Host Lite port 4 differential signal D+ EBI_DATA0 I/O MFP8 EBI data bus bit 0 PC.0 I/O MFP0 General purpose digital I/O pin EBI_DATA0 I/O MFP1 EBI data bus bit 0 I2C2_SDA I/O MFP2 I2C2 data input/output pin CAN2_TXD O MFP3 CAN2 bus transmitter output UART8_RXD I MFP4 UART8 data receiver input pin SPI0_SS1 I/O MFP5 SPI0 slave select 1 pin TM0_TGL I/O MFP7 Timer0 event counter input/toggle output pin PC.1 I/O MFP0 General purpose digital I/O pin EBI_DATA1 I/O MFP1 EBI data bus bit 1 NAND_nCS0 O MFP3 NAND Flash chip enable input UART7_TXD O MFP4 UART7 data transmitter output pin PB.11 PB.12 PC.0 NUC980 SERIES DATASHEET PB.13 PC.1 Oct., 02, 2019 Page 69 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description PC.2 I/O MFP0 General purpose digital I/O pin EBI_DATA2 I/O MFP1 EBI data bus bit 2 NAND_nWP O MFP3 NAND Flash write protect input UART7_RXD I MFP4 UART7 data receiver input pin PC.3 I/O MFP0 General purpose digital I/O pin EBI_DATA3 I/O MFP1 EBI data bus bit 3 VCAP0_CLKO O MFP2 Video image interface 0 sensor clock pin NAND_ALE O MFP3 NAND Flash address latch enable I2C1_SCL I/O MFP4 I2C1 clock pin UART3_TXD O MFP5 UART3 data transmitter output pin CAN0_RXD I MFP7 CAN0 bus receiver input PC.4 I/O MFP0 General purpose digital I/O pin EBI_DATA4 I/O MFP1 EBI data bus bit 4 VCAP0_PCLK I MFP2 Video image interface 0 pixel clock pin NAND_CLE O MFP3 NAND Flash command latch enable I2C1_SDA I/O MFP4 I2C1 data input/output pin UART3_RXD I MFP5 UART3 data receiver input pin SPI0_MOSI I/O MFP6 SPI0 MOSI (Master Out, Slave In) pin CAN0_TXD O MFP7 CAN0 bus transmitter output PC.5 I/O MFP0 General purpose digital I/O pin EBI_DATA5 I/O MFP1 EBI data bus bit 5 VCAP0_HSYNC I MFP2 Video image interface 0 horizontal sync. Pin NAND_nWE O MFP3 NAND Flash write enable SPI0_SS0 I/O MFP5 SPI0 slave select 0 pin SD0_CMD/eMMC0_CMD I/O MFP6 SD0 command/response pin PC.2 PC.3 PC.4 NUC980 SERIES DATASHEET PC.5 eMMC0 command/response pin PC.6 UART1_TXD O MFP7 UART1 data transmitter output pin PC.6 I/O MFP0 General purpose digital I/O pin EBI_DATA6 I/O MFP1 EBI data bus bit 6 VCAP0_VSYNC I MFP2 Video image interface 0 vertical sync. Pin NAND_nRE O MFP3 NAND Flash read enable SC1_RST O MFP4 Smart Card 1 reset pin SPI0_CLK I/O MFP5 SPI0 serial clock pin SD0_CLK/eMMC0_CLK O MFP6 SD0 clock output pin Oct., 02, 2019 Page 70 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description eMMC0 clock output pin PC.7 PC.8 UART1_RXD I MFP7 UART1 data receiver input pin PC.7 I/O MFP0 General purpose digital I/O pin EBI_DATA7 I/O MFP1 EBI data bus bit 7 VCAP0_FIELD I MFP2 Video image interface 0 frame sync. Pin NAND_RDY0 I MFP3 NAND Flash ready/busy pin SC1_CLK O MFP4 Smart Card 1 clock pin SPI0_MOSI I/O MFP5 SPI0 MOSI (Master Out, Slave In) pin SD0_DATA0/eMMC0_DATA I/O 0 MFP6 SD0 data line bit 0 UART1_RTS O MFP7 UART1 request to Send output pin PC.8 I/O MFP0 General purpose digital I/O pin EBI_DATA8 I/O MFP1 EBI data bus bit 8 VCAP0_DATA0 I MFP2 Video image interface 0 data 0 pin NAND_DATA0 I/O MFP3 NAND Flash data bus bit 0 SC1_DAT I/O MFP4 Smart Card 1 data pin SPI0_MISO I/O MFP5 SPI0 MISO (Master In, Slave Out) pin SD0_DATA1/eMMC0_DATA I/O 1 MFP6 SD0 data line bit 1 UART1_CTS I MFP7 UART1 clear to Send input pin PC.9 I/O MFP0 General purpose digital I/O pin EBI_DATA9 I/O MFP1 EBI data bus bit 9 VCAP0_DATA1 I MFP2 Video image interface 0 data 1 pin NAND_DATA1 I/O MFP3 NAND Flash data bus bit 1 SC1_PWR O MFP4 Smart Card 1 power pin SD0_DATA2/eMMC0_DATA I/O 2 MFP6 SD0 data line bit 2 UART4_TXD O MFP7 UART4 data transmitter output pin PC.10 I/O MFP0 General purpose digital I/O pin EBI_DATA10 I/O MFP1 EBI data bus bit 10 VCAP0_DATA2 I MFP2 Video image interface 0 data 2 pin NAND_DATA2 I/O MFP3 NAND Flash data bus bit 2 SC1_CD I MFP4 Smart Card 1 card detect pin MFP6 SD0 data line bit 3 eMMC0 data line bit 0 eMMC0 data line bit 1 NUC980 SERIES DATASHEET PC.9 PC.10 SD0_DATA3/eMMC0_DATA I/O 3 Oct., 02, 2019 eMMC0 data line bit 2 Page 71 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description eMMC0 data line bit 3 PC.11 PC.12 UART4_RXD I MFP7 UART4 data receiver input pin PC.11 I/O MFP0 General purpose digital I/O pin EBI_DATA11 I/O MFP1 EBI data bus bit 11 VCAP0_DATA3 I MFP2 Video image interface 0 data 3 pin NAND_DATA3 I/O MFP3 NAND Flash data bus bit 3 SC0_RST O MFP4 Smart Card 0 reset pin PC.12 I/O MFP0 General purpose digital I/O pin EBI_DATA12 I/O MFP1 EBI data bus bit 12 VCAP0_DATA4 I MFP2 Video image interface 0 data 4 pin NAND_DATA4 I/O MFP3 NAND Flash data bus bit 4 SC0_CLK O MFP4 Smart Card 0 clock pin SD0_nCD I MFP6 SD0 card detect input pin UART8_TXD O MFP7 UART8 data transmitter output pin PC.13 I/O MFP0 General purpose digital I/O pin EBI_DATA13 I/O MFP1 EBI data bus bit 13 VCAP0_DATA5 I MFP2 Video image interface 0 data 5 pin NAND_DATA5 I/O MFP3 NAND Flash data bus bit 5 SC0_DAT I/O MFP4 Smart Card 0 data pin UART8_RXD I MFP7 UART8 data receiver input pin PC.14 I/O MFP0 General purpose digital I/O pin EBI_DATA14 I/O MFP1 EBI data bus bit 14 VCAP0_DATA6 I MFP2 Video image interface 0 data 6 pin NAND_DATA6 I/O MFP3 NAND Flash data bus bit 6 SC0_PWR O MFP4 Smart Card 0 power pin SPI0_MOSI I/O MFP5 SPI0 MOSI (Master Out, Slave In) pin UART8_RTS O MFP7 UART8 request to Send output pin PC.15 I/O MFP0 General purpose digital I/O pin EBI_DATA15 I/O MFP1 EBI data bus bit 15 VCAP0_DATA7 I MFP2 Video image interface 0 data 7 pin NAND_DATA7 I/O MFP3 NAND Flash data bus bit 7 SC0_CD I MFP4 Smart Card 0 card detect pin UART8_CTS I MFP7 UART8 clear to Send input pin PD.0 I/O MFP0 General purpose digital I/O pin PC.13 NUC980 SERIES DATASHEET PC.14 PC.15 PD.0 Oct., 02, 2019 Page 72 of 246 Rev 1.11 NUC980 PD.1 Pin Name Type MFP Description QSPI0_SS1 I/O MFP1 Quad SPI0 slave select 1 pin UART5_TXD O MFP2 UART5 data transmitter output pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin EINT2 I MFP4 External interrupt 2 input pin PD.1 I/O MFP0 General purpose digital I/O pin SPI0_SS1 I/O MFP1 SPI0 slave select 1 pin UART5_RXD I MFP2 UART5 data receiver input pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin EINT3 I MFP4 External interrupt 3 input pin PD.2 I/O MFP0 General purpose digital I/O pin QSPI0_SS0 I/O MFP1 Quad SPI0 slave select 0 pin UART3_TXD O MFP2 UART3 data transmitter output pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin PD.3 I/O MFP0 General purpose digital I/O pin QSPI0_CLK I/O MFP1 Quad SPI0 serial clock pin UART3_RXD I MFP2 UART3 data receiver input pin TM4_TGL I/O MFP3 Timer4 event counter input/toggle output pin PD.4 I/O MFP0 General purpose digital I/O pin QSPI0_MOSI0 I/O MFP1 Quad SPI0 MOSI0 (Master Out, Slave In) pin UART3_RTS O MFP2 UART3 request to Send output pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin PD.5 I/O MFP0 General purpose digital I/O pin QSPI0_MISO0 I/O MFP1 Quad SPI0 MISO0 (Master In, Slave Out) pin UART3_CTS I MFP2 UART3 clear to Send input pin TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin PD.6 I/O MFP0 General purpose digital I/O pin QSPI0_MOSI1 I/O MFP1 Quad SPI0 MOSI1 (Master Out, Slave In) pin UART2_TXD O MFP2 UART2 data transmitter output pin TM0_ECNT I/O MFP3 Timer0 event counter input/toggle output pin CAN0_RXD I MFP4 CAN0 bus receiver input PD.7 I/O MFP0 General purpose digital I/O pin QSPI0_MISO1 I/O MFP1 Quad SPI0 MISO1 (Master In, Slave Out) pin UART2_RXD I MFP2 UART2 data receiver input pin TM1_ECNT I/O MFP3 Timer1 event counter input/toggle output pin PD.2 PD.3 NUC980 SERIES DATASHEET PD.4 PD.5 PD.6 PD.7 Oct., 02, 2019 Page 73 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description CAN0_TXD O MFP4 CAN0 bus transmitter output PD.8 I/O MFP0 General purpose digital I/O pin SPI0_SS0 I/O MFP1 SPI0 slave select 0 pin UART6_CTS I MFP2 UART6 clear to Send input pin TM2_ECNT I/O MFP3 Timer2 event counter input/toggle output pin PD.9 I/O MFP0 General purpose digital I/O pin SPI0_CLK I/O MFP1 SPI0 serial clock pin UART6_RTS O MFP2 UART6 request to Send output pin TM3_ECNT I/O MFP3 Timer3 event counter input/toggle output pin PD.10 I/O MFP0 General purpose digital I/O pin SPI0_MOSI I/O MFP1 SPI0 MOSI (Master Out, Slave In) pin UART6_TXD O MFP2 UART6 data transmitter output pin TM4_ECNT I/O MFP3 Timer4 event counter input/toggle output pin PD.11 I/O MFP0 General purpose digital I/O pin SPI0_MISO I/O MFP1 SPI0 MISO (Master In, Slave Out) pin UART6_RXD I MFP2 UART6 data receiver input pin TM5_ECNT I/O MFP3 Timer5 event counter input/toggle output pin PD.12 I/O MFP0 General purpose digital I/O pin UART4_TXD O MFP1 UART4 data transmitter output pin TM2_TGL I/O MFP2 Timer2 event counter input/toggle output pin CAN2_RXD I MFP4 CAN2 bus receiver input PWM00 O MFP6 PWM00 counter synchronous trigger output pin EBI_DATA1 I/O MFP8 EBI data bus bit 1 PD.13 I/O MFP0 General purpose digital I/O pin UART4_RXD I MFP1 UART4 data receiver input pin TM2_EXT I/O MFP2 Timer2 external capture input/toggle output pin CAN2_TXD O MFP4 CAN2 bus transmitter output PWM01 O MFP6 PWM01 counter synchronous trigger output pin EBI_DATA2 I/O MFP8 EBI data bus bit 2 PD.14 I/O MFP0 General purpose digital I/O pin UART4_RTS O MFP1 UART4 request to Send output pin TM3_TGL I/O MFP2 Timer3 event counter input/toggle output pin I2C3_SCL I/O MFP3 I2C3 clock pin CAN1_RXD I MFP4 CAN1 bus receiver input PD.8 PD.9 PD.10 PD.11 NUC980 SERIES DATASHEET PD.12 PD.13 PD.14 Oct., 02, 2019 Page 74 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description USBHL0_DM A MFP5 USB 1.1 Host Lite port 0 differential signal D- PWM02 O MFP6 PWM02 counter synchronous trigger output pin EBI_DATA3 I/O MFP8 EBI data bus bit 3 PD.15 I/O MFP0 General purpose digital I/O pin UART4_CTS I MFP1 UART4 clear to Send input pin TM3_EXT I/O MFP2 Timer3 external capture input/toggle output pin I2C3_SDA I/O MFP3 I2C3 data input/output pin CAN1_TXD O MFP4 CAN1 bus transmitter output USBHL0_DP A MFP5 USB 1.1 Host Lite port 0 differential signal D+ PWM03 O MFP6 PWM03 counter synchronous trigger output pin EBI_DATA4 I/O MFP8 EBI data bus bit 4 PE.0 I/O MFP0 General purpose digital I/O pin RMII0_RXERR I MFP1 RMII0 Receive Data Error input pin CAN0_RXD I MFP2 CAN0 bus receiver input UART4_CTS I MFP5 UART4 clear to Send input pin USBHL1_DM A MFP6 USB 1.1 Host Lite port 1 differential signal D- VCAP1_HSYNC I MFP7 Video image interface 1 horizontal sync. Pin PE.1 I/O MFP0 General purpose digital I/O pin RMII0_CRSDV I MFP1 RMII0 Carrier Sense/Receive Data input pin CAN0_TXD O MFP2 CAN0 bus transmitter output UART4_RTS O MFP5 UART4 request to Send output pin USBHL1_DP A MFP6 USB 1.1 Host Lite port 1 differential signal D+ VCAP1_VSYNC I MFP7 Video image interface 1 vertical sync. Pin PE.2 I/O MFP0 General purpose digital I/O pin RMII0_RXD1 I MFP1 RMII0 Receive Data bus bit 1 CAN1_RXD I MFP2 CAN1 bus receiver input UART4_RXD I MFP5 UART4 data receiver input pin USBHL2_DM A MFP6 USB 1.1 Host Lite port 2 differential signal D- VCAP1_DATA0 I MFP7 Video image interface 1 data 0 pin PE.3 I/O MFP0 General purpose digital I/O pin RMII0_RXD0 I MFP1 RMII0 Receive Data bus bit 0 CAN1_TXD O MFP2 CAN1 bus transmitter output UART4_TXD O MFP5 UART4 data transmitter output pin USBHL2_DP A MFP6 USB 1.1 Host Lite port 2 differential signal D+ PD.15 PE.0 NUC980 SERIES DATASHEET PE.1 PE.2 PE.3 Oct., 02, 2019 Page 75 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description VCAP1_DATA1 I MFP7 Video image interface 1 data 1 pin PE.4 I/O MFP0 General purpose digital I/O pin RMII0_REFCLK I MFP1 RMII0 mode clock input pin CAN2_RXD I MFP2 CAN2 bus receiver input UART9_CTS I MFP5 UART9 clear to Send input pin USBHL3_DM A MFP6 USB 1.1 Host Lite port 3 differential signal D- VCAP1_DATA2 I MFP7 Video image interface 1 data 2 pin PE.5 I/O MFP0 General purpose digital I/O pin RMII0_TXEN O MFP1 RMII0 Transmit Enable output pin CAN2_TXD O MFP2 CAN2 bus transmitter output UART9_RTS O MFP5 UART9 request to Send output pin USBHL3_DP A MFP6 USB 1.1 Host Lite port 3 differential signal D+ VCAP1_DATA3 I MFP7 Video image interface 1 data 3 pin PE.6 I/O MFP0 General purpose digital I/O pin RMII0_TXD1 O MFP1 RMII0 Transmit Data bus bit 1 CAN3_RXD I MFP2 CAN3 bus receiver input UART9_RXD I MFP5 UART9 data receiver input pin USBHL4_DM A MFP6 USB 1.1 Host Lite port 4 differential signal D- VCAP1_DATA4 I MFP7 Video image interface 1 data 4 pin PE.7 I/O MFP0 General purpose digital I/O pin RMII0_TXD0 O MFP1 RMII0 Transmit Data bus bit 0 CAN3_TXD O MFP2 CAN3 bus transmitter output UART9_TXD O MFP5 UART9 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 Host Lite port 4 differential signal D+ VCAP1_DATA5 I MFP7 Video image interface 1 data 5 pin PE.8 I/O MFP0 General purpose digital I/O pin RMII0_MDIO I/O MFP1 RMII0 PHY Management Data pin UART6_RXD I MFP5 UART6 data receiver input pin USBHL5_DM A MFP6 USB 1.1 Host Lite port 5 differential signal D- VCAP1_DATA6 I MFP7 Video image interface 1 data 6 pin PE.9 I/O MFP0 General purpose digital I/O pin RMII0_MDC O MFP1 RMII0 PHY Management Clock output pin UART6_TXD O MFP5 UART6 data transmitter output pin USBHL5_DP A MFP6 USB 1.1 Host Lite port 5 differential signal D+ PE.4 PE.5 PE.6 NUC980 SERIES DATASHEET PE.7 PE.8 PE.9 Oct., 02, 2019 Page 76 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description VCAP1_DATA7 1 MFP7 Video image interface 1 ata 7 pin PE.10 I/O MFP0 General purpose digital I/O pin USB_OVC I MFP1 USB host bus power over voltage detector CAN3_RXD I MFP2 CAN3 bus receiver input UART9_RXD I MFP3 UART9 data receiver input pin PWM12 O MFP4 PWM12 counter synchronous trigger output pin EINT2 I MFP5 External interrupt 2 input pin I2C0_SDA I/O MFP6 I2C0 data input/output pin VCAP1_FIELD I MFP7 Video image interface 1 frame sync. Pin PE.11 I/O MFP0 General purpose digital I/O pin USB0_VBUSVLD I MFP1 USB0 VBUS vaild indication pin PE.12 I/O MFP0 General purpose digital I/O pin USBH_PWREN O MFP1 HSUSB host power control pin CAN3_TXD O MFP2 CAN3 bus transmitter output UART9_TXD O MFP3 UART9 data transmitter output pin PWM13 O MFP4 PWM13 counter synchronous trigger output pin EINT3 I MFP5 External interrupt 3 input pin I2C0_SCL I/O MFP6 I2C0 clock pin VCAP1_CLKO O MFP7 Video image interface 1 sensor clock pin PF.0 I/O MFP0 General purpose digital I/O pin RMII1_RXERR I MFP1 RMII1 Receive Data Error input pin SD1_CMD/eMMC1_CMD I/O MFP2 SD1 command/response pin PE.10 PE.11 PE.12 NUC980 SERIES DATASHEET eMMC1 command/response pin PF.0 TM0_ECNT I/O MFP3 Timer0 event counter input/toggle output pin SC1_RST O MFP4 Smart Card 1 reset pin UART7_CTS I MFP5 UART7 clear to Send input pin USBHL1_DM A MFP6 USB 1.1 Host Lite port 1 differential signal D- EBI_DATA5 I/O MFP8 EBI data bus bit 5 PF.1 I/O MFP0 General purpose digital I/O pin RMII1_CRSDV I MFP1 RMII1 Carrier Sense/Receive Data input pin SD1_CLK/eMMC1_CLK O MFP2 SD1 clock output pin PF.1 eMMC1 clock output pin TM1_ECNT I/O MFP3 Timer1 event counter input/toggle output pin SC1_CLK O MFP4 Smart Card 1 clock pin Oct., 02, 2019 Page 77 of 246 Rev 1.11 NUC980 PF.2 PF.3 NUC980 SERIES DATASHEET PF.4 Pin Name Type MFP Description UART7_RTS O MFP5 UART7 request to Send output pin USBHL1_DP A MFP6 USB 1.1 Host Lite port 1 differential signal D+ EBI_DATA6 I/O MFP8 EBI data bus bit 6 PF.2 I/O MFP0 General purpose digital I/O pin RMII1_RXD1 I MFP1 RMII1 Receive Data bus bit 1 SD1_DATA0/eMMC1_DATA I/O 0 MFP2 SD1 data line bit 0 TM2_ECNT I/O MFP3 Timer2 event counter input/toggle output pin SC1_DAT I/O MFP4 Smart Card 1 data pin UART7_RXD I MFP5 UART7 data receiver input pin USBHL2_DM A MFP6 USB 1.1 Host Lite port 2 differential signal D- EBI_DATA7 I/O MFP8 EBI data bus bit 7 PF.3 I/O MFP0 General purpose digital I/O pin RMII1_RXD0 I MFP1 RMII1 Receive Data bus bit 0 SD1_DATA1/eMMC1_DATA I/O 1 MFP2 SD1 data line bit 1 TM3_ECNT I/O MFP3 Timer3 event counter input/toggle output pin SC1_PWR O MFP4 Smart Card 1 power pin UART7_TXD O MFP5 UART7 data transmitter output pin USBHL2_DP A MFP6 USB 1.1 Host Lite port 2 differential signal D+ EBI_DATA8 I/O MFP8 EBI data bus bit 8 PF.4 I/O MFP0 General purpose digital I/O pin RMII1_REFCLK I MFP1 RMII1 mode clock input pin SD1_DATA2/eMMC1_DATA I/O 2 MFP2 SD1 data line bit 2 TM4_ECNT I/O MFP3 Timer4 event counter input/toggle output pin SC1_CD I MFP4 Smart Card 1 card detect pin UART3_CTS I MFP5 UART3 clear to Send input pin USBHL3_DM A MFP6 USB 1.1 Host Lite port 3 differential signal D- EBI_DATA9 I/O MFP8 EBI data bus bit 9 PF.5 I/O MFP0 General purpose digital I/O pin RMII1_TXEN O MFP1 RMII1 Transmit Enable output pin MFP2 SD1 data line bit 3 eMMC1 data line bit 0 eMMC1 data line bit 1 eMMC1 data line bit 2 PF.5 SD1_DATA3/eMMC1_DATA I/O 3 Oct., 02, 2019 eMMC1 data line bit 3 Page 78 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description TM5_ECNT I/O MFP3 Timer5 event counter input/toggle output pin PWM00 O MFP4 PWM00 counter synchronous trigger output pin UART3_RTS O MFP5 UART3 request to Send output pin USBHL3_DP A MFP6 USB 1.1 Host Lite port 3 differential signal D+ EBI_DATA10 I/O MFP8 EBI data bus bit 10 PF.6 I/O MFP0 General purpose digital I/O pin RMII1_TXD1 O MFP1 RMII1 Transmit Data bus bit 1 SD1_nCD I MFP2 SD1 card detect input pin TM4_EXT I/O MFP3 Timer4 external capture input/toggle output pin PWM01 O MFP4 PWM01 counter synchronous trigger output pin UART3_RXD I MFP5 UART3 data receiver input pin USBHL4_DM A MFP6 USB 1.1 Host Lite port 4 differential signal D- EBI_DATA11 I/O MFP8 EBI data bus bit 11 PF.7 I/O MFP0 General purpose digital I/O pin RMII1_TXD0 O MFP1 RMII1 Transmit Data bus bit 0 UART1_CTS I MFP2 UART1 clear to Send input pin TM5_EXT I/O MFP3 Timer5 external capture input/toggle output pin PWM02 O MFP4 PWM02 counter synchronous trigger output pin UART3_TXD O MFP5 UART3 data transmitter output pin USBHL4_DP A MFP6 USB 1.1 Host Lite port 4 differential signal D+ EBI_DATA12 I/O MFP8 EBI data bus bit 12 PF.8 I/O MFP0 General purpose digital I/O pin RMII1_MDIO I/O MFP1 RMII1 PHY Management Data pin UART1_RTS O MFP2 UART1 request to Send output pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin PWM03 O MFP4 PWM03 counter synchronous trigger output pin USBHL5_DM A MFP6 USB 1.1 Host Lite port 5 differential signal D- EBI_DATA13 I/O MFP8 EBI data bus bit 13 PF.9 I/O MFP0 General purpose digital I/O pin RMII1_MDC O MFP1 RMII1 PHY Management Clock output pin UART1_RXD I MFP2 UART1 data receiver input pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin PWM10 O MFP4 PWM10 counter synchronous trigger output pin USBHL5_DP A MFP6 USB 1.1 Host Lite port 5 differential signal D+ PF.6 PF.7 NUC980 SERIES DATASHEET PF.8 PF.9 Oct., 02, 2019 Page 79 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description EBI_DATA14 I/O MFP8 EBI data bus bit 14 PF.10 I/O MFP0 General purpose digital I/O pin UART1_TXD O MFP2 UART1 data transmitter output pin TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin PWM11 O MFP4 PWM11 counter synchronous trigger output pin VCAP1_PCLK I MFP7 Video image interface 1 pixel clock pin EBI_DATA15 I/O MFP8 EBI data bus bit 15 PF.11 I/O MFP0 General purpose digital I/O pin UART0_RXD I MFP1 UART0 data receiver input pin PF.12 I/O MFP0 General purpose digital I/O pin UART0_TXD O MFP1 UART0 data transmitter output pin PG.0 I/O MFP0 General purpose digital I/O pin EBI_ADDR0 O MFP1 EBI address bus bit 0 UART2_RXD I MFP2 UART2 data receiver input pin CLK_OUT O MFP3 Internal clock selection output pin PWM00 O MFP6 PWM00 counter synchronous trigger output pin CFG.0_PwrOnSet0 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.1 I/O MFP0 General purpose digital I/O pin EBI_ADDR1 O MFP1 EBI address bus bit 1 UART2_TXD O MFP2 UART2 data transmitter output pin PWM01 O MFP6 PWM01 counter synchronous trigger output pin CFG.1_PwrOnSet1 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.2 I/O MFP0 General purpose digital I/O pin EBI_ADDR2 O MFP1 EBI address bus bit 2 UART2_CTS I MFP2 UART2 clear to Send input pin PWM02 O MFP6 PWM02 counter synchronous trigger output pin CFG.2_PwrOnSet2 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.3 I/O MFP0 General purpose digital I/O pin EBI_ADDR3 O MFP1 EBI address bus bit 3 UART2_RTS O MFP2 UART2 request to Send output pin PWM03 O MFP6 PWM03 counter synchronous trigger output pin CFG.3_PwrOnSet3 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PF.10 PF.11 PF.12 PG.0 NUC980 SERIES DATASHEET PG.1 PG.2 PG.3 Oct., 02, 2019 Page 80 of 246 Rev 1.11 NUC980 PG.4 PG.5 PG.6 PG.7 PG.9 PG.10 Type MFP Description PG.4 I/O MFP0 General purpose digital I/O pin EBI_ADDR18 O MFP1 EBI address bus bit 18 UART5_CTS I MFP2 UART5 clear to Send input pin CFG.4_PwrOnSet4 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.5 I/O MFP0 General purpose digital I/O pin EBI_ADDR12 O MFP1 EBI address bus bit 12 UART5_RTS O MFP2 UART5 request to Send output pin CFG.5_PwrOnSet5 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.6 I/O MFP0 General purpose digital I/O pin EBI_ADDR4 O MFP1 EBI address bus bit 4 UART5_RXD I MFP2 UART5 data receiver input pin PWM10 O MFP6 PWM10 counter synchronous trigger output pin CFG.6_PwrOnSet6 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.7 I/O MFP0 General purpose digital I/O pin EBI_ADDR5 O MFP1 EBI address bus bit 5 UART5_TXD O MFP2 UART5 data transmitter output pin PWM11 O MFP6 PWM11 counter synchronous trigger output pin CFG.7_PwrOnSet7 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.8 I/O MFP0 General purpose digital I/O pin EBI_ADDR6 O MFP1 EBI address bus bit 6 UART8_RTS O MFP2 UART8 request to Send output pin PWM12 O MFP6 PWM12 counter synchronous trigger output pin CFG.8_PwrOnSet8 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.9 I/O MFP0 General purpose digital I/O pin EBI_ADDR7 O MFP1 EBI address bus bit 7 UART8_CTS I MFP2 UART8 clear to Send input pin PWM13 O MFP6 PWM13 counter synchronous trigger output pin CFG.9_PwrOnSet9 IU - System configuration and power on setting with an internal pull-up. Internal pull-up only active automatically during reset PG.10 I/O MFP0 General purpose digital I/O pin EBI_DATA0 I/O MFP1 EBI data bus bit 0 I2C0_SCL I/O MFP2 I2C0 clock pin Oct., 02, 2019 Page 81 of 246 Rev 1.11 NUC980 SERIES DATASHEET PG.8 Pin Name NUC980 PG.11 PG.12 NUC980 SERIES DATASHEET Pin Name Type MFP Description TM5_TGL I/O MFP3 Timer5 event counter input/toggle output pin USBHL4_DP A MFP4 USB 1.1 Host Lite port 4 differential signal D+ CAN2_TXD O MFP5 CAN2 bus transmitter output SPI1_CLK I/O MFP6 SPI1 serial clock pin PWM00 O MFP7 PWM00 counter synchronous trigger output pin I2S_BCLK O MFP8 I2S_ bit clock output pin PG.11 I/O MFP0 General purpose digital I/O pin SPI1_SS0 I/O MFP2 SPI1 slave select 0 pin TM1_TGL I/O MFP3 Timer1 event counter input/toggle output pin CAN0_RXD I MFP4 CAN0 bus receiver input UART5_CTS I MFP5 UART5 clear to Send input pin PWM10 O MFP6 PWM10 counter synchronous trigger output pin JTAG0_TDO O MFP7 JTAG0 data output pin PG.12 I/O MFP0 General purpose digital I/O pin SPI1_CLK I/O MFP2 SPI1 serial clock pin TM1_EXT I/O MFP3 Timer1 external capture input/toggle output pin CAN0_TXD O MFP4 CAN0 bus transmitter output UART5_RTS O MFP5 UART5 request to Send output pin PWM11 O MFP6 PWM11 counter synchronous trigger output pin JTAG0_TCK I MFP7 JTAG0 clock input pin PG.13 I/O MFP0 General purpose digital I/O pin SPI1_MOSI I/O MFP2 SPI1 MOSI (Master Out, Slave In) pin CAN1_RXD I MFP4 CAN1 bus receiver input UART5_RXD I MFP5 UART5 data receiver input pin PWM12 O MFP6 PWM12 counter synchronous trigger output pin JTAG0_TMS I MFP7 JTAG0 test mode selection input pin PG.14 I/O MFP0 General purpose digital I/O pin SPI1_MISO I/O MFP2 SPI1 MISO (Master In, Slave Out) pin CAN1_TXD O MFP4 CAN1 bus transmitter output UART5_TXD O MFP5 UART5 data transmitter output pin PWM13 O MFP6 PWM13 counter synchronous trigger output pin JTAG0_TDI I MFP7 JTAG0 data input pin PG.15 I/O MFP0 General purpose digital I/O pin SPI0_SS1 I/O MFP1 SPI0 slave select 1 pin PG.13 PG.14 PG.15 Oct., 02, 2019 Page 82 of 246 Rev 1.11 NUC980 Pin Name Type MFP Description SPI1_SS1 I/O MFP2 SPI1 slave select 1 pin EINT3 I MFP4 External interrupt 3 input pin JTAG0_nTRST I MFP7 JTAG0 reset input pin NUC980 SERIES DATASHEET Oct., 02, 2019 Page 83 of 246 Rev 1.11 NUC980 5 BLOCK DIAGRAM 5.1 NUC980 Series Block Diagram ARM926EJ-S 300 MHz I-Cache 16 KB Memory Power Control ROM 16.5 KB POR Crypto SRAM 16 KB LVR MMU DDR2 LVD Phripherals AES SHA/HMAC D-Cache 16 KB Phripherals DMA AIC PDMA 0 10-ch TRNG 12-bit ADC 9-ch Timer X 6 RSA ECC Analog WDT/WWDT PWM X 8 PDMA 1 10-ch RTC Bridge AHB Bus Clock Control Storage HS Ext. Crystal Osc. 12 MHz NAND Flash Interface LS Ext. Crystal Osc. 32.768 kHz SD/eMMC Interface X 2 PLL X 2 Quad SPI X 1 APB Bus Connectivity Ethernet MAC X2 CMOS Interface X2 USB 2.0 HS/FS Host / Device EBI USB 1.1 FS Host Lite X 6 GPIO I2S X 1 External Interrupt USB 2.0 HS Transceivers Connectivity USB 2.0 HS Dual Role Transceiver UART X 10 (IrDA,RS-485) USB 2.0 HS Host Mode Transceiver CAN X 4 SPI X 2 I 2C X 4 ISO 7816-3 X 2 Figure 5.1-1 NUC980 Series Block Diagram NUC980 SERIES DATASHEET Oct., 02, 2019 Page 84 of 246 Rev 1.11 NUC980 6 FUNCTIONAL DESCRIPTION 6.1 ARM® ARM926EJ-S CPU Core 6.1.1 Overview The ARM926EJ-S CPU core is a member of the ARM9 family of general-purpose microprocessors. The ARM926EJ-S CPU core is targeted at multi-tasking applications where full memory management, high performance, and low power are all important. The ARM926EJ-S CPU core supports the 32-bit ARM and 16-bit Thumb instruction sets, enabling the user to choose between high performance and high code density. The ARM926EJ-S CPU core includes features for efficient execution of Java byte codes, providing Java performance similar to JIT, but without the associated code overhead. The ARM926EJ-S processor provides support for external coprocessor enabling floating-point or other application-specific hardware acceleration to be added. The ARM926EJ-S CPU core implements ARM architecture version 5TEJ. The ARM926EJ-S processor has a Harvard cached architecture and provides a complete highperformance processor subsystem, including:  An ARM9EJ-S integer core.  A Memory Management Unit (MMU).  Separate instruction and data cache.  Separate instruction and data AMBA AHB bus interfaces. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 85 of 246 Rev 1.11 NUC980 6.2 System Manager 6.2.1 Overview The system management describes the following information and functions. 6.2.2  System Resets  System Power Architecture  System Memory Map  System management registers for Product Identifier (PDID), Power-On Setting, System Wake-Up, Reset Control for on-chip controllers/peripherals, and multi-function pin control.  System Control registers System Reset The system reset can be issued by one of the following listed events. For these reset event flags can be read by RSTSTS register. 6.2.3  Power-On Reset  Low level on the /RESET pin  Watchdog Time Out Reset  Low Voltage Reset  CPU Reset  System Reset System Power Distribution In this chip, the power distribution is divided into six segments. NUC980 SERIES DATASHEET  Analog power from AVDD33 provides 3.3V voltage to analog components operation. These analog components including POR33, 12-bit SAR-ADC, LVD and LVR.  Digital power from VDD12 provides 1.2V voltage to POR12, APLL, APLL, SRAM (16 kB) and all digital logic except RTC.  Digital power from VBAT33 provides 3.3V voltage to LXT and RTC logic.  USB PHY power from VUSB0_VDD33, VUSB0_VDD12 provides 3.3V and 1.2 respectively to USB 2.0 PHY 0, while VUSB1_VDD33, VUSB1_VDD12 provides 3.3V and 1.2 respectively to USB 2.0 PHY 1.  I/O power from MVDD provides 1.8V/2.5V to I/O pins used to connect SDRAM.  I/O power from VDD33 provides 3.3V to HXT and I/O pins (PA ~ PG). Oct., 02, 2019 Page 86 of 246 Rev 1.11 NUC980 USB 2.0 PHY 0 POR12 APLL VUSB1_VDD12 (1.2V) VUSB1_VDD33 (3.3V) DM1 DP1 DM0 DP0 VUSB0_VDD12 (1.2V) VUSB0_VDD33 (3.3V) Figure 6.2-1 shows the power distribution of the NUC980 series. USB 2.0 PHY 1 UPLL DDR IO Cell HXT Ext. Crystal Osc. 12 MHz SRAM (16 kB) MVDD (1.8V) XT_IN XT_OUT VDD12 (1.2V) ROM (16.5 kB) Digital Logic AVDD33 (3.3V) Low Voltage Reset Low Voltage Detection 12-bit SAR-ADC POR33 Normal IO Cell LXT Ext. Crystal Osc. 32.768 kHz RTC with 64B Spare Register VDD33 (3.3V) VBAT33 (3.3V) 6.2.4 System Memory Map This chip supports only little-endian data format and provides 4G-byte addressing space. Figure 6.2-2 describes the memory space definition. The memory space from 0x0000_0000 to 0x1FFF_FFFF is for SDRAM and external devices. The memory space from 0x3C00_0000 to 0x3C00_3FFF is for embedded 16 Kbytes SRAM. The memory space for On-Chip Controllers and Peripherals is from 0xB000_0000 to 0xB00A_3FFF while the memory space from 0xFFFF_0000 to 0xFFFF_41FF is for 16.5 Kbytes internal Boot ROM. This chip provides the shadow memory function. The memory space from 0x8000_0000 to 0x9FFF_FFFF is the shadow memory space for memory space from 0x0000_0000 to 0x1FFF_FFFF. The memory space from 0xBC00_0000 to 0xBC00_3FFF is the shadow memory space for memory space from 0x3C00_0000 to 0x3C00_3FFF. If the DMA of On-Chip Controller wants to access this 16 Kbytes embedded SRAM, it’s necessary to use memory space from 0xBC00_0000 to 0xBC00_3FFF The reserved memory space is un-accessible. Chip’s behavior is undefined and unpredictable while accessing to reserved memory space. Oct., 02, 2019 Page 87 of 246 Rev 1.11 NUC980 SERIES DATASHEET X32_IN X32_OUT Figure 6.2-1 NUC980 Series Power Distribution Diagram NUC980 0x7FFF_FFFF 0xFFFF_FFFF Reserved 0xFFFF_4200 Internal Boot ROM (IBR, 16.5 KB) 0xFFFF_0000 Reserved Reserved 0x602F_0000 0x6000_0000 0xE02F_0000 EBI EBI 0xE000_0000 Reserved 0x3C00_4000 0x3C00_0000 Reserved Internal SRAM (16 KB) 0xBC00_4000 0xBC00_0000 0xB00B_0000 Reserved 0xB004_0000 0xB000_0000 Internal SRAM (16 KB) Reserved On-Chip APB Peripherals On-Chip AHB Peripherals NUC980 SERIES DATASHEET Reserved 0x2000_0000 0xA000_0000 SDRAM 0x0000_0000 SDRAM 0x8000_0000 Figure 6.2-2 NUC980 System Memory Map Diagram Oct., 02, 2019 Page 88 of 246 Rev 1.11 NUC980 The addressing space assigned to each on-chip controller or peripheral described in Table 6.2-1. The detailed register definition, addressing space, and programming details will be described in the following sections. Addressing Space Token Modules SDRAM, External Devices and SRAM Memory Space 0x0000_0000 – 0x1FFF_FFFF SDRAM_BA SDRAM Memory Space 0x6000_0000 – 0x602F_FFFF EXDEV_BA External Devices Memory Space 0x3C00_0000 – 0x3C00_3FFF SRAM_BA SRAM Memory Space (16 KB) Internal Boot ROM (IBR) Memory Space (0xFFFF_0000 ~ 0xFFFF_41FF) 0xFFFF_0000 – 0xFFFF_41FF IBR_BA Internal Boot ROM (IBR) Memory Space (16.5 KB) AHB Modules Memory Space (0xB000_0000 – 0xB003_FFFF) SYS_BA System Global Control Registers 0xB000_0200 – 0xB000_02FF CLK_BA Clock Control Registers 0xB000_2000 – 0xB000_2FFF SDIC_BA SDRAM (SDR/DDR/DDR2) Control Registers 0xB000_4000 – 0xB000_4FFF GPIO_BA GPIO Control Registers 0xB000_8000 – 0xB000_8FFF PDMA0_BA PDMA 0 Control Registers 0xB000_9000 – 0xB000_9FFF PDMA1_BA PDMA 1 Control Registers 0xB001_0000 – 0xB001_0FFF EBI_BA EBI Control Registers 0xB001_2000 – 0xB001_2FFF EMAC0_BA Ethernet MAC 0 Control Registers 0xB002_4000 – 0xB002_4FFF CAP0_BA Capture Sensor Interface 0 Control Registers 0xB001_5000 – 0xB001_5FFF HSUSBH_BA High Speed USB 2.0 Host Control Registers 0xB001_6000 – 0xB001_6FFF HSUSBD_BA High Speed USB 2.0 Device Control Registers 0xB001_7000 – 0xB001_7FFF USBH_BA USB 2.0 Host Control Registers 0xB001_8000 – 0xB001_8FFF SDH_BA SD/SDIO Host Control Registers 0xB001_9000 – 0xB001_9FFF FMI_BA Flash Memory Interface (FMI) Control Registers 0xB001_C000 – 0xB001_EFFF CRYPTO_BA Cryptographic Accelerator Control Registers 0xB002_0000 – 0xB002_0FFF I2S_BA I2S Interface Control Registers 0xB002_2000 – 0xB002_2FFF EMAC1_BA Ethernet MAC 1 Control Registers 0xB001_4000 – 0xB001_4FFF CAP1_BA Capture Sensor Interface 1 Control Registers NUC980 SERIES DATASHEET 0xB000_0000 – 0xB000_01FF APB Modules Memory Space (0xB004_0000 ~ 0xB00A_FFFF) 0xB004_0000 – 0xB004_00FF WDT_BA Watch-Dog Timer Control Registers 0xB004_0100 – 0xB004_01FF WWDT_BA Windowed Watch-Dog Timer Control Registers 0xB004_1000 – 0xB004_1FFF RTC_BA Real Time Clock (RTC) Control Registers 0xB004_2000 – 0xB004_2FFF AIC_BA Advance Interrupt Control Registers 0xB004_3000 – 0xB004_3FFF ADC_BA ADC Control Registers 0xB005_0000 – 0xB005_0FFF TMR_BA01 Timer 0 and Timer 1 Control Registers Oct., 02, 2019 Page 89 of 246 Rev 1.11 NUC980 NUC980 SERIES DATASHEET 0xB005_1000 – 0xB005_1FFF TMR_BA23 Timer 2 and Timer 3 Control Registers 0xB005_2000 – 0xB005_2FFF TMR_BA45 Timer 4 and Timer 5 Control Registers 0xB005_8000 – 0xB005_8FFF PWM0_BA PWM 0 Control Registers 0xB005_9000 – 0xB005_9FFF PWM1_BA PWM 1 Control Registers 0xB006_0000 – 0xB006_0FFF QSPI0_BA QSPI 0 Control Registers 0xB006_1000 – 0xB006_1FFF SPI0_BA SPI 0 Control Registers 0xB006_2000 – 0xB006_2FFF SPI1_BA SPI 1 Control Registers 0xB007_0000 – 0xB007_0FFF UART0_BA UART 0 Control Registers 0xB007_1000 – 0xB007_1FFF UART1_BA UART 1 Control Registers 0xB007_2000 – 0xB007_2FFF UART2_BA UART 2 Control Registers 0xB007_3000 – 0xB007_3FFF UART3_BA UART 3 Control Registers 0xB007_4000 – 0xB007_4FFF UART4_BA UART 4 Control Registers 0xB007_5000 – 0xB007_5FFF UART5_BA UART 5 Control Registers 0xB007_6000 – 0xB007_6FFF UART6_BA UART 6 Control Registers 0xB007_7000 – 0xB007_7FFF UART7_BA UART 7 Control Registers 0xB007_8000 – 0xB007_8FFF UART8_BA UART 8 Control Registers 0xB007_9000 – 0xB007_9FFF UART9_BA UART 9 Control Registers 0xB008_0000 – 0xB008_0FFF I2C0_BA I2C 0 Control Registers 0xB008_1000 – 0xB008_1FFF I2C1_BA I2C 1 Control Registers 0xB008_2000 – 0xB008_2FFF I2C2_BA I2C 2 Control Registers 0xB008_3000 – 0xB008_3FFF I2C3_BA I2C 3 Control Registers 0xB009_0000 – 0xB009_0FFF SC0_BA Smart Card 0 Control Registers 0xB009_1000 – 0xB009_1FFF SC1_BA Smart Card 1 Control Registers 0xB00A_0000 – 0xB00A_0FFF CAN0_BA CAN 0 Control Registers 0xB00A_1000 – 0xB00A_1FFF CAN1_BA CAN 1 Control Registers 0xB00A_2000 – 0xB00A_2FFF CAN2_BA CAN 2 Control Registers 0xB00A_3000 – 0xB00A_3FFF CAN3_BA CAN 3 Control Registers Table 6.2-1 Address Space Assignments for On-Chip Controllers Oct., 02, 2019 Page 90 of 246 Rev 1.11 NUC980 6.2.5 Power-On Setting After power on reset, Power-On setting registers are latched to configure this chip. Table 6.2-2 describes the definition of each power-on setting bit. Power-On Setting Pin Description USB0_ID USB Port 0 Role Selection Power-on Setting Register Bit 0 = USB Port 0 act as a USB host. USBID (SYS_PWRON[16]) 1 = USB Port 0 act as a USB device. PG[1:0] Boot Source Selection 00 = Boot from USB. 01 = Boor from SD0/eMMC. BTSSEL (SYS_PWRON[1:0]) 10 = Boot from NAND Flash. 11 = Boot from SPI Flash. PG.2 QSPI0_CLK Frequency Selection 0 = QSPI0_CLK frequency is 30 MHz. QSPI0CKSEL (SYS_PWRON[2]) 1 = QSPI0_CLK frequency is 50 MHz. PG.3 Watchdog Timer (WDT) Enabled/Disabled Selection 0 = After power-on, WDT Disabled. WDTON (SYS_PWRON[3]) 1 = after power-on WDT Enabled. PG.4 JTAG Interface Selection 0 = Pin PA[6:2] used as JTAG interface. JTAGSEL (SYS_PWRON[4]) 1 = Pin PG[15:11] used as JTAG interface. PG.5 UART 0 Debug Message Output ON/OFF Selection 0 = UART 0 debug message output ON and pin PF[12:11] used as the UART0 functionality. URDBGON (SYS_PWRON[5]) NUC980 SERIES DATASHEET 1 = UART 0 debug message output OFF and pin PF[12:11] used as the GPIO functionality. NAND Flash Page Size selection 00 = NAND Flash page size is 2KB. PG[7:6] 01 = NAND Flash page size is 4KB. NPAGESEL (SYS_PWRON[7:6]) 10 = NAND Flash page size is 8KB. 11 = Ignore Power-On Setting. Oct., 02, 2019 Page 91 of 246 Rev 1.11 NUC980 PG[9:8] Miscellaneous Configuration When BTSSEL = 01, Boot from SD/eMMC, the MISCCFG defines the GPC or GPF used as the booting source. 11 = GPC group used as the booting source. Others = GPF group used as the booting source. When BTSSEL = 10, Boot from NAND Flash, the MISCCFG defines the ECC type. 00 = No ECC 01 = ECC is BCH T12 MISCCFG (SYS_PWRON[9:8]) 10 = ECC is BCH T24 11 = Ignore power-on setting When BTSEL = 11, Boot from SPI Flash, the MISCCFG defines the SPI Flash type and data width. 00 = SPI-NAND Flash with 1-bit mode. 01 = SPI-NAND Flash with 4-bit mode. 10 = SPI-NOR Flash with 4-bit mode. 11 = SPI-NOR Flash with 1-bit mode. Table 6.2-2 Power-On Setting Bit Description NUC980 SERIES DATASHEET Oct., 02, 2019 Page 92 of 246 Rev 1.11 NUC980 6.2.6 Register Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value 0x1030_D016[1] SYS Base Address: SYS_BA = 0xB000_0000 SYS_PDID SYS_BA+0x000 R Product Identifier Register SYS_PWRON SYS_BA+0x004 R/W Power-on Setting Register SYS_LVRDCR SYS_BA+0x020 R/W Low Voltage Reset & Detect Control Register 0x0000_0001 SYS_MISCFCR SYS_BA+0x030 R/W Miscellaneous Function Control Register 0x0000_0200 SYS_MISCIER SYS_BA+0x040 R/W Miscellaneous Interrupt Enable Register 0x0000_0000 SYS_MISCISR SYS_BA+0x044 R/W Miscellaneous Interrupt Status Register 0x0001_0000 SYS_WKUPSER0 SYS_BA+0x050 R/W System Wakeup Source Enable Register 0 0x0000_0000 SYS_WKUPSER1 SYS_BA+0x054 R/W System Wakeup Source Enable Register 1 0x0000_0000 SYS_WKUPSSR0 SYS_BA+0x058 R/W System Wakeup Source Status Register 0 0x0000_0000 SYS_WKUPSSR1 SYS_BA+0x05C R/W System Wakeup Source Status Register 1 0x0000_0000 SYS_AHBIPRST SYS_BA+0x060 R/W AHB IP Reset Control Register 0x0000_0000 SYS_APBIPRST0 SYS_BA+0x064 R/W APB IP Reset Control Register 0 0x0000_0000 SYS_APBIPRST1 SYS_BA+0x068 R/W APB IP Reset Control Register 1 0x0000_0000 SYS_RSTSTS SYS_BA+0x06C R/W Reset Source Active Status Register 0x0000_00XX SYS_GPA_MFPL SYS_BA+0x070 R/W GPIOA Low Byte Multiple Function Control Register 0x0XXX_XX00 SYS_GPA_MFPH SYS_BA+0x074 R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000 SYS_GPB_MFPL SYS_BA+0x078 R/W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPB_MFPH SYS_BA+0x07C R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000 SYS_GPC_MFPL SYS_BA+0x080 R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPC_MFPH SYS_BA+0x084 R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000 SYS_GPD_MFPL SYS_BA+0x088 R/W GPIOD Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPD_MFPH SYS_BA+0x08C R/W GPIOD High Byte Multiple Function Control Register 0x0000_0000 SYS_GPE_MFPL SYS_BA+0x090 R/W GPIOE Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPE_MFPH SYS_BA+0x094 R/W GPIOE High Byte Multiple Function Control Register 0x0000_0000 SYS_GPF_MFPL SYS_BA+0x098 R/W GPIOF Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPF_MFPH SYS_BA+0x09C R/W GPIOF High Byte Multiple Function Control Register 0x0000_0000 Page 93 of 246 ] Rev 1.11 NUC980 SERIES DATASHEET Oct., 02, 2019 0xXXXX_XXXX[2 NUC980 SYS_GPG_MFPL SYS_BA+0x0A0 R/W GPIOG Low Byte Multiple Function Control Register 0x0000_0000 SYS_GPG_MFPH SYS_BA+0x0A4 R/W GPIOG High Byte Multiple Function Control Register 0xXXXX_X000 SYS_DDR_DSCTL SYS_BA+0x0F0 R/W DDR I/O Driving Strength Control Register 0x0000_0000 SYS_GPBL_DSCTL SYS_BA+0x0F4 R/W GPIOB Low Byte Driving Strength Control Register 0x4444_4444 SYS_PORDISCR SYS_BA+0x100 R/W Power-On-reset Disable Control Register 0x0000_00XX SYS_RSTDEBCTL SYS_BA+0x10C R/W Reset Pin De-bounce Control Register 0x0000_04B0 SYS_REGWPCTL SYS_BA+0x1FC R/W Register Write-protection Control Register 0x0000_0000 Note: [1] Dependents on part number. Note: [2] Dependents on power-on setting. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 94 of 246 Rev 1.11 NUC980 6.2.7 Register Description Product Identifier Register (SYS_PDID) Register Offset R/W Description Reset Value SYS_PDID SYS_BA+0x000 R Product Identifier Register 0x1030_D016 31 30 29 28 27 26 25 24 19 18 17 16 9 8 1 0 Reserved 23 22 21 20 PRDNUML6 15 14 PRDNUML5 13 12 11 10 PRDNUML4 7 6 PRDNUML3 5 4 3 PRDNUML2 Bits Description [31:24] Reserved 2 PRDNUML1 Reserved. Product Number Letter 6 0 = D. [23:20] PRDNUML6 1 = F. 2 = G. 3 = H. NUC980 SERIES DATASHEET Product Number Letter 5 [19:16] PRDNUML5 0 = A. 1 = B. [15:12] PRDNUML4 [11:8] PRDNUML3 [7:4] PRDNUML2 [3:0] PRDNUML1 Oct., 02, 2019 Product Number Letter 4 0xD Product Number Letter 3 0x0 Product Number Letter 2 0x1 Product Number Letter 1 0x6 Page 95 of 246 Rev 1.11 NUC980 Power-on Setting Register (SYS_PWRON) Register Offset R/W Description Reset Value SYS_PWRON SYS_BA+0x004 R/W Power-on Setting Register 0xXXXX_XXXX 31 30 29 28 27 26 Reserved 23 22 Reserved 14 24 17 16 TICMOD USBID 9 8 USERID 21 20 19 DRAMSIZE 15 25 18 Reserved 13 12 11 10 Reserved 7 6 NPAGESEL Bits Description [31:29] Reserved [28:24] USERID [23] Reserved MISCCFG 5 4 3 2 URDBGON JTAGSEL WDTON QSPI0CKSEL 1 0 BTSSEL Reserved. User ID (Read Only) A user defined ID. Reserved. DRAM Size 000 = Reserved. NUC980 SERIES DATASHEET 001 = 2 MB 010 = Reserved. [22:20] DRAMSIZE 011 = 8 MB 100 = 16 MB 101 = 32 MB 110 = 64 MB 111 = 128 MB [19:18] Reserved [17] TICMOD Reserved. TIC Mode Enable Bit 0= TIC interface Disabled. 1= TIC interface Enabled. USB ID Pin Status [16] USBID 0= USB port 0 used as a USB device. 1= USB port 0 used as a USB host. Oct., 02, 2019 Page 96 of 246 Rev 1.11 NUC980 Miscellaneous Configuration When pin nRESET transited from low to high, the value of pin PG[9:8] latched to MISCCFG. When BTSSEL = 01, Boot from SD/eMMC, the MISCCFG defines the SD0/eMMC0 or SD1/eMMC1 used as the booting source. 11 = SD0/eMMC0 (GPC group) used as the booting source. Others = SD1/eMMC1 (GPF group) used as the booting source. When BTSSEL = 10, Boot from NAND Flash, the MISCCFG defines the ECC type. 00 = ECC is BCH T8. [9:8] MISCCFG 01 = ECC is BCH T12. 10 = ECC is BCH T24. 11 = Ignore power-on setting. When BTSEL = 11, Boot from SPI Flash, the MISCCFG defines the SPI Flash type and data width. 00 = SPI-NAND Flash with 1-bit mode. 01 = SPI-NAND Flash with 4-bit mode. 10 = SPI-NOR Flash with 4-bit mode. 11 = SPI-NOR Flash with 1-bit mode. NAND Flash Page Size Selection When pin nRESET transited from low to high, the value of pin PG[7:6] latched to NPAGESEL. [7:6] NPAGESEL 00= NAND Flash page size is 2KB. 01= NAND Flash page size is 4KB. 10= NAND Flash page size is 8KB. 11= Ignore power-on setting. UART 0 Debug Message Output ON/OFF Selection URDBGON When pin nRESET transited from low to high, the value of pin PG.5 latched to URDBGON. 0= UART 0 debug message output ON. 1= UART 0 debug message output OFF. JTAG Interface Selection [4] JTAGSEL When pin nRESET transited from low to high, the value of pin PG.4 latched to JTAGSEL. 0 = Pin PA[6:2] used as JTAG interface. 1 = Pin PG[15:11] used as JTAG interface. Watchdog Timer (WDT) ON/OFF Selection [3] WDTON When pin nRESET transited from low to high, the value of pin PG.3 latched to WDTON. 0 = After power-on, WDT Disabled. 1 = after power-on WDT Enabled. QSPI0_CLK Frequency Selection [2] QSPI0CKSEL When pin nRESET transited from low to high, the value of pin PG.2 latched to QSPI0CKSEL. 0 = QSPI0_CLK frequency is 37.5 MHz. 1 = QSPI0_CLK frequency is 75 MHz. Oct., 02, 2019 Page 97 of 246 Rev 1.11 NUC980 SERIES DATASHEET [5] NUC980 Boot Source Selection When pin nRESET transited from low to high, the value of pin PG[1:0] latched to BTSSEL. [1:0] BTSSEL 00= Boot from USB. 01= Boot from SD/eMMC. 10= Boot from NAND Flash. 11= Boot from SPI Flash. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 98 of 246 Rev 1.11 NUC980 Low Voltage Reset & Detect Control Register (SYS_LVRDCR) Register Offset SYS_LVRDCR SYS_BA+0x020 31 30 R/W Description Reset Value R/W Low Voltage Reset & Detect Control Register 0x0000_0001 29 28 27 26 25 24 19 18 17 16 11 10 9 8 LVD_SEL LVD_EN 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 3 Reserved Bits Description [31:10] Reserved 2 LVR_EN Reserved. Low Voltage Detect Threshold Selection [9] LVD_SEL 0 = Low voltage detection level is 2.6V. 1 = Low voltage detection level is 2.8V. Low Voltage Detect Enable Bit [8] LVD_EN 0 = Low voltage detect function Disabled. 1 = Low voltage detect function Enabled. Reserved NUC980 SERIES DATASHEET [7:1] Reserved. Low Voltage Reset Enable Bit [0] LVR_EN 0 = Low voltage reset function Disabled. 1 = Low voltage reset function Enabled. Oct., 02, 2019 Page 99 of 246 Rev 1.11 NUC980 Miscellaneous Function Control Register (SYS_MISCFCR) Register Offset SYS_MISCFCR SYS_BA+0x030 31 30 R/W Description Reset Value R/W Miscellaneous Function Control Register 0x0000_0200 29 28 27 26 25 24 19 18 17 16 12 11 10 9 8 GPIOLBEN USRHDSEN Reserved HDSPUEN WDTRSTEN 4 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 7 SELFTEST 6 13 Reserved 5 Reserved Bits Description [31:13] Reserved Reserved. GPIO Pin Loop-back Enable Bit [12] GPIOLBEN 0 = GPIO input status didn’t reflect pin status if the GPIO configured as functional pin. 1 = GPIO input status did reflect pin status even if the GPIO configured as functional pin. User Configurable USB Host Device Role Selection Enable Bit [11] USRHDSEN 0 = USB host/device role selection decided by HDS pin. 1 = USB host/device role selection decided by USBID (SYS_PWRON[16]). NUC980 SERIES DATASHEET [10] Reserved Reserved. HDS Pin Internal Pull-up Enable Bit [9] HDSPUEN 0 = HDS pin internal pull-up resister Disabled. 1 = HDS pin internal pull-up resister Enabled. WatchDog Timer Reset Connection Enable Bit [8] WDTRSTEN This bit is used to enable the function that connect watch-dog timer reset to nRESET pin. If this bit is enabled, the watch-dog timer reset is connected to nRESET pin internally 0 = Watch-dog timer reset not connected to nRESET pin internally. 1 = Watch-dog timer reset connected to nRESET pin internally. [7:0] Reserved Oct., 02, 2019 Reserved. Page 100 of 246 Rev 1.11 NUC980 Miscellaneous Interrupt Enable Register (SYS_MISCIER) Register Offset R/W Description Reset Value SYS_MISCIER SYS_BA+0x040 R/W Miscellaneous Interrupt Enable Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 USBIDC_IEN LVD_IEN Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 Reserved Bits Description [31:2] Reserved Reserved. USB0_ID Pin Status Change Interrupt Enable Bit [1] USBIDC_IEN 0 = HDS status change interrupt Disabled. 1 = HDS status change interrupt Enabled. Low Voltage Detect Interrupt Enable Bit [0] LVD_IEN 0 = Low voltage detect interrupt Disabled. 1 = Low voltage detect interrupt Enabled. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 101 of 246 Rev 1.11 NUC980 Miscellaneous Interrupt Status Register (SYS_MISCISR) Register Offset R/W Description Reset Value SYS_MISCISR SYS_BA+0x044 R/W Miscellaneous Interrupt Status Register 0x0001_0000 31 30 29 28 27 26 25 24 19 18 17 16 USB0_IDS IBR_RUN_F Reserved 23 22 21 20 Reserved 15 14 13 12 11 10 9 8 3 2 1 0 USBIDC_IS LVD_IS Reserved 7 6 5 4 Reserved Bits Description [31:18] Reserved [17] USB0_IDS Reserved. USB0_ID Status 0 = USB port 0 used as a USB device port. 1 = USB port 0 used as a USB host port. IBR Run Flag [16] IBR_RUN_F 0 = CPU didn’t execute instruction in 0xFFFF_0000 yet. NUC980 SERIES DATASHEET 1 = CPU executed instruction in 0xFFFF_0000. [15:2] Reserved [1] USBIDC_IS Reserved. USB0_ID Pin State Change Interrupt Status 0 = USB0_ID state didn’t change. 1 = USB0_ID state changed from low to high or from high to low. Low Voltage Detect Interrupt Status [0] LVD_IS 0 = No low voltage event. 1 = Low voltage event detected. Oct., 02, 2019 Page 102 of 246 Rev 1.11 NUC980 System Wakeup Source Enable Register 0 (SYS_WKUPSER0) Register Offset SYS_WKUPSER0 SYS_BA+0x050 R/W 31 30 R/W Description Reset Value System Wakeup Source Enable Register 0 0x0000_0000 29 28 27 26 Reserved 25 24 UR9WKEN UR8WKEN 23 22 21 20 19 18 17 16 UR7WKEN UR6WKEN UR5WKEN UR4WKEN UR3WKEN UR2WKEN UR1WKEN UR0WKEN 15 14 13 12 11 10 9 8 TMR5WKEN TMR4WKEN TMR3WKEN TMR2WKEN TMR1WKEN TMR0WKEN Reserved 7 6 5 4 3 2 1 0 EINT3WKEN EINT2WKEN EINT1WKEN EINT0WKEN GPIOWKEN Reserved Reserved WDTWKEN Bits Description [31:26] Reserved [25] UR9WKEN Reserved. UART 9 Wake System Up Enable Bit 0 = UART 9 wake system up function Disabled. 1 = UART 9 wake system up function Enabled. UART 8 Wake System Up Enable Bit [24] UR8WKEN 0 = UART 8 wake system up function Disabled. NUC980 SERIES DATASHEET 1 = UART 8 wake system up function Enabled. UART 7 Wake System Up Enable Bit [23] UR7WKEN 0 = UART 7 wake system up function Disabled. 1 = UART 7 wake system up function Enabled. UART 6 Wake System Up Enable Bit [22] UR6WKEN 0 = UART 6 wake system up function Disabled. 1 = UART 6 wake system up function Enabled. UART 5 Wake System Up Enable Bit [21] UR5WKEN 0 = UART 5 wake system up function Disabled. 1 = UART 5 wake system up function Enabled. UART 4 Wake System Up Enable Bit [20] UR4WKEN 0 = UART 4 wake system up function Disabled. 1 = UART 4 wake system up function Enabled. UART 3 Wake System Up Enable Bit [19] UR3WKEN 0 = UART 3 wake system up function Disabled. 1 = UART 3 wake system up function Enabled. UART 2 Wake System Up Enable Bit [18] UR2WKEN 0 = UART 2 wake system up function Disabled. 1 = UART 2 wake system up function Enabled. Oct., 02, 2019 Page 103 of 246 Rev 1.11 NUC980 UART 1 Wake System Up Enable Bit [17] UR1WKEN 0 = UART 1 wake system up function Disabled. 1 = UART 1 wake system up function Enabled. UART 0 Wake System Up Enable Bit [16] UR0WKEN 0 = UART 0 wake system up function Disabled. 1 = UART 0 wake system up function Enabled. [15:14] Reserved Reserved. TIMER 5 Wake System Up Enable Bit [13] TMR5WKEN 0 = TIMER 5 wake system up function Disabled. 1 = TIMER 5 wake system up function Enabled. TIMER 4 Wake System Up Enable Bit [12] TMR4WKEN 0 = TIMER 4 wake system up function Disabled. 1 = TIMER 4 wake system up function Enabled. TIMER 3 Wake System Up Enable Bit [11] TMR3WKEN 0 = TIMER 3 wake system up function Disabled. 1 = TIMER 3 wake system up function Enabled. TIMER 2 Wake System Up Enable Bit [10] TMR2WKEN 0 = TIMER 2 wake system up function Disabled. 1 = TIMER 2 wake system up function Enabled. TIMER 1 Wake System Up Enable Bit [9] TMR1WKEN 0 = TIMER 1 wake system up function Disabled. 1 = TIMER 1 wake system up function Enabled. TIMER 0 Wake System Up Enable Bit [8] TMR0WKEN 0 = TIMER 0 wake system up function Disabled. 1 = TIMER 0 wake system up function Enabled. NUC980 SERIES DATASHEET External Interrupt 3 Wake System Up Enable Bit [7] EINT3WKEN 0 = External Interrupt 3 wake system up function Disabled. 1 = External Interrupt 3 wake system up function Enabled. External Interrupt 2 Wake System Up Enable Bit [6] EINT2WKEN 0 = External Interrupt 2 wake system up function Disabled. 1 = External Interrupt 2 wake system up function Enabled. External Interrupt 1 Wake System Up Enable Bit [5] EINT1WKEN 0 = External Interrupt 1 wake system up function Disabled. 1 = External Interrupt 1 wake system up function Enabled. External Interrupt 0 Wake System Up Enable Bit [4] EINT0WKEN 0 = External Interrupt 0 wake system up function Disabled. 1 = External Interrupt 0 wake system up function Enabled. GPIO Wake System Up Enable Bit [3] GPIOWKEN 0 = GPIO wake system up function Disabled. 1 = GPIO wake system up function Enabled. [2:1] Reserved Oct., 02, 2019 Reserved. Page 104 of 246 Rev 1.11 NUC980 WDT Wake System Up Enable Bit [0] WDTWKEN 0 = WDT wake system up function Disabled. 1 = WDT wake system up function Enabled. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 105 of 246 Rev 1.11 NUC980 System Wakeup Source Enable Register 1 (SYS_WKUPSER1) Register Offset R/W Description Reset Value SYS_WKUPSER1 SYS_BA+0x054 R/W System Wakeup Source Enable Register 1 31 30 29 28 0x0000_0000 27 26 25 24 20 19 18 17 16 SDHWKEN USBDWKEN 12 11 10 9 8 CAN3WKEN CAN2WKEN CAN1WKEN CAN0WKEN 3 2 1 0 I2C3WKEN I2C2WKEN I2C1WKEN I2C0WKEN Reserved 23 22 21 Reserved 15 14 LVDWKEN 13 Reserved 7 6 RTCWKEN 5 Reserved Bits Description [31:21] Reserved [20] SDHWKEN 4 USBHWKEN EMAC1WKEN EMAC0WKEN Reserved. SDH Wake System Up Enable Bit 0 = SDH wake system up function Disabled. 1 = SDH wake system up function Enabled. USB Device Wake System Up Enable Bit [19] USBDWKEN 0 = USB device wake system up function Disabled. NUC980 SERIES DATASHEET 1 = USB device wake system up function Enabled. USB Host Wake System Up Enable Bit [18] USBHWKEN 0 = USB host wake system up function Disabled. 1 = USB host wake system up function Enabled. Ethernet MAC 1 Wake System Up Enable Bit [17] EMAC1WKEN 0 = Ethernet MAC 1 wake system up function Disabled. 1 = Ethernet MAC 1 wake system up function Enabled. Ethernet MAC 0 Wake System Up Enable Bit [16] EMAC0WKEN 0 = Ethernet MAC 0 wake system up function Disabled. 1 = Ethernet MAC 0 wake system up function Enabled. Low Voltage Detect Wake System Up Enable Bit [15] LVDWKEN 0 = Low Voltage Detect wake system up function Disabled. 1 = Low Voltage Detect wake system up function Enabled. [14:12] Reserved Reserved. CAN 3 Wake System Up Enable Bit [11] CAN3WKEN 0 = CAN 3 wake system up function Disabled. 1 = CAN 3 wake system up function Enabled. Oct., 02, 2019 Page 106 of 246 Rev 1.11 NUC980 CAN 2 Wake System Up Enable Bit [10] CAN2WKEN 0 = CAN 2 wake system up function Disabled. 1 = CAN 2 wake system up function Enabled. CAN 1 Wake System Up Enable Bit [9] CAN1WKEN 0 = CAN 1 wake system up function Disabled. 1 = CAN 1 wake system up function Enabled. CAN 0 Wake System Up Enable Bit [8] CAN0WKEN 0 = CAN 0 wake system up function Disabled. 1 = CAN 0 wake system up function Enabled. RTC Wake System Up Enable Bit [7] RTCWKEN 0 = RTC wake system up function Disabled. 1 = RTC wake system up function Enabled. [6:4] Reserved Reserved. I2C 3 Wake System Up Enable Bit [3] I2C3WKEN 0 = I2C 3 wake system up function Disabled. 1 = I2C 3 wake system up function Enabled. I2C 2 Wake System Up Enable Bit [2] I2C2WKEN 0 = I2C 2 wake system up function Disabled. 1 = I2C 2 wake system up function Enabled. I2C 1 Wake System Up Enable Bit [1] I2C1WKEN 0 = I2C 1 wake system up function Disabled. 1 = I2C 1 wake system up function Enabled. I2C 0 Wake System Up Enable Bit [0] I2C0WKEN 0 = I2C 0 wake system up function Disabled. 1 = I2C 0 wake system up function Enabled. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 107 of 246 Rev 1.11 NUC980 System Wakeup Source Status Register 0 (SYS_WKUPSSR0) Register Offset R/W Description Reset Value SYS_WKUPSSR0 SYS_BA+0x058 R/W System Wakeup Source Status Register 0 31 30 29 28 27 0x0000_0000 26 Reserved 25 24 UR9WKST UR8WKST 23 22 21 20 19 18 17 16 UR7WKST UR6WKST UR5WKST UR4WKST UR3WKST UR2WKST UR1WKST UR0WKST 15 14 13 12 11 10 9 8 TMR5WKST TMR4WKST TMR3WKST TMR2WKST TMR1WKST TMR0WKST Reserved 7 6 5 4 3 2 1 0 EINT3WKST EINT2WKST EINT1WKST EINT0WKST GPIOWKST Reserved Reserved WDTWKST Bits Description [31:26] Reserved [25] UR9WKST Reserved. UART 9 Wake System Up Status 0 = UART 9 didn’t wake system up. 1 = UART 9 wake system up. UART 8 Wake System Up Status [24] UR8WKST 0 = UART 8 didn’t wake system up. NUC980 SERIES DATASHEET 1 = UART 8 wake system up. UART 7 Wake System Up Status [23] UR7WKST 0 = UART 7 didn’t wake system up. 1 = UART 7 wake system up. UART 6 Wake System Up Status [22] UR6WKST 0 = UART 6 didn’t wake system up. 1 = UART 6 wake system up. UART 5 Wake System Up Status [21] UR5WKST 0 = UART 5 didn’t wake system up. 1 = UART 5 wake system up. UART 4 Wake System Up Status [20] UR4WKST 0 = UART 4 didn’t wake system up. 1 = UART 4 wake system up. UART 3 Wake System Up Status [19] UR3WKST 0 = UART 3 didn’t wake system up. 1 = UART 3 wake system up. UART 2 Wake System Up Status [18] UR2WKST 0 = UART 2 didn’t wake system up. 1 = UART 2 wake system up. Oct., 02, 2019 Page 108 of 246 Rev 1.11 NUC980 UART 1 Wake System Up Status [17] UR1WKST 0 = UART 1 didn’t wake system up. 1 = UART 1 wake system up. UART 0 Wake System Up Status [16] UR0WKST 0 = UART 0 didn’t wake system up. 1 = UART 0 wake system up. [15:14] Reserved Reserved. TIMER 5 Wake System Up Status [13] TMR5WKST 0 = TIMER 5 didn’t wake system up. 1 = TIMER 5 wake system up. TIMER 4 Wake System Up Status [12] TMR4WKST 0 = TIMER 4 didn’t wake system up. 1 = TIMER 4 wake system up. TIMER 3 Wake System Up Status [11] TMR3WKST 0 = TIMER 3 didn’t wake system up. 1 = TIMER 3 wake system up. TIMER 2 Wake System Up Status [10] TMR2WKST 0 = TIMER 2 didn’t wake system up. 1 = TIMER 2 wake system up. TIMER 1 Wake System Up Status [9] TMR1WKST 0 = TIMER 1 didn’t wake system up. 1 = TIMER 1 wake system up. TIMER 0 Wake System Up Status [8] TMR0WKST 0 = TIMER 0 didn’t wake system up. 1 = TIMER 0 wake system up. NUC980 SERIES DATASHEET External Interrupt 3 Wake System Up Status [7] EINT3WKST 0 = External Interrupt 3 didn’t wake system up. 1 = External Interrupt 3 wake system up. External Interrupt 2 Wake System Up Status [6] EINT2WKST 0 = External Interrupt 2 didn’t wake system up. 1 = External Interrupt 2 wake system up. External Interrupt 1 Wake System Up Status [5] EINT1WKST 0 = External Interrupt 1 didn’t wake system up. 1 = External Interrupt 1 wake system up. External Interrupt 0 Wake System Up Status [4] EINT0WKST 0 = External Interrupt 0 didn’t wake system up. 1 = External Interrupt 0 wake system up. GPIO Wake System Up Status [3] GPIOWKST 0 = GPIO didn’t wake system up. 1 = GPIO wake system up. [2:1] Reserved Oct., 02, 2019 Reserved. Page 109 of 246 Rev 1.11 NUC980 WDT Wake System Up Status [0] WDTWKST 0 = WDT didn’t wake system up. 1 = WDT wake system up. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 110 of 246 Rev 1.11 NUC980 System Wakeup Source Status Register 1 (SYS_WKUPSSR1) Register Offset R/W Description Reset Value SYS_WKUPSSR1 SYS_BA+0x05C R/W System Wakeup Source Status Register 1 31 30 29 28 27 0x0000_0000 26 25 Reserved 23 22 21 Reserved 15 14 LVDWKST 13 6 RTCWKST 5 19 SDHWKST USBDWKST 12 11 10 9 8 CAN3WKST CAN2WKST CAN1WKST CAN0WKST 3 2 1 0 I2C3WKST I2C2WKST I2C1WKST I2C0WKST 4 Reserved Bits Description [31:25] Reserved [24] ADCWKST ADCWKST 20 Reserved 7 24 18 17 16 USBHWKST EMAC1WKST EMAC0WKST Reserved. ADC Wake System Up Status 0 = ADC didn’t wake system up. 1 = ADC wake system up. [23:21] Reserved [20] SDHWKST Reserved. SDH Wake System Up Status NUC980 SERIES DATASHEET 0 = SDH didn’t wake system up. 1 = SDH wake system up. USB Device Wake System Up Status [19] USBDWKST 0 = USB device didn’t wake system up. 1 = USB device wake system up. USB Host Wake System Up Status [18] USBHWKST 0 = USB host didn’t wake system up. 1 = USB host wake system up. Ethernet MAC 1 Wake System Up Status [17] EMAC1WKST 0 = Ethernet MAC 1 didn’t wake system up. 1 = Ethernet MAC 1 wake system up. Ethernet MAC 0 Wake System Up Status [16] EMAC0WKST 0 = Ethernet MAC 0 didn’t wake system up. 1 = Ethernet MAC 0 wake system up. Low Voltage Detect Wake System Up Status [15] LVDWKST 0 = Low Voltage Detect didn’t wake system up. 1 = Low Voltage Detect wake system up. [14:12] Reserved Oct., 02, 2019 Reserved. Page 111 of 246 Rev 1.11 NUC980 CAN 3 Wake System Up Status [11] CAN3WKST 0 = CAN 3 didn’t wake system up. 1 = CAN 3 wake system up. CAN 2 Wake System Up Status [10] CAN2WKST 0 = CAN 2 didn’t wake system up. 1 = CAN 2 wake system up. CAN 1 Wake System Up Status [9] CAN1WKST 0 = CAN 1 didn’t wake system up. 1 = CAN 1 wake system up. CAN 0 Wake System Up Status [8] CAN0WKST 0 = CAN 0 didn’t wake system up. 1 = CAN 0 wake system up. RTC Wake System Up Status [7] RTCWKST 0 = RTC didn’t wake system up. 1 = RTC wake system up. [6:4] Reserved Reserved. I2C 3 Wake System Up Status [3] I2C3WKST 0 = I2C 3 didn’t wake system up. 1 = I2C 3 wake system up. I2C 2 Wake System Up Status [2] I2C2WKST 0 = I2C 2 didn’t wake system up. 1 = I2C 2 wake system up. I2C 1 Wake System Up Status [1] I2C1WKST 0 = I2C 1 didn’t wake system up. 1 = I2C 1 wake system up. NUC980 SERIES DATASHEET I2C 0 Wake System Up Status [0] I2C0WKST 0 = I2C 0 didn’t wake system up. 1 = I2C 0 wake system up. Oct., 02, 2019 Page 112 of 246 Rev 1.11 NUC980 AHB IP Reset Control Register (SYS_AHBIPRST) Register Offset R/W SYS_AHBIPRST SYS_BA+0x060 R/W 31 30 Description Reset Value AHB IP Reset Control Register 0x0000_0000 29 28 27 26 25 Reserved 23 22 CRYPTORST 21 Reserved 15 14 13 24 SDHRST 20 19 18 17 16 FMIRST USBDRST USBHRST EMAC1RST EMAC0RST 12 11 10 9 8 VCAP1RST VCAP0RST Reserved I2SRST Reserved 7 6 5 4 3 2 1 0 GPIORST SDICRST PDMA1RST PDMA0RST EBIRST CPURST Reserved CHIPRST Bits Description [31:25] Reserved [24] SDHRST Reserved. SDIO Controller Reset Enable Bit 0 = SDIO controller reset Disabled. 1 = SDIO controller reset Enabled. Cryptographic Accelerator Reset Enable Bit [23] CRYPTORST 0 = Cryptographic Accelerator reset Disabled. [22:21] Reserved [20] FMIRST NUC980 SERIES DATASHEET 1 = Cryptographic Accelerator reset Enabled. Reserved. FMI Controller Reset Enable Bit 0 = FMI controller reset Disabled. 1 = FMI controller reset Enabled. USB Device Controller Reset Enable Bit [19] USBDRST 0 = USB device controller reset Disabled. 1 = USB device controller reset Enabled. USB Host Controller (EHCI/OHCI) Reset Enable Bit [18] USBHRST 0 = USB host controller (EHCI/OHCI) reset Disabled. 1 = USB host controller (EHCI/OHCI) reset Enabled. Ethernet MAC 1 Reset Enable Bit [17] EMAC1RST 0 = Ethernet MAC 1 reset Disabled. 1 = Ethernet MAC 1 reset Enabled. Ethernet MAC 0 Reset Enable Bit [16] EMAC0RST 0 = Ethernet MAC 0 reset Disabled. 1 = Ethernet MAC 0 reset Enabled. [15:12] Reserved Oct., 02, 2019 Reserved. Page 113 of 246 Rev 1.11 NUC980 Capture Sensor Interface 1 Reset Enable Bit [11] VCAP1RST 0 = Capture sensor interface 1 reset Disabled. 1 = Capture sensor interface 1 reset Enabled. Capture Sensor Interface 0 Reset Enable Bit [10] VCAP0RST 0 = Capture sensor interface 0 reset Disabled. 1 = Capture sensor interface 0 reset Enabled. [9] Reserved Reserved. I2S Controller Reset Enable Bit [8] I2S 0 = I2S controller reset Disabled. 1 = I2S controller reset Enabled. GPIO Reset Enable Bit [7] GPIORST 0 = GPIO reset Disabled. 1 = GPIO reset Enabled. SDRAM Controller Reset Enable Bit [6] SDICRST 0 = SDRAM controller reset Disabled. 1 = SDRAM Controller reset Enabled. PDMA1 Reset Enable Bit [5] PDMA1RST 0 = PDMA1 reset Disabled. 1 = PDMA1 reset Enabled. PDMA0 Reset Enable Bit [4] PDMA0RST 0 = PDMA0 reset Disabled. 1 = PDMA0 reset Enabled. CPU Pulse Reset Enable Bit This bit is used to generate a reset pulse to Arm926EJ-S™ CPU. NUC980 SERIES DATASHEET [2] CPURST When set this bit high, reset controller generates a 6 system clock long reset pulse to Arm926EJ-S™ CPU. After the reset completed, this bit will be clear to low automatically. 0 = CPU pulse reset Disabled. 1 = CPU pulse reset Enabled. [1] Reserved [0] CHIP Reserved. Chip Reset Enable Bit 0 = Chip reset Disabled. 1 = Chip reset Enabled. Oct., 02, 2019 Page 114 of 246 Rev 1.11 NUC980 APB IP Reset Control Register 0 (SYS_APBIPRST0) Register Offset R/W Description Reset Value SYS_APBIPRST0 SYS_BA+0x064 R/W APB IP Reset Control Register 0 31 30 29 28 27 Reserved 0x0000_0000 26 25 24 Reserved UART9RST UART8RST 23 22 21 20 19 18 17 16 UART7RST UART6RST UART5RST UART4RST UART3RST UART2RST UART1RST UART0RST 15 14 13 12 11 10 9 8 TIMER5RST TIMER4RST TIMER3RST TIMER2RST TIMER1RST TIMER0RST 5 4 3 2 1 0 Reserved 7 6 Reserved Bits Description [31:26] Reserved [25] UART9RST AICRST Reserved Reserved. UART 9 Reset Enable Bit 0 = UART 9 reset Disabled. 1 = UART 9 reset Enabled. UART 8 Reset Enable Bit [24] UART8RST 0 = UART 8 reset Disabled. NUC980 SERIES DATASHEET 1 = UART 8 reset Enabled. UART 7 Reset Enable Bit [23] UART7RST 0 = UART 7 reset Disabled. 1 = UART 7 reset Enabled. UART 6 Reset Enable Bit [22] UART6RST 0 = UART 6 reset Disabled. 1 = UART 6 reset Enabled. UART 5 Reset Enable Bit [21] UART5RST 0 = UART 5 reset Disabled. 1 = UART 5 reset Enabled. UART 4 Reset Enable Bit [20] UART4RST 0 = UART 4 reset Disabled. 1 = UART 4 reset Enabled. UART 3 Reset Enable Bit [19] UART3RST 0 = UART 3 reset Disabled. 1 = UART 3 reset Enabled. UART 2 Reset Enable Bit [18] UART2RST 0 = UART 2 reset Disabled. 1 = UART 2 reset Enabled. Oct., 02, 2019 Page 115 of 246 Rev 1.11 NUC980 UART 1 Reset Enable Bit [17] UART1RST 0 = UART 1 reset Disabled. 1 = UART 1 reset Enabled. UART 0 Reset Enable Bit [16] UART0RST 0 = UART 0 reset Disabled. 1 = UART 0 reset Enabled. [15:14] Reserved Reserved. TIMER 5 Reset Enable Bit [13] TIMER5RST 0 = TIMER 5 reset Disabled. 1 = TIMER 5 reset Enabled. TIMER 4 Reset Enable Bit [12] TIMER4RST 0 = TIMER 4 reset Disabled. 1 = TIMER 4 reset Enabled. TIMER 3 Reset Enable Bit [11] TIMER3RST 0 = TIMER 3 reset Disabled. 1 = TIMER 3 reset Enabled. TIMER 2 Reset Enable Bit [10] TIMER2RST 0 = TIMER 2 reset Disabled. 1 = TIMER 2 reset Enabled. TIMER 1 Reset Enable Bit [9] TIMER1RST 0 = TIMER 1 reset Disabled. 1 = TIMER 1 reset Enabled. TIMER 0 Reset Enable Bit [8] TIMER0RST 0 = TIMER 0 reset Disabled. 1 = TIMER 0 reset Enabled. NUC980 SERIES DATASHEET [7:5] Reserved [4] AICRST Reserved. AIC Reset Enable Bit 0 = AIC reset Disabled. 1 = AIC reset Enabled. [3:0] Reserved Oct., 02, 2019 Reserved. Page 116 of 246 Rev 1.11 NUC980 APB IP Reset Control Register 1 (SYS_APBIPRST1) Register Offset R/W Description Reset Value SYS_APBIPRST1 SYS_BA+0x068 R/W APB IP Reset Control Register 1 31 30 29 28 Reserved 23 22 21 0x0000_0000 27 26 25 24 PWM1RST PWM0RST Reserved ADCRST 19 18 17 16 20 Reserved 15 14 Reserved 13 12 11 10 9 8 SMC1RST SMC0RST CAN3RST CAN2RST CAN1RST CAN0RST 7 6 5 4 3 2 1 0 Reserved SPI1RST SPI0RST QSPI0RST I2C3RST I2C2RST I2C1RST I2C0RST Bits Description [31:28] Reserved [27] PWM1RST Reserved. PWM1 Reset Enable Bit 0 = PWM1 reset Disabled. 1 = PWM1 reset Enabled. PWM0 Reset Enable Bit [26] PWM0RST 0 = PWM0 reset Disabled. [25] Reserved [24] ADCRST NUC980 SERIES DATASHEET 1 = PWM0 reset Enabled. Reserved. ADC Reset Enable Bit 0 = ADC reset Disabled. 1 = ADC reset Enabled. [23:14] Reserved Reserved. SMC 1 Reset Enable Bit [13] SMC1RST 0 = SMC 1 reset Disabled. 1 = SMC 1 reset Enabled. SMC 0 Reset Enable Bit [12] SMC0RST 0 = SMC 0 reset Disabled. 1 = SMC 0 reset Enabled. CAN 3 Reset Enable Bit [11] CAN3RST 0 = CAN 3 reset Disabled. 1 = CAN 3 reset Enabled. CAN 2 Reset Enable Bit [10] CAN2RST 0 = CAN 2 reset Disabled. 1 = CAN 2 reset Enabled. Oct., 02, 2019 Page 117 of 246 Rev 1.11 NUC980 CAN 1 Reset Enable Bit [9] CAN1RST 0 = CAN 1 reset Disabled. 1 = CAN 1 reset Enabled. CAN 0 Reset Enable Bit [8] CAN0RST 0 = CAN 0 reset Disabled. 1 = CAN 0 reset Enabled. [7] Reserved Reserved. SPI 1 Reset Enable Bit [6] SPI1RST 0 = SPI 1 reset Disabled. 1 = SPI 1 reset Enabled. SPI 1 Reset Enable Bit [5] SPI0RST 0 = SPI 0 reset Disabled. 1 = SPI 0 reset Enabled. QSPI 0 Reset Enable Bit [4] QSPI0RST 0 = QSPI 0 reset Disabled. 1 = QSPI 0 reset Enabled. I2C 3 Reset Enable Bit [3] I2C3RST 0 = I2C 3 reset Disabled. 1 = I2C 3 reset Enabled. I2C 1 Reset Enable Bit [2] I2C2RST 0 = I2C 2 reset Disabled. 1 = I2C 2 reset Enabled. I2C 1 Reset Enable Bit [1] I2C1RST 0 = I2C 1 reset Disabled. 1 = I2C 1 reset Enabled. NUC980 SERIES DATASHEET I2C 0 Reset Enable Bit [0] I2C0RST 0 = I2C 0 reset Disabled. 1 = I2C 0 reset Enabled. Oct., 02, 2019 Page 118 of 246 Rev 1.11 NUC980 Reset Source Active Status Register (SYS_RSTSTS) Register Offset R/W Description Reset Value SYS_RSTSTS SYS_BA+0x06C R/W Reset Source Active Status Register 0x0000_00XX 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 Reserved Bits Description [31:5] Reserved [5] WDTRSTS 5 4 3 2 1 0 WDTRSTS CPURSTS CHIPRSTS LVRRSTS PINRSTS PORRSTS Reserved. Chip Reset by Watchdog Timer Status 0 = No reset from watchdog timer. 1 = Watchdog timer had issued reset signal to reset the chip. CPU Reset by CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) Status [4] CPURSTS 0 = No CPU reset from CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]). Chip Reset by CHIP (AHBIPRST[0]) Status [3] CHIPRSTS 0 = No reset from CHIP (AHBIPRST[0]). 1 = CHIP (AHBIPRST[0]) has been high to reset CPU. Chip Reset by LVRD Status [2] LVRRSTS 0 = No reset from LVRD. 1 = LVRD had issued reset signal to reset the chip. Chip Reset by NRESET Pin Status [1] PINRSTS 0 = No reset from nRESET pin. 1 = nRESET pin had issued reset signal to reset the chip. Chip Reset by POR Status [0] PORRSTS 0 = No reset from POR. 1 = POR had issued reset signal to reset the chip. Oct., 02, 2019 Page 119 of 246 Rev 1.11 NUC980 SERIES DATASHEET 1 = CPU_LVL (AHBIPRST[1]) or CPU_PLS (AHBIPRST[2]) has been high to reset the CPU. NUC980 GPIOA Low Byte Multiple Function Control Register (SYS_GPA_MFPL) Register Offset SYS_GPA_MF SYS_BA+0x070 PL 31 R/W Description Reset Value R/W GPIOA Low Byte Multiple Function Control Register 0x0XXX_XX00 30 29 28 27 26 MFP_GPA7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPA2 5 4 3 MFP_GPA1 2 MFP_GPA0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPA7 Pin PA.7 Multi-function Pin Selection [27:24] MFP_GPA6 Pin PA.6 Multi-function Pin Selection [23:20] MFP_GPA5 Pin PA.5 Multi-function Pin Selection [19:16] MFP_GPA4 Pin PA.4 Multi-function Pin Selection [15:12] MFP_GPA3 Pin PA.3 Multi-function Pin Selection [11:8] MFP_GPA2 Pin PA.2 Multi-function Pin Selection [7:4] MFP_GPA1 Pin PA.1 Multi-function Pin Selection [3:0] MFP_GPA0 Pin PA.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPA4 MFP_GPA3 7 24 MFP_GPA6 MFP_GPA5 15 25 Page 120 of 246 Rev 1.11 NUC980 GPIOA High Byte Multiple Function Control Register (SYS_GPA_MFPH) Register Offset SYS_GPA_MF SYS_BA+0x074 PH 31 R/W Description Reset Value R/W GPIOA High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPA15 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPA10 5 4 3 MFP_GPA9 2 MFP_GPA8 Description [31:28] MFP_GPA15 Pin PA.15 Multi-function Pin Selection [27:24] MFP_GPA14 Pin PA.14 Multi-function Pin Selection [23:20] MFP_GPA13 Pin PA.13 Multi-function Pin Selection [19:16] MFP_GPA12 Pin PA.12 Multi-function Pin Selection [15:12] MFP_GPA11 Pin PA.11 Multi-function Pin Selection [11:8] MFP_GPA10 Pin PA.10 Multi-function Pin Selection [7:4] MFP_GPA9 Pin PA.9 Multi-function Pin Selection [3:0] MFP_GPA8 Pin PA.8 Multi-function Pin Selection Page 121 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 17 MFP_GPA12 MFP_GPA11 7 24 MFP_GPA14 MFP_GPA13 15 25 Rev 1.11 NUC980 GPIOB Low Byte Multiple Function Control Register (SYS_GPB_MFPL) Register Offset SYS_GPB_MF SYS_BA+0x078 PL 31 R/W Description Reset Value R/W GPIOB Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPB7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPB2 5 4 3 MFP_GPB1 2 MFP_GPB0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPB7 Pin PB.7 Multi-function Pin Selection [27:24] MFP_GPB6 Pin PB.6 Multi-function Pin Selection [23:20] MFP_GPB5 Pin PB.5 Multi-function Pin Selection [19:16] MFP_GPB4 Pin PB.4 Multi-function Pin Selection [15:12] MFP_GPB3 Pin PB.3 Multi-function Pin Selection [11:8] MFP_GPB2 Pin PB.2 Multi-function Pin Selection [7:4] MFP_GPB1 Pin PB.1 Multi-function Pin Selection [3:0] MFP_GPB0 Pin PB.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPB4 MFP_GPB3 7 24 MFP_GPB6 MFP_GPB5 15 25 Page 122 of 246 Rev 1.11 NUC980 GPIOB High Byte Multiple Function Control Register (SYS_GPB_MFPH) Register Offset SYS_GPB_MF SYS_BA+0x07C PH 31 R/W Description Reset Value R/W GPIOB High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 MFP_GPB13 15 14 MFP_GPB12 13 12 11 10 MFP_GPB11 7 6 8 1 0 MFP_GPB10 5 4 3 MFP_GPB9 2 MFP_GPB8 Description [31:24] Reserved Reserved. [23:20] MFP_GPB13 Pin PB.13 Multi-function Pin Selection [19:16] MFP_GPB12 Pin PB.12 Multi-function Pin Selection [15:12] MFP_GPB11 Pin PB.11 Multi-function Pin Selection [11:8] MFP_GPB10 Pin PB.10 Multi-function Pin Selection [7:4] MFP_GPB9 Pin PB.9 Multi-function Pin Selection [3:0] MFP_GPB8 Pin PB.8 Multi-function Pin Selection Page 123 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 9 Rev 1.11 NUC980 GPIOC Low Byte Multiple Function Control Register (SYS_GPC_MFPL) Register Offset SYS_GPC_MF SYS_BA+0x080 PL 31 R/W Description Reset Value R/W GPIOC Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPC7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPC2 5 4 3 MFP_GPC1 2 MFP_GPC0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPC7 Pin PC.7 Multi-function Pin Selection [27:24] MFP_GPC6 Pin PC.6 Multi-function Pin Selection [23:20] MFP_GPC5 Pin PC.5 Multi-function Pin Selection [19:16] MFP_GPC4 Pin PC.4 Multi-function Pin Selection [15:12] MFP_GPC3 Pin PC.3 Multi-function Pin Selection [11:8] MFP_GPC2 Pin PC.2 Multi-function Pin Selection [7:4] MFP_GPC1 Pin PC.1 Multi-function Pin Selection [3:0] MFP_GPC0 Pin PC.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPC4 MFP_GPC3 7 24 MFP_GPC6 MFP_GPC5 15 25 Page 124 of 246 Rev 1.11 NUC980 GPIOC High Byte Multiple Function Control Register (SYS_GPC_MFPH) Register Offset SYS_GPC_MF SYS_BA+0x084 PH 31 R/W Description Reset Value R/W GPIOC High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPC15 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPC10 5 4 3 MFP_GPC9 2 MFP_GPC8 Description [31:28] MFP_GPC15 Pin PC.15 Multi-function Pin Selection [27:24] MFP_GPC14 Pin PC.14 Multi-function Pin Selection [23:20] MFP_GPC13 Pin PC.13 Multi-function Pin Selection [19:16] MFP_GPC12 Pin PC.12 Multi-function Pin Selection [15:12] MFP_GPC11 Pin PC.11 Multi-function Pin Selection [11:8] MFP_GPC10 Pin PC.10 Multi-function Pin Selection [7:4] MFP_GPC9 Pin PC.9 Multi-function Pin Selection [3:0] MFP_GPC8 Pin PC.8 Multi-function Pin Selection Page 125 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 17 MFP_GPC12 MFP_GPC11 7 24 MFP_GPC14 MFP_GPC13 15 25 Rev 1.11 NUC980 GPIOD Low Byte Multiple Function Control Register (SYS_GPD_MFPL) Register Offset SYS_GPD_MF SYS_BA+0x088 PL 31 R/W Description Reset Value R/W GPIOD Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPD7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPD2 5 4 3 MFP_GPD1 2 MFP_GPD0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPD7 Pin PD.7 Multi-function Pin Selection [27:24] MFP_GPD6 Pin PD.6 Multi-function Pin Selection [23:20] MFP_GPD5 Pin PD.5 Multi-function Pin Selection [19:16] MFP_GPD4 Pin PD.4 Multi-function Pin Selection [15:12] MFP_GPD3 Pin PD.3 Multi-function Pin Selection [11:8] MFP_GPD2 Pin PD.2 Multi-function Pin Selection [7:4] MFP_GPD1 Pin PD.1 Multi-function Pin Selection [3:0] MFP_GPD0 Pin PD.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPD4 MFP_GPD3 7 24 MFP_GPD6 MFP_GPD5 15 25 Page 126 of 246 Rev 1.11 NUC980 GPIOD High Byte Multiple Function Control Register (SYS_GPD_MFPH) Register Offset SYS_GPD_MF SYS_BA+0x08C PH 31 R/W Description Reset Value R/W GPIOD High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPD15 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPD10 5 4 3 MFP_GPD9 2 MFP_GPD8 Description [31:28] MFP_GPD15 Pin PD.15 Multi-function Pin Selection [27:24] MFP_GPD14 Pin PD.14 Multi-function Pin Selection [23:20] MFP_GPD13 Pin PD.13 Multi-function Pin Selection [19:16] MFP_GPD12 Pin PD.12 Multi-function Pin Selection [15:12] MFP_GPD11 Pin PD.11 Multi-function Pin Selection [11:8] MFP_GPD10 Pin PD.10 Multi-function Pin Selection [7:4] MFP_GPD9 Pin PD.9 Multi-function Pin Selection [3:0] MFP_GPD8 Pin PD.8 Multi-function Pin Selection Page 127 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 17 MFP_GPD12 MFP_GPD11 7 24 MFP_GPD14 MFP_GPD13 15 25 Rev 1.11 NUC980 GPIOE Low Byte Multiple Function Control Register (SYS_GPE_MFPL) Register Offset SYS_GPE_MFP SYS_BA+0x090 L 31 R/W Description Reset Value R/W GPIOE Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPE7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPE2 5 4 3 MFP_GPE1 2 MFP_GPE0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPE7 Pin PE.7 Multi-function Pin Selection [27:24] MFP_GPE6 Pin PE.6 Multi-function Pin Selection [23:20] MFP_GPE5 Pin PE.5 Multi-function Pin Selection [19:16] MFP_GPE4 Pin PE.4 Multi-function Pin Selection [15:12] MFP_GPE3 Pin PE.3 Multi-function Pin Selection [11:8] MFP_GPE2 Pin PE.2 Multi-function Pin Selection [7:4] MFP_GPE1 Pin PE.1 Multi-function Pin Selection [3:0] MFP_GPE0 Pin PE.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPE4 MFP_GPE3 7 24 MFP_GPE6 MFP_GPE5 15 25 Page 128 of 246 Rev 1.11 NUC980 GPIOE High Byte Multiple Function Control Register (SYS_GPE_MFPH) Register Offset SYS_GPE_MFP SYS_BA+0x094 H 31 R/W Description Reset Value R/W GPIOE High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 25 24 19 18 17 16 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 MFP_GPE12 13 12 11 10 MFP_GPE11 7 6 MFP_GPE10 5 4 3 MFP_GPE9 MFP_GPE8 Description [31:20] Reserved Reserved. [19:16] MFP_GPE12 Pin PE.12 Multi-function Pin Selection [15:12] MFP_GPE11 Pin PE.11 Multi-function Pin Selection [11:8] MFP_GPE10 Pin PE.10 Multi-function Pin Selection [7:4] MFP_GPE9 Pin PE.9 Multi-function Pin Selection [3:0] MFP_GPE8 Pin PE.8 Multi-function Pin Selection Page 129 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 2 Rev 1.11 NUC980 GPIOF Low Byte Multiple Function Control Register (SYS_GPF_MFPL) Register Offset SYS_GPF_MFP SYS_BA+0x098 L 31 R/W Description Reset Value R/W GPIOF Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPF7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPF2 5 4 3 MFP_GPF1 2 MFP_GPF0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPF7 Pin PF.7 Multi-function Pin Selection [27:24] MFP_GPF6 Pin PF.6 Multi-function Pin Selection [23:20] MFP_GPF5 Pin PF.5 Multi-function Pin Selection [19:16] MFP_GPF4 Pin PF.4 Multi-function Pin Selection [15:12] MFP_GPF3 Pin PF.3 Multi-function Pin Selection [11:8] MFP_GPF2 Pin PF.2 Multi-function Pin Selection [7:4] MFP_GPF1 Pin PF.1 Multi-function Pin Selection [3:0] MFP_GPF0 Pin PF.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPF4 MFP_GPF3 7 24 MFP_GPF6 MFP_GPF5 15 25 Page 130 of 246 Rev 1.11 NUC980 GPIOF High Byte Multiple Function Control Register (SYS_GPF_MFPH) Register Offset SYS_GPF_MFP SYS_BA+0x09C H 31 R/W Description Reset Value R/W GPIOF High Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 25 24 19 18 17 16 9 8 1 0 Reserved 23 22 21 20 Reserved 15 14 MFP_GPF12 13 12 11 10 MFP_GPF11 7 6 MFP_GPF10 5 4 3 MFP_GPF9 MFP_GPF8 Description [31:20] Reserved Reserved. [19:16] MFP_GPF12 Pin PF.12 Multi-function Pin Selection [15:12] MFP_GPF11 Pin PF.11 Multi-function Pin Selection [11:8] MFP_GPF10 Pin PF.10 Multi-function Pin Selection [7:4] MFP_GPF9 Pin PF.9 Multi-function Pin Selection [3:0] MFP_GPF8 Pin PF.8 Multi-function Pin Selection Page 131 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 2 Rev 1.11 NUC980 GPIOG Low Byte Multiple Function Control Register (SYS_GPG_MFPL) Register Offset SYS_GPG_MF SYS_BA+0x0A0 PL 31 R/W Description Reset Value R/W GPIOG Low Byte Multiple Function Control Register 0x0000_0000 30 29 28 27 26 MFP_GPG7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPG2 5 4 3 MFP_GPG1 2 MFP_GPG0 NUC980 SERIES DATASHEET Bits Description [31:28] MFP_GPG7 Pin PG.7 Multi-function Pin Selection [27:24] MFP_GPG6 Pin PG.6 Multi-function Pin Selection [23:20] MFP_GPG5 Pin PG.5 Multi-function Pin Selection [19:16] MFP_GPG4 Pin PG.4 Multi-function Pin Selection [15:12] MFP_GPG3 Pin PG.3 Multi-function Pin Selection [11:8] MFP_GPG2 Pin PG.2 Multi-function Pin Selection [7:4] MFP_GPG1 Pin PG.1 Multi-function Pin Selection [3:0] MFP_GPG0 Pin PG.0 Multi-function Pin Selection Oct., 02, 2019 17 MFP_GPG4 MFP_GPG3 7 24 MFP_GPG6 MFP_GPG5 15 25 Page 132 of 246 Rev 1.11 NUC980 GPIOG High Byte Multiple Function Control Register (SYS_GPG_MFPH) Register Offset SYS_GPG_MF SYS_BA+0x0A4 PH 31 R/W Description Reset Value R/W GPIOG High Byte Multiple Function Control Register 0xXXXX_X000 30 29 28 27 26 MFP_GPG15 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 MFP_GPG10 5 4 3 MFP_GPG9 2 MFP_GPG8 Description [31:28] MFP_GPG15 Pin PG.15 Multi-function Pin Selection [27:24] MFP_GPG14 Pin PG.14 Multi-function Pin Selection [23:20] MFP_GPG13 Pin PG.13 Multi-function Pin Selection [19:16] MFP_GPG12 Pin PG.12 Multi-function Pin Selection [15:12] MFP_GPG11 Pin PG.11 Multi-function Pin Selection [11:8] MFP_GPG10 Pin PG.10 Multi-function Pin Selection [7:4] MFP_GPG9 Pin PG.9 Multi-function Pin Selection [3:0] MFP_GPG8 Pin PG.8 Multi-function Pin Selection Page 133 of 246 NUC980 SERIES DATASHEET Bits Oct., 02, 2019 17 MFP_GPG12 MFP_GPG11 7 24 MFP_GPG14 MFP_GPG13 15 25 Rev 1.11 NUC980 DDR I/O Driving Strength Control Register (SYS_DDR_DSCTL) Register Offset R/W Description Reset Value SYS_DDR_DS CTL SYS_BA+0x0F0 R/W DDR I/O Driving Strength Control Register 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 DATA_DS Bits Description [31:8] Reserved 5 4 ADDR_DS CTRL_DS CLK_DS Reserved. DDR Data I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as data. [7:6] DATA_DS 00 = Reserved. 01 = Reduced Strength. 10 = Reserved. 11 = Full Strength. NUC980 SERIES DATASHEET DDR Address I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as address. [5:4] ADDR_DS 00 = Reserved. 01 = Reduced Strength. 10 = Reserved. 11 = Full Strength. DDR Control I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as control signals. [3:2] CTRL_DS 00 = Reserved. 01 = Reduced Strength. 10 = Reserved. 11 = Full Strength. DDR Clock I/O Driving Strength Selection This bit controls the driving strength for DDR I/O used as clock. [1:0] CLK_DS 00 = Reserved. 01 = Reduced Strength. 10 = Reserved. 11 = Full Strength. Oct., 02, 2019 Page 134 of 246 Rev 1.11 NUC980 GPIOB Low Byte Driving Strength Control Register (SYS_GPBL_DSCTL) Register Offset SYS_GPBL_DS SYS_BA+0x0F4 CTL 31 R/W Description Reset Value R/W GPIOB Low Byte Driving Strength Control Register 0x4444_4444 30 29 28 27 26 DS_GPB7 23 22 21 14 20 19 18 13 6 12 11 16 10 9 8 1 0 DS_GPB2 5 4 3 DS_GPB1 Bits 17 DS_GPB4 DS_GPB3 7 24 DS_GPB6 DS_GPB5 15 25 2 DS_GPB0 Description Pin PB.7 Driving Strength Selection This field controls the pin PB.7 driving strength 000 = Pin PB.7 driving strength is 2.2mA. 001 = Pin PB.7 driving strength is 6.5mA. [31:28] DS_GPB7 010 = Pin PB.7 driving strength is 8.7mA. 011 = Pin PB.7 driving strength is 13.0mA. NUC980 SERIES DATASHEET 100 = Pin PB.7 driving strength is 15.2mA. 101 = Pin PB.7 driving strength is 19.5mA. 110 = Pin PB.7 driving strength is 21.7mA. 111 = Pin PB.7 driving strength is 26.1mA. Others = Reserved. Pin PB.6 Driving Strength Selection This field controls the pin PB.6 driving strength 000 = Pin PB.6 driving strength is 2.2mA. 001 = Pin PB.6 driving strength is 6.5mA. [27:24] DS_GPB6 010 = Pin PB.6 driving strength is 8.7mA. 011 = Pin PB.6 driving strength is 13.0mA. 100 = Pin PB.6 driving strength is 15.2mA. 101 = Pin PB.6 driving strength is 19.5mA. 110 = Pin PB.6 driving strength is 21.7mA. 111 = Pin PB.6 driving strength is 26.1mA. Others = Reserved. Oct., 02, 2019 Page 135 of 246 Rev 1.11 NUC980 Pin PB.5 Driving Strength Selection This field controls the pin PB.5 driving strength 000 = Pin PB.5 driving strength is 2.2mA. 001 = Pin PB.5 driving strength is 6.5mA. [23:20] DS_GPB5 010 = Pin PB.5 driving strength is 8.7mA. 011 = Pin PB.5 driving strength is 13.0mA. 100 = Pin PB.5 driving strength is 15.2mA. 101 = Pin PB.5 driving strength is 19.5mA. 110 = Pin PB.5 driving strength is 21.7mA. 111 = Pin PB.5 driving strength is 26.1mA. Others = Reserved. Pin PB.4 Driving Strength Selection This field controls the pin PB.4 driving strength 000 = Pin PB.4 driving strength is 2.2mA. 001 = Pin PB.4 driving strength is 6.5mA. [19:16] DS_GPB4 010 = Pin PB.4 driving strength is 8.7mA. 011 = Pin PB.4 driving strength is 13.0mA. 100 = Pin PB.4 driving strength is 15.2mA. 101 = Pin PB.4 driving strength is 19.5mA. 110 = Pin PB.4 driving strength is 21.7mA. 111 = Pin PB.4 driving strength is 26.1mA. Others = Reserved. Pin PB.3 Driving Strength Selection This field controls the pin PB.3 driving strength NUC980 SERIES DATASHEET 000 = Pin PB.3 driving strength is 2.2mA. 001 = Pin PB.3 driving strength is 6.5mA. [15:12] DS_GPB3 010 = Pin PB.3 driving strength is 8.7mA. 011 = Pin PB.3 driving strength is 13.0mA. 100 = Pin PB.3 driving strength is 15.2mA. 101 = Pin PB.3 driving strength is 19.5mA. 110 = Pin PB.3 driving strength is 21.7mA. 111 = Pin PB.3 driving strength is 26.1mA. Others = Reserved. Pin PB.2 Driving Strength Selection This field controls the pin PB.2 driving strength 000 = Pin PB.2 driving strength is 2.2mA. 001 = Pin PB.2 driving strength is 6.5mA. [11:8] DS_GPB2 010 = Pin PB.2 driving strength is 8.7mA. 011 = Pin PB.2 driving strength is 13.0mA. 100 = Pin PB.2 driving strength is 15.2mA. 101 = Pin PB.2 driving strength is 19.5mA. 110 = Pin PB.2 driving strength is 21.7mA. 111 = Pin PB.2 driving strength is 26.1mA. Others = Reserved. Oct., 02, 2019 Page 136 of 246 Rev 1.11 NUC980 Pin PB.1 Driving Strength Selection This field controls the pin PB.1 driving strength 000 = Pin PB.1 driving strength is 2.2mA. 001 = Pin PB.1 driving strength is 6.5mA. [7:4] DS_GPB1 010 = Pin PB.1 driving strength is 8.7mA. 011 = Pin PB.1 driving strength is 13.0mA. 100 = Pin PB.1 driving strength is 15.2mA. 101 = Pin PB.1 driving strength is 19.5mA. 110 = Pin PB.1 driving strength is 21.7mA. 111 = Pin PB.1 driving strength is 26.1mA. Others = Reserved. Pin PB.0 Driving Strength Selection This field controls the pin PB.0 driving strength 000 = Pin PB.0 driving strength is 2.2mA. 001 = Pin PB.0 driving strength is 6.5mA. [3:0] DS_GPB0 010 = Pin PB.0 driving strength is 8.7mA. 011 = Pin PB.0 driving strength is 13.0mA. 100 = Pin PB.0 driving strength is 15.2mA. 101 = Pin PB.0 driving strength is 19.5mA. 110 = Pin PB.0 driving strength is 21.7mA. 111 = Pin PB.0 driving strength is 26.1mA. Others = Reserved. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 137 of 246 Rev 1.11 NUC980 Power-On-reset Disable Control Register (SYS_PORDISCR) Register Offset SYS_PORDISC SYS_BA+0x100 R 31 30 R/W Description Reset Value R/W Power-On-reset Disable Control Register 0x0000_00XX 29 28 27 26 25 24 19 18 17 16 11 10 9 8 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 POR_DIS_CODE 7 6 5 4 3 POR_DIS_CODE Bits Description [31:16] Reserved Reserved. Power-on-reset Disable Code (Write-protection Bits) When powered on, the Power-On-Reset (POR) circuit generates a reset signal to reset whole chip function. However, after power is ready, the POR circuit would consume a few power. To minimize the POR circuit power consumption, user to disable POR circuit by writing 0x5AA5 to this field. [15:0] POR_DIS_CODE NUC980 SERIES DATASHEET The POR circuit will become active again when this field is set to other value or chip is reset by other reset source, including /RESET pin, Watchdog, LVR reset and the software chip reset function. This field is protected. It means that before programming it, user has to write “59h”, “16h” and “88h” to address 0xB000_01FC continuously to disable the register protection. Refer to the register REGWRPROT at address SYS_BA+0x1FC for detail. Oct., 02, 2019 Page 138 of 246 Rev 1.11 NUC980 Reset Pin De-bounce Control Register (SYS_RSTDEBCTL) Register Offset SYS_RSTDEB SYS_BA+0x10C CTL 31 30 R/W Description Reset Value R/W Reset Pin De-bounce Control Register 0x0000_04B0 29 28 RSTDEBEN 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 DEBCNT 7 6 5 4 DEBCNT Bits Description Reset Pin De-bounce Enable Bit [31] RSTDEBEN 0 = Reset pin de-bounce Disabled. (Default) 1 = Reset pin de-bounce Enabled. [31:16] Reserved Reserved. Power-on-reset Disable Code (Write-protection Bits) [15:0] DEBCNT This 16-bit external RESET De-bounce Counter can specify the external RESET debounce time up to around 5.46ms (0xFFFF) @ XIN=12 MHz. NUC980 SERIES DATASHEET The default external RESET de-bounce time is 0.1ms (0x04B0) @ XIN = 12 MHz. Oct., 02, 2019 Page 139 of 246 Rev 1.11 NUC980 Register Write-protection Control Register (SYS_REGWPCTL) Some of the system control registers need to be protected to avoid inadvertent write and disturb the chip operation. These system control registers are protected after the power-on reset till user to disable register protection. For user to program these protected registers, a register protection disable sequence needs to be followed by a special programming. The register protection disable sequence is writing the data “59h”, “16h” “88h” to the register REGWRPROT address at 0xB000_01FC continuously. Any different data value, different sequence or any other write to other address during these three data writing will abort the whole sequence. After the protection is disabled, user can check the protection disable bit at address 0xB000_01FC bit0, 1 is protection disable, and 0 is protection enable. Then user can update the target protected register value and then write any data to the address “0xB000_01FC” to enable register protection. This register is write for disable/enable register protection and read for the REGWPCTL status Register Offset SYS_REGWPC SYS_BA+0x1FC TL 31 30 R/W Description Reset Value R/W Register Write-protection Control Register 0x0000_0000 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 Reserved 7 6 5 4 REGWPCTL NUC980 SERIES DATASHEET Bits Description [31:8] Reserved Reserved. Register Write Protection Code Some registers have write-protection function. Writing these registers has to disable the protected function by writing the sequence value “59h”, “16h”, “88h” to this field. After this sequence is completed, the REGWPCTL bit will be set to 1 and write-protection registers can be normal write. [7:0] REGWPCTL REGWPCTL[0] Register Write Protection Disable Index 0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers. Oct., 02, 2019 Page 140 of 246 Rev 1.11 NUC980 Register Write-protection Disable Indicator (Read Only) 0 = Write-protection Enabled for writing protected registers. Any write to the protected register is ignored. 1 = Write-protection Disabled for writing protected registers. The protected registers are: SYS_PDID: Product Identifier Register, address 0xB000_0000. SYS_PWRON: Power-On Setting Register, address 0xB000_0004. [0] REGWPCTL SYS_MISCFCR: Miscellaneous Function Control Register, address 0xB000_0030. SYS_AHBIPRST: AHB IP Reset Control Register, address 0xB000_0060. SYS_APBIPRST0: APB IP Reset Control Register 0, address 0xB000_0064. SYS_APBIPRST1: APB IP Reset Control Register 1, address 0xB000_0068. SYS_PORDISCR: Power-On-Reset Disable Control Register, address 0xB000_0100. SYS_RSTDEBCTL: Reset Pin De-bounce Control Register, address 0xB000_010C. WDT_CTL: WDT Control Register, address 0xB004_0000 WDT_ALTCTL: WDT Alternative Control Register, address 0xB004_0004 NUC980 SERIES DATASHEET Oct., 02, 2019 Page 141 of 246 Rev 1.11 NUC980 6.3 Clock Controller 6.3.1 Overview The clock controller generates all clocks for Video, Audio, CPU, system bus and all functionalities. This chip includes two PLL modules. The clock source for each functionality comes from the PLL, or from the external crystal input directly. For each clock there is a bit on the CLKEN register to control the clock ON or OFF individually, and the divider setting is in the CLK_DIVCTL register. The register can also be used to control the clock enable or disable for power control. 6.3.2 Features  Supports two PLLs, up to 500 MHz, for high performance system operation  External 12 MHz high speed crystal input for precise timing operation  External 32.768 kHz low speed crystal input for RTC function and low speed clock source NUC980 SERIES DATASHEET Oct., 02, 2019 Page 142 of 246 Rev 1.11 NUC980 6.3.3 Block Diagram 6.3.3.1 Clock Controller Top View XTALIN12M (12 MHz) ADC_SW_DIV APLL XTALIN32K (32.768 kHz) PCLK0 PCLK1 PCLK2 UPLL APLLFOUT UPLLFOUT APLL1to8 UPLL1to8 ADivCLK[7:0] ADO_SW_DIV UDivCLK[7:0] SD0_SW_DIV SD1_SW_DIV SEN0_SW_DIV ÷ 4096 ÷ 512 ECLKTMR0 SEN1_SW_DIV UART0_SW_DIV TMR0_SW_DIV UART1_SW_DIV ECLKTMR1 TMR1_SW_DIV UART2_SW_DIV ECLKTMR2 TMR2_SW_DIV UART3_SW_DIV UART4_SW_DIV ECLKTMR3 ADC_CLK ECLKI2S SD0_CLK SD1_CLK SEN0_CLK SEN1_CLK ECLKUART0 ECLKUART1 ECLKUART2 ECLKUART3 ECLKUART4 TMR3_SW_DIV UART5_SW_DIV ECLKTMR4 TMR4_SW_DIV ECLKTMR5 UART6_SW_DIV UART7_SW_DIV TMR5_SW_DIV UART8_SW_DIV ECLKWDT WDT_SW_DIV QSPI0_SW_DIV WWDT_SW_DIV USB_CLK (48 MHz) SPI0_SW_DIV ECLKUART6 ECLKUART7 ECLKUART8 ECLKUART9 NUC980 SERIES DATASHEET ECLKWWDT UART9_SW_DIV ECLKUART5 ECLKQSPI0 ECLKSPI0 USB_SW_DIV RMII0_REFCLK (50 MHz) EMCA0_RXCLK EMCA0_TXCLK SPI1_SW_DIV RMII1_REFCLK (50 MHz) EMAC1_RXCLK EMAC1_TXCLK ECLKSPI1 EMAC0_CLK_DIV (÷ 2, ÷ 20) SMC0_SW_DIV EMAC1_CLK_DIV (÷ 2, ÷ 20) SMC1_SW_DIV ECLKUART8 ECLKUART9 SYS_CLK SYS_SW_DIV CPU_HCLK CPUCLK, HCLK1, HCLK2, HCLK3, HCLK4, PCLK, HCLKSRAM, DDR_CLK, DRAM_CLK, HCLKI2S, HCLKLCD, HCLKUSBH, HCLKUSBD, HCLKEMAC0, HCLKEMAC1 ... PCLKSPI0, PCLKSPI1, PCLKADC, PCLKI2C, PCLPWM, PCLKSMC0, PCLKSMC1 ... HCLK4 HCLK3 EMC0_MDCLK_DIV EMC1_MDCLK_DIV EMAC0_MDCLK EMAC1_MDCLK Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-1 Clock Controller Block Diagram Oct., 02, 2019 Page 143 of 246 Rev 1.11 NUC980 6.3.3.2 ADC Controller Clock Divider XTALIN12M APLLFout CLK_SW4 (4-to-1) (MUX) ADC_SrcCLK ADC_CLK CLK_DIVn (÷ (ADC_N+1)) UPLLFout ADC_S (CLK_DIVCTL7[20:19]) ADC_N (CLK_DIVCTL7[31:24]) ADC (CLK_PCLKEN1[24]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-2 ADC Controller Clock Divider Block Diagram 6.3.3.3 SD Card Host Controller Clock Divider X = 0 and m = 3 X = 1 and m = 9 XTALIN12M APLLFout CLK_SW4 (4-to-1) (MUX) SDx_SrcCLK CLK_DIVn (÷ (SDx_N+1)) SDx_CLK UPLLFout NUC980 SERIES DATASHEET SDx_S (CLK_DIVCTLm[4:3]) SDx_N (CLK_DIVCTLm[15:8]) SDx (CLK_HCLKEN[x*8+22]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-3 SD Card Host Controller Clock Divider Block Diagram Oct., 02, 2019 Page 144 of 246 Rev 1.11 NUC980 6.3.3.4 Timer Clock Divider M = 0, x = 0, 1, 4, 5 M = 1, x = 2, 3 XTALIN12M PCLKm CLK_SW4 (4-to-1) (MUX) PCLKm/4096 ECLKETMRx TIMERx_SrcCLK XTALIN32K TMRxSEL (CLK_DIVCTL8[x*2+17 : x*2+16]) TMRxCKEN (CLK_PCLKEN0[x+8]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-4 Timer Clock Divider Clock Diagram 6.3.3.5 Ethernet MAC Controller Clock Divider x = 0, 1 RMIIx_REFCLK (50 MHz) ÷ 2 EMACx_RXCLK 25 MHz CLK_SW4 (2-to-1) (MUX) EMACx_SrcCLK EMACx_TXCLK 2.5 MHz ÷ 20 OPMOD (EMACx_MCMDR[20]) EMACx (CLK_HCLKEN[x+16]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. 6.3.3.6 2 I S Controller Clock Divider XTALIN12M APLLFout CLK_SW4 (4-to-1) (MUX) I2S_SrcCLK CLK_DIVn (÷ (I2S_N+1)) ECLKI2S UPLLFout I2S_S (CLK_DIVCTL1[20:19]) I2S_N (CLK_DIVCTL1[31:24]) I2S (CLK_HCLKEN[24]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. 2 Figure 6.3-6 I S Controller Clock Divider Block Diagram Oct., 02, 2019 Page 145 of 246 Rev 1.11 NUC980 SERIES DATASHEET Figure 6.3-5 Ethernet MAC Controller Clock Divider Block Diagram NUC980 6.3.3.7 Reference Clock Output Divider XT1_IN APLLFout ACLKOut CLK_SW4 (4-to-1) (MUX) CKO_SrcCLK CKO_CLK CLK_DIVn (÷ (CKO_N+1)) UCLKout UPLLFout CKO_S (CLK_DIVCTL9[20:19]) CKO_N (CLK_DIVCTL9[31:24]) CKO (CLK_HCLKEN[15]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-7 Reference Clock Output Divider Block Diagram 6.3.3.8 Smart Card Host Controller Clock Divider x = 0, 1 ECLKSMCx CLK_DIVn (÷ (SMCx_N+1)) XTALIN12M SMCx_N (CLK_DIVCTL6[x*4+27:x*4+24]) SMCx (CLK_PCLKEN1[x+12]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-8 Smart Card Host Controller Clock Divider Block Diagram NUC980 SERIES DATASHEET 6.3.3.9 CMOS Sensor Clock Divider X = 0 and m = 3 X = 1 and m = 2 XTALIN12M APLLFout CLK_DIVn ÷ (SENSORx_SDIV+1) ACLKOut CLK_SW4 (4-to-1) (MUX) SENSORx_SDIV (CLK_DIVCTLm[18:16]) SENx_SrcCLK CLK_DIVn (÷ (SENSORx_N+1)) SENx_CLK UCLKout UPLLFout CLK_DIVn ÷ (SENSORx_SDIV+1) SENSORx_S (CLK_DIVCTLm[20:19]) SENSORx_N (CLK_DIVCTLm[27:24]) SENSOR (CLK_HCLKEN[27]) & VCAPx (CLK_HCLKEN[x*5+26]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-9 CMOS Sensor Controller Divider Block Diagram Oct., 02, 2019 Page 146 of 246 Rev 1.11 NUC980 6.3.3.10 UART Clock Divider m = 4, x = 0, 1, 2, 3 m = 5, x = 4, 5, 6, 7 m = 6, x = 8, 9 XT1_IN (12 MHz) APLLFout CLK_SW4 (4-to-1) (MUX) UARTX_SrcCLK ECLKUARTx CLK_DIVn (÷ (UARTX_N+1)) UPLLFout X32_IN (32.768 kHz) UARTX_S (CLK_DIVCTLm) UARTX_N (CLK_DIVCTLm) UARTx (CLK_PCLKEN0[x+16]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-10 UART Clock Divider Block Diagram 6.3.3.11 USB 1.1 Host 48 MHz Clock Divider USBPHY0_480M CLK_SW2 (2-to-1) (MUX) USBPHY1_480M USB11_SrcCLK USBID (SYS_PWRON[16]) USB_CLK 48MZ CLK_DIVn (÷ 10) USBH (CLK_HCLKEN[18]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. 6.3.3.12 Watchdog Timer Clock Divider XTALIN12M XT1_IN/512 PCLK2/4096 CLK_SW4 (4-to-1) (MUX) ECLKWDT WDT_SrcCLK XTALIN32K WDT_S (CLK_DIVCTL8[9:8]) WDT (CLK_PCLKEN0[0]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-12 Watchdog Timer Clock Divider Block Diagram Oct., 02, 2019 Page 147 of 246 Rev 1.11 NUC980 SERIES DATASHEET Figure 6.3-11 USB 1.1 Host Controller 48 MHz Clock Divider Block Diagram NUC980 6.3.3.13 Windowed Watchdog Timer Clock Divider XTALIN12M XT1_IN/512 PCLK2/4096 CLK_SW4 (4-to-1) (MUX) ECLKWWDT WWDT_SrcCLK XTALIN32K WWDT_S (CLK_DIVCTL8[11:10]) WWDT (CLK_PCLKEN0[1]) Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-13 Windowed Watchdog Timer Clock Divider Block Diagram NUC980 SERIES DATASHEET Oct., 02, 2019 Page 148 of 246 Rev 1.11 NUC980 6.3.3.14 CPU_HCLK Clock Generator APLL ADivCLK[7:0] APLL 1to8 UPLL DRAM (CLK_HCLKEN[10]) APLLFOUT DDR_CLK HCLK (CLK_HCLKEN[1]) ÷ 2 DRAM_CLK ÷ 2 HCLK UPLLFOUT UPLL 1to8 SRAM (CLK_HCLKEN[8]) HCLKSRAM HCLK1 (CLK_HCLKEN[2]) | HCLK3 (CLK_HCLKEN[3]) | HCLK4 (CLK_HCLKEN[4]) UDivCLK[7:0] HCLK2 XT1_IN HCLK3 (CLK_HCLKEN[3]) SYSDIVEN2, SYSTEM_S[4:3] SYS_SW_DIV CPU_HCLK Clock Generator CPUDIVEN2 EMAC1 (CLK_HCLKEN[17]) HCLK1 EMAC1_MDCLK USBH (CLK_HCLKEN[18]) HCLKUSBH USBD (CLK_HCLKEN[19]) HCLKUSBD FMI (CLK_HCLKEN[20]) HCLKFMI NAND (CLK_HCLKEN[21]) HCLKNAND ÷ 2 CPUCLK CPU HCLKEMAC1 ÷ (MDCLK_N+1) SYS_CLK ÷ 1 or ÷ 2 HCLK3 (CLK_HCLKEN[0]) HCLK1 (CLK_HCLKEN[2]) CRYPTO(CLK_HCLKEN[23]) HCLKCRYPTO VCAP1 (CLK_HCLKEN[31]) HCLKVCAP1 HCLKPDMA0 PDMA0(CLK_HCLKEN[12]) EBI (CLK_HCLKEN[ 9]) HCLKPDMA1 PDMA1(CLK_HCLKEN[13]) GPIO (CLK_HCLKEN[11]) HCLKPIC PIC PCLK0 PCLK0 (CLK_HCLKEN[5]) (CLK_HCLKEN[7]) HCLKEBI HCLKGPIO ÷ 2 HCLK4 (CLK_HCLKEN[4]) HCLK4 EMAC0 (CLK_HCLKEN[16]) HCLKEMAC0 PCLKI2C0 I2C0CKEN(CLK_PCLKEN1[0]) PCLKI2C2 I2C2CKEN(CLK_PCLKEN1[2]) PCLKQSPI0 QSPI0CKEN(CLK_PCLKEN1[4]) PCLKSPI1 SPI1CKEN(CLK_PCLKEN1[6]) PCLKTIMER0 TMR0CKEN(CLK_PCLKEN0[8]) PCLKTIMER1 TMR1CKEN(CLK_PCLKEN0[9]) PCLKTIMER4 PCLKTIMER5 PCLKUART0 UART0CKEN(CLK_PCLKEN0[16]) WWDTCKEN(CLK_PCLKEN0[1]) PCLKWWDT PCLKUART2 UART2CKEN(CLK_PCLKEN0[18]) CAN0CKEN(CLK_PCLKEN1[8]) PCLKCAN0 PCLKUART4 UART4CKEN(CLK_PCLKEN0[20]) CAN1CKEN(CLK_PCLKEN1[9]) PCLKCAN1 PCLKUART6 UART6CKEN(CLK_PCLKEN0[22]) CAN2CKEN(CLK_PCLKEN1[10]) PCLKCAN2 PCLKUART8 UART8CKEN(CLK_PCLKEN0[24]) CAN3CKEN(CLK_PCLKEN1[11]) PCLKCAN3 SMC0CKEN(CLK_PCLKEN1[12]) PCLKSMC0 SMC1CKEN(CLK_PCLKEN1[13]) PCLKSMC1 PWM0CKEN(CLK_PCLKEN1[26]) PCLKPWM0 PWM1CKEN(CLK_PCLKEN1[27]) PCLKPWM1 I2S (CLK_HCLKEN[30]) HCLKSDH HCLKI2S (CLK_HCLKEN[24]) VCAP0 (CLK_HCLKEN[26]) HCLKVCAP0 TMR4CKEN(CLK_PCLKEN0[12]) RTCCKEN(CLK_PCLKEN0[2]) PCLKRTC TMR5CKEN(CLK_PCLKEN0[13]) WDTCKEN(CLK_PCLKEN0[0]) PCLKWDT I2C1CKEN(CLK_PCLKEN1[1]) PCLKI2C3 I2C3CKEN(CLK_PCLKEN1[3]) PCLKSPI0 SPI0CKEN(CLK_PCLKEN1[5]) PCLKTIMER2 TMR2CKEN(CLK_PCLKEN0[10]) PCLKTIMER3 TMR3CKEN(CLK_PCLKEN0[11]) PCLKUART1 UART1CKEN(CLK_PCLKEN0[17]) UART3CKEN(CLK_PCLKEN0[19]) UART5CKEN(CLK_PCLKEN0[21]) UART7CKEN(CLK_PCLKEN0[23]) NUC980 SERIES DATASHEET PCLK2 PCLK1 (CLK_HCLKEN[6]) PCLKUART3 SDH PCLK2 (CLK_HCLKEN[14]) PCLK1 PCLKI2C1 EMAC0_MDCLK ÷ (MDCLK_N+1) PCLKUART5 PCLKUART7 UART9CKEN(CLK_PCLKEN0[25]) PCLKUART9 ADCCKEN(CLK_PCLKEN1[24]) PCLKADC Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Note: Before clock switching, both the pre-selected and newly selected clock sources must be turned on and stable. Figure 6.3-14 CPU_HCLK Clock Generator Block Diagram Oct., 02, 2019 Page 149 of 246 Rev 1.11 NUC980 6.3.4 Functional Description 6.3.4.1 Power Management This chip provides four power management scenarios, including Power-down, Idle and Normal Operating modes, to manage the power consumption. The peripheral clocks can be Enabled / Disabled individually by controlling the corresponding bit in CLKSEL control register. User can turn-off the unused modules’ clock for power saving. 6.3.4.2 Normal Operating Mode In this mode, CPU runs normally and clocks of all functionalities are on. The clock frequency of CPU, DRAM, AHB peripherals and APB peripherals are 300 MHz, 150 MHz, 150 MHz and 75 MHz, respectively. 6.3.4.3 Idle Mode When CPU is not busy, user can put Arm926EJ-S™ processor into a low-power state by the wait for interrupt instruction: MCR p15, 0, , c7, c0, 4 This instruction switches the Arm926EJ-S™ processor into a low-power state until either an interrupt (IRQ or FIQ) or a debug request occurs. In this mode, the clocks of all functionalities are on. The clock frequency of DRAM, AHB peripherals and APB peripherals are 150 MHz, 150 MHz and 75 MHz. 6.3.4.4 Power-down Mode To reduce power consumption further, user could put the chip into Power-down mode by clearing XTAL_EN (CLK_PMCON[0]) to 0 before waiting for interrupt instruction: MCR p15, 0, , c7, c0, 4 In this mode, all clocks (clocks for all functionalities, CPU and the HXT (Ext. Crystall Osc. 12 MHz) stop, except LXT (Ext. Crystal Osc. 32.768 kHz), with SRAM retention. NUC980 SERIES DATASHEET The mechanisms shown below could wake chip up from Power-down mode:  EINT0, EINT1, EINT2 or EINT3 (External Interrupt) pin toggled.  GPIO pin toggled.  Timer 0/1/2/3/4/5 timeout or capture interrupt is active.  WDT time-out interrupt is active.  RTC alarm or relative alarm interrupt is active.  UART 0/1/2/3/4/5/6/7/8/9 – UARTx_nCTS pin toggleed (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9). – UARTx_RXD pin goes low level (x is 0, 1, 2, 3, 4, 5, 6, 7, 8 or 9). – Received data FIFO reached threshold. – Received data FIFO threshold time-out. – RS-485 address match (AAD Mode). 2  I C slave mode address match.  EMAC 0/1 received a Magic Packet.  HSUSBD detected a VBUS change event or USB bus RESET/RESUME event.  USB 1.1 host controller detected a connect/dis-connect/remote-wakeup event. Oct., 02, 2019 Page 150 of 246 Rev 1.11 NUC980  CANx_RXD pin goes low level (x is 0, 1, 2 or 3).  SDH detected card pulg/un-plug event or SDIO card interrupt. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 151 of 246 Rev 1.11 NUC980 6.3.5 Registers Map R: read only, W: write only, R/W: both read and write Register Offset R/W Description Reset Value CLK Base Address: CLK_BA = 0xB000_0200 NUC980 SERIES DATASHEET CLK_PMCON CLK_BA+0x000 R/W Power Management Control Register 0xFFFF_FF03 CLK_HCLKEN CLK_BA+0x010 R/W AHB Devices Clock Enable Control Register 0x0000_4527 CLK_PCLKEN0 CLK_BA+0x018 R/W APB Devices Clock Enable Control Register 0 0x0000_000X CLK_PCLKEN1 CLK_BA+0x01C R/W APB Devices Clock Enable Control Register 1 0x0000_0000 CLK_DIVCTL0 CLK_BA+0x020 R/W Clock Divider Control Register 0 0x0000_00XX CLK_DIVCTL1 CLK_BA+0x024 R/W Clock Divider Control Register 1 0x0000_0000 CLK_DIVCTL2 CLK_BA+0x028 R/W Clock Divider Control Register 2 0x0000_1500 CLK_DIVCTL3 CLK_BA+0x02C R/W Clock Divider Control Register 3 0x0000_0000 CLK_DIVCTL4 CLK_BA+0x030 R/W Clock Divider Control Register 4 0x0000_0000 CLK_DIVCTL5 CLK_BA+0x034 R/W Clock Divider Control Register 5 0x0000_0000 CLK_DIVCTL6 CLK_BA+0x038 R/W Clock Divider Control Register 6 0x0000_0000 CLK_DIVCTL7 CLK_BA+0x03C R/W Clock Divider Control Register 7 0x0000_0000 CLK_DIVCTL8 CLK_BA+0x040 R/W Clock Divider Control Register 8 0x0000_0500 CLK_DIVCTL9 CLK_BA+0x044 R/W Clock Divider Control Register 9 0x0000_0000 CLK_APLLCON CLK_BA+0x060 R/W APLL Control Register 0x1000_0018 CLK_UPLLCON CLK_BA+0x064 R/W UPLL Control Register 0xX000_0018 CLK_PLLSTBC CLK_BA+0x080 R/W NTR PLL Stable Counter and Test Clock Control Register 0x0000_1800 Oct., 02, 2019 Page 152 of 246 Rev 1.11 NUC980 6.3.6 Register Description Power Management Control Register (CLK_PMCON) The chip clock source is from an external crystal. The crystal oscillator can be control on/off by the register XTAL_EN. When turn off the crystal, the chip into power down state. To avoid outputting an unstable clock to system, clock controller implements a pre-scalar counter. After the clock counter count pre-scalar x 256 crystal cycle, the clock controller starts to output the clock to system. Register Offset R/W Description Reset Value CLK_PMCON CLK_BA+0x000 R/W Power Management Control Register 0xFFFF_FF03 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XIN_CTL XTAL_EN Reserved 23 22 21 20 PRESCALE 15 14 13 12 PRESCALE 7 6 Reserved 5 4 SEN1_OFF_S SEN0_OFF_S T T Reserved Bits Description [31:24] Reserved [23:8] PRESCALE Assume the crystal is stable after the Pre-Scalar x 256 crystal cycles. Clock controller wouldn’t output clock to system before the counter reaching (pre-scalar x 256). [7:6] Reserved Reserved. [5] SEN1_OFF_ST Reserved. Pre-scalar Counter 0 = Sensor 1 clock keep on low level. 1 = Sensor 1 clock keep on high level. Sensor Clock Level on Clock Off State [4] SEN0_OFF_ST 0 = Sensor 0 clock keep on low level. 1 = Sensor 0 clock keep on high level. [3:2] Reserved Reserved. Pre-scalar Counter Enable Bit [1] XIN_CTL Crystal pre-divide control for Wake-up from power down mode The chip will delay 256 x pre-scalar cycles after the reset signal to wait the Crystal to stable 0 = The pre-scalar counter Disabled (assume the crystal is stable). 1 = The pre-scalar counter Enabled. Crystal (Power-down) Control [0] XTAL_EN 0 = Crystal off (Power-down mode). 1 = Crystal on (Normal operating mode). Oct., 02, 2019 Page 153 of 246 Rev 1.11 NUC980 SERIES DATASHEET Sensor 1 Clock Level on Clock Off State NUC980 AHB Devices Clock Enable Control Register (CLK_HCLKEN) Register Offset R/W Description Reset Value CLK_HCLKEN CLK_BA+0x010 R/W AHB Devices Clock Enable Control Register 0x0000_4527 31 30 29 28 27 26 25 24 VCAP1 SD1 Reserved Reserved SENSOR VCAP0 Reserved I2S 23 22 21 20 19 18 17 16 CRYPTO SD0 NAND FMI USBD USBH EMAC1 EMAC0 15 14 13 12 11 10 9 8 CKO PCLK2 PDMA1 PDMA0 GPIO SDIC EBI SRAM 7 6 5 4 3 2 1 0 TIC PCLK1 PCLK0 HCLK4 HCLK3 HCLK1 HCLK CPU Bits Description CMOS Sensor Interface Controller 1 Clock Enable Bit [31] VCAP1 0 = CMOS sensor interface controller 1 clock Disabled. 1 = CMOS sensor interface controller 1 clock Enabled. SD Card Controller 1 Clock Enable Bit [30] SD1 0 = SD card controller 1 clock Disabled. 1 = SD card controller 1 clock Enabled. NUC980 SERIES DATASHEET [29:28] Reserved Reserved. CMOS Sensor Reference Clock Output Enable Bit 0 = CMOS sensor reference clock output Disabled. 1 = CMOS sensor reference clock output Enabled. [27] SENSOR Note1: The reference clock output for CMOS sensor interface 0 only Enabled when both VCAP0 and SENSOR Enabled. Note2: The reference clock output for CMOS sensor interface 1 only Enabled when both VCAP1 and SENSOR Enabled. CMOS Sensor Interface Controller 0 Clock Enable Bit [26] VCAP0 0 = CMOS sensor interface controller 0 clock Disabled. 1 = CMOS sensor interface controller 0 clock Enabled. [25] Reserved Reserved. I2S Controller Clock Enable Bit [24] I2S 0 = I2S controller clock Disabled. 1 = I2S controller clock Enabled. Crypto Engine Clock Enable Bit [23] CRYPTO 0 = Crypto engine clock Disabled. 1 = Crypto engine clock Enabled. Oct., 02, 2019 Page 154 of 246 Rev 1.11 NUC980 SD Card Controller 0 Clock Enable Bit [22] SD0 0 = SD card controller 0 clock Disabled. 1 = SD card controller 0 clock Enabled. NAND Engine Clock Enable Bit [21] NAND 0 = NAND controller clock Disabled. 1 = NAND controller clock Enabled. FMI Controller Clock Enable Bit [20] FMI 0 = FMI controller clock Disabled. 1 = FMI controller clock Enabled. USB Device Controller Clock Enable Bit [19] USBD 0 = USB device controller clock Disabled. 1 = USB device controller clock Enabled. USB Host Controller Clock Enable Bit [18] USBH 0 = USB host controller clock Disabled. 1 = USB host controller clock Enabled. Ethernet MAC Controller 1 Clock Enable Bit [17] EMAC1 0 = Ethernet MAC controller 1 clock Disabled. 1 = Ethernet MAC controller 1 clock Enabled. Ethernet MAC Controller 0 Clock Enable Bit [16] EMAC0 0 = Ethernet MAC controller 0 clock Disabled. 1 = Ethernet MAC controller 0 clock Enabled. Reference Clock Output Enable Bit [15] CKO 0 = Reference clock output Disabled. 1 = Reference clock output Enabled. Internal APB-2 Bus Clock Enable Bit PCLK2 NUC980 SERIES DATASHEET [14] 0 = Internal APB-2 bus clock Disabled. 1 = Internal APB-2 bus clock Enabled. PDMA 1 Clock Enable Bit [13] PDMA1 0 = PDMA 1 clock Disabled. 1 = PDMA 1 clock Enabled. PDMA 0 Clock Enable Bit [12] PDMA0 0 = PDMA 0 clock Disabled. 1 = PDMA 0 clock Enabled. GPIO Clock Enable Bit [11] GPIO 0 = GPIO clock Disabled. 1 = GPIO clock Enabled. SDIC Clock Enable Bit [10] SDIC 0 = DDR clock Disabled. 1 = DDR clock Enabled. EBI Controller Clock Enable Bit [9] EBI 0 = EBI controller clock Disabled. 1 = EBI controller clock Enabled. Oct., 02, 2019 Page 155 of 246 Rev 1.11 NUC980 SRAM Controller Clock Enable Bit [8] SRAM 0 = SRAM controller clock Disabled. 1 = SRAM controller clock Enabled. TIC Clock Enable Bit [7] TIC 0 = TIC clock Disabled. 1 = TIC clock Enabled. Internal APB-1 Bus Clock Enable Bit [6] PCLK1 0 = Internal APB-1 bus clock Disabled. 1 = Internal APB-1 bus clock Enabled. Internal APB-0 Bus Clock Enable Bit [5] PCLK0 0 = Internal APB-1 bus clock Disabled. 1 = Internal APB-1 bus clock Enabled. Internal AHB-4 Bus Clock Enable Bit [4] HCLK4 0 = Internal AHB-4 bus clock Disabled. 1 = Internal AHB-4 bus clock Enabled. Internal AHB-3 Bus Clock Enable Bit [3] HCLK3 0 = Internal AHB-3 bus clock Disabled. 1 = Internal AHB-3 bus clock Enabled. Internal AHB-1 Bus Clock Enable Bit [2] HCLK1 0 = Internal AHB-1 bus clock Disabled. 1 = Internal AHB-1 bus clock Enabled. Internal AHB Bus Clock Enable Bit [1] HCLK 0 = Internal AHB bus clock Disabled. 1 = Internal AHB bus clock Enabled. Arm926EJ-S™ CPU Clock Enable Bit NUC980 SERIES DATASHEET [0] CPU 0 = Arm926EJ-S™ CPU clock Disabled. 1 = Arm926EJ-S™ CPU clock Enabled. Oct., 02, 2019 Page 156 of 246 Rev 1.11 NUC980 APB Devices Clock Enable Control Register 0 (CLK_PCLKEN0) Register Offset CLK_PCLKEN0 CLK_BA+0x018 31 R/W Description Reset Value R/W APB Devices Clock Enable Control Register 0 0x0000_000X 30 29 28 27 26 Reserved 23 22 21 25 24 UART9CKEN UART8CKEN 20 19 18 17 16 UART7CKEN UART6CKEN UART5CKEN UART4CKEN UART3CKEN UART2CKEN UART1CKEN UART0CKEN 15 14 Reserved 7 13 12 11 10 9 8 TMR5CKEN TMR4CKEN TMR3CKEN TMR2CKEN TMR1CKEN TMR0CKEN 5 4 3 2 1 0 Reserved RTCCKEN WWDTCKEN WDTCKEN 6 Reserved Bits Description [31:26] Reserved Reserved. UART 9 Clock Enable Bit [25] UART9CKEN 0 = UART 9 clock Disabled. 1 = UART 9 clock Enabled. UART 8 Clock Enable Bit [24] UART8CKEN 0 = UART 8 clock Disabled. 1 = UART 8 clock Enabled. NUC980 SERIES DATASHEET UART 7 Clock Enable Bit [23] UART7CKEN 0 = UART 7 clock Disabled. 1 = UART 7 clock Enabled. UART 6 Clock Enable Bit [22] UART6CKEN 0 = UART 6 clock Disabled. 1 = UART 6 clock Enabled. UART 5 Clock Enable Bit [21] UART5CKEN 0 = UART 5 clock Disabled. 1 = UART 5 clock Enabled. UART 4 Clock Enable Bit [20] UART4CKEN 0 = UART 4 clock Disabled. 1 = UART 4 clock Enabled. UART 3 Clock Enable Bit [19] UART3CKEN 0 = UART 3 clock Disabled. 1 = UART 3 clock Enabled. UART 2 Clock Enable Bit [18] UART2CKEN 0 = UART 2 clock Disabled. 1 = UART 2 clock Enabled. Oct., 02, 2019 Page 157 of 246 Rev 1.11 NUC980 UART 1 Clock Enable Bit [17] UART1CKEN 0 = UART 1 clock Disabled. 1 = UART 1 clock Enabled. UART 0 Clock Enable Bit [16] UART0CKEN 0 = UART 0 clock Disabled. 1 = UART 0 clock Enabled. [15:14] Reserved Reserved. Timer 5 Clock Enable Bit [13] TMR5CKEN 0 = Timer 5 clock Disabled. 1 = Timer 5 clock Enabled. Timer 4 Clock Enable Bit [12] TMR4CKEN 0 = Timer 4 clock Disabled. 1 = Timer 4 clock Enabled. Timer 3 Clock Enable Bit [11] TMR3CKEN 0 = Timer 3 clock Disabled. 1 = Timer 3 clock Enabled. Timer 2 Clock Enable Bit [10] TMR2CKEN 0 = Timer 2 clock Disabled. 1 = Timer 2 clock Enabled. Timer 1 Clock Enable Bit [9] TMR1CKEN 0 = Timer 1 clock Disabled. 1 = Timer 1 clock Enabled. Timer 0 Clock Enable Bit [8] TMR0CKEN 0 = Timer 0 clock Disabled. 1 = Timer 0 clock Enabled. NUC980 SERIES DATASHEET [7:3] Reserved [2] RTCCKEN Reserved. RTC Clock Enable Bit 0 = RTC clock Disabled. 1 =RTC clock Enabled. Windowed Watch-dog Clock Enable Bit [1] WWDTCKEN 0 = Windowed Watch-dog clock Disabled. 1 = Windowed Watch-dog clock Enabled. Watch-dog Clock Enable Bit 0 = Watch-dog clock Disabled. [0] WDTCKEN 1 = Watch-dog clock Enabled. Note: If WDT default Enabled (WDTON(SYS_PWRON[3])=1), this bit is read-only and read back value is always 1. Oct., 02, 2019 Page 158 of 246 Rev 1.11 NUC980 APB Devices Clock Enable Control Register 1 (CLK_PCLKEN1) Register Offset CLK_PCLKEN1 CLK_BA+0x01C 31 R/W Description Reset Value R/W APB Devices Clock Enable Control Register 1 0x0000_0000 30 29 28 Reserved 23 22 21 27 26 25 24 PWM1CKEN PWM0CKEN Reserved ADCCKEN 19 18 17 16 20 Reserved 15 14 Reserved 13 12 11 10 9 8 SMC1CKEN SMC0CKEN CAN3CKEN CAN2CKEN CAN1CKEN CAN0CKEN 7 6 5 4 3 2 1 0 Reserved SPI1CKEN SPI0CKEN QSPI0CKEN I2C3CKEN I2C2CKEN I2C1CKEN I2C0CKEN Bits Description [31:26] Reserved Reserved. PWM 1 Clock Enable Bit [27] PWM1CKEN 0 = PWM 1 clock Disabled. 1 = PWM 1 clock Enabled. PWM 0 Clock Enable Bit [26] PWM0CKEN 0 = PWM 0 clock Disabled. 1 = PWM 0 clock Enabled. Reserved NUC980 SERIES DATASHEET [25] Reserved. ADC Controller Clock Enable Bit [24] ADCCKEN 0 = ADC controller clock Disabled. 1 = ADC controller clock Enabled. [23:14] Reserved [13] SMC1CKEN Reserved. Smart Card Interface 1 Clock Enable Bit 0 = Smart Card interface 1 clock Disabled. 1 = Smart Card interface 1 clock Enabled. Smart Card Interface 0 Clock Enable Bit [12] SMC0CKEN 0 = Smart Card interface 0 clock Disabled. 1 = Smart Card interface 0 clock Enabled. CAN 3 Clock Enable Bit [11] CAN3CKEN 0 = CAN 3 clock Disabled. 1 = CAN 3 clock Enabled. CAN 2 Clock Enable Bit [10] CAN2CKEN 0 = CAN 2 clock Disabled. 1 = CAN 2 clock Enabled. Oct., 02, 2019 Page 159 of 246 Rev 1.11 NUC980 CAN 1 Clock Enable Bit [9] CAN1CKEN 0 = CAN 1 clock Disabled. 1 = CAN 1 clock Enabled. CAN 0 Clock Enable Bit [8] CAN0CKEN 0 = CAN 0 clock Disabled. 1 = CAN 0 clock Enabled. [7] Reserved Reserved. SPI 1 Clock Enable Bit [6] SPI1CKEN 0 = SPI 1 clock Disabled. 1 = SPI 1 clock Enabled. SPI 0 Clock Enable Bit [5] SPI0CKEN 0 = SPI 0 clock Disabled. 1 = SPI 0 clock Enabled. QSPI 0 Clock Enable Bit [4] QSPI0CKEN 0 = QSPI 0 clock Disabled. 1 = QSPI 0 clock Enabled. I2C 3 Clock Enable Bit [3] I2C3CKEN 0 = I2C 3 clock Disabled. 1 = I2C 3 clock Enabled. I2C 2 Clock Enable Bit [2] I2C2CKEN 0 = I2C 2 clock Disabled. 1 = I2C 2 clock Enabled. I2C 1 Clock Enable Bit [1] I2C1CKEN 0 = I2C 1 clock Disabled. 1 = I2C 1 clock Enabled. NUC980 SERIES DATASHEET I2C 0 Clock Enable Bit [0] I2C0CKEN 0 = I2C 0 clock Disabled. 1 = I2C 0 clock Enabled. Oct., 02, 2019 Page 160 of 246 Rev 1.11 NUC980 Clock Divider Control Register 0 (CLK_DIVCTL0) Register Offset R/W Description Reset Value CLK_DIVCTL0 CLK_BA+0x020 R/W Clock Divider Control Register 0 0x0000_00XX 31 30 29 28 27 26 25 24 19 18 17 16 Reserved 23 22 21 20 Reserved 15 14 13 12 CPUDIV2EN 11 10 9 Reserved 7 6 5 Reserved Bits Description [31:17] Reserved 4 8 SYSDIV2EN 3 2 SYSTEM_S 1 0 Reserved Reserved. CPU Clock Divided by 2 Enable Bit [16] CPUDIV2EN This field defines if CPUCLK for Arm926EJ-S™ CPU is SYS_CLK devided by 2 or not. 0 = The frequency of CPUCLK is equal to SYS_CLK. 1 = The frequency of CPUCLK is SYS_CLK devided by 2. [15:9] Reserved Reserved. [8] SYSDIV2EN NUC980 SERIES DATASHEET System Clock Divided by 2 Enable Bit This field defines if SYS_CLK is SYSTEM_SrcCLK devided by 2 or not. 0 = The frequency of SYS_CLK is equal to SYSTEM_SrcCLK. 1 = The frequency of SYS_CLK is SYSTEM_SrcCLK devided by 2. [7:5] Reserved Reserved. System Clock Source Selection This field selects which clock is used to be the source of system clock SYS_CLK. [4:3] SYSTEM_S 00 = SYSTEM_SrcCLK is from XIN. 01 = Reserved. 10 = SYSTEM_SrcCLK is from APLLFout. 11 = SYSTEM_SrcCLK is from UPLLFout. [2:0] Reserved Oct., 02, 2019 Reserved. Page 161 of 246 Rev 1.11 NUC980 Clock Divider Control Register 1 (CLK_DIVCTL1) Register Offset R/W Description Reset Value CLK_DIVCTL1 CLK_BA+0x024 R/W Clock Divider Control Register 1 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 I2S_N 23 22 21 20 Reserved 15 14 I2S_S 13 12 Reserved 11 10 9 8 3 2 1 0 Reserved 7 6 5 4 Reserved Bits Description I2S Controller Clock Divider [31:24] I2S_N This field defines the clock divide number for clock divider to generate the engine clock for I2S controller. The actual clock divide number is (I2S_N + 1). So, ECLKi2s = I2S_SrcCLK / (I2S_N + 1). [23:21] Reserved Reserved. I2S Controller Clock Source Selection NUC980 SERIES DATASHEET This field selects which clock is used to be the source of engine clock for I2S controller. [20:19] I2S_S 00 = I2S_SrcCLK is from XIN. 01 = Reserved. 10 = I2S_SrcCLK is from ACLKOut. 11 = I2S_SrcCLK is from UCLKOut. [18:0] Reserved Oct., 02, 2019 Reserved. Page 162 of 246 Rev 1.11 NUC980 Clock Divider Control Register 2 (CLK_DIVCTL2) Register Offset R/W Description Reset Value CLK_DIVCTL2 CLK_BA+0x028 R/W Clock Divider Control Register 2 0x0000_1500 31 30 29 28 27 26 Reserved 23 22 14 21 20 19 13 12 11 Description [31:28] Reserved 10 5 4 16 9 SPI0_S Reserved Bits 17 SENSOR1_SDIV SPI1_S 6 18 SENSOR1_S Reserved 7 24 SENSOR1_N Reserved 15 25 3 8 QSPI0_S 2 USB_S 1 0 Reserved Reserved. Sensor 1 Clock Divider [27:24] SENSOR1_N This field defines the clock divide number for clock divider to generate the sensor 1 clock. The actual clock divide number is (SENSOR1_N + 1). So, SEN1_CLK = SEN1_SrcCLK / (SENSOR1_N + 1). [23:21] Reserved Reserved. This field selects which clock is used to be the source of sensor 1 clock. [20:19] SENSOR1_S 00 = SEN1_SrcCLK is from XIN. 01 = Reserved. 10 = SEN1_SrcCLK is from ACLKOut. 11 = SEN1_SrcCLK is from UCLKOut. Sensor 1 Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output. This field only takes effect while the SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b10 (APLL) or 2’b11 (UPLL). [18:16] SENSOR1_SDIV If SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b10, ACLKOut = APLLFout ÷ (SENSOR1_SDIV + 1). If SENSOR1_S (CLK_DIVCTL3[20:19]) is 2’b11, UCLKOut = UPLLFout ÷ (SENSOR1_SDIV + 1). [15:14] Reserved Oct., 02, 2019 Reserved. Page 163 of 246 Rev 1.11 NUC980 SERIES DATASHEET Sensor 1 Clock Source Selection NUC980 SPI 1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for SPI 1. [13:12] SPI1_S 00 = SPI1_SrcCLK is from XIN. 01 = SPI1_SrcCLK is from PCLK0. 10 = SPI1_SrcCLK is from ACLKOut. 11 = SPI1_SrcCLK is from UCLKOut. SPI 0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for SPI 0. [11:10] SPI0_S 00 = SPI0_SrcCLK is from XIN. 01 = SPI0_SrcCLK is from PCLK1. 10 = SPI0_SrcCLK is from ACLKOut. 11 = SPI0_SrcCLK is from UCLKOut. QSPI 0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for QSPI 0. [9:8] QSPI0_S 00 = QSPI0_SrcCLK is from XIN. 01 = QSPI0_SrcCLK is from PCLK0. 10 = QSPI0_SrcCLK is from ACLKOut. 11 = QSPI0_SrcCLK is from UCLKOut. [7:5] Reserved Reserved. USB 1.1 Engine Clock Source Selection This field selects which clock is used to be the source of 48 MHz clock for USB 1.1 host controller. [4:3] USB_S 00 = Reserved. 01 = Reserved. 10 = USB11_SrcCLK is from 480 MHz outputted by USB PHY 0. 11 = USB11_SrcCLK is from 480 MHz outputted by USB PHY 1. NUC980 SERIES DATASHEET [2:0] Reserved Oct., 02, 2019 Reserved. Page 164 of 246 Rev 1.11 NUC980 Clock Divider Control Register 3 (CLK_DIVCTL3) Register Offset R/W Description Reset Value CLK_DIVCTL3 CLK_BA+0x02C R/W Clock Divider Control Register 3 0x0000_0000 31 30 29 28 27 26 Reserved 23 22 14 24 SENSOR0_N 21 20 Reserved 15 25 19 18 SENSOR0_S 13 12 17 16 SENSOR0_SDIV 11 10 9 8 3 2 1 0 SD0_N 7 6 5 4 Reserved Bits Description [31:28] Reserved SD0_S Reserved Reserved. Sensor 0 Clock Divider [27:24] SENSOR0_N This field defines the clock divide number for clock divider to generate the sensor 0 clock. The actual clock divide number is (SENSOR0_N + 1). So, SEN0_CLK = SEN0_SrcCLK / (SENSOR0_N + 1). [33:21] Reserved Reserved. This field selects which clock is used to be the source of sensor 0 clock. [20:19] SENSOR0_S 00 = SEN0_SrcCLK is from XIN. 01 = Reserved. 10 = SEN0_SrcCLK is from ACLKOut. 11 = SEN0_SrcCLK is from UCLKOut. Sensor 0 Source Clock Divider This field defines the source clock divide number for clock divider of APLL and UPLL output. This field only takes effect while the SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b10 (APLL) or 2’b11 (UPLL). [18:16] SENSOR0_SDIV If SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b10, ACLKOut = APLLFout ÷ (SENSOR0_SDIV + 1). If SENSOR0_S (CLK_DIVCTL3[20:19]) is 2’b11, UCLKOut = UPLLFout ÷ (SENSOR0_SDIV + 1). SD Card Controller 0 Engine Clock Divider [15:8] SD0_N This field defines the clock divide number for clock divider to generate the engine clock for SD card controller 0. The actual clock divide number is (SD0_N + 1). So, SD0_CLK = SD0_SrcCLK / (SD0_N + 1). [7:5] Reserved Oct., 02, 2019 Reserved. Page 165 of 246 Rev 1.11 NUC980 SERIES DATASHEET Sensor 0 Clock Source Selection NUC980 SD Card Controller 0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for SD card controller 0. [4:3] SD0_S 00: SD0_SrcCLK = XIN. 01: SD0_SrcCLK = Reserved. 10: SD0_SrcCLK = ACLKOut. 11: SD0_SrcCLK = UCLKOut. [2:0] Reserved Reserved. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 166 of 246 Rev 1.11 NUC980 Clock Divider Control Register 4 (CLK_DIVCTL4) Register Offset R/W Description Reset Value CLK_DIVCTL4 CLK_BA+0x030 R/W Clock Divider Control Register 4 0x0000_0000 31 30 29 28 UART3_N 23 22 21 14 20 13 6 18 11 4 24 17 16 Reserved 10 UART1_S 5 UART0_N Bits 19 12 25 Reserved UART2_S UART1_N 7 26 UART3_S UART2_N 15 27 9 8 Reserved 3 UART0_S 2 1 0 Reserved Description UART3 Engine Clock Divider [31:29] UART3_N This field defines the clock divide number for clock divider to generate the engine clock for UART3. The actual clock divide number is (UART3_N + 1). So, ECLKuart3 = UART3_SrcCLK / (UART3_N + 1). UART3 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART3 controller. [28:27] UART3_S 00 = UART3_SrcCLK is from XIN. 10 = UART3_SrcCLK is from ACLKOut. 11 = UART3_SrcCLK is from UCLKOut. [26:24] Reserved Reserved. UART2 Engine Clock Divider [23:21] UART2_N This field defines the clock divide number for clock divider to generate the engine clock for UART2. The actual clock divide number is (UART2_N + 1). So, ECLKuart2 = UART2_SrcCLK / (UART2_N + 1). UART2 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART2 controller. [20:19] UART2_S 00 = UART2_SrcCLK is from XIN. 01 = UART2_SrcCLK is from LXT. 10 = UART2_SrcCLK is from ACLKOut. 11 = UART2_SrcCLK is from UCLKOut. [18:16] Reserved Reserved. UART1 Engine Clock Divider [15:13] UART1_N This field defines the clock divide number for clock divider to generate the engine clock for UART1. The actual clock divide number is (UART1_N + 1). So, ECLKuart1 = UART1_SrcCLK / (UART1_N + 1). Oct., 02, 2019 Page 167 of 246 Rev 1.11 NUC980 SERIES DATASHEET 01 = UART3_SrcCLK is from LXT. NUC980 UART1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART1 controller. [12:11] UART1_S 00 = UART1_SrcCLK is from XIN. 01 = UART1_SrcCLK is from LXT. 10 = UART1_SrcCLK is from ACLKOut. 11 = UART1_SrcCLK is from UCLKOut. [10:8] Reserved Rserved UART0 Engine Clock Divider [7:5] UART0_N This field defines the clock divide number for clock divider to generate the engine clock for UART0. The actual clock divide number is (UART0_N + 1). So, ECLKuart0 = UART0_SrcCLK / (UART0_N + 1). UART0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART0 controller. [4:3] UART0_S 00 = UART0_SrcCLK is from XIN. 01 = UART0_SrcCLK is from LXT. 10 = UART0_SrcCLK is from ACLKOut. 11 = UART0_SrcCLK is from UCLKOut. [2:0] Reserved Reserved. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 168 of 246 Rev 1.11 NUC980 Clock Divider Control Register 5 (CLK_DIVCTL5) Register Offset R/W Description Reset Value CLK_DIVCTL5 CLK_BA+0x034 R/W Clock Divider Control Register 5 0x0000_0000 31 30 29 28 UART7_N 23 22 14 21 20 13 6 18 5 11 4 24 17 16 Reserved 10 UART5_S UART4_N Bits 19 12 25 Reserved UART6_S UART5_N 7 26 UART7_S UART6_N 15 27 9 8 Reserved 3 UART4_S 2 1 0 Reserved Description UART7 Engine Clock Divider [31:29] UART7_N This field defines the clock divide number for clock divider to generate the engine clock for UART7. The actual clock divide number is (UART7_N + 1). So, ECLKuart7 = UART7_SrcCLK / (UART7_N + 1). UART7 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART7 controller. UART7_S 00 = UART7_SrcCLK is from XIN. 01 = UART7_SrcCLK is from LXT. 10 = UART7_SrcCLK is from ACLKOut. 11 = UART7_SrcCLK is from UCLKOut. [26:24] Reserved Reserved. UART6 Engine Clock Divider [23:21] UART6_N This field defines the clock divide number for clock divider to generate the engine clock for UART6. The actual clock divide number is (UART6_N + 1). So, ECLKuart6 = UART6_SrcCLK / (UART6_N + 1). UART6 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART6 controller. [20:19] UART6_S 00 = UART6_SrcCLK is from XIN. 01 = UART6_SrcCLK is from LXT. 10 = UART6_SrcCLK is from ACLKOut. 11 = UART6_SrcCLK is from UCLKOut. [18:16] Reserved Oct., 02, 2019 Reserved. Page 169 of 246 Rev 1.11 NUC980 SERIES DATASHEET [28:27] NUC980 UART5 Engine Clock Divider [15:13] UART5_N This field defines the clock divide number for clock divider to generate the engine clock for UART5. The actual clock divide number is (UART5_N + 1). So, ECLKuart5 = UART5_SrcCLK / (UART5_N + 1). UART5 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART5 controller. [12:11] UART5_S 00 = UART5_SrcCLK is from XIN. 01 = UART5_SrcCLK is from LXT. 10 = UART5_SrcCLK is from ACLKOut. 11 = UART5_SrcCLK is from UCLKOut. [10:8] Reserved Reserved. UART4 Engine Clock Divider [7:5] UART4_N This field defines the clock divide number for clock divider to generate the engine clock for UART4. The actual clock divide number is (UART4_N + 1). So, ECLKuart4 = UART4_SrcCLK / (UART4_N + 1). UART4 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART4 controller. [4:3] UART4_S 00 = UART4_SrcCLK is from XIN. 01 = UART4_SrcCLK is from LXT. 10 = UART4_SrcCLK is from ACLKOut. 11 = UART4_SrcCLK is from UCLKOut. [2:0] Reserved Reserved. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 170 of 246 Rev 1.11 NUC980 Clock Divider Control Register 6 (CLK_DIVCTL6) Register Offset R/W Description Reset Value CLK_DIVCTL6 CLK_BA+0x038 R/W Clock Divider Control Register 6 0x0000_0000 31 30 29 28 27 26 SMC1_N 23 22 25 24 SMC0_N 21 20 19 18 17 16 11 10 9 8 Reserved 15 14 13 12 UART9_N 7 6 UART9_S 5 UART8_N Bits 4 Reserved 3 UART8_S 2 1 0 Reserved Description Smart Card 1 Engine Clock Divider [30:28] SMC1_N This field defines the clock divide number for clock divider to generate the engine clock for Smart card controller. The actual clock divide number is (SMC1_N + 1). So, ECLKsmc1 = XIN12M / (SMC1_N + 1). Smart Card 0 Engine Clock Divider [27:24] SMC0_N This field defines the clock divide number for clock divider to generate the engine clock for Smart card controller. ECLKsmc0 = XIN12M / (SMC0_N + 1). [23:16] Reserved Reserved. UART9 Engine Clock Divider [15:13] UART9_N This field defines the clock divide number for clock divider to generate the engine clock for UART9. The actual clock divide number is (UART9_N + 1). So, ECLKuart9 = UART9_SrcCLK / (UART9_N + 1). UART9 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART9 controller. [12:11] UART9_S 00 = UART9_SrcCLK is from XIN. 01 = UART9_SrcCLK is from LXT. 10 = UART9_SrcCLK is from ACLKOut. 11 = UART9_SrcCLK is from UCLKOut. [10:8] Reserved Oct., 02, 2019 Reserved. Page 171 of 246 Rev 1.11 NUC980 SERIES DATASHEET The actual clock divide number is (SMC0_N + 1). So, NUC980 UART8 Engine Clock Divider [7:5] UART8_N This field defines the clock divide number for clock divider to generate the engine clock for UART8. The actual clock divide number is (UART8_N + 1). So, ECLKuart8 = UART8_SrcCLK / (UART8_N + 1). UART8 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for UART8 controller. [4:3] UART8_S 00 = UART8_SrcCLK is from XIN. 01 = UART8_SrcCLK is from LXT. 10 = UART8_SrcCLK is from ACLKOut. 11 = UART8_SrcCLK is from UCLKOut. [2:0] Reserved Reserved. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 172 of 246 Rev 1.11 NUC980 Clock Divider Control Register 7 (CLK_DIVCTL7) Register Offset R/W Description Reset Value CLK_DIVCTL7 CLK_BA+0x03C R/W Clock Divider Control Register 7 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 ADC_N 23 22 21 20 Reserved 15 14 ADC_S 13 12 Reserved 11 10 9 8 3 2 1 0 Reserved 7 6 5 4 Reserved Bits Description ADC Engine Clock Divider [31:24] ADC_N This field defines the clock divide number for clock divider to generate the engine clock for ADC. The actual clock divide number is (ADC_N + 1). So, ADC_CLK = ADC_SrcCLK / (ADC_N + 1). [23:21] Reserved Reserved. ADC Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for ADC controller. ADC_S 00 = ADC_SrcCLK is from XIN. NUC980 SERIES DATASHEET [20:19] 01 = Reserved. 10 = ADC_SrcCLK is from APLLFOut. 11 = ADC_SrcCLK is from UPLLFOut. [18:0] Reserved Oct., 02, 2019 Reserved. Page 173 of 246 Rev 1.11 NUC980 Clock Divider Control Register 8 (CLK_DIVCTL8) Register Offset R/W Description Reset Value CLK_DIVCTL8 CLK_BA+0x040 R/W Clock Divider Control Register 8 0x0000_0500 31 30 29 28 27 Reserved 23 22 21 20 19 TMR2SEL 14 13 12 6 18 11 17 4 10 3 16 TMR0SEL 9 WWDTSEL 5 24 TMR4SEL TMR1SEL Reserved 7 25 TMR5SEL TMR3SEL 15 26 8 WDTSEL 2 1 0 MDCLKDIV Bits Description Timer 5 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Timer 5 controller. [27:26] TMR5SEL 00: TIMER5_SrcCLK = XIN. 01: TIMER5_SrcCLK = PCLK0. 10: TIMER5_SrcCLK = PCLK0/4096. 11: TIMER5_SrcCLK = 32.768 kHz. Timer 4 Engine Clock Source Selection NUC980 SERIES DATASHEET This field selects which clock is used to be the source of engine clock for Timer 4 controller. [25:24] TMR4SEL 00: TIMER4_SrcCLK = XIN. 01: TIMER4_SrcCLK = PCLK0. 10: TIMER4_SrcCLK = PCLK0/4096. 11: TIMER4_SrcCLK = 32.768 kHz. Timer 3 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Timer 3 controller. [23:22] TMR3SEL 00: TIMER3_SrcCLK = XIN. 01: TIMER3_SrcCLK = PCLK1. 10: TIMER3_SrcCLK = PCLK1/4096. 11: TIMER3_SrcCLK = 32.768 kHz. Timer 2 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Timer 2 controller. [21:20] TMR2SEL 00: TIMER2_SrcCLK = XIN. 01: TIMER2_SrcCLK = PCLK1. 10: TIMER2_SrcCLK = PCLK1/4096. 11: TIMER2_SrcCLK = 32.768 kHz. Oct., 02, 2019 Page 174 of 246 Rev 1.11 NUC980 Timer 1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Timer 1 controller. [19:18] TMR1SEL 00: TIMER1_SrcCLK = XIN. 01: TIMER1_SrcCLK = PCLK0. 10: TIMER1_SrcCLK = PCLK0/4096. 11: TIMER1_SrcCLK = 32.768 kHz. Timer 0 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for Timer 0 controller. [17:16] TMR0SEL 00: TIMER0_SrcCLK = XIN. 01: TIMER0_SrcCLK = PCLK0. 10: TIMER0_SrcCLK = PCLK0/4096. 11: TIMER0_SrcCLK = 32.768 kHz. WWDT Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for WWDT controller. [11:10] WWDTSEL 00: WWDT_SrcCLK = XIN. 01: WWDT_SrcCLK = XIN/512. 10: WWDT_SrcCLK = PCLK2/4096. 11: WWDT_SrcCLK = 32.768 kHz. WDT Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for WDT controller. [9:8] WDTSEL 00: WDT_SrcCLK = XIN. 01: WDT_SrcCLK = XIN/512. 10: WDT_SrcCLK = PCLK2/4096. 11: WDT_SrcCLK = 32.768 kHz. MII Management Interface Clock MDCLKDIV This field defines the clock divide number for clock divider to generate the clock for MII management interface. NUC980 SERIES DATASHEET [7:0] The actual clock divide number is (MDCLK_N + 1). So, MDCLK = HCLK / (MDCLK_N + 1). Oct., 02, 2019 Page 175 of 246 Rev 1.11 NUC980 Clock Divider Control Register 9 (CLK_DIVCTL9) Register Offset R/W Description Reset Value CLK_DIVCTL9 CLK_BA+0x044 R/W Clock Divider Control Register 9 0x0000_0000 31 30 29 28 27 26 25 24 19 18 17 16 CKO_N 23 22 21 20 Reserved 15 14 CKO_S 13 12 Reserved 11 10 9 8 3 2 1 0 SD1_N 7 6 5 4 Reserved Bits SD1_S Reserved Description Reference Clock Out Divide [31:24] CKO_N This field defines the clock divide number for clock divider to generate the reference clock output The actual clock divide number is (CKO_N + 1). So, CKO_CLK = CKO_SrcCLK / (CKO_N + 1). [23:21] Reserved Reserved. Reference Clock Out Source Selection NUC980 SERIES DATASHEET This field selects which clock is used to be the source of reference clock output. [20:19] CKO_S 00 = CKO_SrcCLK is from XIN. 01 = CKO_SrcCLK is from LXT. 10 = CKO_SrcCLK is from ACLKOut. 11 = CKO_SrcCLK is from UCLKOut. [18:16] Reserved Reserved. SD Card Controller 1 Engine Clock Divider [15:8] SD1_N This field defines the clock divide number for clock divider to generate the engine clock for SD card controller 1. The actual clock divide number is (SD1_N + 1). So, SD1_CLK = SD1_SrcCLK / (SD1_N + 1). [7:5] Reserved Reserved. SD Card Controller 1 Engine Clock Source Selection This field selects which clock is used to be the source of engine clock for SD card controller 1. [4:3] SD1_S 00 = SD1_SrcCLK is from XIN. 01 = Reserved. 10 = SD1_SrcCLK is from ACLKOut. 11 = SD1_SrcCLK is from UCLKOut. [2:0] Reserved Oct., 02, 2019 Reserved. Page 176 of 246 Rev 1.11 NUC980 APLL Control Register (CLK_APLLCON), UPLL Control Register (CLK_UPLLCON) Register Offset R/W Description Reset Value CLK_APLLCON CLK_BA+0x060 R/W APLL Control Register 0x1000_0018 CLK_UPLLCON CLK_BA+0x064 R/W UPLL Control Register 0xX000_0018 31 30 29 28 PLL_STB RESETN BYPASS PD 23 22 21 20 27 26 25 24 FRAC 19 18 17 16 11 10 9 8 1 0 FRAC 15 14 13 12 OUT_DV 7 6 IN_DV 5 4 IN_DV 3 2 FB_DV Bits Description [31] PLL_STB PLL Stable Flag 0 = PLL is not stable. 1 = PLL is stable (500us after PLL setting changed). Reset Mode Enable Bit [30] RESETN 0 = PLL is in reset mode. Bypass Mode Enable Bit [29] BYPASS 0 = PLL is in normal operation mode (Default). 1 = PLL is in bypass mode. Power Down Mode Enable Bit [28] PD 0 = PLL is in normal operation mode. 1 = PLL is in power down mode (Default). PLL VCO Output Clock Feedback Divider Fraction Part Set the fraction part (X) of feedback divider factor. [27:16] FRAC Write a non-zero value to this field enables the fraction mode automatically. Please keep this field in 0x0 if don’t want to use the PLL fraction mode. The X = FRAC[11:0] / 212. PLL Output Divider [15:13] OUT_DV Set the output divider factor (P) from 1 to 8. The P = OUT_DV[2:0] + 1. Reference Input Divider [12:7] IN_DV Set the reference divider factor (M) from 1 to 64. The M = IN_DV[5:0] + 1. Oct., 02, 2019 Page 177 of 246 Rev 1.11 NUC980 SERIES DATASHEET 1 = PLL is in normal operation mode (Default). NUC980 PLL VCO Output Clock Feedback Divider Integer Part [6:0] FB_DV Set the feedback divider factor (N) from 1 to 128. The N = FB_DV[6:0] + 1. The formula to calculate the PLL output frequency shown below: N Fpfd Range 1 2 3 4 5 6 7~8 9 ~ 10 11 ~ 40 NUC980 SERIES DATASHEET 41 ~ 128 Table 6.3-1 The Mapping of N and Fpfd Range Oct., 02, 2019 Page 178 of 246 Rev 1.11 NUC980 PLL Stable Counter and Test Clock Control Register (CLK_PLLSTBCNTR) Register Offset CLK_PLLSTBCNTR CLK_BA+0x080 R/W PLL Stable Counter and Test Clock Control Register 31 30 R/W Description 29 28 Reset Value 0x0000_1800 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Reserved 23 22 21 20 Reserved 15 14 13 12 PLLSTBCNT 7 6 5 4 PLLSTBCNT Bits Description [31:24] Reserved Reserved. [15:0] PLLSTBCNT PLL Stable Counter NUC980 SERIES DATASHEET Oct., 02, 2019 Page 179 of 246 Rev 1.11 NUC980 6.4 Advanced Interrpt Controller 6.4.1 Overview An interrupt can temporarily change the sequence of program execution to react to some specific events, such as power failure, watchdog timer timeout, transmit/receive requests from Ethernet MAC Controller, and so on. There are two interrupt types the CPU can process. The first type is the Fast Interrupt Request (FIQ) for servicing timing-critical events, and the second type is the Interrupt Request (IRQ) for servicing other general-purpose events. An FIQ interrupt occurrs when the signal nFIQ to the CPU is asserted, and a IRQ interrupt occurrs when the signal nIRQ to the CPU is asserted. A FIQ interrupt has higher priority than an IRQ interrupt to be processed by CPU. An IRQ service routine in-process can be interrupted by a new coming FIQ interrupt; however, a FIQ service routine in-process cannot be interrupted by a new coming IRQ interrupt. The Advanced Interrupt Controller (AIC) can process up to 64 interrupt sources. Currently, 62 interrupt sources are supported in the system. AIC assigns every interrupt source a unique source number. For example, the watchdog timer interrupt is assigned to source number 1, and window WDT interrupt is assigned to source number 2. Every interrupt source can be configured to have one of eight priority levels, numbered from 0 to 7. Interrupt sources with priority level 0 have the highest priority, and interrupt sources with priority level 7 have the lowest priority. For those interrupt sources with the same priority levels, an interrupt source with a lower source number will have higher priority. An interrupt request generated by an interrupt source with priority level 0 will become a FIQ interrupt to the CPU. An interrupt request generated by an interrupt source with priority levels from 1 to 7 will become a IRQ interrupt to the CPU. Each interrupt source can be configured as disabled or enabled. An interrupt request from a disabled interrupt source is always ignored by AIC, no matter what its source number and priority level are. AIC supports four trigger types for every interrupt source: high-level trigger, low-level trigger, rising-edge trigger, and falling-edge trigger. NUC980 SERIES DATASHEET 6.4.2 Features  AMBA APB interface  62 interrupt sources  Configurable 8 priority levels for each interrupt source  Configurable 4 trigger types for each interrupt source  Configurable disabled/enabled status for each interrupt source  Readable on the current logic value of each interrupt source  Arbitration of interrupt requests from two or more interrupt sources  Easy programming of interrupt service routines Oct., 02, 2019 Page 180 of 246 Rev 1.11 NUC980 6.5 SDRAM Interface Controller 6.5.1 Overview The SDRAM Controller support SDR, DDR, Low-Power DDR and DDR2 type SDRAM. The memory device size type can be from 16M bit and up to 1G bits. Only 16-bit data bus width is supported. The total system memory size can be from 2M bytes and up to 256M bytes for different SDRAM configuration. The SDRAM controller interface to three isolated AHB. All these AHB masters can access the memory independent. Except the memory access, the masters of AHB also could access the SDRAM control registers. For performance and function issue, the SDRAM controller also supports the proprietary EnhancedAHB. The EAHB add the down-count address mode, byte-enable signal and explicit burst access number. The explicit access number function is reached by modify the HBURST signal to EHBURST and it represent the access number. The maximum EAHB access number is 16. The SDRAM controller also builds a BIST module to test the external memory device. An internal arbiter is used to schedule the access from the masters and the BIST request, the BIST request with the highest priority and the then the AHB3 master, AHB2 master and AHB1 master. The SDRAM controller uses 3 pipe queues to improve the SDRAM command and data bus efficiency. The request in queue0 is the SDRAM active data access request. Simultaneous, the requests in queue1 can request the controller to issue the ACTIVE or PRECHARGE command to reduce the access latency for the later command. The queue1 also can issue the READ or WRITE command to close the SDRAM command when advance pipe queue The SDRAM refresh rate is programmable. The Refresh and Power-on control module generate the refresh request signal and SDRAM power on sequence. The SDRAM controller also supports software reset, SDRAM self-refresh and auto power down function. 6.5.2 Features Built-in 128MB/ 64MB/ 16MB SDRAM Memory in LQFP package  Clock speed up to 150 MHz  Support 16-bit data bus width Oct., 02, 2019 Page 181 of 246 NUC980 SERIES DATASHEET  Rev 1.11 NUC980 6.6 External Bus Interface 6.6.1 Overview This chip is equipped with an external bus interface (EBI) for external device use. To save the connections between an external device and a chip, EBI is operating at address bus and data bus multiplex mode. The EBI supports three chip selects that can connect three external devices with different timing setting requirements. 6.6.2 Features  Supports up to three memory banks  Supports dedicated external chip select pin with polarity control for each bank  Supports accessible space up to 1 Mbytes for each bank, actually external addressable space is dependent on package pin out  Supports 8-/16-bit data width  Supports Timing parameters individual adjustment for each memory block  Supports LCD interface i80 mode  Supports PDMA mode  Supports variable external bus base clock (MCLK) which based on HCLK  Supports configurable idle cycle for different access condition: Idle of Write command finish (W2X) and Idle of Read-to-Read (R2R)  Supports address bus and data bus separate mode NUC980 SERIES DATASHEET Oct., 02, 2019 Page 182 of 246 Rev 1.11 NUC980 6.7 General Purpose I/O 6.7.1 Overview This chip has up to 104 General-Purpose I/O (GPIO) pins and can be shared with other function pins depending on the chip configuration. These 104 pins are arranged in 7 ports named as PA, PB, PC, PD, PE, PF and PG. PA, PC, PD and PG has 16 pins on port. PB has 14 pins on port. PE and PF has 13 pins on port. Each of the 104 I/O pins is independent and can be easily configured by user to meet various system configurations and design requirements. The I/O type of each of I/O pins can be configured by software individually as Input, Push-pull output or Open-drain output. After reset, all 104 I/O pins are configured in General-Purpose I/O Input mode. 6.7.2 Features  Three I/O modes: – Push-Pull Output mode – Open-Drain Output mode – Input only with high impendence mode  TTL/Schmitt trigger input selectable  I/O pin can be configured as interrupt source with edge/level setting  Supports High Drive and High Slew Rate I/O mode in PB.0~PB.7  Supports independent pull-up and pull-down control  Enabling the pin interrupt function will also enable the wake-up function NUC980 SERIES DATASHEET Oct., 02, 2019 Page 183 of 246 Rev 1.11 NUC980 6.8 Peripheral DMA Controller 6.8.1 Overview The peripheral direct memory access (PDMA) controller is used to provide high-speed data transfer. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. The PDMA controller has a total of 20 channels and each channel can perform transfer between memory and peripherals or between memory and memory. 6.8.2 Features  Supports 2 PDMA controller, PDMA0 and PDMA1  Supports 10 independently configurable channels  Supports selectable 2 level of priority (fixed priority or round-robin priority)  Supports transfer data width of 8, 16, and 32 bits  Supports source and destination address increment size can be byte, half-word, word or no increment  Supports software and UART, SPI, I2C and Timer request  Supports Scatter-Gather mode to perform sophisticated transfer through the use of the descriptor link list table  Supports single and burst transfer type  Supports time-out function from channel 0 to channel 9  Supports stride function from channel 0 to channel 5 NUC980 SERIES DATASHEET Oct., 02, 2019 Page 184 of 246 Rev 1.11 NUC980 6.9 Timer Controller (TMR) 6.9.1 Overview The timer controller includes six 32-bit timers, Timer0 ~ Timer5, allowing user to easily implement a timer control applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, and event counting by external input pins, and interval measurement by external capture pins. 6.9.2 Features  Six sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter  Independent Clock Source for each Timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through CNT (TIMERx_CNT[23:0])  Supports event counting function to count input event from pin TMx_ECNT (x = 0~5)  Supports toggle output to pin TMx_TGL (x = 0~5)  24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])  Supports event capture from external pin TMx_EXT (x = 0~5) for interval measurement  Supports event capture from RTC 1Hz signal for RTC clock calibration  Supports event capture from external pin TMx_EXT (x = 0~5) to reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated  Supports time-out interrupt or capture interrupt to trigger ADC and PDMA.  Supports Inter-Timer trigger that Timer 0 can trigger Timer 1, Timer 2 can trigger Timer 3, and Timer4 can trigger Timer5. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 185 of 246 Rev 1.11 NUC980 6.10 Pulse Width Modulation (PWM) 6.10.1 Overview This chip has 2 PWM controllers, PWM0 and PWM1. Each PWM controller has 4 independent PWM outputs. PWM0 has 4 independent PWM outputs, CH0~CH3, or 2 complementary PWM pairs, (CH0, CH1), (CH2, CH3) with 2 programmable dead-zone generators. PWM1 has 4 independent PWM outputs, CH4~CH7, or 2 complementary PWM pairs, (CH4, CH5), (CH6, CH7) with 2 programmable dead-zone generators. Each PWM pair has one prescaler, one clock divider, two clock selectors, two 16-bit PWM counters, two 16-bit comparators, and one dead-zone e generator. They are all driven by APB system clock (PCLK) in chip. Each PWM channel can be used as a timer and issue interrupt independently. Two channels PWM Timers in one pair share the same prescaler. The Clock divider provides each PWM channel with 5 divided clock sources (1, 1/2, 1/4, 1/8, 1/16). Each channel receives its own clock signal from clock divider which receives clock from 8-bit prescaler. The 16-bit down-counter in each channel receive clock signal from clock selector and can be used to handle one PWM period. The 16-bit comparator compares PWM counter value with threshold value in register CMR (PWM_CMR[15:0]) loaded previously to generate PWM duty cycle. The clock signal from clock divider is called PWM clock. Dead-Zone generator utilize PWM clock as clock source. Once Dead-Zone generator is enabled, two outputs of the corresponding PWM channel pair will be replaced by the output of Dead-Zone generator. The Dead-Zone generator is used to control off-chip power device. To prevent PWM driving output pin with unsteady waveform, 16-bit down-counter and 16-bit comparator are implemented with double buffering feature. User can feel free to write data to counter buffer register and comparator buffer register without generating glitch. When 16-bit down-counter reaches zero, the interrupt request is generated to inform CPU that time is up. When counter reaches zero, if counter is set as periodic mode, it is reloaded automatically and start to generate next cycle. User can set PWM counter as one-shot mode instead of periodic mode. If counter is set as one-shot mode, counter will stop and generate one interrupt request when it reaches zero. The value of comparator is used for pulse width modulation. The counter control logic changes the output level when down-counter value matches the value of compare register. NUC980 SERIES DATASHEET 6.10.2 Features  8 PWM channels with a 16-bit down counter and an interrupt each  4 complementary PWM pairs, (CH0, CH1), (CH2, CH3), (CH4, CH5), (CH6, CH7), each with a programmable dead-zone generator  Internal 8-bit prescaler and a clock divider for each PWM paired channel  Independent clock source selection for each PWM channel  Internal 16-bit down counter and 16-bit comparator for each independent PWM channel  PWM down-counter supports One-shot or Periodic mode Oct., 02, 2019 Page 186 of 246 Rev 1.11 NUC980 6.11 Watchdog Timer 6.11.1 Overview The purpose of Watchdog Timer (WDT) is to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.11.2 Features  20-bit free running up counter for WDT time-out interval  Selectable time-out interval (24 ~ 220) and the time-out interval is 0.48828125ms ~ 32s if WDT_CLK = 32.768 kHz  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset delay period  Supports to force WDT enabled after chip powered on or reset by setting WDTON (SYS_PWRON [3])  Supports WDT time-out wake-up function only if WDT clock source is selected as LXT. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 187 of 246 Rev 1.11 NUC980 6.12 Windowed Watchdog Timer (WWDT) 6.12.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.12.2 Features  6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the WWDT time-out window period flexible.  Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of WWDT counter. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 188 of 246 Rev 1.11 NUC980 6.13 Real Time Clock (RTC) 6.13.1 Overview The Real Time Clock (RTC) controller provides the real time clock and calendar information. The clock source of RTC controller is from an external 32.768 kHz low-speed crystal which connected at pins X32_IN and X32_OUT (refer to pin Description). The RTC controller provides the real time clock (hour, minute, second) in RTC_TIME (RTC Time Loading Register) as well as calendar information (year, month, day) in RTC_CAL (RTC Calendar Loading Register). It also offers RTC alarm function that user can preset the alarm time in RTC_TALM (RTC Time Alarm Register) and alarm calendar in RTC_CALM (RTC Calendar Alarm Register). The data format of RTC time and calendar message are all expressed in BCD (Binary Coded Decimal) format. The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second which are selected by RTC_TICK (RTC_TICK[2:0] Time Tick Register). When real time and calendar message in RTC_TIME and RTC_CAL are equal to alarm time and calendar settings in RTC_TALM and RTC_CALM, the ALMIF (RTC_INTSTS [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC alarm interrupt signal is generated if the ALMIEN (RTC_INTEN [0] Alarm Interrupt Enable) is enabled. Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or Powerdown mode if the corresponding interrupt enable bit (ALMIEN or TICKIEN) is set to 1 before chip enters Idle or Power-down mode. Real Time Clock (RTC) block can operate with independent power supply (RTC_VDD) while the system power is off. 6.13.2 Features Supports real time counter and calendar counter for RTC time and calendar check.  Supports time (hour, minute, second) and calendar (year, month, day) alarm and alarm mask settings.  Selectable 12-hour or 24-hour time scale.  Supports Leap Year indication.  Supports Day of the Week counter.  Supports frequency compensation mechanism for 32.768 kHz clock source.  All time and calendar message expressed in BCD format.  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.  Supports RTC Time Tick and Alarm match interrupt.  Supports chip wake-up from Idle or Power-down mode while alarm or relative alarm interrupt is generated.  Supports 64 bytes spare registers to store user’s important information.  Supports power on/off control mechanism to control system core power. Oct., 02, 2019 Page 189 of 246 Rev 1.11 NUC980 SERIES DATASHEET  NUC980 6.14 UART Interface Controller (UART) 6.14.1 Overview The chip provides ten channels of Universal Asynchronous Receiver/Transmitters (UART). The UART controller performs Normal Speed UART and supports flow control function. The UART controller performs a serial-to-parallel conversion on data received from the peripheral and a parallel-to-serial conversion on data transmitted from the CPU. Each UART controller channel supports ten types of interrupts. The UART controller also supports IrDA SIR, LIN and, RS-485 function modes and auto-baud rate measuring function. 6.14.2 Features  Full-duplex asynchronous communications  Separates receive and transmit 16/16 bytes entry FIFO for data payloads  Supports hardware auto-flow control  Programmable receiver buffer trigger level  Supports programmable baud rate generator for each channel individually  Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function  Supports 8-bit receiver buffer time-out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting DLY (UART_TOUT [15:8])  Supports Auto-Baud Rate measurement and baud rate compensation function – Support 9600 bps for UART_CLK is selected LXT. NUC980 SERIES DATASHEET  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface characteristics  – Programmable number of data bit, 5-, 6-, 7-, 8- bit character – Programmable parity bit, even, odd, no parity or stick parity bit generation and detection – Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports IrDA SIR function mode –   Supports for 3/16 bit duration for normal mode Supports LIN function mode (Only UART1 /UART2 with LIN function) – Supports LIN master/slave mode – Supports programmable break generation function for transmitter – Supports break detection function for receiver Supports RS-485 function mode – Supports RS-485 9-bit mode  Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction  Supports PDMA transfer function Oct., 02, 2019 Page 190 of 246 Rev 1.11 NUC980 6.15 Smart Card Host Interface 6.15.1 Overview The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully compliant with PC/SC Specifications. It also provides status of card insertion/removal. 6.15.2 Features ISO 7816-3 T = 0, T = 1 compliant  EMV2000 compliant  Three ISO 7816-3 ports  Separates receive/transmit 4 byte entry FIFO for data payloads  Programmable transmission clock frequency  Programmable receiver buffer trigger level  Programmable guard time selection (11 ETU ~ 267 ETU)  One 24-bit timer and two 8-bit timers for Answer to Reset (ATR) and waiting times processing  Supports auto direct / inverse convention function  Supports transmitter and receiver error retry and error number limiting function  Supports hardware activation sequence process, and the time between PWR on and CLK start is configurable  Supports hardware warm reset sequence process  Supports hardware deactivation sequence process  Supports hardware auto deactivation sequence when detected the card removal  Supports UART mode – Full duplex, asynchronous communications – Separates receiving / transmitting 4 bytes entry FIFO for data payloads – Supports programmable baud rate generator – Supports programmable receiver buffer trigger level – Programmable transmitting data delay time between the last stop bit leaving the TXFIFO and the de-assertion by setting EGT (SCn_EGT[7:0]) – Programmable even, odd or no parity bit generation and detection – Programmable stop bit, 1- or 2- stop bit generation Oct., 02, 2019 Page 191 of 246 Rev 1.11 NUC980 SERIES DATASHEET  NUC980 6.16 I²C Serial Interface Controller 6.16.1 Overview I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. There are four sets of I2C controllers which support Power-down wake-up function. 6.16.2 Features The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the I2C bus include: NUC980 SERIES DATASHEET  Supports up to three I2C ports  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Supports Standard mode (100 kbps), Fast mode (400 kbps) and Fast mode plus (1 Mbps)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allow devices with different bit rates to communicate via one serial bus  Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  Programmable clocks allow for versatile rate control  Supports 7-bit addressing and 10-bit addressing mode  Supports multiple address recognition ( four slave address with mask option)  Supports Power-down wake-up function  Supports setup/hold time programmable Oct., 02, 2019 Page 192 of 246 Rev 1.11 NUC980 6.17 Serial Peripheral Interface (SPI) 6.17.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The chip contains up to one set of SPI controllers performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. Each SPI controller can be configured as a master or a slave device and supports the PDMA function to access the data buffer. 6.17.2 Features  Up to two sets of SPI controllers  Supports Master or Slave mode operation  Master mode up to 100 MHz and Slave mode up to 30 MHz (when chip works at VDD = 2.7~3.6V)  Configurable bit length of a transaction word from 8 to 32-bit  Provides separate 4-level depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports Byte Reorder function  Supports Byte or Word Suspend mode  Supports PDMA transfer  Supports one data channel half-duplex transfer  Supports receive-only mode NUC980 SERIES DATASHEET Oct., 02, 2019 Page 193 of 246 Rev 1.11 NUC980 6.18 Quad Serial Peripheral Interface (QSPI) 6.18.1 Overview The Quad Serial Peripheral Interface (QSPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with the 4-wire bi-direction interface. The chip contains one QSPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. The QSPI controller supports 2-bit Transfer mode to perform full-duplex 2-bit data transfer and also supports Dual and Quad I/O Transfer mode and the controller supports the PDMA function to access the data buffer. 6.18.2 Features NUC980 SERIES DATASHEET  Supports Master or Slave mode operation  Master mode up to 100 MHz and Slave mode up to 100 MHz (when chip works at VDD = 2.7~3.6V)  Supports 2-bit Transfer mode  Supports Dual and Quad I/O Transfer mode  Configurable bit length of a transaction word from 8 to 32-bit  Provides separate 8-level depth transmit and receive FIFO buffers  Supports MSB first or LSB first transfer sequence  Supports Byte Reorder function  Supports Byte or Word Suspend mode  Supports PDMA transfer  Supports 3-Wire, no slave selection signal, bi-direction interface  Supports one data channel half-duplex transfer  Supports receive-only mode Oct., 02, 2019 Page 194 of 246 Rev 1.11 NUC980 6.19 I²S Controller (I²S) 6.19.1 Overview The I2S controller consists of I2S and PCM protocols to interface with external audio CODEC. The I2S and PCM interface supports 8, 16, 18, 20 and 24-bit left/right precision in record and playback. When operating in 18/20/24-bit precision, each left/right-channel sample is stored in a 32-bit word. Each left/right-channel sample has 24/20/18 MSB bits of valid data and other LSB bits are the padding zeros. When operating in 16-bit precision, right-channel sample is stored in MSB of a 32-bit word and leftchannel sample is stored in LSB of a 32-bit word. The following are the property of the DMA.  When 16-bit precision, the DMA always 8-beat incrementing burst (FIFO_TH = 0) or 4-beat incrementing burst (FIFO_TH = 1).  When 24/20/18-bit precision, the DMA always 16-beat incrementing burst (FIFO_TH = 0) or 8-beat incrementing burst (FIFO_TH = 1).  Always bus lock when 4-beat or 8-beat or 16-beat incrementing burst.  When reach eighth, quarter, middle and end address of destination address, a DMA_IRQ is triggered to CPU automatically. An AHB master port and an AHB slave port are offered in I2S controller. 6.19.2 Features   Support I2S interface record and playback – Left/right channel – 8, 16, 20, 24-bit data precision – Mater and slave mode Support PCM interface record and playback Two slots – 8, 16, 20, 24-bit data precision – Master mode  Use DMA to playback and record data, with interrupt  Support two addresses for left/right channel data and different slots Oct., 02, 2019 Page 195 of 246 NUC980 SERIES DATASHEET – Rev 1.11 NUC980 6.20 Ethernet MAC Controller (EMAC) 6.20.1 Overview This chip provides 2 Ethernet MAC Controller (EMAC) for Network application. The Ethernet MAC controller consists of IEEE 802.3/Ethernet protocol engine with internal CAM function for recognizing Ethernet MAC addresses; Transmit-FIFO, Receive-FIFO, TX/RX state machine controller, time stamping engine for IEEE 1588, Magic Packet parsing engine and status controller. The EMAC supports RMII (Reduced MII) interface to connect with external Ethernet PHY. 6.20.2 Features  Supports IEEE Std. 802.3 CSMA/CD protocol  Supports Ethernet frame time stamping for IEEE Std. 1588 – 2002 protocol  Supports both half and full duplex for 10 Mbps or 100 Mbps operation  Supports RMII interface  Supports MII Management function to control external Ethernet PHY  Supports pause and remote pause function for flow control  Supports long frame (more than 1518 bytes) and short frame (less than 64 bytes) reception  Supports 16 entries CAM function for Ethernet MAC address recognition  Supports Magic Packet recognition to wake system up from power-down mode  Supports 256 bytes transmit FIFO and 256 bytes receive FIFO  Supports DMA function NUC980 SERIES DATASHEET Oct., 02, 2019 Page 196 of 246 Rev 1.11 NUC980 6.21 High Speed USB 2.0 Device Controller (HSUSBD) 6.21.1 Overview The USB device controller interfaces the AHB bus and the UTMI bus. The USB controller contains both the AHB master interface and AHB slave interface. CPU programs the USB controller registers through the AHB slave interface. For IN or OUT transfer, the USB device controller needs to write data to memory or read data from memory through the AHB master interface. The USB device controller is complaint with USB 2.0 specification and it contains 12 configurable endpoints in addition to control endpoint. These endpoints could be configured to BULK, INTERRUPT or ISOCHRONOUS. The USB device controller has a built-in DMA to relieve the load of CPU. 6.21.2 Features  USB Specification reversion 2.0 compliant  Supports 12 configurable endpoints in addition to Control Endpoint  Each of the endpoints can be Isochronous, Bulk or Interrupt and either IN or OUT direction  Three different operation modes of an in-endpoint － Auto Validation mode, Manual Validation mode, Fly mode  Supports DMA operation  4096 Bytes Configurable RAM used as endpoint buffer  Supports Endpoint Maximum Packet Size up to 1024 bytes NUC980 SERIES DATASHEET Oct., 02, 2019 Page 197 of 246 Rev 1.11 NUC980 6.22 USB 2.0 Host Controller (USBH) 6.22.1 Overview This chip is equipped with a USB 2.0 HS/FS Host Controller (USBH) that supports Enhanced Host Controller Interface (EHCI) and Open Host Controller Interface (OpenHCI, OHCI) Specification, a register-level description of a host controller, to manage the devices and data transfer of Universal Serial Bus (USB). The USBH supports an integrated Root Hub with eight USB ports (two ports with on-chip USB 2.0 high speed transceiver and up to six USB 1.1 Host Lite ports), a DMA for real-time data transfer between system memory and USB bus, port power control and port over current detection. The USBH is responsible for detecting the connect and disconnect of USB devices, managing data transfer, collecting status and activity of USB bus, providing power control and detecting over current of attached USB devices. 6.22.2 Features NUC980 SERIES DATASHEET  Compliant with Universal Serial Bus (USB) Specification Revision 2.0.  Supports Enhanced Host Controller Interface (EHCI) Specification Revision 1.0  Supports Open Host Controller Interface (OpenHCI) Specification Revision 1.0.  Supports high-speed (480Mbps), full-speed (12Mbps) and low-speed (1.5Mbps) USB devices.  Supports Control, Bulk, Interrupt, Isochronous and Split transfers.  Supports an integrated Root Hub.  Supports a port routing logic to route full/low speed device to OHCI controller.  Supports a USB host port with on-chip USB2.0 high speed transceiver shared with USB device (dual-role function).  Supports a USB host only port with on-chip USB2.0 high speed transceiver.  Supports up to six USB 1.1 Host Lite ports.  Supports port power control and port over current detection.  Supports DMA for real-time data transfer. Oct., 02, 2019 Page 198 of 246 Rev 1.11 NUC980 6.23 Controller Area Network (CAN) 6.23.1 Overview The C_CAN consists of the CAN Core, Message RAM, Message Handler, Control Registers and Module Interface. The CAN Core performs communication according to the CAN protocol version 2.0 part A and B. The bit rate can be programmed to values up to 1MBit/s. For the connection to the physical layer, additional transceiver hardware is required. For communication on a CAN network, individual Message Objects are configured. The Message Objects and Identifier Masks for acceptance filtering of received messages are stored in the Message RAM. All functions concerning the handling of messages are implemented in the Message Handler. These functions include acceptance filtering, the transfer of messages between the CAN Core and the Message RAM, and the handling of transmission requests as well as the generation of the module interrupt. The register set of the C_CAN can be accessed directly by the software through the module interface. These registers are used to control/configure the CAN Core and the Message Handler and to access the Message RAM. 6.23.2 Features Supports CAN protocol version 2.0 part A and B  Bit rates up to 1 MBit/s  32 Message Objects  Each Message Object has its own identifier mask  Programmable FIFO mode (concatenation of Message Objects)  Maskable interrupt  Disabled Automatic Re-transmission mode for Time Triggered CAN applications  Programmable loop-back mode for self-test operation  16-bit module interfaces to the AMBA APB bus  Supports wake-up function Oct., 02, 2019 Page 199 of 246 NUC980 SERIES DATASHEET  Rev 1.11 NUC980 6.24 Flash Memory Interface (FMI) 6.24.1 Overview The Flash Memory Interface (FMI) in this chip has DMA unit and FMI unit. The DMA unit provides a DMA (Direct Memory Access) function for FMI to exchange data between system memory (ex. SDRAM) and shared buffer (128 bytes), and the FMI unit control the interface of SD0/eMMC0 or NAND Flash. The interface controller can support SD0/eMMC0 and NAND-type Flash and the FMI is cooperated with DMAC to provide a fast data transfer between system memory and cards. 6.24.2 Features  Supports single DMA channel and address in non-word boundary.  Supports hardware Scatter-Gather function.  Supports 128Bytes shared buffer for data exchange between system memory and Flash device. (Separate into two 64 bytes ping-pong FIFO).  Supports SD0/eMMC0 Flash device.  Supports SLC and MLC NAND type Flash.  Adjustable NAND page sizes. (2048B+spare area, 4096B+spare area and 8192B+spare area).  Supports up to 8bit/12bit/24bit hardware ECC calculation circuit to protect data communication.  Supports programmable NAND timing cycle NUC980 SERIES DATASHEET Oct., 02, 2019 Page 200 of 246 Rev 1.11 NUC980 6.25 Secure Digital Host Controller (SDH) 6.25.1 Overview The Secure Digital Host Controller (SD Host) has DMAC unit and SD unit. The DMAC unit provides a DMA (Direct Memory Access) function for SD to exchange data between system memory and shared buffer (128 bytes), and the SD unit controls the interface of SD/SDHC. The SD Host Controller can support SD/SDHC and cooperated with DMAC to provide a fast data transfer between system memory and cards. 6.25.2 Features  AMBA AHB master/slave interface compatible, for data transfer and register read/write.  Supports single DMA channel.  Supports hardware Scatter-Gather function..  Using single 128 Bytes shared buffer for data exchange between system memory and cards.  Synchronous design for DMA with single clock domain, AHB bus clock (HCLK).  Interface with DMAC for register read/write and data transfer.  Supports SD/SDHC card.  Completely asynchronous design for Secure Digital with two clock domains, HCLK and Engine clock, note that frequency of HCLK should be higher than the frequency of peripheral clock. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 201 of 246 Rev 1.11 NUC980 6.26 Cryptographic Accelerator (CRYPTO) 6.26.1 Overview The Crypto (Cryptographic Accelerator) includes a secure pseudo random number generator (PRNG) core and supports AES, SHA, HMAC, RSA and ECC algorithms. The PRNG core supports 64 bits, 128 bits, 192 bits, and 256 bits random number generation. The AES accelerator is an implementation fully compliant with the AES (Advance Encryption Standard) encryption and decryption algorithm. The AES accelerator supports ECB, CBC, CFB, OFB, CTR, CBCCS1, CBC-CS2, and CBC-CS3 mode. The SHA accelerator is an implementation fully compliant with the SHA-160, SHA-224, SHA-256, SHA384, and SHA-512 and corresponding HMAC algorithms. The ECC accelerator is an implementation fully compliant with elliptic curve cryptography by using polynomial basis in binary field and prime filed. The RSA accelerator is an implementation fully compliant with 1024 and 2048 bit RSA cryptography. 6.26.2 Features  PRNG –  NUC980 SERIES DATASHEET     Supports 64 bits, 128 bits , 192 bits, and 256 bits random number generation AES – Supports FIPS NIST 197 – Supports SP800-38A and addendum – Supports 128, 192, and 256 bits key – Supports both encryption and decryption – Supports ECB, CBC, CFB, OFB , CTR, CBC-CS1, CBC-CS2, and CBC-CS3 mode – Supports key expander SHA – Supports FIPS NIST 180, 180-2 – Supports SHA-160, SHA-224, SHA-256, SHA-384, and SHA-512 HMAC – Supports FIPS NIST 180, 180-2 – Supports HMAC-SHA-160, HMAC-SHA-224, HMAC-SHA-256, HMAC-SHA-384, and HMAC-SHA-512 ECC – Supports both prime field GF(p) and binary filed GF(2m) – Supports NIST P-192, P-224, P-256, P-384, and P-521 – Supports NIST B-163, B-233, B-283, B-409, and B-571 – Supports NIST K-163, K-233, K-283, K-409, and K-571 – Supports point multiplication, addition and doubling operations in GF(p) and GF(2m) – Supports modulus division, multiplication, addition and subtraction operations in GF(p) RSA Oct., 02, 2019 Page 202 of 246 Rev 1.11 NUC980 – Supports both encryption and decryption – Supports up to 2048 bits NUC980 SERIES DATASHEET Oct., 02, 2019 Page 203 of 246 Rev 1.11 NUC980 6.27 Capture Sensor Interface Controller (CAP) 6.27.1 Overview The Image Capture Interface is designed to capture image data from a sensor. After capturing or fetching image data, it will process the image data, and then FIFO output them into frame buffer. 6.27.2 Features  8-bit RGB565 sensor  8-bit YUV422 sensor  Supports CCIR601 YCbCr color range scale to full YUV color range  Supports 4 packaging format for packet data output: YUYV, Y only, RGB565, RGB555  Supports YUV422 planar data output  Supports the CROP function to crop input image to the required size for digital application  Supports the down scaling function to scale input image to the required size for digital application  Supports frame rate control  Supports field detection and even/odd field skip mechanism  Supports packet output dual buffer control through hardware buffer controller  Supports negative/sepia/posterization color effect NUC980 SERIES DATASHEET Oct., 02, 2019 Page 204 of 246 Rev 1.11 NUC980 6.28 Analog to Digitial Converter (ADC) 6.28.1 Overview The NuMicro® NUC980 series contains one 12-bit Successive Approximation Register analog-to-digital converter (SAR A/D converter) with 9 input channels. 6.28.2 Features  Resolution: 12-bit resolution  DNL: +/-1.5 LSB, INL: +/-3 LSB  Data Rate up to 200kSPS  Analog Input Range: VREF to AGND, can be rail-to-rail  Analog Supply: 2.7-3.6V  Digital Supply: 1.2V  9 Single-Ended analog inputs  Auto Power Down  Low Power Consumption: 2170uW (at 200k SPS), < 1uA NUC980 SERIES DATASHEET Oct., 02, 2019 Page 205 of 246 Rev 1.11 NUC980 7 ELECTRICAL CHARACTERISTICS 7.1 Absolute Maximum Ratings PARAMETER SYMBOL MIN. MAX UNIT VVDD12VVSS Core DC Power Supply -0.3 +1.5 V VVDD33VVSS I/O DC Power Supply -0.3 +4.6 V MVDD  MVSS (1) I/O DC Power Supply for SDR Type SDRAM -0.3 +4.6 V MVDD - MVVSS(2) I/O DC Power Supply for DDR,DDR2 Type SDRAM -0.3 +2.3 V VVSS-0.3 +5 V VIN Input Voltage TA Operating Temperature -40 +85 C TST Storage Temperature -55 +150 C IDD Maximum Current into CORE_VDD - 200 mA ISS Maximum Current out of CORE_VSS - 200 mA Maximum Current sunk by a I/O pin - 20 mA Maximum Current sourced by a I/O pin - 30 mA Maximum Current sunk by total I/O pins - 200 mA Maximum Current sourced by total I/O pins - 200 mA IIO Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 206 of 246 Rev 1.11 NUC980 7.2 DC Electrical Characteristics 7.2.1 NUC980 Series DC Electrical Characteristics (VDD33-VSS=3.3V, TA = 25C, FOSC = 12 MHz unless otherwise specified.) Specification Parameter Sym. Test Conditions MIN. TYP. Max. Unit Core Operation voltage VDD12 1.14 1.2 1.32 V I/O Operation Voltage VDD33 2.97 3.3 3.63 V Memory I/O Operation Voltage for DDR or DDR2 MVDD (1) 1.70 1.8 1.90 V Memory I/O Operation Voltage for SDR Type SDRAM MVDD (2) 2.97 3.3 3.63 V Battery Operation Voltage VBAT33 2.0 3.3 3.63 V USB Operation Voltage (1) VUSB0_VDD12 USB Operation Voltage (2) V VUSB1_VDD12 1.14 1.2 1.32 VUSB0_VDD33 2.97 3.3 3.63 V VUSB1_VDD33 Power Ground VSS AVSS -0.3 Analog Operating Voltage AVDD33 2.97 Analog Reference Voltage AVref 0 V 3.3 3.63 V AVDD33 V 150 mA VDD12 = 1.2V IMVDD_1 50 mA IUSB0_VDD12_1 7.5 mA TA = 25C, FOSC = 12 MHz IUSB1_VDD12_1 7.5 mA Frequency of 300/150 MHz. IUSB0_VDD33_1 35 mA All IPs on, all GPIO are input with pull-up. IUSB1_VDD33_1 35 mA IVBAT33_1 100 uA IVDD12 132 mA IMVDD_2 44 mA IUSB0_VDD12_2 7.5 mA TA = 25C, FOSC = 12 MHz IUSB1_VDD12_2 7.5 mA Frequency of 264/132 MHz. IUSB0_VDD33_2 35 mA All IPs on, all GPIO are input with pull-up. IUSB1_VDD33_2 35 mA IVBAT33_2 100 uA MVDD = 1.8V VDD33 = 3.3V Current Consumption of Normal Operating Mode 1 CPUCLK/DDR_CLK is VDD12 = 1.2V MVDD = 1.8V VDD33 = 3.3V Current Consumption of Normal Operating Mode 2 Oct., 02, 2019 Page 207 of 246 CPUCLK/DDR_CLK Rev 1.11 is NUC980 SERIES DATASHEET IVDD12 NUC980 Specification Parameter Sym. Test Conditions MIN. Current Consumption of Power Down Mode System Power Off & RTC VBAT33 Power only TYP. Max. Unit ISTDBY_VDD12 3 mA VDD12 = 1.2V ISTDBY_MVDD 6 mA MVDD = 1.8V ISTDBY_VDD33 5 A VDD33 = 3.3V ISTDBY_USB0_VDD33 0 A VUSB0_VDD33 = 3.3V ISTDBY_USB1_VDD33 0 A VUSB1_VDD33 = 3.3V ISTDBY_USB0_VDD12 2.5 A VUSB0_VDD12 = 1.2V ISTDBY_USB1_VDD12 2.5 A VUSB1_VDD12 = 1.2V ISTDBY_AVDD33 25 A AVDD33 = 3.3V ISTDBY_VBAT33 100 A VBAT33 = 3.3V IVBAT33 10 uA NUC980 SERIES DATASHEET Oct., 02, 2019 Page 208 of 246 Rev 1.11 NUC980 7.2.2 NUC980 Series GPIO Characteristics (VDD33-VSS=3.3 V, TA = 25C, FOSC = 12 MHz unless otherwise specified.) Input Leakage Current PA, PB, PC, PD, PE, PF, PG VVDD33 = 3.63V ILK1 -10 - 10 A VIL1 - - 0.8 V VDD33 = 3.63V VIH1 2.0 - - V VDD33 = 3.63V 0.3*VDD33 V 0V < VIN < VVDD33 Input Low Voltage PA, PB, PC, PD, PE, PF, PG (TTL input) Input High Voltage PA, PB, PC, PD, PE, PF, PG (TTL input) Input Low Voltage PA, PB, PC, PD, PE, PF, PG, (Schmitt input) VIL2 Input High Voltage PA, PB, PC, PD, PE, PF, PG, (Schmitt input) VIH2 0.7*VDD33 V Hysteresis voltage PA, PB, PC, PD, PE, PF, PG (Schmitt input) VHY 0.2*VDD33 V ISR21 8 mA ISK1 8 mA Source Current PA, PB, PC, PD, PE, PF, PG, (Push-pull Mode) Sink Current PA, PB, PC, PD, PE, PF, PG (Push-pull Mode) PA, PB, PC, PD, PE, PF, PG, HDS Input Pull-down Resistance PA, PB, PC, PD, PE, PF, PG Oct., 02, 2019 RPU - - 82 kΩ VIN=VDD33-0.4 VDD33 = 3.63V VIN=VSS+0.4 VDD33=3.63V, apply GPIO pin Vin= 0V and measure the input current Reverse the current to Resistor value, R=V/I RPD - - 91 kΩ VDD33=3.63V, apply GPIO pin Vin= 3.63V and measure the input current Reverse the current to Resistor value, R=V/I Page 209 of 246 Rev 1.11 NUC980 SERIES DATASHEET Input Pull-up Resistance VDD33 = 3.63V NUC980 7.3 AC Electrical Characteristics 7.3.1 External 12MHz High Speed Crystal Symbol Parameter Min. Typ. Max Unit Test Conditions VHXT Operation Voltage 2.97 3.3 3.63 V VHXT = VDD33 TA Temperature -40 - 85 C - fHXT Clock Frequency - 12 - MHz - IHXT Operating Current - 0.8 - mA TA=25OC, AVDD33=3.3V Note: Guaranteed by characterization results, not tested in production. 7.3.1.1 Typical Crystal Application Circuits Crystal ESR (ohm) C1, C2 12 MHz < 50 15 pf XT1_IN XT1_OUT 12 MHz Crystal NUC980 SERIES DATASHEET C1 C2 Vss Vss Figure 7.3-1 Typical HXT Crystal Application Circuit Oct., 02, 2019 Page 210 of 246 Rev 1.11 NUC980 7.3.2 Symbol External 32.768 kHz Low Speed Crystal Parameter Min. Typ. Max Unit Operation Voltage 2.97 3.3 3.63 V TA Temperature -40 - 85 C fLXT Clock Frequency - 32.768 - kHz VLXT ILXT Operating Current 1.6 uA Test Conditions VLXT = VBAT33 O TA=25 C, VBAT33=3.3V Note: Guaranteed by characterization results, not tested in production. 7.3.2.1 Typical Crystal Application Circuits Crystal C1 C2 32.768 kHz 15 pf 15 pf X32_IN X32_OUT Crystal C1 C2 NUC980 SERIES DATASHEET Vss Vss Figure 7.3-2 Typical LXT Crystal Application Circuit Oct., 02, 2019 Page 211 of 246 Rev 1.11 NUC980 7.3.3 Power Sequence & nRESET Timing 7.3.3.1 Power up Sequence Power up Sequence & nRESET Timing Case 1 When TVDD33 ≥ TMVDD ≥ TVDD12 (the time of delay gap between < 0.5mS is prefer). Note: 1. The time of delay gap is meaning that timing between TVDD33 with TVDD12. 2. If the time of delay gap < 0.5mS will be effective to prevent that transient phenomenon by power-on. NUC980 SERIES DATASHEET Figure 7.3-3 Power up Sequence & nRESET timing Case 1 Oct., 02, 2019 Page 212 of 246 Rev 1.11 NUC980 Power up Sequence & nRESET Timing Case 2 When TVDD12 ≥ TMVDD ≥ TVDD33, it is acceptable as the below figure. (the time of delay gap between < 1mS is prefer) Note: 1. The time of delay gap is meaning that timing between TVDD12 with TVDD33. 2. The time of delay gap < 1mS is prefer although NUC980 has that protection of latchup prevention. NUC980 SERIES DATASHEET Figure 7.3-4 Power up Sequence & nRESET timing Case 2 7.3.3.2 Power down Sequence, Power down sequence between AVDD33/VDD33, VDD12 and MVDD is don’t care. Note: 1. TVDD12 represents VDD12 powered time. 2. TMVDD represents MVDD powered time. 3. TVDD33 represents VDD33/AVDD33 powered. Oct., 02, 2019 Page 213 of 246 Rev 1.11 NUC980 7.3.4 nRESET PIN characteristics Symbol Parameter Min. Typ. Max. unit Test Conditions VILR Negative going threshold (Schmitt input), nRESET - - 0.3*VDD33 V VDD33 = 3.3V VIHR Positive going threshold (Schmitt Input), nRESET 0.7*VDD33 - - V VDD33 = 3.3V RRST Internal nRESET pin pull up resistor - - 84 KΩ VDD33=3.63V, apply nRESET pin Vin= 3.63V and measure the input current Reverse the current to Resistor value, R=V/I tFR1 32 nRESET input filtered time uS VDD33 = 3.3V Note: Guaranteed by characterization and design results, not tested in production. 7.3.5 PLL characteristics Symbol Parameter fPLL_IN PLL input clock fPLL_OUT TS Conditions Min Typ Max 12 Unit MHz PLL multiplier output clock 25 500 MHz PLL stable time[*1] 100 200 µs Jitter Cycle-to-cycle Jitter[*2] IDD12 Power consumption Peak to peak @ 300M 150 VDD12=1.2V@500MHz ps 3 mA Note: Guaranteed by characterization and design results, not tested in production. NUC980 SERIES DATASHEET Oct., 02, 2019 Page 214 of 246 Rev 1.11 NUC980 7.3.6 EBI Timing Symbol Parameter Min Typ Max Unit Test Condition TtACS Address Setup Time to EBI_nCS Falling Edge - 0 - THCLK[1] - TtCOS EBI_nCS Setup Time to EBI_nWE or EBI_nOE Falling Edge - 1 - THCLK[1] - TtACC EBI_nWE or EBI_nOE Active Low Time 1 - 32 THCLK[1] - TtCOH EBI_nCS Hold Time from EBI_nWE or EBI_nOE Rising Edge 0 - 8 THCLK[1] - TSU_EBI_RD EBI_DATA Read Setup Time to EBI_nOE Rising Edge 1 - - THCLK[1] - Notes: 1. THCLK is the period of EBI’s operating clock. Table 7.3-1 EBI Characteristics EBI_ADDR[9:0] TtACS EBI_nCS[4:0] TtCOS TtCOH NUC980 SERIES DATASHEET EBI_nWE, EBI_nBE[1:0] TtACC+2 EBI_DATA[15:0 (Write)] Valid Data TtCOS EBI_nOE TtCOH TtACC+2 TSU_EBI_RD EBI_DATA[15:0 (Read)] Valid Data Figure 7.3-5 External Bus Interface Timing Diagram Oct., 02, 2019 Page 215 of 246 Rev 1.11 NUC980 7.3.7 I2C Interface Timing Symbol Parameter Standard Mode[1][2] Fast Mode[1][2] Min Max Min Max Unit tLOW SCL low period 4.7 - 1.3 - µs tHIGH SCL high period 4 - 0.6 - µs tSU; STA Repeated START condition setup time 4.7 - 0.6 - µs tHD; STA START condition hold time 4 - 0.6 - µs tSU; STO STOP condition setup time 4 - 0.6 - µs tBUF Bus free time 4.7[3] - 1.2[3] - µs tSU;DAT Data setup time 250 - 100 - ns tHD;DAT Data hold time 0[4] 3.45[5] 0[4] 0.8[5] µs tr SCL/SDA rise time - 1000 20+0.1Cb 300 ns tf SCL/SDA fall time - 300 - 300 ns Cb Capacitive load for each bus line - 400 - 400 pF Notes: 1. Guaranteed by characteristic, not tested in production 2. HCLK must be higher than 2 MHz to achieve the maximum standard mode I 2C frequency. It must be higher than 8 MHz to achieve the maximum fast mode I2C frequency. 3. I2C controller must be retriggered immediately at slave mode after receiving STOP condition. NUC980 SERIES DATASHEET 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL. 5. The maximum hold time of the Start condition has only to be met if the interface does not stretch the low period of SCL signal. 2 Table 7.3-2 I C Interface Characteristics STOP Repeated START START STOP I2C_SDA TBUF TLOW TR I2C_SCL THD_STA TF THIGH THD_DAT TSU_DAT TSU_STA TSU_STO Figure 7.3-6 I2C Interface Timing Diagram Oct., 02, 2019 Page 216 of 246 Rev 1.11 NUC980 7.3.8 7.3.8.1 SPI Interface Timing SPI Master Mode Timing Specificaitons Symbol FSPICLK 1/ TSPICLK Test Conditions Parameter Min Typ Max Unit - - 100 MHz SPI clock frequency tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tDS Data input setup time 1.8 - - ns tDH Data input hold time 3.8 - - ns tV Data output valid time - - 1.1 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: Table 7.3-3 SPI Master Mode Characteristics tCLKH tCLKL CLKP=0 SPICLK SPIx_CLK CLKP=1 tV Data Valid Data Valid tDS SPIx_MISO MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV SPIx_MOSI MOSI Data Valid tDS MISO SPIx_MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 7.3-7 SPI Master Mode Timing Diagram Oct., 02, 2019 Page 217 of 246 Rev 1.11 NUC980 SERIES DATASHEET SPIx_MOSI MOSI NUC980 7.3.8.2 Symbol SPI Slave Mode Timing Test Conditions Specificaitons Parameter Min Typ Max Unit FSPICLK SPI clock frequency 1/ TSPICLK - - 30 MHz tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tSS Slave select setup time 1 TSPICLK + 2ns - ns tSH Slave select hold time 1 TSPICLK - - ns tDS Data input setup time 1 - - ns tDH Data input hold time 3 - - ns tV Data output valid time - - 10 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: Table 7.3-4 SPI Slave Mode Characteristics NUC980 SERIES DATASHEET Oct., 02, 2019 Page 218 of 246 Rev 1.11 NUC980 SSACTPOL=1 SPIx_SS SPI SS tSS tSH SSACTPOL=0 tCLKH CLKPOL=0 TXNEG=1 RXNEG=0 tCLKL SPIx_CLK SPI Clock CLKPOL=1 TXNEG=0 RXNEG=1 tV SPISPI data output data output (SPI_MISO) (SPIx_MISO) Data Valid Data Valid tDS SPI SPIdata datainput input (SPI_MOSI) (SPIx_MOSI) Data Valid SSACTPOL=1 SPI SS SPIx_SS tDH Data Valid tSS tSH SSACTPOL=0 CLKPOL=0 TXNEG=0 RXNEG=1 tCLKH tCLKL SPIx_CLK SPI Clock CLKPOL=1 TXNEG=1 RXNEG=0 SPI data input SPI data input (SPI_MOSI) (SPIx_MOSI) Data Valid tDS NUC980 SERIES DATASHEET SPI data output SPI data output (SPI_MISO) (SPIx_MISO) tV Data Valid tDH Data Valid Data Valid Figure 7.3-8 SPI Slave Mode Timing Diagram Oct., 02, 2019 Page 219 of 246 Rev 1.11 NUC980 7.3.9 QSPI Interface Timing 7.3.9.1 QSPI Master Mode Timing Specificaitons Symbol FSPICLK 1/ TSPICLK Test Conditions Parameter Min Typ Max Unit - - 100 MHz SPI clock frequency tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tDS Data input setup time 1.8 - - ns tDH Data input hold time 3.8 - - ns tV Data output valid time - - 1.5 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: Table 7.3-5 QSPI Master Mode Characteristics tCLKH tCLKL CLKP=0 SPICLK QSPIx_CLK CLKP=1 tV NUC980 SERIES DATASHEET QSPIx_MOSI MOSI Data Valid Data Valid tDS QSPIx_MISO MISO Data Valid CLKP=0, TX_NEG=1, RX_NEG=0 or CLKP=1, TX_NEG=0, RX_NEG=1 tDH Data Valid tV QSPIx_MOSI MOSI Data Valid tDS MISO QSPIx_MISO Data Valid CLKP=0, TX_NEG=0, RX_NEG=1 or CLKP=1, TX_NEG=1, RX_NEG=0 tDH Data Valid Data Valid Figure 7.3-9 QSPI Master Mode Timing Diagram Oct., 02, 2019 Page 220 of 246 Rev 1.11 NUC980 7.3.9.2 QSPI Slave Mode Timing Specificaitons Symbol FSPICLK 1/ TSPICLK Test Conditions Parameter SPI clock frequency Min Typ Max Unit - - 30 MHz tCLKH Clock output High time TSPICLK / 2 ns tCLKL Clock output Low time TSPICLK / 2 ns tSS Slave select setup time 1 TSPICLK + 2ns - - ns tSH Slave select hold time 1 TSPICLK - - ns tDS Data input setup time 2.1 - - ns tDH Data input hold time 4.1 - - ns tV Data output valid time - - 11.5 ns 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF 2.7 V ≤ VDD ≤ 3.6 V, CL = 30 pF Note: Table 7.3-6 QSPI Slave Mode Characteristics NUC980 SERIES DATASHEET Oct., 02, 2019 Page 221 of 246 Rev 1.11 NUC980 SSACTPOL=1 QSPIx_SS SPI SS tSS tSH SSACTPOL=0 tCLKH CLKPOL=0 TXNEG=1 RXNEG=0 tCLKL QSPIx_CLK SPI Clock CLKPOL=1 TXNEG=0 RXNEG=1 tV QSPI SPIdata dataoutput output (SPI_MISO) (QSPIx_MISO) Data Valid Data Valid tDS QSPI SPI data data input input (SPI_MOSI) (QSPIx_MOSI) Data Valid SSACTPOL=1 SPI SS QSPIx_SS tDH Data Valid tSS tSH SSACTPOL=0 CLKPOL=0 TXNEG=0 RXNEG=1 tCLKH tCLKL QSPIx_CLK SPI Clock CLKPOL=1 TXNEG=1 RXNEG=0 NUC980 SERIES DATASHEET QSPI SPIdata dataoutput output (SPI_MISO) (QSPIx_MISO) QSPI SPIdata datainput input (SPI_MOSI) (QSPIx_MOSI) tV Data Valid tDS Data Valid tDH Data Valid Data Valid Figure 7.3-10 QSPI Slave Mode Timing Diagram Oct., 02, 2019 Page 222 of 246 Rev 1.11 NUC980 7.3.10 I2S Interface Timing Symbol Parameter Min Typ Max Unit Test Condition TP_I2S_BITCLK I2S_BITCLK Period 50 - - ns - TH_I2S_BITCLK I2S_BITCLK High Time 25 - - ns - TL_I2S_BITCLK I2S_BITCLK Low Time 25 - - ns - TDLY_I2S_DO I2S_BITCLK Rising to Valid I2S_WS or I2S_DATAO Delay - - 6 ns - THD_I2S_DO I2S_WS or I2S_DATAO Hold Time from I2S_BITCLK Rising 1 - - ns TSU_I2S_DI I2S_DATAI Setup Time to I2S_BITCLK Rising 5 - - ns - THD_I2S_DI I2S_DATAI Hold Time from I2S_BITCLK Rising 3 - - ns - 2 Table 7.3-7 I S Interface Characteristics TP_I2S_BITCLK TL_I2S_BITCLK TH_I2S_BITCLK I2S_BITCLK I2S_DATAI NUC980 SERIES DATASHEET TSU_I2S_DI THD_I2S_DI I2S_WS I2S_DATAO TDLY_I2S_DO THD_I2S_DO Figure 7.3-11 I2S Interface Timing Diagram Oct., 02, 2019 Page 223 of 246 Rev 1.11 NUC980 7.3.11 Ethernet Interface Timing 7.3.11.1 RMII Interface Timing Symbol Parameter Min Typ Max Unit Test Condition - 20.0 +/- 50 ppm - ns - TP_RMII_REFCLK RMII_REFCLK Period TH_RMII_REFCLK RMII_REFCLK High Time 8.0 10.0 12.0 ns - TL_RMII_REFCLK RMII_REFCLK Low Time 8.0 10.0 12.0 ns - TDLY_RMII_TX RMII_REFCLK Rising to Valid RMII_TXEN, RMII_TXDATA0 and RMII_TXDATA1 Delay - - 17.3 ns - TSU_RMII_RX RMII_CRSDV, RMII_RXDATA0 and RMII_RXDATA1 Setup Time to RMII_REFCLK Rising 5 - - ns - THD_RMII_RX RMII_CRSDV, RMII_RXDATA0 and RMII_RXDATA1 Hold Time from RMII_REFCLK Rising 2 - - ns - Table 7.3-8 RMII Interface Characteristics TP_RMII_REFCLK TH_RMII_REFCLK TL_RMII_REFCLK RMIIx_REFCLK NUC980 SERIES DATASHEET RMIIx_TXEN RMIIx_TXDATA0 RMIIx_TXDATA1 TDLY_RMII_TX RMIIx_CRSDV RMIIx_RXDATA0 RMIIx_RXDATA1 TSU_RMII_RX THD_RMII_RX Figure 7.3-12 RMII Interface Timing Diagram Oct., 02, 2019 Page 224 of 246 Rev 1.11 NUC980 7.3.11.2 Ethernet PHY Management Interface Timing Symbol Parameter Min Typ Max Unit Test Condition TP_RMII_MDC RMII_MDC Period 400 - - ns - TH_RMII_MDC RMII_MDC High Time 200 - - ns - TL_RMII_MDC RMII_MDC Low Time 200 - - ns - TDLY_RMII_MDIOWR RMII_MDC Falling to Valid RMII_MDIO Delay - - 10 ns - TSU_RMII_MDIORD RMII_MDIO Setup Time to RMII_MDC Rising 10 - - ns - THD_RMII_MDIORD RMII_MDIO Hold Time from RMII_MDC Rising 10 - - ns - Table 7.3-9 Ethernet PHY Management Interface Characteristics TP_RMII_MDC TH_RMII_MDC TL_RMII_MDC RMIIx_MDC RMIIx_MDIO (Write) TDLY_RMII_MDIOWR NUC980 SERIES DATASHEET RMIIx_MDIO (Read) TSU_RMII_MDIORD THD_RMII_MDIORD Figure 7.3-13 Ethernet PHY Management Interface Timing Diagram Oct., 02, 2019 Page 225 of 246 Rev 1.11 NUC980 7.3.12 NAND Interface Timing Symbol Parameter Min Typ Max Unit Test Condition TH_NAND_nWE NAND_nWE High Time - 13.34[1] - ns - TL_NAND_nWE NAND_nWE Low Time - 40[2] - ns - TDLY_DATA_OUT NAND_nRE Falling to Valid NAND_DATA Delay - - 35[3] ns - THD_DATA_OUT NAND_DATA Hold Time from NAND_nRE Rising - - 30[3] ns - TSU_DATA_IN NAND_DATA Setup Time to NAND_nWE Rising 20[3] - - ns - THD_DATA_IN NAND_DATA Hold Time from NAND_nWE Rising 10[3] - - ns - Notes: 1. NAND controller operating clock is 150 MHz and HI_WID (FMI_NANDTMCTL[15:8]) is 0x1. 2. NAND controller operating clock is 150 MHz and LO_WID (FMI_NANDTMCTL[7:0]) is 0x5. 3. NAND controller operating clock is 150 MHz. Table 7.3-10 NAND Interface Characteristics NAND_nCS0 NAND_nCS1 NAND_ALE NAND_CLE NUC980 SERIES DATASHEET NAND_nRE THD_DATA_OUT TDLY_DATA_OUT NAND_DATA[7:0] (Read) NAND_nWE TL_NAND_nWE TH_NAND_nWE THD_DATA_IN TSU_DATA_IN NAND_DATA[7:0] (Write) Figure 7.3-14 NAND Interface Timing Diagram Oct., 02, 2019 Page 226 of 246 Rev 1.11 NUC980 7.3.13 SD Interface Timing 7.3.13.1 Default Mode Timing Symbol Parameter Min Typ Max Unit Test Condition 40 - - ns - 2,500 - - ns SD_CLK Period TP_SD_CLK (Data Transfer Mode) TP_SD_CLK_ID SD_CLK Period (Identification Mode) TH_SD_CLK SD_CLK High Time - 20 - ns - TL_SD_CLK SD_CLK Low Time - 20 - ns - 5 - - ns - 5 - - ns - - - 14 ns - SD_DATA Setup Time to TSU_SD_IN SD_CLK Rising SD_DATA Hold SD_CLK Rising THD_SD_IN TDLY_SD_OUT Time from SD_CLK Falling to Valid SD_DATA Delay Table 7.3-11 SD Interface Default Mode Characteristics TP_SD_CLK TL_SD_CLK TH_SD_CLK SDx_CLK NUC980 SERIES DATASHEET SDx_CMD SDx_DATA[3:0] (Input Mode) TSU_SD_IN THD_SD_IN SDx_CMD SDx_DATA[3:0] (Output Mode) TDLY_SD_OUT Figure 7.3-15 SD Interface Default Mode Timing Diagram Oct., 02, 2019 Page 227 of 246 Rev 1.11 NUC980 7.3.13.2 High-Speed Mode Timing Symbol Parameter Min Typ Max Unit Test Condition TP_SD_CLK SD_CLK Period 20 - - ns - TH_SD_CLK SD_CLK High Time 7 - - ns - TL_SD_CLK SD_CLK Low Time 7 - - ns - 6 - - ns - 2 - - ns - - - 14 ns - 2.5 - - ns - SD_DATA Setup Time to TSU_SD_IN SD_CLK Rising SD_DATA Hold Time from SD_CLK Rising THD_SD_IN TDLY_SD_OUT THD_SD_OUT SD_CLK Falling to Valid SD_DATA Delay SD_DATA Hold Time from SD_CLK Rising Table 7.3-12 SD Interface High-Speed Mode Characteristics TP_SD_CLK TL_SD_CLK TH_SD_CLK SDx_CLK SDx_CMD SDx_DATA[3:0] (Input Mode) NUC980 SERIES DATASHEET TSU_SD_IN THD_SD_IN SDx_CMD SDx_DATA[3:0] (Output Mode) TDLY_SD_OUT THD_SD_OUT Figure 7.3-16 SD Interface High-Speed Mode Timing Diagram Oct., 02, 2019 Page 228 of 246 Rev 1.11 NUC980 7.3.14 Capture Sensor Interface Timing Symbol Parameter Min Typ Max Unit Test Condition 20 - - ns - TP_VCAP_PCLK VCAP_PCLK Period TH_VCAP_PCLK VCAP_PCLK High Time - 10.0 - ns - TL_VCAP_PCLK VCAP_PCLK Low Time - 10.0 - ns - TSU_VCAP_IN VCAP_HSYNC, VCAP_VSYNC, VCAP_FIELD and VCAP_DATA Setup Time to VCAP_PCLK Rising 4 - - ns - THD_VCAP_IN VCAP_HSYNC, VCAP_VSYNC, VCAP_FIELD and VCAP_DATA Hold Time from VCAP_PCLK Rising 1 - - ns - Table 7.3-13 Capture Sensor Interface Characteristics TP_VCAP_PCLK TL_VCAP_PCLK TH_VCAP_PCLK VCAP_PCLK VCAP_HSYNC VCAP_VSYNC VCAP_FIELD VCAP_DATA TSU_VCAP_IN THD_VCAP_IN NUC980 SERIES DATASHEET Figure 7.3-17 Capture Sensor Interface Timing Diagram Oct., 02, 2019 Page 229 of 246 Rev 1.11 NUC980 7.4 Analog Characteristics 7.4.1 12-bit SARADC Symbol Min. Typ. Max. Unit Resolution - 12 - Bit DNL Differential Nonlinearity Error - ±1 - LSB VREF is external AVref pin INL Integral Nonlinearity Error - -1.2 - LSB VREF is external AVref pin EO Offset Error - +3.7 - LSB VREF is external AVref pin EG Gain Error (Transfer Gain) - -6.6 - LSB VREF is external AVref pin EA Absolute Error - 4.2 - LSB VREF is external AVref pin - - Parameter Monotonic Guaranteed FADC ADC Clock Frequency - - TADC Conversion Time - 20 FS AVDD33 Sample Rate Supply Voltage Test Conditions 16 MHz Clock - 200k SPS 2.97 3.3 3.63 V IDDA1 Supply Current (Avg.) - 1.2 mA ADC channel 1 high speed mode IDDA2 Supply Current (Avg.) - 1.0 mA ADC channel 1 low speed mode IDDA3 Supply Current (Avg.) - 0.4 mA Leakage Current - 0.1 - uA Reference Voltage 2 - AVDD33 V VIN Analog Input Voltage 0 - AVref V RIN Analog Input Impedance - - 2 MΩ CIN Capacitance - 25.6 pF 2.5 V ILK AVREF NUC980 SERIES DATASHEET VBG Band-gap 2.5V voltage output Oct., 02, 2019 Page 230 of 246 VBG no trim for VREF output, the accuracy is 6% typically at 100ppm/℃ Rev 1.11 NUC980 7.4.2 Low Voltage Detection (LVD) and Low Voltage Reset (LVR) Symbol Parameter AVDD33 Operation Voltage ILVDR Operating Current ILK Quiescent Current TA Temperature VTH_LVD Min. Typ. Max Unit 2.0 3.3 3.63 V - uA - 21 Test Conditions LVR_EN (SYS_LVRDCR[0]) = 0, - 0.1 0.5 uA -40 - 85 C - 2.295 2.55 2.805 V LVD_SEL (SYS_LVRDCR[9]) = 0 2.475 2.75 3.025 V LVD_SEL (SYS_LVRDCR[9]) = 1 2.115 2.35 2.585 V - 0.045 0.05 0.055 V LVD_SEL (SYS_LVRDCR[9]) = 0 0.045 0.05 0.055 V LVD_SEL (SYS_LVRDCR[9]) = 1 0.045 0.05 0.055 V - LVD_EN (SYS_LVRDCR[8]) = 0 LVD Threshold Voltage VTH_LVR LVR Threshold Voltage VHY_LVD LVD Hysteresis VHY_LVR LVR Hysteresis Note: Guaranteed by characterization results, not tested in production. 7.4.3 3.3V Power-On Reset (POR33) Symbol TA Parameter Temperature Min Typ Max Unit Test Condition -40 25 85 C - VPOR33 Reset Voltage - 1.83 - V AVDD33 rising from 0V to 3.3V IPOR33 Quiescent current - 5 - nA Vin > reset voltage 7.4.4 1.2V Power-On Reset (POR12) Symbol TA Parameter Temperature Min Typ Max Unit Test Condition -40 25 85 C - VPOR12 Reset Voltage - 0.76 - V VDD12 rising from 0V to 1.2V IPOR12 Quiescent current - 10 - nA Vin > reset voltage Note: Guaranteed by characterization results, not tested in production. Oct., 02, 2019 Page 231 of 246 Rev 1.11 NUC980 SERIES DATASHEET Note: Guaranteed by characterization results, not tested in production. NUC980 7.4.5 USB 2.0 PHY 7.4.5.1 Low/Full-Speed DC Electrical Specifications Symbol Parameter Min Typ Max Unit Test Condition VOL Output Low (Driven) - - 0.3 V 1.5K RPU on DP to 3.6v VOH Output High (Driven) 2.8 - - V 15K RPD on DP, DM to GND VDI Differential Input Sensitivity 0.2 - - V |VUSB0_DP–VUSB0_DM| VCM Differential Common-Mode Range 0.8 - 2.5 V VIL Single-Ended Input Low - - 0.8 V - VIH Single-Ended Input High 2.0 - - V - RPU Pull-Up Resistor 1.35 1.5 1.65 kΩ RPD_DP D+ Pull-Down Resistor 13.5 15 16.5 kΩ RPD_DM D- Pull-Down Resistor 13.5 15 16.5 kΩ - 44 Ω Steady state drive[1] ZDRV Driver Output Resistance 28 CIN Transceiver Low-Speed Donwstream Port Capacitance 200 600 pF Pin to GND CIN Transceiver Low-Speed Upstream Port Capacitance 50 150 pF Pin to GND CIN Transceiver Full-Speed Capacitance 50 pF Note: NUC980 SERIES DATASHEET 1. Driver output resistance doesn’t include series resistor resistance. 2. Guaranteed by characterization results, not tested in production. 7.4.5.2 High-Speed DC Electrical Specifications Symbol Parameter Min Typ Max Unit Test Condition VHSDI High Speed Differential Input Signal Level 150 - - mV |VUSB0_DP–VUSB0_DM| VHSQ High Speed Squelch Detection Threshold 100 125 150 mV |VUSB0_DP–VUSB0_DM| VHSCM High Speed Common Mode Voltage Range -50 - 500 mV VHSOH High Speed Data Signaling High 300 400 440 mV VHSOL High Speed Data Signaling Low -10 0 10 mV VCHIRPJ Chirp J Level 700 - 1100 mV VCHIRPK Chirp K Level -900 - -500 mV RHSDRV High Speed Driver Output Resistance 40.5 45 49.5 Ω Note: Guaranteed by characterization results, not tested in production. Oct., 02, 2019 Page 232 of 246 Rev 1.11 NUC980 7.4.5.3 USB Low-Speed Driver AC Electrical Characteristics Symbol Parameter Min Typ Max Unit Test Condition TLRISE Rise Time 75 - 300 ns CL=200pF, 10% to 90% of |VOH-VOL| TLFALL Fall Time 75 - 300 ns CL=200pF, 10% to 90% of |VOH-VOL| VLCR Crossover Voltage 1.3 - 2.0 V Excluding the first transition from idle state Test Condition Note: Guaranteed by characterization results, not tested in production. 7.4.5.4 USB Full-Speed Driver AC Electrical Characteristics Symbol Parameter Min Typ Max Unit VFRISE Rise Time 4 - 20 ns CL=50pF, 10% to 90% of |VOH-VOL| VFFALL Fall Time 4 - 20 ns CL=50pF, 10% to 90% of |VOH-VOL| VFCR Crossover Voltage 1.3 - 2.0 V Excluding the first transition from idle state Note: Guaranteed by characterization results, not tested in production. 7.4.5.5 USB High-Speed Driver AC Electrical Characteristics Symbol Parameter Min Typ Max Unit Test Condition VHRISE High Speed Driver Rise Time 500 - 900 ps CL