GigaDevice Semiconductor Inc.
GD32VF103
RISC-V 32-bit MCU
Datasheet
GD32VF103 Datasheet
Table of Contents
Table of Contents ........................................................................................................... 1
List of Figures ................................................................................................................ 4
List of Tables .................................................................................................................. 5
1. General description ................................................................................................. 7
2. Device overview ....................................................................................................... 8
2.1.
Device information ...................................................................................................... 8
2.2.
Block diagram ............................................................................................................ 10
2.3.
Pinouts and pin assignment ..................................................................................... 11
2.4.
Memory map .............................................................................................................. 14
2.5.
Clock tree ................................................................................................................... 18
2.6.
Pin definitions ............................................................................................................ 19
2.6.1.
GD32VF103Vx LQFP100 pin definitions .............................................................................. 19
2.6.2.
GD32VF103Rx LQFP64 pin definitions ................................................................................ 26
2.6.3.
GD32VF103Cx LQFP48 pin definitions ................................................................................ 30
2.6.4.
GD32VF103Tx QFN36 pin definitions .................................................................................. 34
3. Functional description .......................................................................................... 37
3.1.
System and memory architecture ............................................................................ 37
3.2.
On-chip memory ........................................................................................................ 37
3.3.
Clock, reset and supply management ...................................................................... 37
3.4.
Boot modes ................................................................................................................ 38
3.5.
Power saving modes ................................................................................................. 39
3.6.
Analog to digital converter (ADC) ............................................................................ 39
3.7.
Digital to analog converter (DAC) ............................................................................. 40
3.8.
DMA ............................................................................................................................ 40
3.9.
General-purpose inputs/outputs (GPIOs) ................................................................ 40
3.10.
Timers and PWM generation ................................................................................. 41
3.11.
Real time clock (RTC) ............................................................................................ 42
3.12.
Inter-integrated circuit (I2C) .................................................................................. 42
3.13.
Serial peripheral interface (SPI) ............................................................................ 44
3.14.
Universal synchronous asynchronous receiver transmitter (USART) ............... 44
1
GD32VF103 Datasheet
3.15.
Inter-IC sound (I2S) ................................................................................................ 44
3.16.
Universal serial bus full-speed (USBFS) .............................................................. 45
3.17.
Controller area network (CAN) .............................................................................. 45
3.18.
External memory controller (EXMC) ..................................................................... 45
3.19.
Debug mode ........................................................................................................... 45
3.20.
Package and operation temperature ..................................................................... 46
4. Electrical characteristics ....................................................................................... 47
4.1.
Absolute maximum ratings ....................................................................................... 47
4.2.
Operating conditions characteristics ....................................................................... 47
4.3.
Power consumption .................................................................................................. 49
4.4.
EMC characteristics .................................................................................................. 53
4.5.
Power supply supervisor characteristics ................................................................ 54
4.6.
Electrical sensitivity .................................................................................................. 55
4.7.
External clock characteristics .................................................................................. 55
4.8.
Internal clock characteristics ................................................................................... 57
4.9.
PLL characteristics.................................................................................................... 58
4.10.
Memory characteristics ......................................................................................... 59
4.11.
NRST pin characteristics ....................................................................................... 59
4.12.
GPIO characteristics .............................................................................................. 60
4.13.
ADC characteristics ............................................................................................... 62
4.14.
Temperature sensor characteristics ..................................................................... 63
4.15.
DAC characteristics ............................................................................................... 63
4.16.
I2C characteristics ................................................................................................. 64
4.17.
SPI characteristics ................................................................................................. 65
4.18.
I2S characteristics.................................................................................................. 67
4.19.
USART characteristics ........................................................................................... 69
4.20.
CAN characteristics ............................................................................................... 69
4.21.
USBFS characteristics ........................................................................................... 70
4.22.
EXMC characteristics............................................................................................. 70
4.23.
TIMER characteristics ............................................................................................ 71
4.24.
WDGT characteristics ............................................................................................ 72
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GD32VF103 Datasheet
4.25.
Parameter conditions............................................................................................. 72
5. Package information.............................................................................................. 73
5.1.
LQFP100 package outline dimensions..................................................................... 73
5.2.
LQFP64 package outline dimensions....................................................................... 75
5.3.
LQFP48 package outline dimensions....................................................................... 77
5.4.
QFN36 package outline dimensions ........................................................................ 79
5.5.
Thermal characteristics ............................................................................................ 81
6. Ordering information ............................................................................................. 83
7. Revision History..................................................................................................... 84
3
GD32VF103 Datasheet
List of Figures
Figure 2-1. GD32VF103 block diagram ............................................................................................ 10
Figure 2-2. GD32VF103Vx LQFP100 pinouts.................................................................................... 11
Figure 2-3. GD32VF103Rx LQFP64 pinouts .................................................................................... 12
Figure 2-4. GD32VF103Cx LQFP48 pinouts .................................................................................... 13
Figure 2-5. GD32VF103Tx QFN36 pinouts ....................................................................................... 13
Figure 2-6. GD32VF103 clock tree .................................................................................................... 18
Figure 4-1. Recommended power supply decoupling capacitors (1)(2) .......................................... 48
Figure 4-2. Typical supply current consumption in Run mode ..................................................... 53
Figure 4-3. Typical supply current consumption in Sleep mode .................................................. 53
Figure 4-4. Recommended external NRST pin circuit(1) ................................................................. 60
Figure 4-5. I/O port AC characteristics definition ........................................................................... 61
Figure 4-6. I2C bus timing diagram .................................................................................................. 65
Figure 4-7. SPI timing diagram - master mode ............................................................................... 66
Figure 4-8. SPI timing diagram - slave mode .................................................................................. 67
Figure 4-9. I2S timing diagram - master mode ................................................................................ 68
Figure 4-10. I2S timing diagram - slave mode ................................................................................. 69
Figure 4-11. USBFS timings: definition of data signal rise and fall time ..................................... 70
Figure 5-1. LQFP100 package outline .............................................................................................. 73
Figure 5-2. LQFP100 recommended footprint ................................................................................. 74
Figure 5-3. LQFP64 package outline ................................................................................................ 75
Figure 5-4. LQFP64 recommended footprint ................................................................................... 76
Figure 5-5. LQFP48 package outline ................................................................................................ 77
Figure 5-6. LQFP48 recommended footprint ................................................................................... 78
Figure 5-7. QFN36 package outline .................................................................................................. 79
Figure 5-8. QFN36 recommended footprint ..................................................................................... 80
4
GD32VF103 Datasheet
List of Tables
Table 2-1. GD32VF103 devices features and peripheral list (LQFP64, LQFP100) ......................... 8
Table 2-2. GD32VF103 devices features and peripheral list (QFN36, LQFP48) ............................. 9
Table 2-3. GD32VF103 memory map ................................................................................................ 14
Table 2-4. GD32VF103Vx LQFP100 pin definitions......................................................................... 19
Table 2-5. GD32VF103Rx LQFP64 pin definitions .......................................................................... 26
Table 2-6. GD32VF103Cx LQFP48 pin definitions .......................................................................... 30
Table 2-7. GD32VF103Tx QFN36 pin definitions ............................................................................. 34
Table 4-1. Absolute maximum ratings(1)(4) ....................................................................................... 47
Table 4-2. DC operating conditions.................................................................................................. 47
Table 4-3. Clock frequency(1) ............................................................................................................ 48
Table 4-4. Operating conditions at Power up/ Power down(1) ....................................................... 48
Table 4-5. Start-up timings of Operating conditions (1)(2)(3) ............................................................. 48
Table 4-6. Power saving mode wakeup timings characteristics(1)(2) ............................................. 48
Table 4-7. Power consumption characteristics(2)(3)(4)(5) ................................................................... 49
Table 4-8. EMS characteristics(1) ...................................................................................................... 54
Table 4-9. Power supply supervisor characteristics ...................................................................... 54
Table 4-10. ESD characteristics(1) ..................................................................................................... 55
Table 4-11. Static latch-up characteristics(1) ................................................................................... 55
Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic.................... 55
Table 4-13. High speed external clock characteristics (HXTAL in bypass mode) ...................... 56
Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics .................................................................................................................................... 56
Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode) ............... 57
Table 4-16. High speed internal clock (IRC8M) characteristics .................................................... 57
Table 4-17. Low speed internal clock (IRC40K) characteristics.................................................... 58
Table 4-18. PLL characteristics ........................................................................................................ 58
Table 4-19. PLL1/2 characteristics ................................................................................................... 58
Table 4-20. Flash memory characteristics ...................................................................................... 59
Table 4-21. NRST pin characteristics ............................................................................................... 59
Table 4-22. I/O port DC characteristics(1)(3) ...................................................................................... 60
Table 4-23. I/O port AC characteristics(1)(2) ...................................................................................... 61
Table 4-24. ADC characteristics ....................................................................................................... 62
Table 4-25. ADC RAIN max for fADC = 14 MHz(1).................................................................................. 62
Table 4-26. Temperature sensor characteristics(1) ......................................................................... 63
Table 4-27. DAC characteristics ....................................................................................................... 63
Table 4-28. I2C characteristics(1)(2) .................................................................................................... 64
Table 4-29. Standard SPI characteristics(1)...................................................................................... 65
Table 4-30. I2S characteristics(1)(2) .................................................................................................... 67
Table 4-31. USART0 characteristics(1).............................................................................................. 69
Table 4-32. USART1-2/UART3-4 characteristics(1) .......................................................................... 69
5
GD32VF103 Datasheet
Table 4-33. USBFS start up time....................................................................................................... 70
Table 4-34. USBFS DC electrical characteristics ............................................................................ 70
Table 4-35. USBFS electrical characteristics(1) ............................................................................... 70
Table 4-36. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)(3) ..................................... 70
Table 4-37. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)(3) .................................... 71
Table 4-38. TIMER characteristics(1) ................................................................................................. 71
Table 4-39. FWDGT min/max timeout period at 40 kHz (IRC40K)(1)............................................... 72
Table 4-40. WWDGT min/max timeout value at 54 MHz (fPCLK1)(1) .................................................. 72
Table 5-1. LQFP100 package dimensions ....................................................................................... 73
Table 5-2. LQFP64 package dimensions ......................................................................................... 75
Table 5-3. LQFP48 package dimensions ......................................................................................... 77
Table 5-4. QFN36 package dimensions ........................................................................................... 79
Table 5-5. Package thermal characteristics(1) ................................................................................. 81
Table 6-1. Part ordering code for GD32VF103xx devices .............................................................. 83
Table 7-1. Revision history ............................................................................................................... 84
6
GD32VF103 Datasheet
1.
General description
The GD32VF103 device is a 32-bit general-purpose microcontroller based on the RISC-V
core with best ratio in terms of processing power, reduced power consumption and peripheral
set. The RISC-V processor core is tightly coupled with an Enhancement Core-Local Interrupt
Controller (ECLIC), SysTick timer and advanced debug support.
The GD32VF103 device incorporates the RISC-V 32-bit processor core operating at 108 MHz
frequency with Flash accesses zero wait states to obtain maximum efficiency. It provides up
to 128 KB on-chip Flash memory and 32 KB SRAM memory. An extensive range of enhanced
I/Os and peripherals connect to two APB buses. The devices offer up to two 12-bit ADCs, up
to two 12-bit DACs, up to four general 16-bit timers, two basic timers plus a PWM advanced
timer, as well as standard and advanced communication interfaces: up to three SPIs, two
I2Cs, three USARTs, two UARTs, two I2Ss, two CANs, an USBFS.
The device operates from a 2.6 to 3.6 V power supply and available in –40 to +85 °C
temperature range. Several power saving modes provide the flexibility for maximum
optimization between wakeup latency and power consumption, an especially important
consideration in low power applications.
The above features make the GD32VF103 devices suitable for a wide range of
interconnection applications, especially in areas such as industrial control, motor drives,
power monitor and alarm systems, consumer and handheld equipment, POS, vehicle GPS,
LED display and so on.
7
GD32VF103 Datasheet
2.
Device overview
2.1.
Device information
Table 2-1. GD32VF103 devices features and peripheral list (LQFP64, LQFP100)
GD32VF103
Flash
Part Number
RB
R8
R6
R4
VB
V8
Code area (KB)
128
64
32
16
128
64
Data area (KB)
0
0
0
0
0
0
Total (KB)
128
64
32
16
128
64
32
20
10
6
32
20
ADC
Connectivity
Timers
SRAM (KB)
General
4
4
2
2
4
4
timer(16-bit)
(1-4)
(1-4)
(1-2)
(1-2)
(1-4)
(1-4)
Advanced
1
1
1
1
1
1
timer(16-bit)
(0)
(0)
(0)
(0)
(0)
(0)
SysTick
1
1
1
1
1
1
Basic timer(16-
2
2
2
2
2
2
bit)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
Watchdog
2
2
2
2
2
2
RTC
1
1
1
1
1
1
U(S)ART
5
5
2
2
5
5
2
2
1
1
2
2
(0-1)
(0-1)
(0-1)
(0-1)
3/2
3/2
3/2
3/2
(0-2) / (1-2)
(0-2) / (1-2)
(0-2) / (1-2)
(0-2) / (1-2)
CAN
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
GPIO
51
51
51
51
80
80
EXMC
-
-
-
-
1
1
EXTI
16
16
16
16
16
16
Units
2
2
2
2
2
2
Channels
16
16
16
16
16
16
DAC
2
2
2
2
2
2
I2C
SPI/I2S
Package
1/-
LQFP64
1/-
LQFP100
8
GD32VF103 Datasheet
Table 2-2. GD32VF103 devices features and peripheral list (QFN36, LQFP48)
GD32VF103
Part Number
Code area
Flash
(KB)
Data area
(KB)
Total (KB)
ADC
Connectivity
Timers
SRAM (KB)
TB
T8
T6
T4
CB
C8
C6
C4
128
64
32
16
128
64
32
16
0
0
0
0
0
0
0
0
128
64
32
16
128
64
32
16
32
20
10
6
32
20
10
6
General
4
4
2
2
4
4
2
2
timer(16-bit)
(1-4)
(1-4)
(1-2)
(1-2)
(1-4)
(1-4)
(1-2)
(1-2)
Advanced
1
1
1
1
1
1
1
1
timer(16-bit)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
SysTick
1
1
1
1
1
1
1
1
Basic
2
2
2
2
2
2
2
2
timer(16-bit)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
(5-6)
Watchdog
2
2
2
2
2
2
2
2
RTC
1
1
1
1
1
1
1
1
U(S)ART
2
2
2
2
3
3
2
2
I2C
1
1
1
1
2
2
1
1
(0-1)
(0-1)
3/2
3/2
1/-
1/-
(0-2) / (1-2)
(0-2) / (1-2)
SPI/I2S
1/-
1/-
1/-
1/-
CAN
2
2
2
2
2
2
2
2
USBFS
1
1
1
1
1
1
1
1
GPIO
26
26
26
26
37
37
37
37
EXMC
-
-
-
-
-
-
-
-
EXTI
16
16
16
16
16
16
16
16
Units
2
2
2
2
2
2
2
2
Channels
10
10
10
10
10
10
10
10
DAC
2
2
2
2
2
2
2
2
Package
QFN36
LQFP48
9
GD32VF103 Datasheet
2.2.
Block diagram
Figure 2-1. GD32VF103 block diagram
JTAG
ECLIC
ICode DCode System
RISC_V
CPU
Fmax:108MHz
POR/ PDR
Flash
Memory
Controller
Ibus
Flash
Memory
PLL
F max : 108MHz
Dbus
FMC
Master
Master
GP DMA1
Slave
Master
Slave
EXMC
CRC
LDO
1.2V
RCU
AHB Peripherals
Slave
AHB Matrix
GP DMA0
USB
FS
SRAM
Controller
AHB to APB
Bridge2
IRC
8MHz
SRAM
HXTAL
3-25MHz
AHB to APB
Bridge1
Slave
LVD
Interrput request
CAN0
USART0
Slave
12-bit
SAR ADC
Slave
SPI0
WWDGT
ADC0~1
TIMER1~3
EXTI
SPI1~2
GPIOA
USART1~2
GPIOB
I2C0
Powered By V DDA
GPIOE
APB1: Fmax = 54MHZ
GPIOD
APB2: Fmax = 108MHz
GPIOC
Powered By VDDA
I2C1
FWDGT
RTC
DAC
TIMER0
TIMER4~6
UART3~4
CAN1
10
GD32VF103 Datasheet
2.3.
Pinouts and pin assignment
Figure 2-2. GD32VF103Vx LQFP100 pinouts
PA14
PA15
PC10
PC11
PC12
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB4
PB3
PB5
PB6
PB7
BOOT0
PB8
PB9
PE0
PE1
VSS_3
VDD_3
PE2
1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PE3
PE4
2
74
VSS_2
3
73
NC
PE5
PE6
4
72
PA13
5
71
PA12
VBAT
6
PC13-TAMPER-RTC
PC14-OSC32IN
7
70
69
PA10
8
68
PA9
PC15-OSC32OUT
9
67
PA8
VSS_5
10
66
PC9
VDD_5
11
65
PC8
64
PC7
63
PC6
14
62
PD15
OSCIN
12
GigaDevice GD32VF103Vx
LQFP100
VDD_2
PA11
OSCOUT
NRST
PC0
13
15
61
PD14
PC1
16
60
PD13
PC2
PC3
17
59
PD12
18
58
PD11
VSSA
19
57
PD10
VREFVREF+
20
56
PD9
21
55
PD8
VDDA
22
54
PB15
PA0-WKUP
23
53
PB14
PA1
24
52
PB13
PA2
25
51
PB12
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VSS_1
VDD_1
PB11
PB10
PE15
PE14
PE13
PE11
PE12
PE10
PE9
PE8
PE7
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
11
GD32VF103 Datasheet
Figure 2-3. GD32VF103Rx LQFP64 pinouts
PA14
PA15
PC10
PC11
PC12
PD2
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VBAT
1
48
VDD_2
PC13-TAMPER-RTC
2
47
VSS_2
PC14-OSC32IN
3
46
PA13
PC15-OSC32OUT
PD0-OSCIN
4
45
PA12
5
44
PA11
PD1 OSCOUT
6
43
PA10
42
PA9
NRST
PC0
7
PC1
9
PC2
PC3
VSSA
GigaDevice GD32VF103Rx
LQFP64
41
PA8
40
PC9
10
39
PC8
11
38
PC7
12
37
PC6
VDDA
13
36
PB15
PA0-WKUP
14
35
PB14
PA1
15
34
PB13
PA2
16
33
PB12
8
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VSS_1
VDD_1
PB11
PB10
PB2
PB1
PC5
PB0
PA7
PC4
PA6
PA5
PA4
VDD_4
PA3
VSS_4
12
GD32VF103 Datasheet
Figure 2-4. GD32VF103Cx LQFP48 pinouts
PA14
PA15
PB3
PB4
PB5
PB6
PB7
BOOT0
PB8
PB9
VSS_3
VDD_3
48 47 46 45 44 43 42 41 40 39 38 37
VBAT
1
36
VDD_2
PC13-TAMPER-RTC
2
35
VSS_2
PC14-OSC32IN
3
34
PA13
PC15-OSC32OUT
PD0-OSCIN
4
33
PA12
5
32
PA11
PD1-OSCOUT
NRST
VSSA
6
31
PA10
30
PA9
8
29
VDDA
9
28
PA8
PB15
PA0-WKUP
10
27
PB14
PA1
PA2
11
26
PB13
12
25
PB12
GigaDevice GD32VF103Cx
LQFP48
7
13 14 15 16 17 18 19 20 21 22 23 24
VSS_1
PA15
PA14
VDD_1
PB11
PB10
PB2
PB1
PA7
PB0
PA6
PA5
PA4
PA3
Figure 2-5. GD32VF103Tx QFN36 pinouts
PA1
PA2
PB3
PB4
PA0-WKUP
PB5
VDDA
PB6
OSCIN/PD0
OSCOUT/PD1
NRST
VSSA
PB7
BOOT0
VSS_3
VDD_3
36 35 34 33 32 31 30 29 28
1
27
2
26
VDD_2
3
25
PA13
24
5 GigaDevice GD32VF103Tx 23
QFN36
6
22
7
21
PA12
PA9
8
PA8
4
20
9
19
10 11 12 13 14 15 16 17 18
VSS_2
PA11
PA10
VDD_1
VSS_1
PB2
PB0
PB1
PA7
PA6
PA5
PA4
PA3
13
GD32VF103 Datasheet
2.4.
Memory map
Table 2-3. GD32VF103 memory map
Pre-defined
Regions
Bus
External
device
AHB
Address
Peripherals
0xA000 0000 - 0xA000 0FFF
EXMC_SWREG
0x9000 0000 - 0x9FFF FFFF
Reserved
0x7000 0000 - 0x8FFF FFFF
Reserved
External RAM
EXMC 0x6000 0000 - 0x6FFF FFFF
NOR/PSRAM/SRA
M
Peripheral
AHB
0x5000 0000 - 0x5003 FFFF
USBFS
0x4008 0000 - 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
Reserved
0x4002 BC00 - 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Reserved
0x4002 A000 - 0x4002 AFFF
Reserved
0x4002 8000 - 0x4002 9FFF
Reserved
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
Reserved
0x4002 6000 - 0x4002 63FF
Reserved
0x4002 5000 - 0x4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
Reserved
0x4002 3C00 - 0x4002 3FFF
Reserved
0x4002 3800 - 0x4002 3BFF
Reserved
0x4002 3400 - 0x4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
Reserved
0x4002 2400 - 0x4002 27FF
Reserved
0x4002 2000 - 0x4002 23FF
FMC
0x4002 1C00 - 0x4002 1FFF
Reserved
0x4002 1800 - 0x4002 1BFF
Reserved
0x4002 1400 - 0x4002 17FF
Reserved
0x4002 1000 - 0x4002 13FF
RCU
0x4002 0C00 - 0x4002 0FFF
Reserved
0x4002 0800 - 0x4002 0BFF
Reserved
0x4002 0400 - 0x4002 07FF
DMA1
0x4002 0000 - 0x4002 03FF
DMA0
0x4001 8400 - 0x4001 FFFF
Reserved
14
GD32VF103 Datasheet
Pre-defined
Regions
Bus
APB2
APB1
Address
Peripherals
0x4001 8000 - 0x4001 83FF
Reserved
0x4001 7C00 - 0x4001 7FFF
Reserved
0x4001 7800 - 0x4001 7BFF
Reserved
0x4001 7400 - 0x4001 77FF
Reserved
0x4001 7000 - 0x4001 73FF
Reserved
0x4001 6C00 - 0x4001 6FFF
Reserved
0x4001 6800 - 0x4001 6BFF
Reserved
0x4001 5C00 - 0x4001 67FF
Reserved
0x4001 5800 - 0x4001 5BFF
Reserved
0x4001 5400 - 0x4001 57FF
Reserved
0x4001 5000 - 0x4001 53FF
Reserved
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
Reserved
0x4001 4400 - 0x4001 47FF
Reserved
0x4001 4000 - 0x4001 43FF
Reserved
0x4001 3C00 - 0x4001 3FFF
Reserved
0x4001 3800 - 0x4001 3BFF
USART0
0x4001 3400 - 0x4001 37FF
Reserved
0x4001 3000 - 0x4001 33FF
SPI0
0x4001 2C00 - 0x4001 2FFF
TIMER0
0x4001 2800 - 0x4001 2BFF
ADC1
0x4001 2400 - 0x4001 27FF
ADC0
0x4001 2000 - 0x4001 23FF
Reserved
0x4001 1C00 - 0x4001 1FFF
Reserved
0x4001 1800 - 0x4001 1BFF
GPIOE
0x4001 1400 - 0x4001 17FF
GPIOD
0x4001 1000 - 0x4001 13FF
GPIOC
0x4001 0C00 - 0x4001 0FFF
GPIOB
0x4001 0800 - 0x4001 0BFF
GPIOA
0x4001 0400 - 0x4001 07FF
EXTI
0x4001 0000 - 0x4001 03FF
AFIO
0x4000 CC00 - 0x4000 FFFF
Reserved
0x4000 C800 - 0x4000 CBFF
Reserved
0x4000 C400 - 0x4000 C7FF
Reserved
0x4000 C000 - 0x4000 C3FF
Reserved
0x4000 8000 - 0x4000 BFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
Reserved
0x4000 7800 - 0x4000 7BFF
Reserved
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PMU
15
GD32VF103 Datasheet
Pre-defined
Regions
Bus
Address
Peripherals
0x4000 6C00 - 0x4000 6FFF
BKP
0x4000 6800 - 0x4000 6BFF
CAN1
0x4000 6400 - 0x4000 67FF
CAN0
0x4000 6000 - 0x4000 63FF
0x4000 5C00 - 0x4000 5FFF
SRAM
Code
AHB
AHB
Shared USB/CAN
SRAM 512bytes
USB device FS
registers
0x4000 5800 - 0x4000 5BFF
I2C1
0x4000 5400 - 0x4000 57FF
I2C0
0x4000 5000 - 0x4000 53FF
UART4
0x4000 4C00 - 0x4000 4FFF
UART3
0x4000 4800 - 0x4000 4BFF
USART2
0x4000 4400 - 0x4000 47FF
USART1
0x4000 4000 - 0x4000 43FF
Reserved
0x4000 3C00 - 0x4000 3FFF
SPI2/I2S2
0x4000 3800 - 0x4000 3BFF
SPI1/I2S1
0x4000 3400 - 0x4000 37FF
Reserved
0x4000 3000 - 0x4000 33FF
FWDGT
0x4000 2C00 - 0x4000 2FFF
WWDGT
0x4000 2800 - 0x4000 2BFF
RTC
0x4000 2400 - 0x4000 27FF
Reserved
0x4000 2000 - 0x4000 23FF
Reserved
0x4000 1C00 - 0x4000 1FFF
Reserved
0x4000 1800 - 0x4000 1BFF
Reserved
0x4000 1400 - 0x4000 17FF
TIMER6
0x4000 1000 - 0x4000 13FF
TIMER5
0x4000 0C00 - 0x4000 0FFF
TIMER4
0x4000 0800 - 0x4000 0BFF
TIMER3
0x4000 0400 - 0x4000 07FF
TIMER2
0x4000 0000 - 0x4000 03FF
TIMER1
0x2007 0000 - 0x3FFF FFFF
Reserved
0x2006 0000 - 0x2006 FFFF
Reserved
0x2003 0000 - 0x2005 FFFF
Reserved
0x2002 0000 - 0x2002 FFFF
Reserved
0x2001 C000 - 0x2001 FFFF
Reserved
0x2001 8000 - 0x2001 BFFF
Reserved
0x2000 0000 - 0x2001 7FFF
SRAM
0x1FFF F810 - 0x1FFF FFFF
Reserved
0x1FFF F800 - 0x1FFF F80F
Option Bytes
0x1FFF B000 - 0x1FFF F7FF
Boot loader
16
GD32VF103 Datasheet
Pre-defined
Regions
Bus
Address
Peripherals
0x1FFF 7A10 - 0x1FFF AFFF
Reserved
0x1FFF 7800 - 0x1FFF 7A0F
Reserved
0x1FFF 0000 - 0x1FFF 77FF
Reserved
0x1FFE C010 - 0x1FFE FFFF
Reserved
0x1FFE C000 - 0x1FFE C00F
Reserved
0x1001 0000 - 0x1FFE BFFF
Reserved
0x1000 0000 - 0x1000 FFFF
Reserved
0x083C 0000 - 0x0FFF FFFF
Reserved
0x0830 0000 - 0x083B FFFF
Reserved
0x0802 0000 - 0x082F FFFF
Reserved
0x0800 0000 - 0x0801 FFFF
Main Flash
0x0030 0000 - 0x07FF FFFF
Reserved
0x0000 0000 - 0x002F FFFF
Aliased to Main
Flash or Boot loader
17
GD32VF103 Datasheet
2.5.
Clock tree
Figure 2-6. GD32VF103 clock tree
(to FMC)
USB OTG
Prescaler
÷1,1.5,2,2.5
1
SCS[1:0]
CK_FMC
CK_IRC8M
8 MHz
IRC8M
0
1
PLLSEL
PREDV0
0
1
CK_USBFS
(to USBFS)
00
/2
3-25 MHz
HXTAL
48 MHz
×2,3,4
…,32
PLL
CK_PLL
10
AHB
Prescaler
÷1,2...512
CK_SYS
108 MHz max
CK_AHB
108 MHz max
CK_EXMC
EXMC enable
(to EXMC)
HCLK
01
PLLMF
AHB enable
/1,2,3…
15,16
(to AHB bus,RISC-V core,SRAM,DMA)
CK_CST
Clock
Monitor
÷4
(to RISC-V core SysTick)
FCLK
PREDV0SEL
EXT1 to
CK_OUT
(free running clock)
CK_HXTAL
APB1
Prescaler
÷1,2,4,8,16
CK_APB1
PCLK1
to APB1 peripherals
54 MHz max
Peripheral enable
×8..14,16,
20
PLL1
TIMER1,2,3,4,5,6
if(APB1 prescale
=1)x1
else x 2
CK_PLL1
×8..14,16,
20
PLL2
0
CK_PLL2
x2
CK_I2S
1
APB2
Prescaler
÷1,2,4,8,16
CK_RTC
01
(to RTC)
10
RTCSRC[1:0]
40 KHz
IRC40K
CK_OUT0
CK_APB2
PCLK2
to APB2 peripherals
108 MHz max
Peripheral enable
I2S1/2SEL
PLL2MF
11
32.768 KHz
LXTAL
to TIMER1,2,3,4,
5,6
PLL1MF
/1,2,3…
15,16
PREDV1
/128
CK_TIMERx
TIMERx
enable
TIMER0
if(APB2 prescale
=1)x1
else x 2
ADC
Prescaler
÷2,4,6,8,12,1
6
CK_TIMERx
TIMERx
enable
to TIMER0
CK_ADCx to ADC0,1
14 MHz max
CK_FWDGT
(to FWDGT)
00xx
0100
0101
0110
0111
1000
1001
1010
1011
NO CLK
CK_SYS
CK_IRC8M
CK_HXTAL
/2
CK_PLL
CK_PLL1
/2
CK_PLL2
EXT1
CK_PLL2
CKOUT0SEL[3:0]
Legend:
HXTAL: High speed external clock
LXTAL: Low speed external clock
IRC8M: High speed internal clock
IRC40K: Low speed internal clock
18
GD32VF103 Datasheet
2.6.
Pin definitions
2.6.1.
GD32VF103Vx LQFP100 pin definitions
Table 2-4. GD32VF103Vx LQFP100 pin definitions
Pin
I/O
Type(1)
Level(2)
1
I/O
5VT
PE3
2
I/O
5VT
PE4
3
I/O
5VT
PE5
4
I/O
5VT
PE6
5
I/O
5VT
VBAT
6
P
Pin Name
Pins
PE2
PC13TAMPER-
Functions description
Default: PE2
Alternate: EXMC_A23
Default: PE3
Alternate: EXMC_A19
Default: PE4
Alternate: EXMC_A20
Default: PE5
Alternate: EXMC_A21
Default: PE6
Alternate: EXMC_A22
Default: VBAT
Default: PC13
7
I/O
8
I/O
9
I/O
VSS_5
10
P
Default: VSS_5
VDD_5
11
P
Default: VDD_5
OSCIN
12
I
OSCOUT
13
O
NRST
14
I/O
PC0
15
I/O
PC1
16
I/O
PC2
17
I/O
PC3
18
I/O
VSSA
19
P
RTC
PC14OSC32IN
PC15OSC32OUT
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
Default: VSSA
19
GD32VF103 Datasheet
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
Functions description
VREF-
20
P
Default: VREF-
VREF+
21
P
Default: VREF+
VDDA
22
P
Default: VDDA
Default: PA0
PA0-WKUP
23
I/O
Alternate: WKUP, USART1_CTS,
ADC01_IN0, TIMER1_CH0 _ETI,
TIMER4_CH0,
Default: PA1
PA1
24
I/O
Alternate: USART1_RTS, ADC01_IN1,
TIMER1_CH1, TIMER4_CH1,
Default: PA2
PA2
25
I/O
Alternate: USART1_TX, ADC01_IN2,
TIMER1_CH2, TIMER4_CH2
Default: PA3
PA3
26
I/O
Alternate: USART1_RX, ADC01_IN3,
TIMER1_CH3, TIMER4_CH3
VSS_4
27
P
Default: VSS_4
VDD_4
28
P
Default: VDD_4
Default: PA4
PA4
29
I/O
Alternate: SPI0_NSS, USART1_CK,
ADC01_IN4, DAC_OUT0
Remap: SPI2_NSS, I2S2_WS
Default: PA5
PA5
30
I/O
Alternate: SPI0_SCK, ADC01_IN5,
DAC_OUT1
Default: PA6
PA6
31
I/O
Alternate: SPI0_MISO, ADC01_IN6,
TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
32
I/O
Alternate: SPI0_MOSI, ADC01_IN7,
TIMER2_CH1
Remap: TIMER0_CH0_ON
PC4
33
I/O
PC5
34
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
35
I/O
Alternate: ADC01_IN8, TIMER2_CH2
Remap: TIMER0_CH1_ON
20
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PB1
PB1
36
I/O
Alternate: ADC01_IN9, TIMER2_CH3
Remap: TIMER0_CH2_ON
PB2
37
I/O
5VT
Default: PB2, BOOT1
Default: PE7
PE7
38
I/O
5VT
Alternate: EXMC_D4
Remap: TIMER0_ETI
Default: PE8
PE8
39
I/O
5VT
Alternate: EXMC_D5
Remap: TIMER0_CH0_ON
Default: PE9
PE9
40
I/O
5VT
Alternate: EXMC_D6
Remap: TIMER0_CH0
Default: PE10
PE10
41
I/O
5VT
Alternate: EXMC_D7
Remap: TIMER0_CH1_ON
Default: PE11
PE11
42
I/O
5VT
Alternate: EXMC_D8
Remap: TIMER0_CH1
Default: PE12
PE12
43
I/O
5VT
Alternate: EXMC_D9
Remap: TIMER0_CH2_ON
Default: PE13
PE13
44
I/O
5VT
Alternate: EXMC_D10
Remap: TIMER0_CH2
Default: PE14
PE14
45
I/O
5VT
Alternate: EXMC_D11
Remap: TIMER0_CH3
Default: PE15
PE15
46
I/O
5VT
Alternate: EXMC_D12
Remap: TIMER0_BRKIN
Default: PB10
PB10
47
I/O
5VT
Alternate: I2C1_SCL, USART2_TX,
Remap: TIMER1_CH2
Default: PB11
PB11
48
I/O
5VT
Alternate: I2C1_SDA, USART2_RX
Remap: TIMER1_CH3
VSS_1
49
P
Default: VSS_1
VDD_1
50
P
Default: VDD_1
21
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PB12
PB12
51
I/O
5VT
Alternate: SPI1_NSS, I2C1_SMBA,
USART2_CK, TIMER0_BRKIN, I2S1_WS,
CAN1_RX
Default: PB13
PB13
52
I/O
5VT
Alternate: SPI1_SCK, USART2_CTS,
TIMER0_CH0_ON, I2S1_CK, CAN1_TX,
Default: PB14
PB14
53
I/O
5VT
Alternate: SPI1_MISO, USART2_RTS,
TIMER0_CH1_ON
Default: PB15
PB15
54
I/O
5VT
Alternate: SPI1_MOSI, TIMER0_CH2_ON,
I2S1_SD
Default: PD8
PD8
55
I/O
5VT
Alternate: EXMC_D13
Remap: USART2_TX
Default: PD9
PD9
56
I/O
5VT
Alternate: EXMC_D14
Remap: USART2_RX
Default: PD10
PD10
57
I/O
5VT
Alternate: EXMC_D15
Remap: USART2_CK
Default: PD11
PD11
58
I/O
5VT
Alternate: EXMC_A16/EXMC_CLE
Remap: USART2_CTS
Default: PD12
PD12
59
I/O
5VT
Alternate: EXMC_A17/EXMC_ALE
Remap: TIMER3_CH0, USART2_RTS
Default: PD13
PD13
60
I/O
5VT
Alternate: EXMC_A18
Remap: TIMER3_CH1
Default: PD14
PD14
61
I/O
5VT
Alternate: EXMC_D0
Remap: TIMER3_CH2
Default: PD15
PD15
62
I/O
5VT
Alternate: EXMC_D1
Remap: TIMER3_CH3
Default: PC6
PC6
63
I/O
5VT
Alternate: I2S1_MCK
Remap: TIMER2_CH0
22
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PC7
PC7
64
I/O
5VT
Alternate: I2S2_MCK
Remap: TIMER2_CH1
PC8
65
I/O
5VT
PC9
66
I/O
5VT
Default: PC8
Remap: TIMER2_CH2
Default: PC9
Remap: TIMER2_CH3
Default: PA8
PA8
67
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0,
CK_OUT0, USBFS_SOF
Default: PA9
PA9
68
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
Default: PA10
PA10
69
I/O
5VT
Alternate: USART0_RX, TIMER0_CH2,
USBFS_ID
Default: PA11
PA11
70
I/O
5VT
Alternate: USART0_CTS, CAN0_RX,
USBFS_DM, TIMER0_CH3
Default: PA12
PA12
71
I/O
5VT
Alternate: USART0_RTS, USBFS_DP,
CAN0_TX, TIMER0_ETI
I/O
5VT
Default: JTMS
PA13
72
NC
73
VSS_2
74
P
Default: VSS_2
VDD_2
75
P
Default: VDD_2
PA14
76
I/O
Remap: PA13
-
5VT
Default: JTCK
Remap: PA14
Default: JTDI
PA15
77
I/O
5VT
Alternate: SPI2_NSS, I2S2_WS
Remap: TIMER1_CH0_ETI, PA15, SPI0_NSS
Default: PC10
PC10
78
I/O
5VT
Alternate: UART3_TX
Remap: USART2_TX, SPI2_SCK, I2S2_CK
Default: PC11
PC11
79
I/O
5VT
Alternate: UART3_RX
Remap: USART2_RX, SPI2_MISO
PC12
80
I/O
5VT
Default: PC12
Alternate: UART4_TX
23
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Remap: USART2_CK, SPI2_MOSI, I2S2_SD
Default: PD0
PD0
81
I/O
5VT
Alternate: EXMC_D2
Remap: CAN0_RX
Default: PD1
PD1
82
I/O
5VT
Alternate: EXMC_D3
Remap: CAN0_TX
PD2
83
I/O
5VT
PD3
84
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX
Default: PD3
Remap: USART1_CTS
Default: PD4
PD4
85
I/O
5VT
Alternate: EXMC_NOE
Remap: USART1_RTS
Default: PD5
PD5
86
I/O
5VT
Alternate: EXMC_NWE
Remap: USART1_TX
Default: PD6
PD6
87
I/O
5VT
Alternate: EXMC_NWAIT
Remap: USART1_RX
Default: PD7
PD7
88
I/O
5VT
Alternate: EXMC_NE0
Remap: USART1_CK
Default: JTDO
PB3
89
I/O
5VT
Alternate:SPI2_SCK, I2S2_CK
Remap: PB3, TIMER1_CH1, SPI0_SCK
Default: NJTRST
PB4
90
I/O
5VT
Alternate: SPI2_MISO
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
91
Alternate: I2C0_SMBA, SPI2_MOSI, I2S2_SD
I/O
Remap: TIMER2_CH1, SPI0_MOSI,
CAN1_RX
Default: PB6
PB6
92
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0
Remap: USART0_TX, CAN1_TX
Default: PB7
PB7
93
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1,
EXMC_NADV
24
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Remap: USART0_RX
BOOT0
94
I
Default: BOOT0
Default: PB8
PB8
95
I/O
5VT
Alternate: TIMER3_CH2
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
96
I/O
5VT
Alternate: TIMER3_CH3
Remap: I2C0_SDA, CAN0_TX
Default: PE0
PE0
97
I/O
5VT
PE1
98
I/O
5VT
VSS_3
99
P
Default: VSS_3
VDD_3
100
P
Default: VDD_3
Alternate: TIMER3_ETI, EXMC_NBL0
Default: PE1
Alternate: EXMC_NBL1
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
25
GD32VF103 Datasheet
2.6.2.
GD32VF103Rx LQFP64 pin definitions
Table 2-5. GD32VF103Rx LQFP64 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
PC0
8
I/O
PC1
9
I/O
PC2
10
I/O
PC3
11
I/O
VSSA
12
P
Default: VSSA
VDDA
13
P
Default: VDDA
PA0-WKUP
14
I/O
PC13TAMPER-RTC
PC14OSC32IN
PC15OSC32OUT
Functions description
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PC0
Alternate: ADC01_IN10
Default: PC1
Alternate: ADC01_IN11
Default: PC2
Alternate: ADC01_IN12
Default: PC3
Alternate: ADC01_IN13
Default: PA0
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0 _ETI, TIMER4_CH0(3)
Default: PA1
PA1
15
I/O
Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,
TIMER4_CH1(3)
Default: PA2
PA2
16
I/O
Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,
TIMER4_CH2(3)
Default: PA3
PA3
17
I/O
Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,
TIMER4_CH3(3)
VSS_4
18
P
Default: VSS_4
VDD_4
19
P
Default: VDD_4
26
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PA4
PA4
20
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
I/O
DAC_OUT0
Remap:SPI2_NSS(3), I2S2_WS(3)
PA5
21
Default: PA5
I/O
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
22
I/O
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
23
I/O
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1
Remap: TIMER0_CH0_ON
PC4
24
I/O
PC5
25
I/O
Default: PC4
Alternate: ADC01_IN14
Default: PC5
Alternate: ADC01_IN15
Default: PB0
PB0
26
I/O
Alternate: ADC01_IN8, TIMER2_CH2,
Remap: TIMER0_CH1_ON
Default: PB1
PB1
27
I/O
Alternate: ADC01_IN9, TIMER2_CH3,
Remap: TIMER0_CH2_ON
PB2
28
I/O
5VT
Default: PB2, BOOT1
Default: PB10
PB10
29
I/O
5VT
Alternate: I2C1_SCL(3), USART2_TX(3),
Remap: TIMER1_CH2
Default: PB11
PB11
30
I/O
5VT
Alternate: I2C1_SDA(3), USART2_RX(3),
Remap: TIMER1_CH3
VSS_1
31
P
Default: VSS_1
VDD_1
32
P
Default: VDD_1
Default: PB12
PB12
33
I/O
5VT
Alternate: SPI1_NSS(3), I2C1_SMBA(3),
USART2_CK(3), TIMER0_BRKIN, I2S1_WS(3),
CAN1_RX
Default: PB13
PB13
34
I/O
5VT
Alternate: SPI1_SCK(3), USART2_CTS(3),
TIMER0_CH0_ON, I2S1_CK(3), CAN1_TX
PB14
35
I/O
5VT
Default: PB14
Alternate: SPI1_MISO(3), USART2_RTS(3),
27
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
TIMER0_CH1_ON
Default: PB15
PB15
36
I/O
5VT
Alternate: SPI1_MOSI(3), TIMER0_CH2_ON,
I2S1_SD(3)
Default: PC6
PC6
37
I/O
5VT
Alternate: I2S1_MCK(3)
Remap: TIMER2_CH0
Default: PC7
PC7
38
I/O
5VT
Alternate: I2S2_MCK(3)
Remap: TIMER2_CH1
PC8
39
I/O
5VT
PC9
40
I/O
5VT
Default: PC8
Remap: TIMER2_CH2
Default: PC9
Remap: TIMER2_CH3
Default: PA8
PA8
41
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF
Default: PA9
PA9
42
I/O
5VT
Alternate: USART0_TX, TIMER0_CH1,
USBFS_VBUS
PA10
43
I/O
5VT
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
44
I/O
5VT
Alternate: USART0_CTS, CAN0_RX, USBFS_DM,
TIMER0_CH3
Default: PA12
PA12
45
I/O
5VT
Alternate: USART0_RTS, USBFS_DP, CAN0_TX,
TIMER0_ETI
5VT
Default: JTMS
PA13
46
I/O
VSS_2
47
P
Default: VSS_2
VDD_2
48
P
Default: VDD_2
PA14
49
I/O
5VT
Remap: PA13
Default: JTCK
Remap: PA14
Default: JTDI
PA15
50
I/O
5VT
Alternate: SPI2_NSS(3), I2S2_WS(3)
Remap: TIMER1_CH0 _ETI, PA15, SPI0_NSS
Default: PC10
PC10
51
I/O
5VT
Alternate: UART3_TX(3)
Remap: USART2_TX(3), SPI2_SCK(3), I2S2_CK(3)
28
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Default: PC11
PC11
52
I/O
5VT
Alternate: UART3_RX(3)
Remap: USART2_RX(3), SPI2_MISO(3)
Default: PC12
PC12
53
I/O
5VT
Alternate: UART4_TX(3)
Remap: USART2_CK(3), SPI2_MOSI(3), I2S2_SD(3)
PD2
54
I/O
5VT
Default: PD2
Alternate: TIMER2_ETI, UART4_RX(3)
Default: JTDO
PB3
55
I/O
5VT
Alternate:SPI2_SCK(3), I2S2_CK(3)
Remap: PB3, TIMER1_CH1, SPI0_SCK
Default: NJTRST
PB4
56
I/O
5VT
Alternate: SPI2_MISO(3)
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
57
Alternate: I2C0_SMBA, SPI2_MOSI(3), I2S2_SD(3)
I/O
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
58
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0(3)
Remap: USART0_TX, CAN1_TX
Default: PB7
PB7
59
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1(3)
Remap: USART0_RX
BOOT0
60
I
Default: BOOT0
Default: PB8
PB8
61
I/O
5VT
Alternate: TIMER3_CH2(3)
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
62
I/O
5VT
Alternate: TIMER3_CH3(3)
Remap: I2C0_SDA, CAN0_TX
VSS_3
63
P
Default: VSS_3
VDD_3
64
P
Default: VDD_3
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available in GD32VF103R8/B devices.
29
GD32VF103 Datasheet
2.6.3.
GD32VF103Cx LQFP48 pin definitions
Table 2-6. GD32VF103Cx LQFP48 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
VBAT
1
P
2
I/O
3
I/O
4
I/O
OSCIN
5
I
OSCOUT
6
O
NRST
7
I/O
VSSA
8
P
Default: VSSA
VDDA
9
P
Default: VDDA
PC13TAMPERRTC
PC14OSC32IN
PC15OSC32OUT
Functions description
Default: VBAT
Default: PC13
Alternate: TAMPER-RTC
Default: PC14
Alternate: OSC32IN
Default: PC15
Alternate: OSC32OUT
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PA0
PA0-WKUP
10
I/O
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0_ETI, TIMER4_CH0(3)
Default: PA1
PA1
11
I/O
Alternate: USART1_RTS, ADC01_IN1,
TIMER4_CH1(3) ,TIMER1_CH1
Default: PA2
PA2
12
I/O
Alternate: USART1_TX, TIMER4_CH2(3),ADC01_IN2,
TIMER1_CH2
Default: PA3
PA3
13
I/O
Alternate: USART1_RX, TIMER4_CH3(3), ADC01_IN3,
TIMER1_CH3
Default: PA4
PA4
14
I/O
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4
DAC_OUT0
Remap: SPI2_NSS(3)，I2S2_WS(3)
PA5
15
I/O
PA6
16
I/O
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
30
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
17
I/O
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1
Remap: TIMER0_CH0_ON
Default: PB0
PB0
18
I/O
Alternate: ADC01_IN8, TIMER2_CH2
Remap: TIMER0_CH1_ON
Default: PB1
PB1
19
I/O
Alternate: ADC01_IN9, TIMER2_CH3
Remap: TIMER0_CH2_ON
PB2
20
I/O
5VT
Default: PB2, BOOT1
Default: PB10
PB10
21
I/O
5VT
Alternate: I2C1_SCL(3), USART2_TX(3)
Remap: TIMER1_CH2
Default: PB11
PB11
22
I/O
5VT
Alternate: I2C1_SDA(3), USART2_RX(3)
Remap: TIMER1_CH3
VSS_1
23
P
Default: VSS_1
VDD_1
24
P
Default: VDD_1
Default: PB12
PB12
25
I/O
5VT
Alternate: SPI1_NSS(3), I2S1_WS(3), I2C1_SMBA(3),
USART2_CK(3), TIMER0_BRKIN, CAN1_RX
Default: PB13
PB13
26
I/O
5VT
Alternate: SPI1_SCK(3), I2S1_CK(3), USART2_CTS(3),
TIMER0_CH0_ON, CAN1_TX
Default: PB14
PB14
27
I/O
5VT
Alternate: SPI1_MISO(3), USART2_RTS(3),
TIMER0_CH1_ON
PB15
28
I/O
5VT
Default: PB15
Alternate: SPI1_MOSI(3), TIMER0_CH2_ON, I2S1_SD(3)
Default: PA8
PA8
29
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF
PA9
30
I/O
5VT
PA10
31
I/O
5VT
PA11
32
I/O
5VT
Default: PA9
Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
Alternate: USART0_CTS, CAN0_RX, TIMER0_CH3,
31
GD32VF103 Datasheet
Pin Name
Pins
Pin
I/O
Type(1)
Level(2)
Functions description
USBFS_DM
Default: PA12
PA12
33
I/O
5VT
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI,
USBFS_DP
5VT
Default: JTMS
PA13
34
I/O
VSS_2
35
P
Default: VSS_2
VDD_2
36
P
Default: VDD_2
PA14
37
I/O
5VT
Remap: PA13
Default: JTCK
Remap: PA14
Default: JTDI
PA15
38
I/O
5VT
Alternate:SPI2_NSS(3), I2S2_WS(3)
Remap: TIMER1_CH0 _ETI, PA15, SPI0_NSS
Default: JTDO
PB3
39
I/O
5VT
Alternate:SPI2_SCK(3),I2S2_CK(3)
Remap: PB3, TIMER1_CH1, SPI0_SCK
Default: NJTRST
PB4
40
I/O
5VT
Alternate:SPI2_MISO(3)
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
41
Alternate: I2C0_SMBA ,SP12_MOSI(3), I2S2_SD(3)
I/O
Remap: TIMER2_CH1, SPI0_MOSI,CAN1_RX
Default: PB6
PB6
42
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0(3)
Remap: USART0_TX,CAN1_TX
Default: PB7
PB7
43
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1(3)
Remap: USART0_RX
BOOT0
44
I
Default: BOOT0
Default: PB8
PB8
45
I/O
5VT
Alternate: TIMER3_CH2(3)
Remap: I2C0_SCL, CAN0_RX
Default: PB9
PB9
46
I/O
5VT
Alternate: TIMER3_CH3(3)
Remap: I2C0_SDA, CAN0_TX
VSS_3
47
P
Default: VSS_3
VDD_3
48
P
Default: VDD_3
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
32
GD32VF103 Datasheet
(3) Functions are available in GD32VF103C8/B devices.
33
GD32VF103 Datasheet
2.6.4.
GD32VF103Tx QFN36 pin definitions
Table 2-7. GD32VF103Tx QFN36 pin definitions
Pin
I/O
Type(1)
Level(2)
Pin Name
Pins
Functions description
OSCIN
2
I
OSCOUT
3
O
NRST
4
I/O
VSSA
5
P
Default: VSSA
VDDA
6
P
Default: VDDA
Default: OSCIN
Remap: PD0
Default: OSCOUT
Remap: PD1
Default: NRST
Default: PA0
PA0-WKUP
7
I/O
Alternate: WKUP, USART1_CTS, ADC01_IN0,
TIMER1_CH0_ETI，TIMER4_CH0(3)
Default: PA1
PA1
8
I/O
Alternate: USART1_RTS, ADC01_IN1, TIMER1_CH1,
TIMER4_CH1(3)
Default: PA2
PA2
9
I/O
Alternate: USART1_TX, ADC01_IN2, TIMER1_CH2,
TIMER4_CH2(3)
Default: PA3
PA3
10
I/O
Alternate: USART1_RX, ADC01_IN3, TIMER1_CH3,
TIMER4_CH3(3)
Default: PA4
PA4
11
I/O
Alternate: SPI0_NSS, USART1_CK, ADC01_IN4,
DAC_OUT0
PA5
12
I/O
Default: PA5
Alternate: SPI0_SCK, ADC01_IN5, DAC_OUT1
Default: PA6
PA6
13
I/O
Alternate: SPI0_MISO, ADC01_IN6, TIMER2_CH0
Remap: TIMER0_BRKIN
Default: PA7
PA7
14
I/O
Alternate: SPI0_MOSI, ADC01_IN7, TIMER2_CH1
Remap: TIMER0_CH0_ON
Default: PB0
PB0
15
I/O
Alternate: ADC01_IN8, TIMER2_CH2
Remap: TIMER0_CH1_ON
Default: PB1
PB1
16
I/O
Alternate: ADC01_IN9, TIMER2_CH3
Remap: TIMER0_CH2_ON
34
GD32VF103 Datasheet
Pin
I/O
Type(1)
Level(2)
17
I/O
5VT
VSS_1
18
P
Default: VSS_1
VDD_1
19
P
Default: VDD_1
Pin Name
Pins
PB2
Functions description
Default: PB2,BOOT1
Default: PA8
PA8
20
I/O
5VT
Alternate: USART0_CK, TIMER0_CH0, CK_OUT0,
USBFS_SOF
PA9
21
I/O
5VT
PA10
22
I/O
5VT
Default: PA9
Alternate: USART0_TX, TIMER0_CH1, USBFS_VBUS
Default: PA10
Alternate: USART0_RX, TIMER0_CH2, USBFS_ID
Default: PA11
PA11
23
I/O
5VT
Alternate: USART0_CTS, CAN0_RX,
TIMER0_CH3,
USBFS_DM
Default: PA12
PA12
24
I/O
5VT
Alternate: USART0_RTS, CAN0_TX, TIMER0_ETI,
USBFS_DP
5VT
Default: JTMS
PA13
25
I/O
VSS_2
26
P
Default: VSS_2
VDD_2
27
P
Default: VDD_2
PA14
28
I/O
5VT
PA15
29
I/O
5VT
PB3
30
I/O
5VT
PB4
31
I/O
5VT
Remap: PA13
Default: JTCK
Remap: PA14
Default: JTDI
Remap: TIMER1_CH0 _ETI, PA15, SPI0_NSS
Default: JTDO
Remap: PB3, TIMER1_CH1, SPI0_SCK
Default: NJTRST
Remap: TIMER2_CH0, PB4, SPI0_MISO
Default: PB5
PB5
32
I/O
Alternate: I2C0_SMBA
Remap: TIMER2_CH1, SPI0_MOSI, CAN1_RX
Default: PB6
PB6
33
I/O
5VT
Alternate: I2C0_SCL, TIMER3_CH0(3)
Remap: USART0_TX, CAN1_TX
Default: PB7
PB7
34
I/O
5VT
Alternate: I2C0_SDA , TIMER3_CH1(3)
Remap: USART0_RX
BOOT0
35
I
Default: BOOT0
VSS_3
36
P
Default: VSS_3
35
GD32VF103 Datasheet
Pin Name
Pins
VDD_3
1
Pin
I/O
Type(1)
Level(2)
P
Functions description
Default: VDD_3
Notes:
(1) Type: I = input, O = output, P = power.
(2) I/O Level: 5VT = 5 V tolerant.
(3) Functions are available in GD32VF103T8/B devices.
36
GD32VF103 Datasheet
3.
Functional description
3.1.
System and memory architecture
The devices of GD32VF103 series are 32-bit general-purpose microcontrollers based on the
32bit RISC-V processor. The RISC-V processor includes three AHB buses known as I-Code,
D-Code and System buses. All memory accesses of the RISC-V processor are executed on
the three buses according to the different purposes and the target memory spaces. The
memory organization uses a Harvard architecture, pre-defined memory map and up to 4 GB
of memory space, making the system flexible and extendable.
3.2.
On-chip memory
Up to 128 Kbytes of Flash memory
All memory region of the MCU executes instructions without waiting time
32 Kbytes of SRAM
The RISC-V processor is structured in Harvard architecture which can use separate buses to
fetch instructions and load/store data. 128 Kbytes of inner Flash at most, which includes code
Flash and data Flash, is available for storing programs and data, and there is no waiting time
within code Flash area when CPU executes instructions. The Table 2-3. GD32VF103
memory map shows the memory map of the GD32VF103 series of devices, including code,
SRAM, peripheral, and other pre-defined regions.
3.3.
Clock, reset and supply management
Internal 8 MHz factory-trimmed RC and external 3 to 25 MHz crystal oscillator
Internal 40 KHz RC calibrated oscillator and external 32.768 KHz crystal oscillator
Integrated system clock PLL
2.6 to 3.6 V application supply and I/Os
Supply Supervisor: POR (Power On Reset), PDR (Power Down Reset), and low voltage
detector (LVD)
The Clock Control unit provides a range of frequencies and clock functions. These include an
Internal 8M RC oscillator (IRC8M), a High Speed crystal oscillator (HXTAL), a Low Speed
Internal 40K RC oscillator (IRC40K), a Low Speed crystal oscillator (LXTAL), a Phase Lock
Loop (PLL), a HXTAL clock monitor, clock prescalers, clock multiplexers and clock gating
circuitry. The frequency of AHB, APB2 and the APB1 domains can be configured by each
prescaler. The maximum frequency of the AHB, APB2 and APB1 domains is 108 MHz/108
MHz/54 MHz. See Figure 2-6. GD32VF103 clock tree for details.
GD32VF103 Reset Control includes the control of three kinds of reset: power reset, system
37
GD32VF103 Datasheet
reset and backup domain reset. The system reset resets the processor core and peripheral
IP components except for the JTAG-DP controller and the Backup domain. Power-on reset
(POR) and power-down reset (PDR) are always active, and ensures proper operation starting
from/down to 2.6 V. The device remains in reset mode when VDD is below a specified
threshold. The embedded low voltage detector (LVD) monitors the power supply, compares
it to the voltage threshold and generates an interrupt as a warning message for leading the
MCU into security.
Power supply schemes:
VDD range: 2.6 to 3.6 V, external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VDDA range: 2.6 to 3.6 V, external analog power supplies for ADC, reset blocks, RCs and
PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
VBAT range: 1.8 to 3.6 V, power supply for RTC, external clock 32 KHz oscillator and
backup registers (through power switch) when VDD is not present.
3.4.
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from main flash memory (default)
Boot from system memory
Boot from on-chip SRAM
The boot loader is located in the internal boot ROM memory (system memory). It is used to
reprogram the Flash memory by using USART0 (PA9 and PA10), USART1 (PD5 and PD6),
USBFS in device mode (PA9, PA11 and PA12). It also can be used to transfer and update the
Flash memory code, the data and the vector table sections.
38
GD32VF103 Datasheet
3.5.
Power saving modes
The MCU supports three kinds of power saving modes to achieve even lower power
consumption. They are sleep mode, deep-sleep mode, and standby mode. These operating
modes reduce the power consumption and allow the application to achieve the best balance
between the CPU operating time, speed and power consumption.
Sleep mode
In sleep mode, only clock of core is off. All peripherals continue to operate and any
interrupt/event can wake up the system.
Deep-sleep mode
In deep-sleep mode, all clocks in the 1.2V domain are off, and all of IRC8M, HXTAL and
PLLs are disabled. Only the contents of SRAM and registers are retained. Any interrupt
or wakeup event from EXTI lines can wake up the system from the deep-sleep mode
including the 16 external lines, the RTC alarm/ time stamp/ tamper, the LVD output, USB
Wakeup. When exiting the deep-sleep mode, the IRC8M is selected as the system clock.
Standby mode
In standby mode, the whole 1.2V domain is power off, the LDO is shut down, and all of
IRC8M, HXTAL and PLLs are disabled. The contents of SRAM and registers (except
Backup registers) are lost. There are four wakeup sources for the Standby mode,
including the external reset from NRST pin, the RTC alarm/ time stamp/ tamper, the
FWDGT reset, and the rising edge on WKUP pin.
3.6.
Analog to digital converter (ADC)
12-bit SAR ADC engine with up to 1MSPS conversion rate
12-bit, 10-bit, 8-bit or 6-bit configurable resolution
Hardware oversampling ratio adjustable from 2 to 256x improves resolution to 16-bit
Conversion range: VSSA to VDDA (2.6 to 3.6 V)
Temperature sensor
Up to two 12-bit 1MSPS multi-channel ADCs are integrated in the device. Each is a total of
up to 16 multiplexed external channels with 2 internal channels for temperature sensor and
voltage reference measurement. An analog watchdog block can be used to detect the
channels, which are required to remain within a specific threshold window. A configurable
channel management block of analog inputs also can be used to perform conversions in
single, continuous, scan or discontinuous mode to support more advanced usages.
The ADCs can be triggered from the events generated by the general level 0 timers
(TIMERx=1,2,3) and the advanced timers (TIMER0) with internal connection. The
temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 2.6 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output voltage
into a digital value.
39
GD32VF103 Datasheet
To ensure a high accuracy on ADC and DAC, the ADC/DAC independent external reference
voltage should be connected to VREF+/VREF- pins. According to the different packages, VREF+
pin can be connected to VDDA pin, or external reference voltage, VREF- pin must be connected
to VSSA pin. The VREF+ pin is only available on no less than 100-pin packages, or else the VREF+
pin is not available and internally connected to VDDA. The VREF- pin is only available on no less
than 100-pin packages, or else the VREF- pin is not available and internally connected to VSSA.
3.7.
Digital to analog converter (DAC)
Two 12-bit DAC converters of independent output channel
8-bit or 12-bit mode in conjunction with the DMA controller
The two 12-bit buffered DAC channels are used to generate variable analog outputs. The
DACs are designed with integrated resistor strings structure. The DAC channels can be
triggered by the timer TRGO outputs or EXTI with DMA support. In dual DAC channel
operation, conversions could be done independently or simultaneously. The maximum output
value of the DAC is VREF+.
3.8.
DMA
7 channel DMA0 controller and 5 channel DMA1 controller
Peripherals supported: TIMERs, ADC, SPIs, I2Cs, USARTs, DAC, I2S
The direct memory access (DMA) controllers provide a hardware method of transferring data
between peripherals and/or memory without intervention from the CPU, thereby freeing up
bandwidth for other system functions. Three types of access method are supported:
peripheral to memory, memory to peripheral, memory to memory
Each channel is connected to fixed hardware DMA requests. The priorities of DMA channel
requests are determined by software configuration and hardware channel number. Transfer
size of source and destination are independent and configurable.
3.9.
General-purpose inputs/outputs (GPIOs)
Up to 80 fast GPIOs, all mappable on 16 external interrupt lines
Analog input/output configurable
Alternate function input/output configurable
There are up to 80 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0
~ PC15, PD0 ~ PD15, PE0 ~ PE15 for the device to implement logic input/output functions.
Each GPIO port has related control and configuration registers to satisfy the requirements of
specific applications. The external interrupt on the GPIO pins of the device have related
control and configuration registers in the Interrupt/event Controller Unit (EXTI). The GPIO
40
GD32VF103 Datasheet
ports are pin-shared with other alternative functions (AFs) to obtain maximum flexibility on the
package pins. The GPIO pins can be used as alternative functional pins by configuring the
corresponding registers regardless of the AF input or output pins. Each of the GPIO pins can
be configured by software as output (push-pull or open-drain), input, peripheral alternate
function or analog mode. Each GPIO pin can be configured as pull-up, pull-down or no pullup/pull-down. All GPIOs are high-current capable except for analog mode.
3.10.
Timers and PWM generation
Up to one 16-bit advanced timer (TIMER0), four 16-bit general timers(TIMERx=1,2,3,4),
and two 16-bit basic timer (TIMER5 & TIMER6)
Up to 4 independent channels of PWM, output compare or input capture for each general
timer and external trigger input
16-bit, motor control PWM advanced timer with programmable dead-time generation for
output match
Encoder interface controller with two inputs using quadrature decoder
64-bit SysTick timer up counter
2 watchdog timers (Free watchdog timer and window watchdog timer)
The advanced timer (TIMER0) can be seen as a three-phase PWM multiplexed on 6 channels.
It has complementary PWM outputs with programmable dead-time generation. It can also be
used as a complete general timer. The 4 independent channels can be used for
Input capture
Output compare
PWM generation (edge-aligned or center-aligned counting modes)
Single pulse mode output
If configured as a general 16-bit timer, it can be synchronized with external signals or to
interconnect with other general timers together which have the same architecture and
features.
The general timer, known as TIMERx=1,2,3,4 can be used for a variety of purposes including
general time, input signal pulse width measurement or output waveform generation such as
a single pulse generation or PWM output, up to 4 independent channels for input
capture/output compare. The general timer also supports an encoder interface with two inputs
using quadrature decoder.
The basic timer, known as TIMER5 and TIMER6 are mainly used for DAC trigger generation.
They can also be used as a simple 16-bit time base.
The GD32VF103 have two watchdog peripherals, free watchdog timer and window watchdog
timer. They offer a combination of high safety level, flexibility of use and timing accuracy.
The free watchdog timer includes a 12-bit down-counting counter and a 3-bit prescaler, it is
clocked from an independent 40 KHz internal RC and as it operates independently of the
41
GD32VF103 Datasheet
main clock, it can operate in deep-sleep and standby modes. It can be used either as a
watchdog to reset the device when a problem occurs, or as a free-running timer for application
timeout management.
The window watchdog timer is based on a 7-bit down counter that can be set as free-running.
It can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early wakeup interrupt capability and the counter can be frozen in
debug mode.
The SysTick timer is dedicated for OS, but could also be used as a standard up counter. The
features are shown below:
A 64-bit up counter
Maskable system interrupt generation when the counter and comparison values are
equal
3.11.
Programmable clock source
Real time clock (RTC)
32-bit up-counter with a programmable 20-bit prescaler
Alarm function
Interrupt and wake-up event
The real time clock is an independent timer which provides a set of continuously running
counters which can be used with suitable software to provide a clock calendar function, and
provides an alarm interrupt and an expected interrupt. The RTC features a 32-bit
programmable counter for long-term measurement using the compare register to generate an
alarm. A 20-bit prescaler is used for the time base clock and is by default configured to
generate a time base of 1 second from a clock at 32.768 KHz from external crystal oscillator.
3.12.
Inter-integrated circuit (I2C)
Up to two I2C bus interfaces can support both master and slave mode with a frequency
up to 400 KHz
Provide arbitration function, optional PEC (packet error checking) generation and
checking
Supports 7-bit and 10-bit addressing mode and general call addressing mode
The I2C interface is an internal circuit allowing communication with an external I2C interface
which is an industry standard two line serial interface used for connection to external
hardware. These two serial lines are known as a serial data line (SDA) and a serial clock line
(SCL). The I2C module provides transfer rate of up to 100 KHz in standard mode, up to 400
KHz in the fast mode and up to 1 MHz in the fast mode plus. The I2C module also has an
arbitration detect function to prevent the situation where more than one master attempts to
42
GD32VF103 Datasheet
transmit data to the I2C bus at the same time. A CRC-8 calculator is also provided in I2C
interface to perform packet error checking for I2C data.
43
GD32VF103 Datasheet
3.13.
Serial peripheral interface (SPI)
Up to three SPI interfaces with a frequency of up to 27 MHz
Support both master and slave mode
Hardware CRC calculation and transmit automatic CRC error checking
The SPI interface uses 4 pins, among which are the serial data input and output lines (MISO
& MOSI), the clock line (SCK) and the slave select line (NSS). Both SPIs can be served by
the DMA controller. The SPI interface may be used for a variety of purposes, including simplex
synchronous transfers on two lines with a possible bidirectional data line or reliable
communication using CRC checking.
3.14.
Universal synchronous asynchronous receiver transmitter
(USART)
Up to three USARTs and two UARTs with operating frequency up to 6.75 MHz
Supports both asynchronous and clocked synchronous serial communication modes
IrDA SIR encoder and decoder support
LIN break generation and detection
USARTs support ISO 7816-3 compliant smart card interface
The USART (USART0, USART1 and USART2) are used to translate data between parallel
and serial interfaces, provides a flexible full duplex data exchange using synchronous or
asynchronous transfer. It is also commonly used for RS-232 standard communication. The
USART includes a programmable baud rate generator which is capable of dividing the system
clock to produce a dedicated clock for the USART transmitter and receiver. The USART also
supports DMA function for high speed data communication except UART4.
3.15.
Inter-IC sound (I2S)
Two I2S bus Interfaces with sampling frequency from 8 KHz to 192 KHz
Support either master or slave mode
The Inter-IC sound (I2S) bus provides a standard communication interface for digital audio
applications by 3-wire serial lines. GD32VF103 contain two I2S-bus interfaces that can be
operated with 16/32 bit resolution in master or slave mode, pin multiplexed with SPI1 and
SPI2. The audio sampling frequency from 8 KHz to 192 KHz is supported with less than 0.5%
accuracy error.
44
GD32VF103 Datasheet
3.16.
Universal serial bus full-speed (USBFS)
One USB device/host/OTG full-speed Interface with frequency up to 12 Mbit/s
Internal main PLL for USB CLK compliantly
The Universal Serial Bus (USB) is a 4-wire bus with 4 bidirectional endpoints. The device
controller enables 12 Mbit/s data exchange with integrated transceivers in device/host/OTG
mode. Full-speed peripheral is compliant with the USB 2.0 specification. Transaction
formatting is performed by the hardware, including CRC generation and checking. The status
of a completed USB transfer or error condition is indicated by status registers. An interrupt is
also generated if enabled. The dedicated 48 MHz clock is generated from the internal main
PLL (the clock source must use a HXTAL crystal oscillator) and the operating frequency
divided from APB1 should be 12 MHz above.
3.17.
Controller area network (CAN)
Two CAN2.0B interface with communication frequency up to 1 Mbit/s
Internal main PLL for USB CLK compliantly
Controller area network (CAN) is a method for enabling serial communication in field bus. The
CAN protocol has been used extensively in industrial automation and automotive applications.
It can receive and transmit standard frames with 11-bit identifiers as well as extended frames
with 29-bit identifiers. Each CAN has three mailboxes for transmission and two FIFOs of three
message deep for reception. It also provides 28 scalable/configurable identifier filter banks
for selecting the incoming messages needed and discarding the others.
3.18.
External memory controller (EXMC)
Supported external memory: SRAM, PSRAM, ROM and NOR-Flash
Up to 16-bit data bus
Support to interface with Motorola 6800 and Intel 8080 type LCD directly
External memory controller (EXMC) is an abbreviation of external memory controller. It has
one bank for external device support. The EXMC also can be configured to interface with the
most common LCD module of Motorola 6800 and Intel 8080 series and reduce the system
cost and complexity.
3.19.
Debug mode
Support standard JTAG debugging interface and mature interactive debugging tool GDB
Support up to four hardware breakpoints
45
GD32VF103 Datasheet
The RISC-V Core does not support trace debugging. Hardware breakpoints are mainly used
to set breakpoints at read-only sections (such as Flash).
3.20.
Package and operation temperature
LQFP100 (GD32VF103Vx), LQFP64 (GD32VF103Rx), LQFP48 (GD32VF103Cx),
QFN36 (GD32VF103Tx)
Operation temperature range: -40°C to +85°C (industrial level)
46
GD32VF103 Datasheet
4.
Electrical characteristics
4.1.
Absolute maximum ratings
The maximum ratings are the limits to which the device can be subjected without permanently
damaging the device. Note that the device is not guaranteed to operate properly at the
maximum ratings. Exposure to the absolute maximum rating conditions for extended periods
may affect device reliability.
Table 4-1. Absolute maximum ratings(1)(4)
Symbol
VDD
External voltage
range(2)
Min
Max
Unit
VSS - 0.3
VSS + 3.6
V
VDDA
External analog supply voltage
VSSA - 0.3
VSSA + 3.6
V
VBAT
External battery supply voltage
VSS - 0.3
VSS + 3.6
V
VSS - 0.3
VDD + 3.6
V
Input voltage on other I/O
VSS - 0.3
3.6
V
|ΔVDDX|
Variations between different VDD power pins
—
50
mV
|VSSX −VSS|
Variations between different ground pins
—
50
mV
IIO
Maximum current for GPIO pins
—
±25
mA
TA
Operating temperature range
-40
+85
°C
Power dissipation at TA = 85°C of LQFP100
—
697
Power dissipation at TA = 85°C of LQFP64
—
647
Power dissipation at TA = 85°C of LQFP48
—
621
Power dissipation at TA = 85°C of QFN36
—
926
TSTG
Storage temperature range
-65
+150
°C
TJ
Maximum junction temperature
—
125
°C
VIN
PD
(1)
(2)
(3)
(4)
4.2.
Parameter
Input voltage on 5V tolerant
pin(3)
mW
Guaranteed by design, not tested in production.
All main power and ground pins should be connected to an external power source within the allowable range.
VIN maximum value cannot exceed 5.5 V.
It is recommended that VDD and VDDA are powered by the same source. The maximum difference between VDD
and VDDA does not exceed 300 mV during power-up and operation.
Operating conditions characteristics
Table 4-2. DC operating conditions
Min(1) Typ
Max(1) Unit
Symbol
Parameter
Conditions
VDD
Supply voltage
—
2.6
3.3
3.6
V
VDDA
Analog supply voltage
Same as VDD
2.6
3.3
3.6
V
VBAT
Battery supply voltage
—
1.8
—
3.6
V
(1)
Based on characterization, not tested in production.
47
GD32VF103 Datasheet
Figure 4-1. Recommended power supply decoupling capacitors(1)(2)
VBAT
100 nF
VSS
N * VDD
4.7 μF + N * 100 nF
VSS
VDDA
1 μF
10 nF
VSSA
VREF+
1 μF
(1)
(2)
10 nF
VREF-
The VREF+ and VREF- pins are only available on no less than 100-pin packages, or else the VREF+ and VREF- pins
are not available and internally connected to VDDA and VSSA pins.
All decoupling capacitors need to be as close as possible to the pins on the PCB board.
Table 4-3. Clock frequency(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
AHB clock frequency
—
—
108
MHz
fAPB1
APB1 clock frequency
—
—
54
MHz
fAPB2
APB2 clock frequency
—
—
108
MHz
Min
Max
Unit
0
∞
20
∞
(1)
Guaranteed by design, not tested in production.
Table 4-4. Operating conditions at Power up/ Power down(1)
Symbol
tVDD
(1)
Parameter
Conditions
VDD rise time rate
—
VDD fall time rate
μs/V
Guaranteed by design, not tested in production.
Table 4-5. Start-up timings of Operating conditions (1)(2)(3)
(1)
(2)
(3)
Symbol
Parameter
tstart-up
Start-up time
Conditions
Typ
Clock source from HXTAL
132
Clock source from IRC8M
132
Unit
ms
Based on characterization, not tested in production.
After power-up, the start-up time is the time between the rising edge of NRST high and the main function.
PLL is off.
Table 4-6. Power saving mode wakeup timings characteristics(1)(2)
Symbol
Parameter
Typ
tSleep
Wakeup from Sleep mode
4.5
Wakeup from Deep-sleep mode（LDO On）
6.0
Wakeup from Deep-sleep mode（LDO in low power mode）
6.0
Wakeup from Standby mode
118.8
tDeep-sleep
tStandby
Unit
μs
ms
48
GD32VF103 Datasheet
(1)
(2)
4.3.
Based on characterization, not tested in production.
The wakeup time is measured from the wakeup event to the point at which the application code reads the first
instruction under the below conditions: VDD = VDDA = 3.3 V, IRC8M = System clock = 8 MHz.
Power consumption
The power measurements specified in the tables represent that code with data executing from
on-chip Flash with the following specifications.
Table 4-7. Power consumption characteristics(2)(3)(4)(5)
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
—
35.00
—
mA
—
20.05
—
mA
—
32.30
—
mA
—
18.90
—
mA
—
23.50
—
mA
—
13.40
—
mA
—
16.60
—
mA
—
9.90
—
mA
—
13.10
—
mA
—
8.10
—
mA
—
9.80
—
mA
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 108 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 96 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 72 MHz, All peripherals
enabled
IDD+IDDA
Supply current
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
(Run mode)
System clock = 72 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 48 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock =36 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 36 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
49
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 24 MHz, All peripherals
—
6.50
—
mA
—
7.60
—
mA
—
5.30
—
mA
—
5.30
—
mA
—
4.10
—
mA
—
1.80
—
mA
—
1.30
—
mA
—
1.30
—
mA
—
1.00
—
mA
—
26.20
—
mA
—
11.35
—
mA
—
24.10
—
mA
—
10.70
—
mA
—
18.70
—
mA
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 16 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System clock = 8 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System clock = 4 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System clock = 2 MHz, All peripherals
disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
All peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 108 MHz, CPU clock off,
Supply current
(Sleep mode)
All peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 96 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
50
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
System Clock = 72 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 72 MHz, CPU clock off, All
—
8.70
—
mA
—
13.40
—
mA
—
6.70
—
mA
—
1.80
—
mA
—
5.70
—
mA
—
8.30
—
mA
—
4.90
—
mA
—
6.50
—
mA
—
4.30
—
mA
—
4.70
—
mA
—
3.60
—
mA
—
1.40
—
mA
—
0.90
—
mA
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 48 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 36 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 24 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 16 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 25 MHz,
System Clock = 8 MHz, CPU clock off, All
peripherals disabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 4 MHz,
System Clock = 4 MHz, CPU clock off, All
peripherals disabled
51
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min Typ(1) Max
Unit
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
—
1.00
—
mA
—
0.70
—
mA
2200
μA
peripherals enabled
VDD = VDDA = 3.3 V, HXTAL = 2 MHz,
System Clock = 2 MHz, CPU clock off, All
peripherals disabled
460.0
VDD = VDDA = 3.3 V, LDO in normal power
Supply current
(Deep-Sleep
mode)
and normal driver mode, IRC40K off, RTC
—
0
off, All GPIOs analog mode
427.5
VDD = VDDA = 3.3 V, LDO in normal power
and low driver mode, IRC40K off, RTC off,
—
0
2200
μA
—
7.62
22
μA
—
7.49
22
μA
—
6.32
22
μA
—
2.18
—
μA
—
2.10
—
μA
—
1.97
—
μA
All GPIOs analog mode
VDD = VDDA = 3.3 V, LDO off, LXTAL off,
IRC40K on, RTC on
Supply current
VDD = VDDA = 3.3 V, LDO off, LXTAL off,
(Standby mode)
IRC40K on, RTC off
VDD = VDDA = 3.3 V, LDO off, LXTAL off,
IRC40K off, RTC off
VDD off, VDDA off, VBAT = 3.6 V, LXTAL on
Battery supply
IBAT
current (Backup
mode)
with external crystal, RTC on
VDD off, VDDA off, VBAT = 3.3 V, LXTAL on
with external crystal, RTC on
VDD off, VDDA off, VBAT = 2.6 V, LXTAL on
with external crystal, RTC on
(1)
(2)
(3)
(4)
(5)
Based on characterization, not tested in production.
Unless otherwise specified, all values given for TA = 25 °C and test result is mean value.
When System Clock is less than 4 MHz, an external source is used, and the HXTAL bypass function is needed,
no PLL.
When System Clock is greater than 8 MHz, a crystal 8 MHz is used, and the HXTAL bypass function is closed,
using PLL.
When analog peripheral blocks such as ADCs, DACs, HXTAL, LXTAL, IRC8M, or IRC40K are ON, an
additional power consumption should be considered.
52
GD32VF103 Datasheet
Figure 4-2. Typical supply current consumption in Run mode
Figure 4-3. Typical supply current consumption in Sleep mode
4.4.
EMC characteristics
EMS (electromagnetic susceptibility) includes ESD (Electrostatic discharge, positive and
negative) and FTB (Burst of Fast Transient voltage, positive and negative) testing result is
given in the Table 4-8. EMS characteristics, based on the EMS levels and classes
compliant with IEC 61000 series standard.
53
GD32VF103 Datasheet
Table 4-8. EMS characteristics
Symbol
VESD
(1)
Parameter
Conditions
Voltage applied to all device pins to
induce a functional disturbance
VDD = 3.3 V, TA = 25 °C
LQFP100, fHCLK = 108 MHz
(1)
4.5.
3A
conforms to IEC 61000-4-2
Fast transient voltage burst applied to
VFTB
Level/Class
VDD = 3.3 V, TA =
25 °C
induce a functional disturbance through
LQFP100, fHCLK = 108 MHz
100 pF on VDD and VSS pins
conforms to IEC 61000-4-2
4A
Based on characterization, not tested in production
Power supply supervisor characteristics
Table 4-9. Power supply supervisor characteristics
Symbol
VLVD(1)
Parameter
Conditions
Min
Typ
Max
LVDT = 000(rising edge)
—
2.18
—
LVDT = 000(falling edge)
—
2.08
—
LVDT = 001(rising edge)
—
2.29
—
LVDT = 001(falling edge)
—
2.19
—
LVDT = 010(rising edge)
—
2.38
—
LVDT = 010(falling edge)
—
2.28
—
LVDT = 011(rising edge)
—
2.49
—
Low voltage
LVDT = 011(falling edge)
—
2.38
—
Detector level selection
LVDT = 100(rising edge)
—
2.58
—
LVDT = 100(falling edge)
—
2.48
—
LVDT = 101(rising edge)
—
2.68
—
LVDT = 101(falling edge)
—
2.58
—
LVDT = 110(rising edge)
—
2.78
—
LVDT = 110(falling edge)
—
2.68
—
LVDT = 111(rising edge)
—
2.88
—
LVDT = 111(falling edge)
—
2.78
—
—
—
100
—
mV
—
2.44
—
V
—
1.86
—
V
VLVDhyst(2)
LVD hystersis
VPOR(1)
Power on reset threshold
Unit
V
—
VPDR(1)
Power down reset
54
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
threshold
VPDRhyst(2)
PDR hysteresis
—
600
—
mV
tRSTTEMPO(2)
Reset temporization
—
2
—
ms
(1)
(2)
4.6.
Based on characterization, not tested in production
Guaranteed by design, not tested in production
Electrical sensitivity
The device is strained in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharges (ESD) are applied directly to the pins of the sample. Static latch-up
(LU) test is based on the two measurement methods.
Table 4-10. ESD characteristics(1)
Symbol
VESD(HBM)
VESD(CDM)
(1)
Parameter
Conditions
Electrostatic discharge
TA = 25 °C;
voltage (human body model)
JESD22-A114
Electrostatic discharge
TA = 25 °C;
voltage (charge device model)
JESD22-C101
Min
Typ
Max
Unit
—
—
5000
V
—
—
500
V
Min
Typ
Max
Unit
—
—
±200
mA
—
—
5.4
V
Based on characterization, not tested in production.
Table 4-11. Static latch-up characteristics(1)
Symbol
Parameter
Conditions
I-test
LU
TA = 25 °C; JESD78
Vsupply over voltage
(1)
4.7.
Based on characterization, not tested in production.
External clock characteristics
Table 4-12. High speed external clock (HXTAL) generated from a crystal/ceramic
characteristics
55
GD32VF103 Datasheet
Symbol
fHXTAL
RF
(1)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
2.6 V ≤ VDD ≤ 3.6 V
3
8
25
MHz
Feedback resistor
VDD = 3.3 V
—
400
—
kΩ
—
—
20
30
pF
Crystal or ceramic duty cycle
—
48
50
52
%
Oscillator transconductance
Startup
—
35
—
mA/V
—
1.4
—
mA
—
1.8
—
ms
(2)
Recommended matching
CHXTAL
(2)(3)
capacitance on OSCIN and
OSCOUT
Ducy(HXTAL)
(2)
gm(2)
IDDHXTAL
(1)
Crystal or ceramic operating
VDD = 3.3 V, fHCLK =
fIRC8M = 8 MHz
current
TA = 25 °C
VDD = 3.3 V, fHCLK =
tSUHXTAL
(1)
Crystal or ceramic startup time
fIRC8M = 8 MHz
TA = 25 °C
(1)
(2)
(3)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CHXTAL1 = CHXTAL2 = 2*(CLOAD - CS), For CHXTAL1 and CHXTAL2, it is recommended matching capacitance on OSCIN
and OSCOUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
Table 4-13. High speed external clock characteristics (HXTAL in bypass mode)
Symbol
Parameter
fHXTAL_ext(1)
External clock source or oscillator
frequency
Conditions
Min
Typ
Max
Unit
VDD = 3.3 V
1
—
50
MHz
0.7 VDD
—
VDD
V
VSS
—
0.3 VDD
V
OSCIN input pin high level
VHXTALH(2)
voltage
VHXTALL(2)
VDD = 3.3 V
OSCIN input pin low level voltage
tH/L(HXTAL)
(2)
OSCIN high or low time
—
5
—
—
ns
tR/F(HXTAL)
(2)
OSCIN rise or fall time
—
—
—
10
ns
OSCIN input capacitance
—
—
5
—
pF
Duty cycle
—
40
—
60
%
CIN(2)
Ducy(HXTAL)
(1)
(2)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-14. Low speed external clock (LXTAL) generated from a crystal/ceramic
characteristics
Symbol
fLXTAL
(1)
Parameter
Conditions
Min
Typ
Max
Unit
Crystal or ceramic frequency
VDD = 3.3 V
—
32.768
—
kHz
—
—
10
20
pF
—
48
50
52
%
—
11
—
μA/V
—
1.97
—
μA
Recommended matching
CLXTAL
(2) (3)
capacitance on OSC32IN and
OSC32OUT
Ducy(LXTAL)
(2)
gm(2)
IDDLXTAL (1)
Crystal or ceramic duty cycle
Oscillator transconductance
Crystal or ceramic operating
current
—
56
GD32VF103 Datasheet
tSULXTAL
(1)
(2)
(3)
(4)
(1) (4)
Crystal or ceramic startup time
—
—
1.8
—
s
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
CLXTAL1 = CLXTAL2 = 2*(CLOAD - CS), For CLXTAL1 and CLXTAL2, it is recommended matching capacitance on OSC32IN
and OSC32OUT. For CLOAD, it is crystal/ceramic load capacitance, provided by the crystal or ceramic
manufacturer. For CS, it is PCB and MCU pin stray capacitance.
tSULXTAL is the startup time measured from the moment it is enabled (by software) to the 32.768 kHz oscillator
stabilization flags is SET. This value varies significantly with the crystal manufacturer.
Table 4-15. Low speed external user clock characteristics (LXTAL in bypass mode)
Symbol
Parameter
External clock source or oscillator
fLXTAL_ext(1)
frequency
OSC32IN input pin high level
VLXTALH(2)
VLXTALL
voltage
tR/F(LXTAL)
(2)
CIN(2)
Ducy(LXTAL)
(1)
(2)
4.8.
(2)
Typ
Max
Unit
VDD = 3.3 V
—
32.768
1000
kHz
—
0.7 VDD
—
VDD
—
VSS
—
0.3 VDD
OSC32IN high or low time
—
450
—
—
OSC32IN rise or fall time
—
—
—
50
OSC32IN input capacitance
—
—
5
—
pF
Duty cycle
—
30
50
70
%
voltage
tH/L(LXTAL) (2)
Min
V
OSC32IN input pin low level
(2)
Conditions
ns
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Internal clock characteristics
Table 4-16. High speed internal clock (IRC8M) characteristics
Symbol
Parameter
Conditions
Min
Typ Max Unit
VDD = VDDA = 3.3 V
—
8
—
MHz
-2.5
—
+1.5
%
-1.2
—
+1.2
%
VDD = VDDA = 3.3 V, TA = 25 °C
-1
—
+1
%
—
—
0.5
—
%
DucyIRC8M(2) IRC8M oscillator duty cycle
VDD = VDDA = 3.3 V
48
50
52
%
IRC8M oscillator operating
VDD = VDDA = 3.3 V,
current
fHCLK = fHXTAL_PLL = 108 MHz
—
80
—
μA
IRC8M oscillator startup
VDD = VDDA = 3.3 V,
time
fHCLK = fHXTAL_PLL = 108 MHz
—
2
—
μs
High Speed Internal
fIRC8M
Oscillator (IRC8M)
frequency
VDD = VDDA = 3.3 V,
IRC8M oscillator Frequency
accuracy, Factory-trimmed
ACCIRC8M
TA = -40°C ~ +85 °C(1)
VDD = VDDA = 3.3 V,
TA = 0°C ~ +85 °C(1)
IRC8M oscillator Frequency
accuracy, User trimming
step(1)
IDDAIRC8M(1)
tSUIRC8M(1)
57
GD32VF103 Datasheet
(1)
(2)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Table 4-17. Low speed internal clock (IRC40K) characteristics
Symbol
fIRC40K(1)
IDDAIRC40K(2)
tSUIRC40K(2)
(1)
(2)
4.9.
Parameter
Conditions
Low Speed Internal oscillator
VDD = VDDA = 3.3 V,
(IRC40K) frequency
TA = -40 °C ~ +85 °C
IRC40K oscillator operating
current
IRC40K oscillator startup
time
Min
Typ
Max
Unit
30
40
60
kHz
—
2
—
μA
—
100
—
μs
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 108 MHz
TA = 25 °C
VDD = VDDA = 3.3 V,
fHCLK = fHXTAL_PLL = 108 MHz
TA = 25 °C
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
PLL characteristics
Table 4-18. PLL characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
fVCO(2)
tLOCK(2)
IDDA(1)(3)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
1
—
25
MHz
PLL output clock frequency
—
16
—
108
MHz
—
32
—
—
MHz
—
—
—
400
μs
VCO freq = 216 MHz
—
906
—
μA
—
35
—
PLL VCO output clock
frequency
PLL lock time
Current consumption on
VDDA
Cycle to cycle Jitter
JitterPLL(1)(4)
（rms）
Cycle to cycle Jitter
System clock
（peak to peak）
(1)
(2)
(3)
(4)
ps
—
371
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
System clock = HXTAL = 8 MHz, fPLLOUT = 108 MHz.
Value given with main PLL running.
Table 4-19. PLL1/2 characteristics
Symbol
fPLLIN
(1)
fPLLOUT
(2)
Parameter
Conditions
Min
Typ
Max
Unit
PLL input clock frequency
—
1
—
25
MHz
PLL output clock frequency
—
16
—
108
MHz
fVCO(2)
VCO output frequency
—
32
—
216
MHz
tLOCK(2)
PLL lock time
—
—
—
400
μs
VCO freq = 216 MHz
—
145
—
μA
IDDA(1)(3)
Current consumption on
VDDA
58
GD32VF103 Datasheet
Cycle to cycle Jitter
JitterPLL(1)(4)
—
（rms）
4.10.
—
System clock
Cycle to cycle Jitter
ps
—
（peak to peak）
(1)
(2)
(3)
(4)
35
371
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
System clock = HXTAL = 8 MHz, fPLLOUT = 108 MHz.
Value given with main PLL running
Memory characteristics
Table 4-20. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1) Typ(1)
Max(2)
Unit
Number of guaranteed
PECYC
program /erase cycles
TA = -40 °C ~ +85 °C
100
—
—
kcycles
before failure (Endurance)
tRET
Data retention time
TA = 125 °C
—
20
—
years
wtPROG
Word programming time
TA = -40 °C ~ +85 °C
—
37.5
86
μs
tERASE
Page erase time
TA = -40 °C ~ +85 °C
—
45
300
ms
tMERASE(128K)
Mass erase time
TA = -40 °C ~ +85 °C
—
1
3.2
s
Min
Typ
Max
-0.5
—
0.3 VDD
0.7 VDD
—
VDD + 0.5
—
210
—
mV
—
40
—
kΩ
(1)
(2)
4.11.
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
NRST pin characteristics
Table 4-21. NRST pin characteristics
Symbol
VIL(NRST)
(1)
VIH(NRST)
Vhyst(1)
Rpu
(1)
(2)
(2)
(1)
Parameter
NRST Input low level voltage
NRST Input high level voltage
Conditions
2.6 V ≤ VDD = VDDA ≤
Schmidt trigger Voltage hysteresis
Pull-up equivalent resistor
3.6 V
—
Unit
V
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
59
GD32VF103 Datasheet
Figure 4-4. Recommended external NRST pin circuit
VDD
(1)
VDD
External reset circuit
10 kΩ
RPU
NRST
K
100 nF
GND
(1)
4.12.
Unless the voltage on NRST pin go below VIL(NRST) level, the device would not generate a reliable reset.
GPIO characteristics
Table 4-22. I/O port DC characteristics(1)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.6 V ≤ VDD = VDDA ≤ 3.6 V
—
—
0.3 VDD
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
—
—
0.3 VDD
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
0.7 VDD
—
—
V
2.6 V ≤ VDD = VDDA ≤ 3.6 V
0.7 VDD
—
—
V
Low level output voltage
VDD = 2.6 V
—
—
0.3
for each IO Pins
VDD = 3.3 V
—
—
0.3
(IIO = +8 mA)
VDD = 3.6 V
—
—
0.3
Low level output voltage
VDD = 2.6 V
—
—
1
for each IO Pins
VDD = 3.3 V
—
—
0.8
(IIO = +20 mA)
VDD = 3.6 V
—
—
0.7
High level output voltage
VDD = 2.6 V
2.3
—
—
for each IO Pins
VDD = 3.3 V
3.0
—
—
(IIO = +8 mA)
VDD = 3.6 V
3.3
—
—
High level output voltage
VDD = 2.6 V
1.5
—
—
for each IO Pins
VDD = 3.3 V
2.6
—
—
(IIO = +20 mA)
VDD = 3.6 V
2.8
—
—
Standard IO Low level input
VIL
voltage
5V-tolerant IO Low level
input voltage
Standard IO High level
VIH
input voltage
5V-tolerant IO High level
input voltage
VOL
VOL
VOH
VOH
RPU(2)
RPD(2)
Internal pull-up
All pins
VIN = VSS
—
40
—
resistor
PA10
—
—
10
—
Internal pull-
All pins
VIN = VDD
—
40
—
V
V
V
V
kΩ
kΩ
60
GD32VF103 Datasheet
down resistor
(1)
(2)
(3)
—
PA10
—
10
—
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
All pins except PC13 / PC14 / PC15. Since PC13 to PC15 are supplied through the Power Switch, which can
only be obtained by a small current, the speed of GPIOs PC13 to PC15 should not exceed 2 MHz when they
are in output mode(maximum load: 30 pF).
Table 4-23. I/O port AC characteristics(1)(2)
GPIOx_MDy[1:0] bit value(3)
GPIOx_CTL->MDy[1:0] = 10
（IO_Speed = 2 MHz）
GPIOx_CTL->MDy[1:0] = 01
（IO_Speed = 10 MHz）
GPIOx_CTL->MDy[1:0] = 11
（IO_Speed = 50 MHz）
Parameter
Conditions
Maximum frequency(4)
Maximum frequency(4)
Maximum frequency(4)
Max Unit
VDD =2.6 V, CL = 10 pF
6
VDD =2.6 V, CL = 30 pF
4
VDD =2.6 V, CL = 50 pF
2
VDD =3.3 V, CL = 10 pF
8
VDD =3.3 V, CL = 30 pF
6
VDD =3.3 V, CL = 50 pF
4
VDD =2.6 V, CL = 10 pF
16
VDD =2.6 V, CL = 30 pF
12
VDD =2.6 V, CL = 50 pF
10
VDD =3.3 V, CL = 10 pF
20
VDD =3.3 V, CL = 30 pF
16
VDD =3.3 V, CL = 50 pF
14
VDD =2.6 V, CL = 10 pF
108
VDD =2.6 V, CL = 30 pF
100
VDD =2.6 V, CL = 50 pF
72
VDD =3.3 V, CL = 10 pF
108
VDD =3.3 V, CL = 30 pF
100
VDD =3.3 V, CL = 50 pF
80
MHz
MHz
MHz
Based on characterization, not tested in production.
Unless otherwise specified, all test results given for TA = 25 ℃.
The I/O speed is configured using the GPIOx_CTL -> MDy[1:0] bits. Refer to the GD32VF103xx user manual
which is selected to set the GPIO port output speed.
(4) The maximum frequency is defined in Figure 4-5 and maximum frequency cannot exceed 108 MHz.
(1)
(2)
(3)
Figure 4-5. I/O port AC characteristics definition
90%
EXTERNAL
OUTPU T
ON 50pF
90%
50%
50%
10%
tr(IO)out
10%
tf(IO)out
T
If (tr + tf) ≤ 2/3 T, then maximum frequency is achieved .
The duty cycle is （45%-55%）when loaded by 50 pF
61
GD32VF103 Datasheet
4.13.
ADC characteristics
Table 4-24. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VIN(1)
ADC input voltage range
—
0
—
VREF+
V
fADC(1)
ADC clock
—
0.6
—
14
MHz
12-bit
0.04
—
1
10-bit
0.05
—
1.17
8-bit
0.06
—
1.4
6-bit
0.08
—
1.75
fS(1)
Sampling rate
VAIN(1)
Analog input voltage
16 external; 2 internal
0
—
VDDA
V
VREF+(2)
Positive Reference Voltage
—
2.4
—
VDDA
V
—
—
VSSA
—
V
See Equation 1
—
—
320
kΩ
—
—
—
0.55
kΩ
—
—
5.5
pF
fADC = 14 MHz
0.1
—
17.1
μs
12-bit
—
14
—
10-bit
—
12
—
8-bit
—
10
—
6-bit
—
8
—
—
—
—
1
VREF-(2)
RAIN(2)
RADC(2)
Negative Reference
Voltage
External input impedance
Input sampling switch
resistance
CADC(2)
Input sampling capacitance
ts(2)
Sampling time
No pin/pad capacitance
included
Total conversion
tCONV(2)
time(including sampling
time)
tSU(2)
(1)
(2)
MSPS
Startup time
1/ fADC
μs
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
Equation 1: RAIN max formula RAIN <
Ts
fADC *CADC *ln(2N+2 )
-RADC
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 4-25. ADC RAIN max for fADC = 14 MHz(1)
Ts(cycles)
ts(us)
RAINmax (kΩ)
1.5
0.11
1.46
7.5
0.54
9.49
13.5
0.96
17.5
28.5
2.04
37.6
41.5
2.96
55
55.5
3.96
73.7
71.5
5.11
95
62
GD32VF103 Datasheet
(1)
4.14.
Ts(cycles)
ts(us)
RAINmax (kΩ)
239.5
17.11
320
Guaranteed by design, not tested in production.
Temperature sensor characteristics
Table 4-26. Temperature sensor characteristics(1)
Symbol
Parameter
Min
Typ
Max
Unit
TL
VSENSE linearity with temperature
—
±1.5
—
°C
Avg_Slope
Average slope
—
4.1
—
mV/°C
V25
Voltage at 25 °C
—
1.45
—
V
ADC sampling time when reading the temperature
—
17.1
—
μs
tS_temp
(1)
(2)
4.15.
(2)
Based on characterization, not tested in production.
Shortest sampling time can be determined in the application by multiple iterations.
DAC characteristics
Table 4-27. DAC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA(1)
Operating voltage
—
2.6
3.3
3.6
V
VREF+(2)
Positive Reference Voltage
—
2.4
—
VDDA
V
—
—
VSSA
—
V
5
—
—
kΩ
—
—
15
kΩ
—
—
50
pF
—
0.2
—
—
V
—
—
—
—
—
0.5
—
—
—
—
470
—
μA
—
570
—
μA
VREF-(2)
RLOAD(2)
Ro(2)
CLOAD(2)
Negative Reference
Voltage
Load resistance
Impedance output with
buffer OFF
Load capacitance
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer ON
DAC_OUT Higher DAC_OUT voltage
(2)
max
with buffer ON
DAC_OUT Lower DAC_OUT voltage
min(2)
with buffer OFF
DAC_OUT Higher DAC_OUT voltage
max(2)
with buffer OFF
Resistive load with
buffer ON
—
No pin/pad capacitance
included
VDDA0.2
—
VDDA1LSB
V
mV
V
With no load, middle
IDDA(1)
DAC current consumption
in quiescent mode
code(0x800) on the input,
VREF+ = 3.6 V
With no load, worst
code(0xF1C) on the input,
63
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
90
—
μA
—
298
—
μA
DAC in 12-bit mode
—
—
±3
LSB
VREF+ = 3.6 V
With no load, middle
code(0x800) on the input,
IDDVREF+(1)
DAC current consumption
VREF+ = 3.6 V
in quiescent mode
With no load, worst
code(0xF1C) on the input,
VREF+ = 3.6 V
DNL(1)
error
INL(1)
Integral non-linearity
DAC in 12-bit mode
—
—
±4
LSB
Offset(1)
Offset error
DAC in 12-bit mode
—
—
±12
LSB
GE(1)
Gain error
DAC in 12-bit mode
—
—
±0.5
%
Tsetting(1)
Settling time
—
0.3
1
μs
Twakeup(2)
Wakeup from off state
—
5
10
μs
—
—
4
MS/s
55
80
—
dB
Update
rate(2)
PSRR(2)
(1)
(2)
4.16.
Differential non-linearity
CLOAD ≤ 50 pF, RLOAD ≥ 5
kΩ
—
Max frequency for a correct
DAC_OUT change from
CLOAD ≤ 50 pF, RLOAD ≥ 5
kΩ
code i to i ± 1 LSBs
Power supply rejection
—
ratio (to VDDA)
Based on characterization, not tested in production.
Guaranteed by design, not tested in production.
I2C characteristics
Table 4-28. I2C characteristics(1)(2)
Standard
Symbol
tSCL(H)
Parameter
SCL clock high
time
tSCL(L)
SCL clock low time
tsu(SDA)
SDA setup time
th(SDA)
SDA data hold time
tr(SDA/SCL)
tf(SDA/SCL)
th(STA)
SDA and SCL rise
time
SDA and SCL fall
time
Start condition hold
mode
Conditions
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
—
4.0
—
0.6
—
0.2
—
μs
—
4.7
—
1.3
—
0.5
—
μs
250
—
100
—
50
—
ns
0(3)
3450
0
900
0
450
ns
—
—
1000
—
300
—
120
ns
—
—
300
—
300
—
120
ns
—
4.0
—
0.6
—
0.26
—
μs
—
—
64
GD32VF103 Datasheet
Standard
Symbol
Parameter
Conditions
mode
Fast mode
Fast mode
plus
Unit
Min
Max
Min
Max
Min
Max
—
4.7
—
0.6
—
0.26
—
μs
—
4.0
—
0.6
—
0.26
—
μs
—
4.7
—
1.3
—
0.5
—
μs
time
Repeated Start
ts(STA)
condition
setup time
Stop condition
ts(STO)
setup time
Stop to Start
tbuff
condition time (bus
free)
(1)
(2)
(3)
Guaranteed by design, not tested in production.
To ensure the standard mode I2C frequency, f PCLK1 must be at least 2 MHz. To ensure the fast mode I2C
frequency, fPCLK1 must be at least 4 MHz. To ensure the fast mode plus I2C frequency, fPCLK1 must be at least a
multiple of 10 MHz.
The device should provide a data hold time of 300 ns at least in order to bridge the undefined region of the
falling edge of SCL.
Figure 4-6. I2C bus timing diagram
tsu(STA)
SDA
70%
30%
tf(SDA)
tr(SDA)
tSCL(H)
th(STA)
SCL
tbuff
th(SDA)
tsu(SDA)
70%
30%
tSCL(L)
4.17.
tr(SCL)
tf(SCL)
tsu(STO)
SPI characteristics
Table 4-29. Standard SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
—
—
—
27
MHz
tSCK(H)
SCK clock high time
35
37
39
ns
tSCK(L)
SCK clock low time
35
37
39
ns
Master mode, fPCLKx = 108 MHz,
presc = 8
Master mode, fPCLKx = 108 MHz,
presc = 8
SPI master mode
tV(MO)
Data output valid time
—
—
7
—
ns
tH(MO)
Data output hold time
—
—
4
—
ns
65
GD32VF103 Datasheet
tSU(MI)
Data input setup time
—
1
—
—
ns
tH(MI)
Data input hold time
—
0
—
—
ns
SPI slave mode
(1)
tSU(NSS)
NSS enable setup time
fPCLK = 54 MHz
0
—
—
ns
tH(NSS)
NSS enable hold time
fPCLK = 54 MHz
1
—
—
ns
tA(SO)
Data output access time
—
—
9
—
ns
tDIS(SO)
Data output disable time
—
—
8
—
ns
tV(SO)
Data output valid time
—
—
10
—
ns
tH(SO)
Data output hold time
—
—
10
—
ns
tSU(SI)
Data input setup time
—
0
—
—
ns
tH(SI)
Data input hold time
—
1
—
—
ns
Based on characterization, not tested in production.
Figure 4-7. SPI timing diagram - master mode
tSCK
SCK (CKPH=0 CKPL=0)
SCK (CKPH=0 CKPL=1)
SCK (CKPH=1 CKPL=0)
tSCK(H)
tSCK(L)
SCK (CKPH=1 CKPL=1)
tSU(MI)
MISO
D[0]
LF=1,FF16=0
D[7]
tH(MI)
MOSI
D[0]
D[7]
tV(MO)
tH(MO)
66
GD32VF103 Datasheet
Figure 4-8. SPI timing diagram - slave mode
NSS
tSCK
tSU(NSS)
SCK (CKPH=0 CKPL=0)
tSCK(H)
SCK (CKPH=0 CKPL=1)
tSCK(L)
tH(NSS)
tH(SO)
tDIS(SO)
tV(SO)
tA(SO)
MISO
D[0]
D[7]
tSU(SI)
D[0]
MOSI
D[7]
tH(SI)
4.18.
I2S characteristics
Table 4-30. I2S characteristics(1)(2)
Symbol
Parameter
Conditions
Master mode (data: 16 bits,
fCK
Clock frequency
Audio frequency = 96 kHz)
Slave mode
Min
3.070
Typ
Max
3.072 3.074
Unit
MHz
—
10
—
—
162
—
ns
—
163
—
ns
tH
Clock high time
tL
Clock low time
tV(WS)
WS valid time
Master mode
—
2
—
ns
tH(WS)
WS hold time
Master mode
—
2
—
ns
tSU(WS)
WS setup time
Slave mode
0
—
—
ns
tH(WS)
WS hold time
Slave mode
1
—
—
ns
Slave mode
—
50
—
%
Ducy(SCK)
I2S slave input clock duty
cycle
—
tSU(SD_MR)
Data input setup time
Master mode
3
—
—
ns
tsu(SD_SR)
Data input setup time
Slave mode
0
—
—
ns
Master receiver
0
—
—
ns
Slave receiver
1
—
—
ns
—
12
—
ns
—
10
—
ns
tH(SD_MR)
tH(SD_SR)
Data input hold time
tV(SD_ST)
Data output valid time
tH(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
Slave transmitter
67
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
—
10
—
ns
—
7
—
ns
(after enable edge)
tV(SD_MT)
Data output valid time
tH(SD_MT)
Data output hold time
(1)
(2)
Master transmitter
(after enable edge)
Master transmitter
(after enable edge)
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Figure 4-9. I2S timing diagram - master mode
tCK
CPOL=0
tL
CPOL=1
tV(WS)
tH
tH(WS)
WS output
tV(SD_MT)
SD transmit
SD receive
tH(SD_MT)
D[0]
D[0]
tSU(SD_MR)
tH(SD_MR)
68
GD32VF103 Datasheet
Figure 4-10. I2S timing diagram - slave mode
tCK
CPOL=0
tL
CPOL=1
tH
tH(WS)
WS input
tSU(WS)
tH(SD_ST)
tV(SD_ST)
SD transmit
D[0]
SD receive
D[0]
tSU(SD_SR)
tH(SD_SR)
4.19.
USART characteristics
Table 4-31. USART0 characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 108 MHz
—
—
54
MHz
tSCK(H)
SCK clock high time
fPCLKx = 108 MHz
4.63
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 108 MHz
4.63
—
—
ns
(1)
Guaranteed by design, not tested in production.
Table 4-32. USART1-2/UART3-4 characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
SCK clock frequency
fPCLKx = 108 MHz
—
—
54
MHz
tSCK(H)
SCK clock high time
fPCLKx = 108 MHz
9.26
—
—
ns
tSCK(L)
SCK clock low time
fPCLKx = 108 MHz
9.26
—
—
ns
(1)
4.20.
Guaranteed by design, not tested in production.
CAN characteristics
Refer to Table 4-22. I/O port DC characteristics(1) for more details on the input/output
alternate function characteristics (CANTX and CANRX).
69
GD32VF103 Datasheet
4.21.
USBFS characteristics
Table 4-33. USBFS start up time
Symbol
Parameter
Max
Unit
tSTARTUP(1)
USBFS startup time
1
μs
(1)
Guaranteed by design, not tested in production.
Table 4-34. USBFS DC electrical characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
USBFS operating voltage
—
3
—
3.6
V
VDI
Differential input sensitivity
I(USBDP, USBDM)
0.2
—
—
VCM Differential common mode range
Includes VDI range
0.8
—
2.5
VSE Single ended receiver threshold
—
1.3
—
2.0
Input
levels(1)
Output
VOL
Static output level low
RL of 1.55 kΩ to 3.3 V
—
0.04
0.3
levels(2)
VOH
Static output level high
RL of 21 kΩ to VSS
2.8
3.3
3.6
(1)
(2)
V
V
Guaranteed by design, not tested in production.
Based on characterization, not tested in production.
Table 4-35. USBFS electrical characteristics(1)
(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tR
Rise time
CL = 50 pF
4
—
20
ns
tF
Fall time
CL = 50 pF
4
—
20
ns
tRFM
Rise / fall time matching
tR / tF
90
—
110
%
vCRS
Output signal crossover voltage
—
1.3
—
2.0
V
Guaranteed by design, not tested in production.
Figure 4-11. USBFS timings: definition of data signal rise and fall time
Crossover
points
Differential
data lines
VCRS
VSS
tf
4.22.
tr
EXMC characteristics
Table 4-36. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
64.1
66.1
ns
tV(NOE_NE)
EXMC_NEx low to EXMC_NOE low
26.9
—
ns
tw(NOE)
EXMC_NOE low time
36.2
38.2
ns
th(NE_NOE)
EXMC_NOE high to EXMC_NE high hold time
0
—
ns
70
GD32VF103 Datasheet
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tv(A_NOE)
Address hold time after EXMC_NOE high
0
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
th(BL_NOE)
EXMC_BL hold time after EXMC_NOE high
0
—
ns
tsu(DATA_NE)
Data to EXMC_NEx high setup time
37.2
—
ns
tsu(DATA_NOE)
Data to EXMC_NOEx high setup time
37.2
—
ns
th(DATA_NOE)
Data hold time after EXMC_NOE high
0
—
ns
th(DATA_NE)
Data hold time after EXMC_NEx high
0
—
ns
tv(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
8.3
10.3
ns
8.3
10.3
ns
Th(AD_NADV)
(1)
(2)
(3)
EXMC_AD(address) valid hold time after
EXMC_NADV high
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 108 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
Table 4-37. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)(3)
Symbol
Parameter
Min
Max
Unit
tw(NE)
EXMC_NE low time
45.5
47.5
ns
tV(NWE_NE)
EXMC_NEx low to EXMC_NWE low
8.3
—
ns
tw(NWE)
EXMC_NWE low time
26.9
28.9
ns
th(NE_NWE)
EXMC_NWE high to EXMC_NE high hold time
8.3
—
ns
tv(A_NE)
EXMC_NEx low to EXMC_A valid
0
—
ns
tV(NADV_NE)
EXMC_NEx low to EXMC_NADV low
0
—
ns
tw(NADV)
EXMC_NADV low time
8.3
10.3
ns
8.3
—
ns
th(AD_NADV)
EXMC_NADV high
th(A_NWE)
Address hold time after EXMC_NWE high
8.3
—
ns
th(BL_NWE)
EXMC_BL hold time after EXMC_NWE high
8.3
—
ns
tv(BL_NE)
EXMC_NEx low to EXMC_BL valid
0
—
ns
tv(DATA_NADV)
EXMC_NADV high to DATA valid
8.3
—
ns
th(DATA_NWE)
Data hold time after EXMC_NWE high
8.3
—
ns
(1)
(2)
(3)
4.23.
EXMC_AD(address) valid hold time after
CL = 30 pF.
Guaranteed by design, not tested in production.
Based on configure: fHCLK = 108 MHz, AddressSetupTime = 0, AddressHoldTime = 1, DataSetupTime = 1.
TIMER characteristics
Table 4-38. TIMER characteristics(1)
Symbol
Parameter
tres
Timer resolution time
fEXT
Timer external clock
Conditions
Min
Max
Unit
—
1
—
tTIMERxCLK
fTIMERxCLK = 108 MHz
9.26
—
ns
—
0
fTIMERxCLK / 2
MHz
71
GD32VF103 Datasheet
Symbol
Parameter
Conditions
Min
Max
Unit
frequency
fTIMERxCLK = 108 MHz
0
54
MHz
Timer resolution
—
—
16
bit
16-bit counter clock period
—
1
65536
tTIMERxCLK
607
μs
RES
tCOUNTER
when internal clock is
selected
tMAX_COUNT
(1)
4.24.
Maximum possible count
fTIMERxCLK = 108 MHz 0.0093
—
—
fTIMERxCLK = 108 MHz
—
65536x65536 tTIMERxCLK
39.8
s
Guaranteed by design, not tested in production.
WDGT characteristics
Table 4-39. FWDGT min/max timeout period at 40 kHz (IRC40K)(1)
Prescaler divider
PR[2:0] bits
1/4
(1)
Min timeout RLD[11:0] = Max timeout RLD[11:0]
0x000
= 0xFFF
000
0.025
409.525
1/8
001
0.025
819.025
1/16
010
0.025
1638.025
1/32
011
0.025
3276.025
1/64
100
0.025
6552.025
1/128
101
0.025
13104.025
1/256
110 or 111
0.025
26208.025
Unit
ms
Guaranteed by design, not tested in production.
Table 4-40. WWDGT min/max timeout value at 54 MHz (fPCLK1)(1)
PSC[1:0]
1/1
00
75.8
1/2
01
151.7
1/4
10
303.4
1/8
11
606.8
(1)
4.25.
Min timeout value
Prescaler divider
CNT[6:0] = 0x40
Unit
Max timeout value
CNT[6:0] = 0x7F
Unit
4.85
μs
9.7
19.4
ms
38.8
Guaranteed by design, not tested in production.
Parameter conditions
Unless otherwise specified, all values given for VDD = VDDA = 3.3 V, TA = 25 °C.
72
GD32VF103 Datasheet
5.
Package information
5.1.
LQFP100 package outline dimensions
Figure 5-1. LQFP100 package outline
A3
A2 A
c
θ
A1
F
eB
D
D1
51
75
0.25
50
76
L
L1
DETAIL: F
E1
E
b
b1
100
c1 c
26
BASE METAL
1
25
b
e
WITH PLATING
B B
SECTION B-B
Table 5-1. LQFP100 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
15.80
16.00
16.20
D1
13.90
14.00
14.10
E
15.80
16.00
16.20
E1
13.90
14.00
14.10
e
—
0.50
—
eB
15.05
—
15.35
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
73
GD32VF103 Datasheet
(Original dimensions are in millimeters)
Figure 5-2. LQFP100 recommended footprint
16.70
76
100
14.30
75
25
51
50
26
12.30
16.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
74
GD32VF103 Datasheet
5.2.
LQFP64 package outline dimensions
Figure 5-3. LQFP64 package outline
A3
A2 A
θ
c
A1
F
eB
D
D1
33
48
0.25
32
49
L
L1
DETAIL: F
E1
E
b
b1
c1 c
BASE METAL
64
17
WITH PLATING
1
e
b
SECTION B-B
16
B B
Table 5-2. LQFP64 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
11.80
12.00
12.20
D1
9.90
10.00
10.10
E
11.80
12.00
12.20
E1
9.90
10.00
10.10
e
—
0.50
—
eB
11.25
—
11.45
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
75
GD32VF103 Datasheet
Figure 5-4. LQFP64 recommended footprint
12.70
64
49
10.30
48
16
33
17
32
7.80
12.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
76
GD32VF103 Datasheet
LQFP48 package outline dimensions
Figure 5-5. LQFP48 package outline
A3
A2 A
θ
A1
c
5.3.
F
eB
D
D1
36
0.25
25
L
24
37
L1
DETAIL: F
E1 E
b
b1
13
48
c1c
BASE METAL
WITH PLATING
1
12
b
e
SECTION B-B
BB
Table 5-3. LQFP48 package dimensions
Symbol
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
A3
0.59
0.64
0.69
b
0.18
—
0.26
b1
0.17
0.20
0.23
c
0.13
—
0.17
c1
0.12
0.13
0.14
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
e
—
0.50
—
eB
8.10
—
8.25
L
0.45
—
0.75
L1
—
1.00
—
θ
0°
—
7°
(Original dimensions are in millimeters)
77
GD32VF103 Datasheet
Figure 5-6. LQFP48 recommended footprint
9.70
37
48
7.30
36
12
25
24
13
5.80
9.70
0.30
1
1.20
0.50
(Original dimensions are in millimeters)
78
GD32VF103 Datasheet
QFN36 package outline dimensions
Figure 5-7. QFN36 package outline
Nd
D2
D
36
36
1
1
h
PIN 1#
Laser Mark
2
e
b1
b
L1
L
E2
Ne
h
E
2
EXPOSED THERMAL
PAD ZONE
TOP VIEW
BOTTOM VIEW
A1
A
c
5.4.
SIDE VIEW
Table 5-4. QFN36 package dimensions
Symbol
Min
Typ
Max
A
0.80
0.85
0.90
A1
0
0.02
0.05
b
0.18
0.23
0.30
b1
—
0.16
—
c
0.18
0.20
0.23
D
5.90
6.00
6.10
D2
3.80
3.90
4.00
E
5.90
6.00
6.10
E2
3.80
3.90
4.00
e
—
0.50
—
h
0.30
0.35
0.40
L
0.50
0.55
0.60
L1
—
0.10
—
Nd
3.95
4.00
4.05
Ne
3.95
4.00
4.05
(Original dimensions are in millimeters)
79
GD32VF103 Datasheet
Figure 5-8. QFN36 recommended footprint
6.70
36
28
4.80
27
4.28
6.70
3.85
0.28
1
3.85
19
10
18
9
0.95
0.50
(Original dimensions are in millimeters)
80
GD32VF103 Datasheet
5.5.
Thermal characteristics
Thermal resistance is used to characterize the thermal performance of the package device,
which is represented by the Greek letter “θ”. For semiconductor devices, thermal resistance
represents the steady-state temperature rise of the chip junction due to the heat dissipated
on the chip surface.
θJA: Thermal resistance, junction-to-ambient.
θJB: Thermal resistance, junction-to-board.
θJC: Thermal resistance, junction-to-case.
ᴪJB: Thermal characterization parameter, junction-to-board.
ᴪJT: Thermal characterization parameter, junction-to-top center.
θJA =(TJ -TA )/PD
(5-1)
θJB =(TJ -TB )/PD
(5-2)
θJC =(TJ -TC )/PD
(5-3)
Where, TJ = Junction temperature.
TA = Ambient temperature
TB = Board temperature
TC = Case temperature which is monitoring on package surface
PD = Total power dissipation
θJA represents the resistance of the heat flows from the heating junction to ambient air. It is
an indicator of package heat dissipation capability. Lower θJA can be considerate as better
overall thermal performance. θJA is generally used to estimate junction temperature.
θJB is used to measure the heat flow resistance between the chip surface and the PCB board.
θJC represents the thermal resistance between the chip surface and the package top case.
θJC is mainly used to estimate the heat dissipation of the system (using heat sink or other heat
dissipation methods outside the device package).
Table 5-5. Package thermal characteristics(1)
Symbol
θJA
θJB
Condition
Natural convection, 2S2P PCB
Cold plate, 2S2P PCB
Package
Value
LQFP100
57.42
LQFP64
61.80
LQFP48
64.40
QFN36
43.20
LQFP100
31.68
LQFP64
42.83
Unit
°C/W
°C/W
81
GD32VF103 Datasheet
Symbol
θJC
ᴪJB
ᴪJT
(1)
Condition
Cold plate, 2S2P PCB
Natural convection, 2S2P PCB
Natural convection, 2S2P PCB
Package
Value
LQFP48
42.32
QFN36
16.51
LQFP100
13.85
LQFP64
21.98
LQFP48
22.47
QFN36
16.18
LQFP100
41.28
LQFP64
43.05
LQFP48
42.42
QFN36
16.64
LQFP100
0.75
LQFP64
1.58
LQFP48
1.74
QFN36
1.07
Unit
°C/W
°C/W
°C/W
Thermal characteristics are based on simulation, and meet JEDEC specification.
82
GD32VF103 Datasheet
6.
Ordering information
Table 6-1. Part ordering code for GD32VF103xx devices
Ordering code
Flash (KB)
Package
Package type
GD32VF103VBT6
128
LQFP100
Green
GD32VF103V8T6
64
LQFP100
Green
GD32VF103RBT6
128
LQFP64
Green
GD32VF103R8T6
64
LQFP64
Green
GD32VF103R6T6
32
LQFP64
Green
GD32VF103R4T6
16
LQFP64
Green
GD32VF103CBT6
128
LQFP48
Green
GD32VF103C8T6
64
LQFP48
Green
GD32VF103C6T6
32
LQFP48
Green
GD32VF103C4T6
16
LQFP48
Green
GD32VF103TBU6
128
QFN36
Green
GD32VF103T8U6
64
QFN36
Green
GD32VF103T6U6
32
QFN36
Green
GD32VF103T4U6
16
QFN36
Green
Temperature
operating range
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
Industrial
-40 °C to +85 °C
83
GD32VF103 Datasheet
7.
Revision History
Table 7-1. Revision history
Revision No.
Description
Date
1.0
Initial Release
Jun.5, 2019
1.
1.1
Clock tree modification, the factor for CK_CST changes
from 8 to 4, refers to Clock tree.
2.
Add I2C fast mode plus related information, refers to I2C
Sep.16,2019
characteristics.
1.
Chapter Electrical characteristics electrical
characteristics update.
1.2
2.
Chapter Package information package information
update.
3.
Feb.15,2020
Delete the PD0,PD1 remap to OSC pins information in
packages no less than100 pins, refers to Pin definitions.
1.
Chapter PLL characteristics modification.
2.
Add description of VREF+ and VREF- connection in chapter
Analog to digital converter (ADC).
1.3
3.
Modify the LDO mode conditions in Power consumption.
4.
Delete EXMC characteristics comments in chapter EXMC
Dec.15,2020
characteristics.
5.
TSTG range changes to -65°C~+150°C in Absolute
maximum ratings.
1.
1.4
Add I2C, SPI, I2S timing diagrams, refers to I2C
characteristics, SPI characteristics and I2S
Mar.29,2021
characteristics.
1.
Update SPI and I2S timing diagrams, refers to SPI
characteristics and I2S characteristics.
2.
1.5
Update package information and ordering information,
refers to Package information and Ordering
Dec.14, 2021
information.
3.
Modify WDGT characteristics, refers to WDGT
characteristics.
1.
Add PD parameter in Table 4-1. Absolute maximum
ratings(1)(4) .
2.
1.6
Modify I2C timing diagrams, refers to I2C
characteristics.
3.
Modify LQFP64 package information, refer to LQFP64
Jun.7, 2022
package outline dimensions.
4.
Update NRST external pin circuit, refer to Figure 4-4.
Recommended external NRST pin circuit(1)
84
GD32VF103 Datasheet
5.
EXMC related pin update, refer to Pin definitions.
85
GD32VF103 Datasheet
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