AW87318
May 2017 V1.1
High efficiency、Low noise、Constant large volume、Multi-level AGC
Eighth generation Class K Audio Amplifier
FEATURES
DESCRIPTION
Multi-Level AGC audio algorithm ， effectively
eliminate noise, make sound pure natural
Low noise：43μV
Ultra-low distortion：0.008%
Power amplifier overall efficiency is up to 83%
Speaker and Receiver two-in-one application
AW87318 is specifically designed to eliminate smart
mobile phone music noise, to enhance overall sound
quality, which is a new high efficiency, low noise,
ultra-low distortion, constant large volume, upgrading
eighth generation class K audio amplifiers. AW87318
integrated Awinic proprietary multi-level AGC audio
algorithm, effectively eliminate music noise, improve
sound quality and volume. Using a new generation
K-Chargepump technology, efficiency reaches 93%,
power amplifier’s overall efficiency reaches 83%,
greatly prolong the mobile phone usage time. AW87318
noise floor is as low as to 43uV, with 98.8dB high
signal-to-noise-ratio(SNR). The ultra-low distortion
0.008% and unique multi-level AGC technology brings
high quality music enjoyment.
AW87318 has 0.6W,0.7W,0.8W,0.9W,1W,1.1W and
1.2W seven subdivision selectable speaker-guard
output power levels, which is suitable for different rated
power speakers. With multi-level AGC audio algorithms,
the music is pure natural and melodious. Within lithium
battery voltage range (3.3V--4.35V), output power is
constant, preventing voice becomes smaller and
smaller during usage of cell phone.
AW87318 supports speaker and receiver two-in-one
application. In receiver mode, the output noise is as low
as to 19uV, amplifier is in class D mode, powered by
VBAT.
AW87318 has built-in over current protection,
over-temperature protection and short circuit protection
function, effectively protect the chip. AW87318 uses
small 0.4mm pitch 1.6mmx1.68mm CSP-14 package.
Receiver：1V/V，Vn=19uV，THD+N=0.025%
Receiver：3V/V，Vn=22uV，THD+N=0.025%
Selectable speaker-guard power level ： 0.6W,
0.7W, 0.8W, 0.9W, 1W, 1.1W, 1.2W
Within Lithium battery voltage range, maintained
constant large volume
Support 6ohm speaker
Compatible with AW8736，AW8737
Super TDD-Noise suppression
Excellent pop-click suppression
One wire pulse control
High PSRR：-68dB（217Hz）
ESD protection：±6kV (HBM)
Small 0.4mm pitch 1.6mm×1.68mm CSP-14package
APPLICATIONS
Smart phone
APPLICATION DIAGRAM
VBAT
CS1
4.7uF
CF1
2.2uF
CS2
0.1uF
A3,B3
VDD
A4
Pulse Input
1
3
5
4
Single-End
Input
Speake r
Audio
DAC
2
10
33nF
3KΩ
Cin
Rin
A2
MUX
Receiver
Cin
33nF
Rin
C1
C1P C1N
D1
C2P
SHDN
PVDD
AW87318
A1
B1
C2N
D3
COUT
4.7uF
10V
INN
Cd
220pF
BB
D2
CF2
2.2uF
VOP
SPK/
REC
B4
B1
INP
3KΩ
VON
C2
1nF
D4
B2
C3
1nF
GND
C2,C4
Figure1
AW87318 application diagram
All trademarks are the property of their respective owners.
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1
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
PIN CONFIGURATION AND TOP MARK
AW87318CSR TOP VIEW
VON
D
GND
C
VDD
VOP
B
INN
VDD
SHDN
A
2
3
D
C2P
C1P
C
C1N
GND
B
C2N
A
INP
1
AW87318CSR MARKING
PVDD
2
1
4
3
4
K318–AW87318CSR
XXXX–Production tracking code
Please notice the pin number
Figure 2
K318
XXXX
AW87318 pin diagram top view and device marking
PIN DESCRIPTION
Number
Symbol
Description
A1
A2
A3
A4
B1
B3
B4
C1
C2，C4
D1
D2
D3
D4
INP
INN
VDD
SHDN
C2N
VDD
VOP
C1N
GND
C2P
C1P
PVDD
VON
Positive audio input terminal
Negative audio input terminal
Power supply
Chip power down pin，active low；one wire pulse control；
Negative side of the external charge pump flying capacitor C2
Power supply
Positive audio output terminal
Negative side of the external charge pump flying capacitor C1
Ground
Positive side of the external charge pump flying capacitor C2
Positive side of the external charge pump flying capacitor C1
Boost charge pump output voltage
Negative audio output terminal
AWINIC CLASS K FAMILY
ITEM
TEST CONDITION
AW8736
AW8737
AW87317
AW8738
AW87318
PVDD(V)
VDD=4.2V
5.8
6.05
6.05
6.05
6.05
Ouput
noise(μV)
VDD=4.2V，f=20Hz to 20kHz，input ac
grounded，8V/V,A-weighting
125
52
53
40
43
VDD=3.6V，Po=1.0W，RL=8Ω+33μH
75
80
80
83
83
Efficiency(%)
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
FUNCTIONAL DIAGRAM
C1P
VDD
C1N
C2P
C2N
SHDN
OVP
SHDN&BIAS
PVDD
K-Chargepump
Current
Limit
SEGMENTED
OTP
OSC
Multi-level
AGC
VOP
INP
INPUT
BUFFER
Ultra Low
EMI
output
stage
Class-K
Modulator
INN
VON
OCP
NCN
Noise
Cancellor
AW87318
GND
Figure 3
AW87318 functional diagram
APPLICATION DIAGRAM
VBAT
CS1
4.7uF
CF1
2.2uF
CS2
0.1uF
A3,B3
VDD
A4
Pulse Input
1
Receiver
3
Single-End
Input
Speake r
Audio
DAC
2
5
4
10
33nF
3KΩ
Cin
Rin
A2
MUX
BB
33nF
Rin
C1
C1P C1N
D1
C2P
SHDN
PVDD
AW87318
A1
B1
C2N
D3
COUT
4.7uF
10V
INN
Cd
220pF
Cin
D2
CF2
2.2uF
VOP
SPK/
REC
B4
B1
INP
3KΩ
VON
C2
1nF
D4
B2
C3
1nF
GND
C2,C4
Figure 4
AW87318 speaker mode application diagram (Note 1)
Note1：when single-ended input，input audio signal can arbitrarily connect to one of INN，INP input terminal，the other
terminal connects to ground through input capacitor and resistance.
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
VBAT
CS1
4.7uF
A3,B3
VDD
A4
Pulse Input
1
5
4
Single-End
Input
Speake r
Audio
DAC
3
2
10
33nF
3KΩ
Cin
Rin
A2
MUX
Receiver
Cin
Rin
33nF
3KΩ
D2
D1
C1
C2P
C1P C1N
SHDN
PVDD
AW87318
A1
B1
C2N
D3
COUT
4.7uF
10V
INN
Cd
220pF
BB
CF2
2.2uF
CF1
2.2uF
CS2
0.1uF
VOP
SPK/
REC
B4
B1
INP
VON
C2
1nF
D4
B2
C3
1nF
GND
C2,C4
Figure 5
AW87318 receiver mode application diagram
ORDERING INFORMATION
Product Type
Operation
temperature range
Package
Device
Marking
Moisture
Sensitivity
Level
Environmental
Information
Delivery
Form
AW87318CSR
-40℃～85℃
CSP-14
K318
MSL1
ROHS+HF
Tape and
Reel
3000 pcs
AW87318
Shipment
R: Tape & Reel
Package type
CS: CSP14
ABSOLUTE MAXIMUM RATING(Note2)
Parameter
Range
Supply Voltage VDD
-0.3V to 6V
Chargepump output voltage PVDD
-0.3V to 7V
VOP,VON
-0.3V to PVDD+0.3V
C1P ,C2P
-0.3V to PVDD+0.3V
C1N,C2N
-0.3V to VDD+0.3V
INP，INN Input Pin Voltage
-0.3V to VDD +0.3V
Package Thermal Resistance θJA
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84.9℃/W
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
-40℃ to 85℃
Ambient Temperature Range
165℃
Maximum Junction Temperature TJMAX
-65℃ to 150℃
Storage Temperature Range TSTG
260℃
Lead Temperature（Soldering 10 Seconds）
ESD Rating
（Note
3）
HBM（human body model）
±6KV
CDM
±1.5KV
MM
±250V
Latch-up
Test Condition：JEDEC STANDARD NO.78D NOVEMBER 2011
+IT：450mA
-IT：-450mA
Note 2：Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
Note 3：The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin. Test method:
MIL-STD-883H Method 3015.8
MODE DESCRIPTION(TA=25℃,VDD=4.2V)
AW87318 audio amplifier outer input capacitor is Cin，outer input resist is Rin，inner input resist is 6.6KΩ，
gain Av is 159.5K/(Rin+6.6K). Recommended typical application is：
1、 Cin=33nF，Rin=3KΩ，Av=16.6V/V；
MODE
Enable
Signal
Gain
（V/V）
AGC Power（W）
RL=8Ω
+33μH
RL=6Ω
+33μH
RL=4Ω
+15μH
RL=3Ω
+15μH
MODE1
16.6
1.2
1.6
—
—
MODE2
16.6
1.1
1.5
—
—
MODE3
16.6
1.0
1.3
2.0
—
MODE4
16.6
0.9
1.2
1.8
—
MODE5
16.6
0.8
1.0
1.6
2.0
MODE6
16.6
0.7
0.9
1.4
1.8
MODE7
16.6
0.6
0.8
1.2
1.6
MODE8
1
MODE9
3
MODE10
16.6
1.75W@
THD=1%
2.05W@
THD=1%
2.4W@
THD=1%
2.35W@
THD=1%
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Multi-Level
AGC
Function
Receiver
Mode
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
ELECTRICAL CHARACTERISTICS
Test condition：TA=25℃, VDD=3.6V，RL=8Ω+33μH，f=1kHz（unless otherwise noted）
Parameter
Test conditions
Min
Typ
Max
Units
VDD
Power supply voltage
3.0
5.5
V
VIH
SHDN high input voltage
1.3
VDD
V
VIL
SHDN low input voltage
0
0.35
V
30
mV
1
μA
|VOS|
Output offset voltage
Vin=0V，VDD=3.0V to 5.5V
-30
ISD
Shutdown current
VDD=3.6V， SHDN =0V
TTG
Thermal AGC start temperature
threshold
150
℃
TTGR
Thermal AGC exit temperature
threshold
130
℃
TSD
Over temperature protection
threshold
160
℃
TSDR
Over temperature
recovery threshold
120
℃
TON
Start-up time
40
ms
protection
0
K-Chargepump
1.5*
VDD =3.0V to 4V
PVDD
V
VDD
Output voltage
VDD >4V
6.05
V
OVP hysteresis
VDD >4V
50
mV
FCP
Charge Pump frequency
VDD=3.0V to 5.5V
ηCP
Charge pump efficiency
VDD=3.6V，Iload=200mA
TST
Soft-start time
No load，COUT=4.7μF
Vhys
IL
0.8
1.06
1.33
93
MHz
%
1
1.2
1.4
ms
200
300
400
mA
VDD=4.2V，Vin=0，no load
10
15
mA
VDD=3.6V，Po=1.0W，RL=8Ω+33μH
83
%
VDD=3.6V，Po=1.0W，RL=6Ω+33μH
83
%
Current limit when PVDD short
to ground
Class K power amplifier（mode1-mode7，mode10）
Iq
Quiescent current
η
Efficiency
Fosc
Modulation frequency
VDD=3.0V to 5.5V
Av
gain
external input resistance=3kΩ
600
800
1000
Vin
Recommend input voltage
VDD=3.0V to 5.5V
Rini
Inner input resistance
mode1~mode7，mode10
6.6
kΩ
Fhin
Input high pass filter corner
frequency
Cin=33nF，external input resistance=3kΩ
502
Hz
16.6
kHz
V/V
1
Vp
VDD=4.2V，RL=8Ω+33μH
1.08
1.2
1.32
W
VDD=4.2V，RL=6Ω+33μH
1.44
1.6
1.76
W
VDD=4.2V，RL=4Ω+15μH
2.16
2.4
2.64
W
VDD=4.2V，RL=3Ω+15μH
2.16
2.4
2.64
W
Mode2 Multi-Level AGC power
VDD=4.2V，RL=8Ω+33μH
0.99
1.1
1.21
W
Mode2 Multi-Level AGC power
VDD=4.2V，RL=6Ω+33μH
1.35
1.5
1.65
W
Mode1 Multi-Level AGC power
Pagc
Pagc
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
Parameter
Test conditions
Min
Typ
Max
Units
VDD=4.2V，RL=4Ω+15μH
1.98
2.2
2.42
W
VDD=4.2V，RL=3Ω+15μH
2.16
2.4
2.64
W
VDD=4.2V，RL=8Ω+33μH
0.9
1
1.1
W
VDD=4.2V，RL=6Ω+33μH
1.17
1.3
1.43
W
VDD=4.2V，RL=4Ω+15μH
1.8
2
2.2
W
VDD=4.2V，RL=3Ω+15μH
2.16
2.4
2.64
W
VDD=4.2V，RL=8Ω+33μH
0.81
0.9
0.99
W
VDD=4.2V，RL=6Ω+33μH
1.08
1.2
1.32
W
VDD=4.2V，RL=4Ω+15μH
1.62
1.8
1.98
W
VDD=4.2V，RL=3Ω+15μH
2.16
2.4
2.64
W
VDD=4.2V，RL=8Ω+33μH
0.72
0.8
0.88
W
VDD=4.2V，RL=6Ω+33μH
0.9
1
1.1
W
VDD=4.2V，RL=4Ω+15μH
1.44
1.6
1.76
W
VDD=4.2V，RL=3Ω+15μH
1.8
2.0
2.2
W
VDD=4.2V，RL=8Ω+33μH
0.63
0.7
0.77
W
VDD=4.2V，RL=6Ω+33μH
0.81
0.9
0.99
W
VDD=4.2V，RL=4Ω+15μH
1.26
1.4
1.54
W
VDD=4.2V，RL=3Ω+15μH
1.62
1.8
1.98
W
VDD=4.2V，RL=8Ω+33μH
0.54
0.6
0.66
W
VDD=4.2V，RL=6Ω+33μH
0.72
0.8
0.88
W
VDD=4.2V，RL=4Ω+15μH
1.08
1.2
1.32
W
VDD=4.2V，RL=3Ω+15μH
1.44
1.6
1.76
W
Mode3 Multi-Level AGC power
Mode4 Multi-Level AGC power
Mode5 Multi-Level AGC power
Mode6 Multi-Level AGC power
Mode7 Multi-Level AGC power
PSRR
SNR
Power supply rejection ratio
217Hz
-68
dB
1kHz
-68
dB
VDD=4.2V，Po=1.7W，THD+N=1%，RL=8Ω+33μH，
Av=8V/V
98.8
dB
VDD=4.2V，Po=2.0W，THD+N=1%，RL=6Ω+33μH，
Av=8V/V
98.2
dB
43
μVrms
48
μVrms
57
μVrms
VDD=3.6V,Po=1W,RL=8Ω+33μH,f=1kHz,Mode1
0.008
%
VDD=3.6V,Po=1W,RL=6Ω+33μH,f=1kHz,Mode10
0.009
%
THD+N=10%，f=1kHz，RL=8Ω+33μH，VDD=4.2V
2.15
W
THD+N=1%，f=1kHz，RL=8Ω+33μH，VDD=4.2V
1.75
W
THD+N=10%，f=1kHz，RL=8Ω+33μH，VDD=3.6V
1.6
W
THD+N=1%，f=1kHz，RL=8Ω+33μH，VDD=3.6V
1.28
W
THD+N=10%，f=1kHz，RL=6Ω+33μH，VDD=4.2V
2.52
W
VDD=4.2V，Vp-p_sin=200mV
Signal-to-noise ratio
VDD=4.2V，f=20Hz to 20kHz，
input ac grounded，Av=8V/V
Vn
Output noise voltage
VDD=4.2V，f=20Hz to 20kHz，
input ac grounded，Av=12V/V
A-weighting
VDD=4.2V，f=20Hz to 20kHz，
input ac grounded，Av=16V/V
THD+N
PO
PO
Total harmonic distortion+noise
Mode10 output power
Mode10 output power
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
Parameter
Test conditions
Min
Typ
Max
Units
THD+N=1%，f=1kHz，RL=6Ω+33μH，VDD=4.2V
2.05
W
THD+N=10%，f=1kHz，RL=6Ω+33μH，VDD=3.6V
1.82
W
THD+N=1%，f=1kHz，RL=6Ω+33μH，VDD=3.6V
1.5
W
THD+N=10%，f=1kHz，RL=4Ω+15μH，VDD=4.2V
2.8
W
THD+N=1%，f=1kHz，RL=4Ω+15μH，VDD=4.2V
2.4
W
THD+N=10%，f=1kHz，RL=4Ω+15μH，VDD=3.6V
2.02
W
THD+N=1%，f=1kHz，RL=4Ω+15μH，VDD=3.6V
1.68
W
THD+N=10%，f=1kHz，RL=3Ω+15μH，VDD=4.2V
2.63
W
THD+N=1%，f=1kHz，RL=3Ω+15μH，VDD=4.2V
2.35
W
THD+N=10%，f=1kHz，RL=3Ω+15μH，VDD=3.6V
1.85
W
THD+N=1%，f=1kHz，RL=3Ω+15μH，VDD=3.6V
1.65
W
Receiver (mode8-mode9)
Iq
Quiescent current
VDD=4.2V，Vin=0，no load
5
η
Efficiency
VDD=3.6V, Po=0.8W, RL=8Ω+33μH，mode9
86
Modulation frequency
VDD=3.0V to 5.5V
Fosc
Av
Fhin
Vn
Vn
600
mA
%
1000
kHz
external input resistance=3kΩ，mode8
1
V/V
external input resistance=3kΩ，mode9
3
V/V
mode8
106.6
kΩ
mode9
36.6
kΩ
Cin=33nF, external input resistance=3kΩ,mode8
44
Hz
Cin=33nF, external input resistance=3kΩ,mode9
122
Hz
VDD=4.2V，f=20Hz to 20kHz，
input ac grounded，Av=1V/V
19
μVrms
22
μVrms
VDD=4.2V,Po=0.1W,RL=8Ω+33μH,f=1kHz,mode8
0.025
%
VDD=4.2V,Po=0.4W,RL=8Ω+33μH,f=1kHz,mode9
0.025
%
gain
Input high pass filter corner
frequency
Output noise voltage
Output noise voltage
A-weighting
VDD=4.2V，f=20Hz to 20kHz，
input ac grounded，Av=3V/V
THD+N
800
7.5
Total harmonic distortion+noise
One wire pulse control
TH
SHDN high level duration time
VDD=3.0V to 5.5V
0.75
2
10
μs
TL
SHDN low level duration time
VDD=3.0V to 5.5V
0.75
2
10
μs
TLATCH
SHDN turn on delay time
VDD=3.0V to 5.5V
150
500
μs
TOFF
SHDN turn off delay time
VDD=3.0V to 5.5V
150
500
μs
（Note
Multi-Level AGC
4）
TATF
Fast attack time
-13.5dB gain attenuation completed
1.5
ms
TATS
Slow attack time
-13.5dB gain attenuation completed
6
ms
TATT
Total attack time
-13.5dB gain attenuation completed
7.5
ms
TRLT
Release time
13.5dB gain release completed
280
ms
AMAX
Maximum attenuation
-13.5
dB
Note 4：Attack time points to 13.5dB gain attenuation time；Release time points to 13.5dB gain recovery time.
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
MEASUREMENT SETUP
AW87318 features switching digital output, as shown in Figure 6. Need to connect a low pass filter to
VOP/VON output respectively to filter out switch modulation frequency, then measure the differential output of
filter to obtain analog output signal.
10nF
500Ω
VOP
INP
Rin
Cin
30kHz
Low-Pass Fliter
AW87318
VON
INN
500Ω
Rin
Cin
10nF
Figure 6
AW87318 test setup
Low pass filter uses resistance and capacitor values listed in Table 1.
Rfilter
Cfilter
Low-pass cutoff frequency
500Ω
10nF
32kHz
1kΩ
4.7nF
34kHz
Table 1
AW87318 recommended values for low pass filter
Output Power Calculation
According to the above test methods, the differential analog output signal is obtained at the output of the low
pass filter. The valid values Vo_rms of the differential signal as shown below:
Vo_rms
The power calculation of Speaker is as follows：
PL
(Vo _ rms)2
RL
（RL：load impedance of the speaker）
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
TYPICAL CHARACTERISTICS
Efficiency vs Po
K-chargepump Efficiency
100
100
90
90
VDD=3.6V
VDD=4.2V
80
VDD=4.2V
70
Efficiency( % )
Efficiency( % )
80
VDD=3.6V
60
50
40
30
70
60
50
40
30
20
20
RL=8Ω+33μH
10
CF1,CF2=2.2μF
COUT =4.7μF
10
0
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
0
0.2
0.4
0.6
0.8
Po ( W )
1
1.2
1.4
1.6
1.8
2
10K
20K
10K
20K
Po ( W )
GAIN vs FREQUENCY
OUTPUT POWER vs VDD
1.4
24
AW87318 Po keep constant
MODE1
1.2
22
20
1.0
18
MODE4
16
Gain( V/V )
NCN Output Power( W )
MODE2
MODE3
MODE5
0.8
MODE6
MODE7
0.6
MODE1~MODE7
Rine=3kΩ
Cin=1μF
RL=8Ω+33μH
14
12
10
8
0.4
6
4
0.2
2
RL=8Ω+33μH
0
3.3
3.5
3.7
3.9
20
4.3
4.1
50
100
1K
VDD ( V )
FREQUENCY ( Hz )
GAIN vs FREQUENCY
2.4
2.2
6.0
MODE8
Rine=3kΩ
Cin=1μF
RL=8Ω+33μH
5.5
5.0
1.8
4.5
1.6
4.0
Gain( V/V )
Gain( V/V )
2.0
GAIN vs FREQUENCY
1.4
1.2
1.0
0.8
3.5
3.0
2.5
2.0
0.6
1.5
0.4
1.0
0.2
0.5
20
MODE9
Rine=3kΩ
Cin=1μF
RL=8Ω+33μH
50
100
1K
10K
20
50
100
1K
FREQUENCY ( Hz )
FREQUENCY ( Hz )
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20K
10
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
THD+N vs FREQUENCY
THD+N vs FREQUENCY
10
10
MODE10 0.8W
VDD=4.2V
Rine=3kΩ
Cin=1μF
RL=8Ω+33μH
1
THD+N (%)
THD+N (%)
1
0.1
0.01
0.001
20
MODE10 1W
VDD=4.2V
Rine=3kΩ
Cin=1μF
RL=6Ω+33μH
0.1
0.01
50
100
10K
1K
20K
0.001
20
50
100
Po vs VIN
2
Mode1
VDD=4.2V
f=1kHz
RL=8Ω+33μH
Mode2
VDD=4.2V
f=1kHz
RL=8Ω+33μH
1
0.5
Po (W)
Po (W)
1
Multi-level AGC
0.5
Multi-level AGC
0.26
1.30
0.28
0.1
0.5
2
1
0.5
0.1
VIN ( Vp )
Mode4
VDD=4.2V
f=1kHz
RL=8Ω+33μH
1
0.5
Po (W)
1
Multi-level AGC
0.5
Multi-level AGC
0.24
1.18
0.25
0.1
1.1
0.1
0.5
1
2
0.1
0.5
1
2
VIN ( Vp )
VIN ( Vp )
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2
Po vs VIN
2
Mode3
VDD=4.2V
f=1kHz
RL=8Ω+33μH
0.1
1
VIN ( Vp )
Po vs VIN
2
1.21
0.1
0.1
Po (W)
20K
FREQUENCY ( Hz )
Po vs VIN
2
10K
1K
FREQUENCY ( Hz )
11
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
Po vs VIN
2
Po vs VIN
2
Mode5
VDD=4.2V
f=1kHz
RL=8Ω+33μH
1
Po (W)
Po (W)
1
Mode6
VDD=4.2V
f=1kHz
RL=8Ω+33μH
0.5
0.23
Multi-level AGC
0.5
1.07
0.21
Multi-level AGC
0.96
0.1
0.1
0.5
0.1
0.5
0.1
2
1
VIN ( Vp )
2
PSRR vs FREQUENCY
Po vs VIN
0
2
Mode6
VDD=4.2V
f=1kHz
RL=8Ω+33μH
1
1
VIN ( Vp )
Mode10
Rine=3kΩ
Cin=1μF
RL=8Ω+33μH
-10
-20
PSRR (dB)
Po (W)
-30
0.5
Multi-level AGC
0.20
-40
-50
VDD=4.2V
VDD=3.6V
-60
0.92
-70
-80
0.1
-90
0.5
0.1
1
2
20
100
VIN ( Vp )
1K
10K 20K
FREQUENCY ( Hz )
STARTUP SEQUENCE
SHUTDOWN SEQUENCE
SHDN
SHDN
VOP&VON
10ms/div
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VOP&VON
100μs/div
Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
MULTI-LEVEL-AGC
ATTACK SEQUENCE
MULTI-LEVEL-AGC
RELEASE SEQUENCE
Vin
Vin
VOP-VON
VOP-VON
100ms/div
5ms/div
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
DETAILED FUNCTIONAL DESCRIPTION
AW87318 is specifically designed to eliminate smart mobile phone music noise, to enhance overall sound
quality, which is a new high efficiency, low noise, ultra-low distortion, constant large volume, upgrading eighth
generation class K audio amplifiers. AW87318 integrated Awinic proprietary multi-level AGC audio algorithm,
effectively eliminate music noise, improve sound quality and volume. Using a new generation K-Chargepump
technology, efficiency reaches 93%, power amplifier’s overall efficiency reaches 83%, greatly prolong the
mobile phone usage time. AW87318 noise floor is as low as to 43uV, with 98.8dB high
signal-to-noise-ratio(SNR). The ultra-low distortion 0.008% and unique multi-level AGC technology brings
high quality music enjoyment.
AW87318 has 0.6W,0.7W,0.8W,0.9W,1W,1.1W and 1.2W seven subdivision selectable speaker-guard output
power levels, which is suitable for different rated power speakers. With multi-level AGC audio algorithms, the
music is pure natural and melodious. Within lithium battery voltage range (3.3V--4.35V), output power is
constant, preventing voice becomes smaller and smaller during usage of cell phone.
AW87318 supports speaker and receiver two-in-one application. In receiver mode, the output noise is as low
as to 19uV, amplifier is in class D mode, powered by VBAT.
The AW87318 built in excellent pop-click noise suppression circuit, effectively avoids pop-click noise during
shutdown, wakeup, and power-up/down operation of AW87318.
The AW87318 uses Awinic proprietary TDD-Noise suppression technology and EMI suppression technology,
effectively restrain TDD-Noise and EMI interference.
AW87318 has built-in over current protection, over-temperature protection and short circuit protection function,
effectively protect the chip. AW87318 uses small 0.4mm pitch 1.6mmx1.68mm CSP-14 package. The
AW87317 is specified over the industrial temperature range of -40℃ to 85℃.
CONSTANT OUTPUT POWER
In the mobile phone audio applications, the AGC function to promote music volume and quality is very
attractive, but as the lithium battery voltage drops, general power amplifier output power will reduce gradually,
leads to smaller and smaller music volume. So, it is hard to provide high quality music within the battery
voltage range. The AW87318 integrated Awinic proprietary multi-level AGC audio algorithm, within lithium
battery voltage range(3.3V-4.35V), output power is constant, the output power cannot drop along with lithium
battery voltage lower down. Even if the battery voltage drops, AW87318 can still provide high quality large
volume music enjoyment. AW87318 has ten operation modes, first seven modes have Multi-level AGC
function, the output power levels are 1.2W,1.1W,1W,0.9W,0.8W,0.7W, 0.6W,respectively.
Multi-level AGC technology
In the actual audio application, system output power tends to be more than rated power of speaker, such as
in the 5V power supply, as for 8ohms speaker, the maximum undistorted power is about
1.56W, but many speakers’ rated power is about 0.5W, if there is no output power control,
the overload signal can cause damage to the speaker. The audio power amplifier with NCN function (that is
single-level AGC) can protect the speaker effectively, with the increase of input signal, the output
power increases. When output power exceeds the setting threshold, the NCN function reduces the
internal gain of amplifier and restricts the output power under the set threshold.
But the NCN function has the attack time setting, which is the tradeoff between auditory effect and crack
distortion noise, if the attack time is longer, the audio volume will be greater, but crack distortion will also
increase; if the attack time is shorter, the crack distortion will decrease, but the audio volume will be
reduced. General music has large peak factor, which is in the range of about 40~60dB, when playing
music, the big peak signal output exceeds the maximum output amplitude, there will be more
crack distortion, and obvious noise will be heard in some music, so it is need to use multi-level AGC
technology to dynamically adjust the audio power amplifier, to increase music volume, at the same
time, eliminate the emergence of obvious noise in large volume music and improve sound quality.
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
AW87318 integrated Awinic proprietary multi-Level AGC algorithm technology, effectively eliminating
the noise in the music, make sound pure natural, and
greatly enhancing
the sound volume. The
single-level AGC function and multi-level AGC function is shown in figure 7.
Single-level AGC
Multi-level AGC
Constant output power
threshold voltage
More Crack Distortion
Crack distortion voltage
Constant output power
threshold voltage
Few Of Crack Distortion
Single-level AGC function: detect constant
output voltage，within attack time，output
has more crack distortion, and more noise
Multi-level AGC function: simultaneously detect crack distortion
voltage and constant output voltage, within attack time, output
has few of crack distortion, effectively eliminate noise
Figure 7
Single-level AGC/Multi-level AGC Operation Principle
Attack time
Attack time is the time multi-level AGC takes for the gain to be attenuated -13.5dB once the audio signal
exceeds the constant output power threshold voltage. When the output signal crack noise occurred, the Fast
AGC of Multi-level AGC launched, attenuated the gain with 10dB within 1.5ms. When the crack noise
eliminated, the Slow AGC of Multi-level AGC launched, attenuated the gain slowly, with 3.5dB within 6ms.
According to smart mobile phone music noise features and demands for improve music quality and volume,
adoption of the Awinic proprietary technology ‘Multi-level AGC’ inside AW87318, which keeping the music
rhythm effectively, and at the same time eliminating the crack distortion, protecting the speaker.
Release time
Release time is the time multi-level AGC takes for the gain to return to its normal level once the audio signal is
smaller than crack distortion voltage or constant output power threshold voltage. According to smart mobile
phone music noise features and demands for improve music quality and volume, release time of AW87318 is
set to be 280ms, which can effectively eliminate the noise, make music sound pure natural.
K-Chargepump
AW87318 adopts a new generation of charge pump technology：K -Chargepump structure, it has high
efficiency and large driving ability, working frequency is 1.1MHz，built in soft start circuit, current limiting
control loop and over-voltage-protection(OVP) loop, guaranteeing system stable and reliable operation.
High Efficiency
AW87318 uses K-chargepump structure，booster output voltage PVDD is 1.5 times of supply voltage VDD,
the ideal efficiency can reach 100%. K-chargepump efficiency is the ratio of output power to input power, that
is
POUT
*100%
PIN
For example, in an ideal M times charge pump, the input current IIN is M times of output current IOUT，the
efficiency formula can be written as：
POUT
V *I
V
*100% OUT OUT *100% OUT *100%
PIN
VIN * M * I OUT
M *VIN
M is charge pump work mode variable (1.5 times), VOUT is charge pump output voltage, VIN is power supply
voltage, IOUT is load current. For K-chargepump, the output voltage is 1.5 times of the input voltage, due to
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
the charge pump internal switch loss and IC static current loss, the actual efficiency will be up to 93%.
Therefore, K-chargepump booster technology can greatly improve the power efficiency.
Charge Pump Structure
Figure 8 is charge pump basic principle diagram, the charge pump used in AW87318 has seven switches, the
output voltage PVDD is 1.5 times as input voltage VDD through seven switches timing control.
S1
S6
C1P
+
VDD
CIN
4.7uF
CF1
2.2uF
S4
PVDD
COUT
4.7uF
C1N
S2
+
S7
C2P
CF2
2.2uF
S5
S3
C2N
Figure 8 Charge Pump Principle Diagram
The operation of the charge pump has two phases. In Φ 1, as shown in figure 9, switches S1, S2 and S3 are
closed, VDD charges to the flying capacitor CF1 CF2.
S1
C1P
+
VDD
CIN
4.7uF
S6
CF1
2.2uF
S4
PVDD
COUT
4.7uF
C1N
S2
+
S7
C2P
CF2
2.2uF
S3
S5
C2N
Charging Phase
Figure 9
Φ1: Flying Capacitor Charging
In Φ 2, as shown in figure 10: switches S1, S2 and S3 are disconnected, switches S4, S5, S6 and S7 are
closed. Because the voltage across the capacitor can't mutation, so the voltage on flying capacitor CF1 CF2,
is added to the VDD, which make PVDD risen to a higher voltage.
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
S1
C1P
+
VDD
CIN
4.7uF
S6
CF1
2.2uF
S4
PVDD
COUT
4.7uF
C1N
S2
+
S7
C2P
CF2
2.2uF
S3
S5
C2N
Discharging Phase
Figure 10
Φ2： Flying capacitor charge transfer to the output capacitance COUT
Soft start
K-chargepump has integrated soft start function in order to limit supply power inrush current during start-up.
The supply current is limited to be 350 mA, and the soft start time is 1.2 ms.
Current Limitation Control
K-chargepump has integrated the current limitation control loop. In normal operation, when the heavy load or
a situation that make charge pump flow through very large current, the current limitation control loop will
control charge pump maximum output current capacity, that is 2 A.
Over Voltage Protection(OVP)Control
K-chargepump’s output voltage PVDD is a multiple of the input voltage VDD, which provide a high voltage rail
for internal power amplifier circuits, allowing the amplifiers provide greater output dynamic range in the lithium
battery voltage range, so as to realize the large volume, high quality class K audio enjoyment. K-chargepump
has integrated the over voltage protection control loop, when the input voltage VDD is greater than 4V, the
output voltage PVDD is no longer a multiple of VDD, but is controlled by over voltage protection(OVP) loop
and is stable in 6.05V, and the hysteresis voltage is about 50mV.
Speaker & Receiver two-in-one application
AW87318 mode8, mode9 are receiver modes, the gain can be optional, 1V/V and 3V/V, respectively,
which make the application flexible. Receiver modes use speakers’ signal path, which has ultra-low
distortion and a strong driving ability. So it is suitable for high definition voice application. Another
advantage is that there is no need of additional external components, less system cost and PCB layout
space.
In Figure 5 typical application, input capacitance Cin=33nF, input resistance Rine=3kohm, speaker
mode gain is about 16.6V/V, the input high-pass corner frequency is at 502Hz; When receiver mode gain
is 1V/V, the output noise of receiver is 19uV，the input high-pass corner frequency is at 44Hz. AW87318
can achieve speaker and receiver two-in-one application without changing any hardware.
One-wire pulse control
One wire pulse control technology only needs a single GPIO port to operate the chip, complete a variety of
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
functions, it is very popular in the area of the GPIO port shortage and portable systems.
When the control signal line is longer, because of the signal integrity or radio frequency interference problem,
it will produce the narrow glitch signal. Awinic one wire pulse control technology integrated the Deglitch circuit
in internal control pin, which can effectively eliminate the influence of the glitch signal, as shown in figure 11.
AW87318
SHDN
Control signal with glitch
Deglitch
Glitch is eleminated
Figure 11 Awinic Deglitch function diagram
The traditional one wire pulse control technology still receives pulse signal from control port when chip is
startup, so when the master control chip (such as mobile phone BB) sends wrong pulse during normal
operation, the system will enter into error states. AW87318 uses one wire pulse latch technology, after the
master control chip has sent pulses, the state will be latched, no longer receive the latter mis-sending pulse
signals, as shown in figure 12.
TLATCH
STATE 4
Traditional One Wire
Pulse Control
STATE 3
Shielding abnormal
pulse signal
STATE 4
STATE 3
Anti-interference One
Wire Pulse Control
Figure 12 Anti-interference One Wire Pulse Control Function Diagram
One Wire Pulse Control
AW87318 select each mode through the detection of number of the pulse signal rising edge of SHDN pin, as
shown in figure 13: When SHDN pin pull high from shutdown mode, there is only a rising edge, AW87318
enter into mode 1,Multi-level AGC output power is 1.2W; When high-low-high signal set to SHDN pin, there
are two rising edges, AW87318 enter into mode 2, Multi-level AGC output power is 1.1W; When there are
three rising edges, AW87318 enter into mode 3, Multi-level AGC output power is 1W; When there are four
rising edges, AW87318 enter into mode 4, Multi-level AGC output power is 0.9W…; AW87318 has ten
operation modes, the number of the rising edges does not allow more than ten.
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Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD
AW87318
May 2017 V1.1
MODE1
MODE2
MODE3
MODE4
0.75μs
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