RS256M16V0DB-107AT

4Gb: x4, x8, x16 DDR3 SRAM Features DDR3 SDRAM RS1024M4V0DA – 128 Meg x 4 x 8 Banks RS512M8V0DA – 64 Meg x 8 x 8 Banks RS256M16V0DB– 32 Meg x 16 x 8 Banks Features • • • • • • • • • • • • • • • • • • VDD = VDDQ = +1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS (READ) latency (CL) Posted CAS Addictive latency (AL) Programmable CAS (WRITE) latency (CWL) based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 0°C to 95°C – 64ms, 8,192 cycle refresh at 0°C to 85°C – 32ms, 8,192 cycle refresh at 85°C to 95°C Self refresh temperature (SRT) Write leveling Multipurpose register Output driver calibration Options • Rayson • Configuration – 1 Gig x 4 – 512 Meg x 8 – 256 Meg x 16 • Product Code – DDR3 • Density – 4 Gigabyte • Voltage/Refresh – 1.5V/8k refresh • FBGA package (Pb-free) - x4, x8 – 78-ball (8mm x 10.5mm) • FBGA package (Pb-free) - x16 – 96-ball (8mm x 14mm) • Timing - cycle time – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) 1 Marking RS 1,024M4 512M8 256M16 Vx3 0x3 A DA DB -107 -125 -15E -187E Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Features Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) Target tRCD-tRP-CL -1071,2 -1251,2 -15E1 -187E 1866 1600 1333 1066 13-13-13 11-11-11 9-9-9 7-7-7 t RCD (ns) 13.91 13.75 13.5 13.1 t RP (ns) CL (ns) 13.91 13.75 13.5 13.1 13.91 13.75 13.5 13.1 Notes:1.Backward compatible to 1066, CL = 7 (-187E). 2.Backward compatible to 1333, CL = 9 (-15E). 3.Backward compatible to 1066, CL = 8 (-187). Table 2: Addressing Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Page size 1 Gig × 4 512 Meg × 8 256 Meg × 16 128 Meg x 4 x 8 banks 8K 64K (A[15:0]) 8 (BA[2:0]) 2K (A[11, 9:0]) 1KB 64 Meg x 8 x 8 banks 8K 64K (A[15:0]) 8 (BA[2:0]) 1K (A[9:0]) 1KB 32 Meg x 16 x 8 banks 8K 32K (A[14:0]) 8 (BA[2:0]) 1K (A[9:0]) 2KB Marketing Part Number Chart 2 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Input/Output Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Electrical Specifications – IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Electrical Characteristics – IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Electrical Specifications – DC and AC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Slew Rate Definitions for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Slew Rate Definitions for Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 ODT Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 ODT Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 ODT Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Output Driver Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 34 Ohm Output Driver Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 34 Ohm Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34 Ohm Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Alternative 40 Ohm Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 40 Ohm Driver Output Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Output Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Reference Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Slew Rate Definitions for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Slew Rate Definitions for Differential Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Speed Bin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Electrical Characteristics and AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Notes: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 Command and Address Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Data Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 DESELECT (DES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 ZQ CALIBRATION LONG (ZQCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 ZQ CALIBRATION SHORT (ZQCS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 3 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Table of Contents SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Input Clock Frequency Change. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Write Leveling Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 Write Leveling Mode Exit Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 DLL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 Precharge Power-Down (Precharge PD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 DLL Enable/DLL Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 OUTPUT ENABLE/DISABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 TDQS Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 WRITE LEVELING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 POSTED CAS ADDITIVE Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 CAS Write Latency (CWL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 AUTO SELF REFRESH (ASR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 SELF REFRESH TEMPERATURE (SRT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 SRT vs. ASR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 DYNAMIC ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 MULTIPURPOSE REGISTER (MPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 MPR Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 MPR Register Address Definitions and Bursting Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 MPR Read Predefined Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 ZQ CALIBRATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 ACTIVATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 DQ Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Extended Temperature Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Nominal ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Dynamic ODT Special Use Case. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Synchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 ODT Latency and Posted ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 4 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Table of Contents Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 ODT Off During READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Asynchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189 Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry). . . . . . . . . . . . . . . . . . . . . . . .191 Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) . . . . . . . . . . . . . . . . . . . . . . . . .193 Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) . . . . . . . . . . . . . . . . . . . . . . . .195 5 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 33: Figure 34: Figure 35: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: Figure 57: Figure 58: Figure 63: Figure 64: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1 Gig x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 512 Meg x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 256 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 78-Ball FBGA – x4, x8 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 96-Ball FBGA – x16 Ball Assignments (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 78-Ball FBGA – x4, x8; “DA” .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 78-Ball FBGA – x4, x8; “DA” .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 78-Ball FBGA – x4, x8; “DH” .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 96-Ball FBGA – x16; “DB“.... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 96-Ball FBGA – x16; “DC“ ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Thermal Measurement Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Vix for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Single-Ended Requirements for Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Nominal Slew Rate Definition for Single-Ended Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# . . . . . . . . . . . . .50 ODT Levels and I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 t AON and tAOF Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 t AONPD and tAOFPD Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 tADC Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Output Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 DQ Output Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Differential Output Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Reference Output Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Nominal Slew Rate Definition for Single-Ended Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . .66 Nominal Differential Output Slew Rate Definition for DQS, DQS# . . . . . . . . . . . . . . . . . . . . . . . .67 Nominal Slew Rate for tIH (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Tangent Line for tIS (Command and Address – Clock). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Tangent Line for tIH (Command and Address – Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Nominal Slew Rate for tDH (DQ – Strobe). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 Tangent Line for tDS (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Tangent Line for tDH (DQ – Strobe) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 DLL Enable Mode to DLL Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 DLL Disable Mode to DLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 DLL Disable tDQSCK Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Change Frequency During Precharge Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 Write Leveling Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 Exit Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 MRS-to-MRS Command Timing (tMRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 MRS-to-nonMRS Command Timing (tMOD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Mode Register 0 (MR0) Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 Mode Register 1 (MR1) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 READ Latency (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Mode Register 2 (MR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 CAS Write Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Mode Register 3 (MR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Multipurpose Register (MPR) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 ZQ Calibration Timing (ZQCL and ZQCS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 6 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM List of Figures Figure 65: Example: tFAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Figure 66: READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Figure 68: Consecutive READ Bursts (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Figure 70: READ (BL8) to WRITE (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Figure 72: READ to PRECHARGE (BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 Figure 74: READ to PRECHARGE (AL = 5, CL = 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Figure 75: READ with Auto Precharge (AL = 4, CL = 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Figure 77: Data Strobe Timing – READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Figure 78: Method for Calculating tLZ and tHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Figure 79: tRPRE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Figure 80: tRPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 Figure 81: tWPRE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Figure 82: tWPST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 Figure 83: Write Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via MRS or OTF. . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 Figure 86: Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Figure 87: WRITE (BL8) to READ (BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 Figure 92: WRITE (BC4 OTF) to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Figure 93: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Figure 94: Self Refresh Entry/Exit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Figure 95: Active Power-Down Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) . . . . . . . . . . . . . . . . . . .171 Figure 99: Power-Down Entry After WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 Figure 100:Power-Down Entry After WRITE with Auto Precharge (WRAP) . . . . . . . . . . . . . . . . . . . . . . . . . .172 Figure 101:REFRESH to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 Figure 102:ACTIVATE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Figure 103:PRECHARGE to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 Figure 104:MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Figure 105:Power-Down Exit to Refresh to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174 Figure 106:RESET Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .175 Figure 107:On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176 Figure 109:Dynamic ODT: Without WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181 Figure 112:Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 . . . . . . . .183 Figure 113:Synchronous ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 Figure 114:Synchronous ODT (BC4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 Figure 117:Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry192 Figure 120:Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping . . . .196 7 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Table 48: Table 49: Table 50: Table 51: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 78-Ball FBGA – x4, x8 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 96-Ball FBGA – x16 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Timing Parameters used for IDD Measurements – Clock Units . . . . . . . . . . . . . . . . . . . . . . . . . . .29 IDD0 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 IDD1 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 IDD Measurement Conditions for Power-Down Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 IDD2N and IDD3N Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 IDD2NT Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 IDD4R Measurement Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 IDD4W Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 IDD5B Measurement Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 IDD7 Measurement Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 IDD Maximum Limits – Die Rev D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 IDD Maximum Limits – Die Rev E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 DC Electrical Characteristics and Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Input Switching Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Control and Address Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Clock, Data, Strobe, and Mask Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Differential Input Operating Conditions (CK, CK# and DQS, DQS#) . . . . . . . . . . . . . . . . . . . . . .45 Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS#. . . . . . . . . . . . . . . . . . . .47 Single-Ended Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 On-Die Termination DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 RTT Effective Impedances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 ODT Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ODT Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 34Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 34Ω Driver Pull-Up and Pull-Down Impedance Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.575V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 34Ω Driver IOH/IOL Characteristics: VDD = VDDQ = 1.425V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 34Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 34Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 40Ω Driver Impedance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 40Ω Output Driver Sensitivity Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 40Ω Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Single-Ended Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Differential Output Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Single-Ended Output Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 DDR3-1066 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 DDR3-1333 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 8 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM List of Tables Table 52: Table 53: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Table 82: Table 83: Table 84: Table 85: Table 86: Table 87: Table 89: DDR3-1600 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 DDR3-1866 Speed Bins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Electrical Characteristics and AC Operating Conditions for Speed Extensions . . . . . . . . . . . . .81 Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based . . . . . .91 Derating Values for tIS/tIH – AC175/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Derating Values for tIS/tIH – AC150/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Derating Values for tIS/tIH – AC135/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Derating Values for tIS/tIH – AC125/DC100-Based. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Minimum Required Time tVAC Above VIH(AC) for Valid Transition . . . . . . . . . . . . . . . . . . . . . . .94 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based . . . . . . . . . . . . .99 Derating Values for tDS/tDH – AC175/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Derating Values for tDS/tDH – AC150/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Derating Values for tDS/tDH – AC135/DC100-Based . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid Transition. . . . . . . . . . . . . . . . . .102 Truth Table – Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 READ Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 WRITE Command Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 READ Electrical Characteristics, DLL Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Write Leveling Matrix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 MPR Functional Description of MR3 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 MPR Readouts and Burst Order Bit Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Self Refresh Temperature and Auto Self Refresh Description. . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Self Refresh Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 Command to Power-Down Entry Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 Power-Down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 Truth Table – ODT (Nominal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 ODT Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 Write Leveling with Dynamic ODT Special Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 Dynamic ODT Specific Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 Mode Registers for Rtt_nom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Mode Registers for Rtt_wr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Timing Diagrams for Dynamic ODT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180 Synchronous ODT Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period . . . . . . . . . . . .192 9 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM State Diagram State Diagram Figure 1: Simplified State Diagram CKE L Power applied Power on Reset procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL From any state RESET ZQ calibration MRS SRX REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active powerdown Precharge powerdown Activating PDX CKE L CKE L PDE Bank active READ WRITE WRITE WRITE AP READ AP READ Writing READ WRITE WRITE AP Reading READ AP WRITE AP READ AP PRE, PREA Writing PRE, PREA PRE, PREA Precharging Reading Automatic sequence Command sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE PREA = PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 10 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Functional Description Functional Description The DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the data strobes. The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble. Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select the bank and the starting column location for the burst access. DDR3 SDRAM use READ and WRITE BL8 and BC4. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time. A self refresh mode is provided, along with a power-saving, power-down mode. General Notes • The functionality and the timing specifications discussed in this data sheet are for the DLL enable mode of operation (normal operation). • Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. • The terms “DQS” and “CK” found throughout the data sheet are to be interpreted as DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise. • Complete functionality may be described throughout the entire document, and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. • Any specific requirement takes precedence over a general statement. • Any functionality not specifically stated herewithin is considered undefined, illegal, and not supported and can result in unknown operation. • Row addressing is denoted as A[n:0]. For example: 1Gb: n = 12 (x16); 1Gb: n = 13 (x4, x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4, x8). 11 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Functional Description • Dynamic ODT has a special use case: when DDR3 devices are architected for use in a single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer to the Dynamic ODT Special Use Case section. • A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be used, use the lower byte for data transfers and terminate the upper byte as noted: – Connect UDQS to ground via 1kΩ* resistor. – Connect UDQS# to VDD via 1kΩ* resistor. – Connect UDM to VDD via 1kΩ* resistor. – Connect DQ[15:8] individually to either VSS, VDD, or VREF via 1kΩ resistors,* or float DQ[15:8]. *If ODT is used, 1kΩ resistor should be changed to 4x that of the selected ODT. 12 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Functional Block Diagrams Functional Block Diagrams DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally configured as an 8-bank DRAM. Figure 2: 1 Gig x 4 Functional Block Diagram ODT control ODT ZQ RZQ To pullup/pulldown networks ZQ CAL RESET# ZQCL, ZQCS CKE VSSQ A12 Control logic CK, CK# VDDQ/2 BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh 16 counter 19 Rowaddress MUX 16 16 Bank 0 rowaddress 65,536 latch and decoder RTT_NOM RTT_WR Columns 0, 1, and 2 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 CK,CK# sw2 sw1 DLL (1 . . . 4) Bank 0 memory array (65,536 x 256 x 32) 32 READ FIFO and data MUX 4 DQ[3:0] READ drivers DQ[3:0] DQS, DQS# VDDQ/2 Sense amplifiers 32 BC4 RTT_NOM RTT_WR 8,192 BC4 OTF I/O gating DM mask logic 3 A[15:0] BA[2:0] 19 Address register 3 DM (1, 2) Bank control logic 32 Data interface Column decoder Columnaddress counter/ latch DQS, DQS# VDDQ/2 256 (x32) 11 sw2 sw1 4 Data WRITE drivers and input logic 8 RTT_NOM RTT_WR sw1 sw2 DM 3 Columns 0, 1, and 2 CK,CK# 13 Column 2 (select upper or lower nibble for BC4) Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Functional Block Diagrams Figure 3: 512 Meg x 8 Functional Block Diagram ODT control ODT ZQ ZQ CAL RESET# RZQ Control logic CKE VSSQ To ODT/output drivers ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# Refresh counter Mode registers Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF CK, CK# sw1 (1 . . . 8) 19 Bank 0 Memory array (65,536 x 128 x 64) Bank 0 rowaddress 65,536 latch and decoder 16 16 sw2 DLL 16 Rowaddress MUX RTT_WR RTT_NOM Columns 0, 1, and 2 64 DQ8 READ FIFO and data MUX 8 TDQS# DQ[7:0] Read drivers DQ[7:0] DQS, DQS# VDDQ/2 Sense amplifiers 64 BC4 8,192 19 Address register BC4 OTF RTT_WR sw1 sw2 I/O gating DM mask logic 3 A[15:0] BA[2:0] RTT_NOM (1, 2) Bank control logic 3 VDDQ/2 (128 x64) 64 8 Data interface Data Column decoder Columnaddress counter/ latch 10 DQS/DQS# Write drivers and input logic RTT_NOM RTT_WR sw1 sw2 7 DM/TDQS (shared pin) 3 Columns 0, 1, and 2 CK, CK# Column 2 (select upper or lower nibble for BC4) Figure 4: 256 Meg x 16 Functional Block Diagram ODT control ODT ZQ RZQ ZQ CAL RESET# Control logic CKE VSSQ To ODT/output drivers ZQCL, ZQCS A12 VDDQ/2 CK, CK# BC4 (burst chop) Command decode CS# RAS# CAS# WE# Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 OTF Mode registers Refresh counter 18 Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 15 15 Bank 0 rowaddress latch and decoder 32,768 RTT_WR CK, CK# sw2 sw1 DLL (1 . . . 16) 13 Rowaddress MUX RTT_NOM Column 0, 1, and 2 Bank 0 memory array (32,768 x 128 x 128) 128 READ FIFO and data MUX 16 DQ[15:0] READ drivers LDQS, LDQS#, UDQS, UDQS# DQ[15:0] VDDQ/2 Sense amplifiers BC4 128 16,384 Address register 3 LDQS, LDQS# I/O gating DM mask logic 3 18 Bank control logic (1 . . . 4) 128 Data interface Column decoder Columnaddress counter/ latch UDQS, UDQS# VDDQ/2 (128 x128) 10 RTT_WR sw2 sw1 BC4 OTF A[14:0] BA[2:0] RTT_NOM 16 Data WRITE drivers and input logic RTT_NOM sw1 RTT_WR sw2 7 (1, 2) 3 Columns 0, 1, and 2 CK, CK# 14 Column 2 (select upper or lower nibble for BC4) LDM/UDM Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Ball Assignments and Descriptions Figure 5: 78-Ball FBGA – x4, x8 Ball Assignments (Top View) 1 2 3 VSS VDD VSS VDDQ 4 5 6 7 8 9 NC NF, NF/TDQS# VSS VDD VSSQ DQ0 DM, DM/TDQS VSSQ VDDQ DQ2 DQS DQ1 DQ3 VSSQ NF, DQ6 DQS# VDD VSS VSSQ A B C D VSSQ E VREFDQ NF, DQ7 NF, DQ5 VDDQ VDDQ NF, DQ4 F NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 A14 A8 VSS G H J K L M N Notes: 1. Ball descriptions listed in Table 3 on page 17 are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3 on page 17). 15 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Figure 6: 96-Ball FBGA – x16 Ball Assignments (Top View) 1 2 3 VDDQ DQ13 VSSQ 4 5 6 7 8 9 DQ15 DQ12 VDDQ VSS VDD VSS UDQS# DQ14 VSSQ VDDQ DQ11 DQ9 UDQS DQ10 VDDQ VSSQ VDDQ UDM DQ8 VSSQ VDD VSS VSSQ DQ0 LDM VSSQ VDDQ VDDQ DQ2 LDQS DQ1 DQ3 VSSQ VSSQ DQ6 LDQS# VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ NC VSS RAS# CK VSS NC ODT VDD CAS# CK# VDD CKE NC CS# WE# A10/AP ZQ NC VSS BA0 BA2 NC VREFCA VSS VDD A3 A0 A12/BC# BA1 VDD VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS RESET# A13 NC A8 VSS A B C D E F G H J K L M N P R T Notes: 1. Ball descriptions listed in Table 4 on page 19 are listed as “x4, x8” if unique; otherwise, x4 and x8 are the same. 2. A comma separates the configuration; a slash defines a selectable function. Example D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 4 on page 19). 16 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10/AP, A11, A12/BC#, A13, A14 Input BA0, BA1, BA2 Input CK, CK# Input CKE Input CS# Input DM Input ODT Input RAS#, CAS#, WE# Input RESET# Input DQ0, DQ1, DQ2, DQ3 DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 DQS, DQS# I/O Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active powerdown (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with the input data during a write access. Although the DM ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on the x8. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ. Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ. TDQS, TDQS# Output I/O I/O Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled, DM is disabled, and the TDQS and TDQS# balls provide termination resistance. 17 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued) Symbol Type VDD VDDQ VREFCA Supply Supply Supply VREFDQ VSS VSSQ ZQ NC NF Description Power supply: 1.5V ±0.075V. DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Supply Ground. Supply DQ ground: Isolated on the device for improved noise immunity. Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). – No function: When configured as a x4 device, these balls are NF. When configured as a x8 device, these balls are defined as TDQS#, DQ[7:4]. 18 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions Symbol Type Description A0, A1, A2, A3, A4, A5, A6, A7, A8, A9 A10/AP, A11, A12/BC#, A13 Input BA0, BA1, BA2 Input CK, CK# Input CKE Input CS# Input LDM Input ODT Input RAS#, CAS#, WE# Input RESET# Input UDM Input DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7 I/O Address inputs: Provide the row address for ACTIVATE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop, LOW = BC4 burst chop). Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to VREFCA. Clock: CK and CK# are differential clock inputs. All control and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#. Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW provides PRECHARGE power-down and SELF REFRESH operations (all banks idle), or active powerdown (row active in any bank). CKE is synchronous for power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA. Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command code. CS# is referenced to VREFCA. Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write access. Although the LDM ball is input-only, the LDM loading is designed to match that of the DQ and DQS balls. LDM is referenced to VREFDQ. On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA. Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered and are referenced to VREFCA. Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and DC LOW ≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous. Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte input data is masked when UDM is sampled HIGH along with that input data during a WRITE access. Although the UDM ball is input-only, the UDM loading is designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ. Data input/output: Lower byte of bidirectional data bus for the x16 configuration. DQ[7:0] are referenced to VREFDQ. 19 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Ball Assignments and Descriptions Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued) Symbol Type DQ8, DQ9, DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 LDQS, LDQS# I/O UDQS, UDQS# VDD VDDQ VREFCA VREFDQ VSS VSSQ ZQ NC Description Data input/output: Upper byte of bidirectional data bus for the x16 configuration. DQ[15:8] are referenced to VREFDQ. I/O Lower byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data. I/O Upper byte data strobe: Output with read data. Edge-aligned with read data. Input with write data. DQS is center-aligned to write data. Supply Power supply: 1.5V ±0.075V. Supply DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity. Supply Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation. Supply Reference voltage for data: VREFDQ must be maintained at all times (excluding self refresh) for proper device operation. Supply Ground. Supply DQ ground: Isolated on the device for improved noise immunity. Reference External reference ball for output drive calibration: This ball is tied to an external 240Ω resistor (RZQ), which is tied to VSSQ. – No connect: These balls should be left unconnected (the ball has no connection to the DRAM or to other balls). 20 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Package Dimensions Package Dimensions Figure 7: 78-Ball FBGA – x4, “DA” 0.155 Seating Plane A 0.12 A 1.8 CTR Nonconductive overmold 78X Ø0.45 Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 9 8 7 Ball A1 ID Ball A1 ID 3 2 1 A B C D E F G H J K L M N 10.5 ±0.1 9.6 CTR 0.8 TYP 0.8 TYP 1.1 ±0.1 6.4 CTR 0.25 MIN 8±0.1 Notes: 1. All dimensions are in millimeters. 21 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Package Dimensions Figure 8: 78-Ball FBGA – x8; “DA” 0.155 Seating plane 0.12 A A 78X Ø0.45 Dimensions apply to solder balls postreflow on Ø0.35 SMD ball pads. 1.8 CTR Nonconductive overmold Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F 9.6 CTR G 10.5 ±0.1 H J K L M 0.8 TYP N 0.8 TYP 1.1 ±0.1 6.4 CTR 0.25 MIN 8±0.1 Notes: 1. All dimensions are in millimeters. 22 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Package Dimensions Figure 9: 78-Ball FBGA – x4, x8; “DH” 0.155 Seating plane A 0.12 A 1.8 CTR nonconductive overmold 78X Ø0.47 Dimensions apply to solder balls postreflow on Ø0.42 SMD ball pads. Ball A1 ID (covered by SR) 9 8 7 Ball A1 ID 3 2 1 A B C D E F G H J K L M N 10.6 ±0.1 9.6 CTR 0.8 TYP 1.1 ±0.1 0.8 TYP 6.4 CTR 0.25 MIN 7.5 ±0.1 Notes: 1. All dimensions are in millimeters. 23 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Package Dimensions Figure 10: 96-Ball FBGA – x16; “DB“ 0.155 Seating plane 0.12 A 1.8 CTR Nonconductive overmold A 96X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. Ball A1 ID 9 8 7 3 2 Ball A1 ID 1 A B C D E F G H 12 CTR J 14 ±0.1 K L M N P R 0.8 TYP T 0.8 TYP 1.1 ±0.1 6.4 CTR 0.25 MIN 8±0.1 Notes: 1. All dimensions are in millimeters. 24 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Package Dimensions Figure 11: 96-Ball FBGA – x16; “DC“ 0.155 Seating plane 0.12 A 1.8 CTR Nonconductive overmold A 96X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.35 SMD ball pads. Ball A1 ID Ball A1 ID 9 8 7 3 2 1 A B C D E F G H 12 CTR J 13.5 ±0.1 K L M N P R 0.8 TYP T 0.8 TYP 1.1 ±0.1 6.4 CTR 0.25 MIN 7.5± 0.1 25 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed in Table 5 may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 5: Absolute Maximum Ratings Symbol Parameter Min Max Units Notes VDD VDDQ VIN, VOUT TC TSTG VDD supply voltage relative to VSS VDD supply voltage relative to VSSQ Voltage on any pin relative to VSS Operating case temperature Storage temperature –0.4 –0.4 –0.4 0 –55 1.975 1.975 1.975 95 150 V V V °C °C 1 2, 3 Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 × VDDQ. When VDD and VDDQ are less than 500mV, VREF may be ≤300mV. 2. MAX operating case temperature. TC is measured in the center of the package (see Figure 12 on page 28). 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 26 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications Input/Output Capacitance Table 6: Input/Output Capacitance Note 1 applies to the entire table DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Capacitance Parameters CK and CK# ΔC: CK to CK# Single-end I/O: DQ, DM Differential I/O: DQS, DQS#, TDQS, TDQS# ΔC: DQS to DQS#, TDQS, TDQS# ΔC: DQ to DQS Inputs (CTRL, CMD, ADDR) ΔC: CTRL to CK ΔC: CMD_ADDR to CK ZQ pin capacitance Reset pin capacitance Symbol Min Max Min Max Min Max Min Max Units Notes CCK CDCK CIO CIO 0.8 0 1.5 1.5 1.6 0.15 3.0 3.0 0.8 0 1.5 1.5 1.4 0.15 2.5 2.5 0.8 0 1.5 1.5 1.4 0.15 2.3 2.3 0.8 0 1.4 1.4 1.3 0.15 2.2 2.2 pF pF pF pF CDDQS CDIO CI CDI_CTRL 0 –0.5 0.75 –0.5 –0.5 – – 0.2 0.3 1.35 0.3 0.5 3.0 3.0 0 –0.5 0.75 –0.4 –0.4 – – 0.15 0.3 1.3 0.2 0.4 3.0 3.0 0 –0.5 0.75 –0.4 –0.4 – – 0.15 0.3 1.3 0.2 0.4 3.0 3.0 0 –0.5 0.75 –0.4 –0.5 – – 0.15 0.3 1.3 0.2 0.3 3.0 3.0 pF pF pF pF pF pF pF CDI_CMD_ADDR CZO CRE 2 3 3 4 5 6 7 Notes: 1. VDD = +1.5V ±0.075mV, VDDQ = VDD, VREF = VSS, f = 100 MHz, TC = 25°C. VOUT(DC) = 0.5 × VDDQ, VOUT (peak-to-peak) = 0.1V. 2. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 3. Includes TDQS, TDQS#. CDDQS is for DQS vs. DQS# and TDQS vs. TDQS# separately. 4. CDIO = CIO (DQ) - 0.5 × (CIO [DQS] + CIO [DQS#]). 5. Excludes CK, CK#; CTRL = ODT, CS#, and CKE; CMD = RAS#, CAS#, and WE#; ADDR = A[n:0], BA[2:0]. 6. CDI_CTRL = CI (CTRL) - 0.5 × (CCK [CK] + CCK [CK#]). 7. CDI_CMD_ADDR = CI (CMD_ADDR) - 0.5 × (CCK [CK] + CCK [CK#]). 27 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Thermal Characteristics Thermal Characteristics Table 7: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature 0 to 85 0 to 95 3.9 TBD 1.6 3.9 °C °C °C/W TC TC ΘJC 1, 2, 3 1, 2, 3, 4 5 Junction-to-case (TOP) 78-ball “GKF” 78-ball “GQF” 82-ball “GHF” 96-ball “GPF” Notes: 1. MAX operating case temperature. TC is measured in the center of the package (see Figure 12). 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs interval refresh rate. The use of SRT or ASR (if available) must be enabled. 5. The thermal resistance data is based off of a number of samples from multiple lots and should be viewed as a typical number. Figure 12: Thermal Measurement Point (L/2) Tc test point L (W/2) W 28 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions Electrical Specifications – IDD Specifications and Conditions Within the following IDD measurement tables, the following definitions and conditions are used, unless stated otherwise: • • • • • • • • • • • • • • • • Table 8: LOW: VIN ≤ VIL(AC) MAX; HIGH: VIN ≥ VIH(AC) MIN Mid-level: Inputs are VREF = VDD/2 RON set to RZQ/7, that is, 34Ω RTT_NOM set to RZQ/6, that is, 40Ω. RTT_WR set to RZQ/2, that is, 120Ω. QOFF is enabled in MR1 ODT is enabled in MR1 (RTT_NOM) and MR2 (RTT_WR) TDQS is disabled in MR1 External DQ/DQS/DM load resister is 25Ω to VDDQ/2 Burst lengths are BL8 fixed AL equals 0 (except in IDD7) IDD specifications are tested after the device is properly initialized Input slew rate is specified by AC parametric test conditions Optional ASR is disabled READ burst type uses nibble sequential (MR0 [3] 0) Loop patterns must be executed at least once prior to current measurements begin Timing Parameters used for IDD Measurements – Clock Units DDR3-1066 IDD Parameter -187E -187 -15E 7-7-7 8-8-8 9-9-9 t CK (MIN) IDD CL IDD tRCD (MIN) I DD t RC (MIN) IDD t RAS (MIN) IDD tRP (MIN) t FAW x4, x8 x16 t RRD IDD x4, x8 x16 t RFC 1Gb 2Gb 4Gb DDR3-1333 -15 -125E 10-10-10 10-10-10 1.5 1.875 7 7 27 20 7 20 27 4 6 59 86 139 DDR3-1600 8 8 28 20 8 20 27 4 6 59 86 139 9 9 33 24 9 20 30 4 5 74 107 174 29 -125 -107 11-11-11 13-13-13 Units 1.07 13 13 45 32 13 26 33 5 6 103 150 243 ns CK CK CK CK CK CK CK CK CK CK CK CK 1.25 10 10 34 24 10 20 30 4 5 74 107 174 10 10 38 28 10 24 32 5 6 88 128 208 DDR3-1866 11 11 39 28 11 24 32 5 6 88 128 208 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions Data A[2:0] A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE# 1 2 × nRC 0 0 1 1 0 0 0 0 0 0 0 – 1 0 0 0 0 0 0 0 0 0 0 – 1 0 0 0 0 0 0 0 0 0 0 – 1 1 1 1 0 0 0 0 0 0 0 – 1 1 1 1 0 0 0 0 0 0 0 – Repeat cycles 1 through 4 until nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 0 0 – Repeat cycles 1 through 4 until nRC - 1, truncate if needed ACT 0 0 1 1 0 0 0 0 0 F 0 – D 1 0 0 0 0 0 0 0 0 F 0 – D 1 0 0 0 0 0 0 0 0 F 0 – D# 1 1 1 1 0 0 0 0 0 F 0 – D# 1 1 1 1 0 0 0 0 0 F 0 – Repeat cycles nRC + 1 through nRC + 4 until nRC - 1 + nRAS -1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 F 0 – Repeat cycles nRC + 1 through nRC + 4 until 2 × RC - 1, truncate if needed Repeat sub-loop 0, use BA[2:0] = 1 2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7 nRAS Static HIGH 0 Toggling CAS# ACT D D D# D# RAS# Command 0 1 2 3 4 CS# Cycle Number IDD0 Measurement Loop Sub-loop CKE CK, CK# Table 9: nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRAS Notes: 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. Only selected bank (single) active. 30 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions nRCD nRAS Static HIGH Toggling 0 nRC nRC + 1 nRC + 2 nRC + 3 nRC + 4 nRC + nRCD nRC + nRAS Data3 A[2:0] 0 0 1 1 0 0 0 0 0 0 0 – 1 0 0 0 0 0 0 0 0 0 0 – 1 0 0 0 0 0 0 0 0 0 0 – 1 1 1 1 0 0 0 0 0 0 0 – 1 1 1 1 0 0 0 0 0 0 0 – Repeat cycles 1 through 4 until nRCD - 1, truncate if needed RD 0 1 0 1 0 0 0 0 0 0 0 00000000 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 0 0 – Repeat cycles 1 through 4 until nRC - 1, truncate if needed ACT 0 0 1 1 0 0 0 0 0 F 0 – D 1 0 0 0 0 0 0 0 0 F 0 – D 1 0 0 0 0 0 0 0 0 F 0 – D# 1 1 1 1 0 0 0 0 0 F 0 – D# 1 1 1 1 0 0 0 0 0 F 0 – Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed RD 0 1 0 1 0 0 0 0 0 F 0 00110011 Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed PRE 0 0 1 0 0 0 0 0 0 F 0 – Repeat cycle nRC + 1 through nRC + 4 until 2 × nRC - 1, truncate if needed Repeat sub-loop 0, use BA[2:0] = 1 1 2 × nRC 2 4 × nRC Repeat sub-loop 0, use BA[2:0] = 2 3 6 × nRC Repeat sub-loop 0, use BA[2:0] = 3 4 8 × nRC Repeat sub-loop 0, use BA[2:0] = 4 5 10 × nRC Repeat sub-loop 0, use BA[2:0] = 5 6 12 × nRC Repeat sub-loop 0, use BA[2:0] = 6 7 14 × nRC Repeat sub-loop 0, use BA[2:0] = 7 Notes: 1. 2. 3. 4. A[6:3] A[9:7] A[10] A[15:11] BA[2:0] ODT WE# CAS# ACT D D D# D# RAS# Command 0 1 2 3 4 CS# Cycle Number Sub-loop CKE CK, CK# Table 10: IDD1 Measurement Loop DQs, DQS, DQS# are mid-level unless driven as required by the READ (RD) command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. Only selected bank (single) active. 31 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions I 11: IDD Measurement Conditions for Power-Down Currents Table Name Timing pattern CKE External clock t CK t RC tRAS t RCD t RRD t RC CL AL CS# Command inputs Row/column addr Bank addresses DM Data I/O Output buffer DQ, DQS ODT2 Burst length Active banks Idle banks Special notes IDD2P0 Precharge Power-Down Current (Slow Exit)1 IDD2P1 Precharge Power-Down Current (Fast Exit)1 IDD2Q Precharge Quiet Standby Current IDD3P Active PowerDown Current n/a LOW Toggling t CK (MIN) IDD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a LOW Toggling tCK(MIN) I DD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a HIGH Toggling tCK(MIN) I DD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 None All n/a n/a LOW Toggling tCK (MIN) I DD n/a n/a n/a n/a n/a n/a n/a HIGH LOW LOW LOW LOW Mid-level Enabled Enabled, off 8 All None n/a Notes: 1. MR0[12] defines DLL on/off behavior during precharge power-down only; DLL on (fast exit, MR0[12] = 1) and DLL off (slow exit, MR0[12] = 0). 2. “Enabled, off“ means the MR bits are enabled, but the signal is LOW. 32 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data 0 0 0 0 – – – – A[10] 0 0 F F A[15:11] CAS# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 BA[2:0] RAS# 0 0 1 1 ODT CS# 1 1 1 1 WE# Command Static HIGH D D D# D# 1 0 1 2 3 4–7 2 8–11 Repeat sub-loop 0, use BA[2:0] = 2 3 12–15 Repeat sub-loop 0, use BA[2:0] = 3 4 16–19 Repeat sub-loop 0, use BA[2:0] = 4 5 20–23 Repeat sub-loop 0, use BA[2:0] = 5 6 24–27 Repeat sub-loop 0, use BA[2:0] = 6 7 28–31 Repeat sub-loop 0, use BA[2:0] = 7 0 Toggling Cycle Number Sub-loop CKE CK, CK# Table 12: IDD2N and IDD3N Measurement Loop Notes: 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. All banks closed during IDDD2N, all banks open during IDD3N. A[2:0] Data – – – – A[10] A[9:7] A[15:11] BA[2:0] 0 0 0 0 ODT RAS# 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat sub-loop 0, use BA[2:0] = 1; ODT = 0 WE# CS# 0 0 1 1 CAS# Command 1 1 1 1 A[6:3] Static HIGH D D D# D# 1 0 1 2 3 4–7 2 8–11 Repeat sub-loop 0, use BA[2:0] = 2; ODT = 1 3 12–15 Repeat sub-loop 0, use BA[2:0] = 3; ODT = 1 4 16–19 Repeat sub-loop 0, use BA[2:0] = 4; ODT = 0 5 20–23 Repeat sub-loop 0, use BA[2:0] = 5; ODT = 0 6 24–27 Repeat sub-loop 0, use BA[2:0] = 6; ODT = 1 7 28–31 Repeat sub-loop 0, use BA[2:0] = 7; ODT = 1 0 Toggling Cycle Number Sub-loop CKE CK, CK# Table 13: IDD2NT Measurement Loop Notes: 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. 3. All banks closed. 33 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data3 0 0 0 0 0 0 0 0 00000000 – – – 00110011 – – – A[10] 0 0 0 0 F F F F A[15:11] CAS# 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 BA[2:0] RAS# 1 0 1 1 1 0 1 1 ODT CS# 0 1 1 1 0 1 1 1 WE# Command Static HIGH RD D D# D# RD D D# D# 1 0 1 2 3 4 5 6 7 8–15 2 16–23 Repeat sub-loop 0, use BA[2:0] = 2 3 24–31 Repeat sub-loop 0, use BA[2:0] = 3 4 32–39 Repeat sub-loop 0, use BA[2:0] = 4 5 40–47 Repeat sub-loop 0, use BA[2:0] = 5 6 48–55 Repeat sub-loop 0, use BA[2:0] = 6 7 56–63 Repeat sub-loop 0, use BA[2:0] = 7 0 Toggling Cycle Number Sub-loop CKE CK, CK# Table 14: IDD4R Measurement Loop Notes: 1. 2. 3. 4. DQs, DQS, DQS# are mid-level when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. All banks open. 34 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions A[9:7] A[6:3] A[2:0] Data3 0 0 0 0 0 0 0 0 00000000 – – – 00110011 – – – A[10] 0 0 0 0 F F F F A[15:11] CAS# 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 0 Repeat sub-loop 0, use BA[2:0] = 1 BA[2:0] RAS# 1 0 1 1 1 0 1 1 ODT CS# 0 1 1 1 0 1 1 1 WE# Command Static HIGH WR D D# D# WR D D# D# 1 0 1 2 3 4 5 6 7 8–15 2 16–23 Repeat sub-loop 0, use BA[2:0] = 2 3 24–31 Repeat sub-loop 0, use BA[2:0] = 3 4 32–39 Repeat sub-loop 0, use BA[2:0] = 4 5 40–47 Repeat sub-loop 0, use BA[2:0] = 5 6 48–55 Repeat sub-loop 0, use BA[2:0] = 6 7 56–63 Repeat sub-loop 0, use BA[2:0] = 7 0 Toggling Cycle Number Sub-loop CKE CK, CK# Table 15: IDD4W Measurement Loop Notes: 1. 2. 3. 4. DQs, DQS, DQS# are mid-level when not driving in burst sequence. DM is LOW. Burst sequence is driven on each DQ signal by the WRITE (WR) command. All banks open. 35 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions Sub-loop Cycle Number Command CS# RAS# CAS# WE# ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data CKE CK, CK# Table 16: IDD5B Measurement Loop 0 0 REF 0 0 0 1 0 0 0 0 0 0 0 – D D D# D# 1 1 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 Repeat sub-loop 1a, use BA[2:0] = 1 0 0 F F 0 0 0 0 – – – – 1b 1 2 3 4 5–8 1c 9–12 Repeat sub-loop 1a, use BA[2:0] = 2 1d 13–16 Repeat sub-loop 1a, use BA[2:0] = 3 1e 17–20 Repeat sub-loop 1a, use BA[2:0] = 4 1f 21–24 Repeat sub-loop 1a, use BA[2:0] = 5 1g 25–28 Repeat sub-loop 1a, use BA[2:0] = 6 1h 29–32 Repeat sub-loop 1a, use BA[2:0] = 7 2 33–nRFC - 1 Repeat sub-loop 1a through 1h until nRFC - 1, truncate if needed Static HIGH Toggling 1a Notes: 1. DQs, DQS, DQS# are mid-level. 2. DM is LOW. Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test CKE External clock tCK t RC t RAS tRCD t RRD tRC CL AL CS# Command inputs Row/column addresses Bank addresses Data I/O Output buffer DQ, DQS ODT1 Burst length IDD6: Self Refresh Current Normal Temperature Range TC = 0°C to 85°C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0°C to 95°C IDD8: Reset2 LOW Off, CK and CK# = LOW n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, mid-level n/a LOW Off, CK and CK# = LOW n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Enabled Enabled, mid-level n/a Mid-level Mid-level n/a n/a n/a n/a n/a n/a n/a n/a Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level Mid-level n/a 36 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 IDD Test Active banks Idle banks SRT ASR IDD6: Self Refresh Current Normal Temperature Range TC = 0°C to 85°C IDD6ET: Self Refresh Current Extended Temperature Range TC = 0°C to 95°C IDD8: Reset2 n/a n/a disabled (normal) disabled n/a n/a enabled (extended) disabled None All n/a n/a Notes: 1. Enabled, mid-level means the MR command is enabled, but the signal is mid-level. 2. During a cold boot RESET (initialization), the current reading is valid once power is stable and RESET has been LOW for 1ms; during a warm boot RESET (while operating), the current reading is valid after RESET has been LOW for 200ns + tRFC. 37 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – IDD Specifications and Conditions 1 Static HIGH Toggling 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Notes: 1. 2. 3. 4. ACT RDA D D D ACT RDA D ACT RDA D D D Data3 A[2:0] A[6:3] A[9:7] A[10] 1 0 0 A[15:11] 0 1 0 BA[2:0] CAS# 0 0 1 ODT RAS# ACT RDA D WE# CS# 0 1 2 3 nRRD nRRD + 1 nRRD + 2 nRRD + 3 2 × nRRD 3 × nRRD 4 × nRRD 4 × nRRD + 1 nFAW nFAW + nRRD nFAW + 2 × nRRD nFAW + 3 × nRRD nFAW + 4 × nRRD nFAW + 4 × nRRD + 1 2 × nFAW 2 × nFAW + 1 2 × nFAW + 2 2 × nFAW + 3 2 × nFAW + nRRD 2 × nFAW + nRRD + 1 2 × nFAW + nRRD + 2 2 × nFAW + nRRD + 3 2 × nFAW + 2 × nRRD 2 × nFAW + 3 × nRRD 2 × nFAW + 4 × nRRD 2 × nFAW + 4 × nRRD + 1 3 × nFAW 3 × nFAW + nRRD 3 × nFAW + 2 × nRRD 3 × nFAW + 3 × nRRD 3 × nFAW + 4 × nRRD 3 × nFAW + 4 × nRRD + 1 Command 0 Cycle Number Sub-loop CKE CK, CK# Table 18: IDD7 Measurement Loop 1 0 0 0 0 0 0 0 – 1 0 0 0 1 0 0 0 00000000 0 0 0 0 0 0 0 0 – Repeat cycle 2 until nRRD - 1 0 0 1 1 0 1 0 0 0 F 0 – 0 1 0 1 0 1 0 1 0 F 0 00110011 1 0 0 0 0 1 0 0 0 F 0 – Repeat cycle nRRD + 2 until 2 × nRRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 1, use BA[2:0] = 3 1 0 0 0 0 3 0 0 0 F 0 – Repeat cycle 4 × nRRD until nFAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1 use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1 use BA[2:0] = 7 1 0 0 0 0 7 0 0 0 F 0 – Repeat cycle nFAW + 4 × nRRD until 2 × nFAW - 1, if needed 0 0 1 1 0 0 0 0 0 F 0 – 0 1 0 1 0 0 0 1 0 F 0 00110011 1 0 0 0 0 0 0 0 0 F 0 – Repeat cycle 2 × nFAW + 2 until 2 × nFAW + nRRD - 1 0 0 1 1 0 1 0 0 0 0 0 – 0 1 0 1 0 1 0 1 0 0 0 00000000 1 0 0 0 0 1 0 0 0 0 0 – Repeat cycle 2 × nFAW + nRRD + 2 until 2 × nFAW + 2 × nRRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 1 0 0 0 0 3 0 0 0 0 0 – Repeat cycle 2 × nFAW + 4 × nRRD until 3 × nFAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11 use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11 use BA[2:0] = 7 1 0 0 0 0 7 0 0 0 0 0 – Repeat cycle 3 × nFAW + 4 × nRRD until 4 × nFAW - 1, if needed DQs, DQS, DQS# are mid-level unless driven as required by the RD command. DM is LOW. Burst sequence is driven on each DQ signal by the RD command. AL = CL - 1. 38 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Characteristics – IDD Specifications Electrical Characteristics – IDD Specifications IDD values are for full operating range of voltage and temperature unless otherwise noted. Table 19: IDD Maximum Limits – Die Rev D Speed Bin IDD Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Notes IDD0 x4, x8 x16 x4 x8 x16 All All All All x4, x8 x16 All x4, x8 x16 x4 x8 x16 x4 x8 x16 All All All x4, x8 x16 All 60 75 70 77 105 20 30 39 42 40 45 53 52 68 135 147 220 115 125 180 205 22 28 210 260 IDD2P0 + 2mA 65 80 75 82 110 20 32 44 45 45 50 58 57 73 155 167 240 135 145 200 210 22 28 250 285 IDD2P0 + 2mA 75 90 80 87 115 20 37 47 50 50 55 63 62 77 175 187 280 155 165 225 220 22 28 290 320 IDD2P0 + 2mA 85 100 85 92 120 20 42 52 55 55 60 68 67 82 195 207 300 175 185 250 230 22 28 330 360 n/a mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2, 3 2, 4 1, 2 1, 2 1, 2 IDD1 IDD2P0 (slow) IDD2P1 (fast) IDD2Q IDD2N IDD2NT IDD3P IDD3N IDD4R IDD4W IDD5B IDD6 IDD6ET IDD7 IDD8 Notes: 1. 2. 3. 4. 5. TC = 85°C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = 85°C. TC = 85°C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0°C ≤ TC ≤ 85°C: 5a. When TC < 0°C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7% 5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2PX must be derated by 30%; and IDD6 must be derated by 80%. 39 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Characteristics – IDD Specifications Table 20: IDD Maximum Limits – Die Rev E Speed Bin IDD Width DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units Notes IDD0 x4, x8 tbd tbd tbd tbd mA 1, 2 IDD1 x16 tbd tbd tbd tbd mA 1, 2 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 x16 tbd tbd tbd tbd mA 1, 2 IDD2P0 (slow) All tbd tbd tbd tbd mA 1, 2 IDD2P1 (fast) All tbd tbd tbd tbd mA 1, 2 IDD2Q All tbd tbd tbd tbd mA 1, 2 IDD2N All tbd tbd tbd tbd mA 1, 2 IDD2NT x4, x8 tbd tbd tbd tbd mA 1, 2 x16 tbd tbd tbd tbd mA 1, 2 IDD3P All tbd tbd tbd tbd mA 1, 2 IDD3N All tbd tbd tbd tbd mA 1, 2 IDD4R x4 tbd tbd tbd tbd mA 1, 2 IDD4W x8 tbd tbd tbd tbd mA 1, 2 x16 tbd tbd tbd tbd mA 1, 2 x4 tbd tbd tbd tbd mA 1, 2 x8 tbd tbd tbd tbd mA 1, 2 x16 tbd tbd tbd tbd mA 1, 2 IDD5B All tbd tbd tbd tbd mA 1, 2 IDD6 All tbd tbd tbd tbd mA 1, 2, 3 IDD6ET All tbd tbd tbd tbd mA 2, 4 x4, x8 tbd tbd tbd tbd mA 1, 2 x16 tbd tbd tbd tbd mA 1, 2 All IDD2P + 2mA IDD2P + 2mA IDD2P + 2mA IDD2P + 2mA mA 1, 2 IDD7 IDD8 Notes: 1. 2. 3. 4. 5. TC = 85°C; SRT and ASR are disabled. Enabling ASR could increase IDDx by up to an additional 2mA. Restricted to TC (MAX) = 85°C. TC = 85°C; ASR and ODT are disabled; SRT is enabled. The IDD values must be derated (increased) on IT-option devices when operated outside of the range 0°C ≤ TC ≤ 85°C: 5a. When TC < 0°C: IDD2P and IDD3P must be derated by 4%; IDD4R and IDD5W must be derated by 2%; and IDD6 and IDD7 must be derated by 7% 5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5W must be derated by 2%; IDD2PX must be derated by 30%; and IDD6 must be derated by 80%. 40 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Electrical Specifications – DC and AC DC Operating Conditions Table 21: DC Electrical Characteristics and Operating Conditions All voltages are referenced to VSS Parameter/Condition Supply voltage I/O supply voltage Input leakage current Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.1V (All other pins not under test = 0V) VREF supply leakage current VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Symbol Min Nom Max Units Notes VDD VDDQ II 1.425 1.425 –2 1.5 1.5 – 1.575 1.575 2 V V µA 1, 2 1, 2 IVREF –1 – 1 µA 3, 4 Notes: 1. VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ. 2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the DC (0Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters. 3. VREF (see Table 21). 4. The minimum limit requirement is for testing purposes. The leakage current on the VREF pin should be minimal. Input Operating Conditions Table 22: DC Electrical Characteristics and Input Conditions All voltages are referenced to VSS Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Input reference voltage command/address bus I/O reference voltage DQ bus I/O reference voltage DQ bus in SELF REFRESH Command/address termination voltage (system level, not direct DRAM input) Symbol Min Nom Max Units Notes VIL VIH VSS See Table 20 0.49 × VDD 0.49 × VDD VSS – n/a n/a 0.5 × VDD 0.5 × VDD 0.5 × VDD 0.5 × VDDQ See Table 20 VDD 0.51 × VDD 0.51 × VDD VDD – V V V V V V 1, 2 2, 3 4 5 VREFCA(DC) VREFDQ(DC) VREFDQ(SR) VTT Notes: 1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC). 2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency. 3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC). 4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH, within restrictions outlined in the SELF REFRESH section. 5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and MAX values are system-dependent. 41 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Table 23: Input Switching Conditions Parameter/Condition Symbol DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Units 175 +150 – – +100 –100 +100 – –150 –175 – – +135 +125 +100 –100 –125 –130 – – mV mV mV mV mV mV mV mV mV mV – +150 – +100 –100 – –150 – – – +135 +100 –100 –135 – – mV mV mV mV mV mV mV mV Command and Address Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low DC voltage: Logic 0 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 VIH(AC175) MIN VIH(AC150) MIN VIH(AC135) MIN VIH(AC125) MIN VIH(DC100) MIN VIL(DC100) MAX VIL(DC125) MAX VIL(DC130) MAX VIL(AC150) MAX VIL(AC175) MAX +175 +150 – – +100 –100 +100 – –150 –175 DQ and DM Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high AC voltage: Logic 1 Input high DC voltage: Logic 1 Input low DC voltage: Logic 0 Input low DC voltage: Logic 0 Input low AC voltage: Logic 0 Input low AC voltage: Logic 0 VIH(AC175) MIN VIH(AC150) MIN VIH(AC135) MIN VIH(DC100) MIN VIL(DC100) MAX VIL(DC135) MAX VIL(AC150) MAX VIL(AC)175 MAX +175 +150 – +100 –100 – –150 –175 Notes: 1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs. 2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC). 3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC). 4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak). 42 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Figure 13: Input Signal VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V VDDQ 0.925V VIH(AC) 0.850V VIH(DC) Minimum VIL and VIH levels 0.925V 0.850V VIH(AC) VIH(DC) 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V 0.650V 0.575V VIL(DC) VIL(AC) VREF + AC noise VREF + DC error VREF - DC error VREF - AC noise 0.650V VIL(DC) 0.575V VIL(AC) 0.0V VSS VSS - 0.4V narrow pulse width –0.40V Notes: 1. Numbers in diagrams reflect nominal values. AC Overshoot/Undershoot Specification Table 24: Control and Address Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 14 on page 44) Maximum peak amplitude allowed for undershoot area (see Figure 15 on page 44) Maximum overshoot area above VDD (see Figure 14 on page 44) Maximum undershoot area below VSS (see Figure 15 on page 44) 43 DDR3800 DDR31066 DDR31333 DDR31600 DDR31866 0.4V 0.4V 0.4V 0.4V TBD 0.4V 0.4V 0.4V 0.4V TBD 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns TBD 0.67 Vns 0.5 Vns 0.4 Vns 0.33 Vns TBD Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Table 25: Clock, Data, Strobe, and Mask Pins Parameter Maximum peak amplitude allowed for overshoot area (see Figure 14 on page 44) Maximum peak amplitude allowed for undershoot area (see Figure 15 on page 44) Maximum overshoot area above VDD/VDDQ (see Figure 14 on page 44) Maximum undershoot area below VSS/VSSQ (see Figure 15 on page 44) DDR3800 DDR31066 DDR31333 DDR31600 DDR31866 0.4V 0.4V 0.4V 0.4V TBD 0.4V 0.4V 0.4V 0.4V TBD 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns TBD 0.25 Vns 0.19 Vns 0.15 Vns 0.13 Vns TBD Figure 14: Overshoot Maximum amplitude Overshoot area Volts (V) VDD/VDDQ Time (ns) Figure 15: Undershoot VSS/VSSQ Volts (V) Undershoot area Maximum amplitude Time (ns) 44 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Table 26: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) Parameter/Condition Differential input voltage logic high - slew Differential input voltage logic low - slew Differential input voltage logic high Differential input voltage logic low Differential input crossing voltage relative to VDD/2 for DQS, DQS#; CK, CK# Differential input crossing voltage relative to VDD/2 for CK, CK# Single-ended high level for strobes Single-ended high level for CK, CK# Single-ended low level for strobes Single-ended low level for CK, CK# Symbol Min Max Units Notes VIHDIFF(AC)slew VILDIFF(AC)slew VIHDIFF(AC) VILDIFF(AC) +200 n/a 2 × (VIH(AC)-VREF) VSS/VSSQ VREF(DC) - 150 n/a –200 VDD/VDDQ 2 × (VREF - VIL(AC)) VREF(DC) + 150 mV mV mV mV mV 4 4 5 6 7 VREF(DC) - 175 VREF(DC) + 175 mV 7, 8 VDDQ/2 + VIH(AC) VDD/2 + VIH(AC) VSSQ VSS VDDQ VDD VDDQ/2 - VIL(AC) VDD/2 - VIL(AC) mV mV mV mV 5 5 6 6 VIX VIX (175) VSHE VSEL Notes: 1. 2. 3. 4. 5. 6. 7. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ. Reference is VREFCA(DC) for clock and for VREFDQ(DC) for strobe. Differential input slew rate = 2 V/ns Defines slewrate reference points, relative to input crossing voltages. MAX limit is relative to single-ended signals, the overshoot specifications are applicable. MIN limit is relative to single-ended signals, the undershoot specifications are applicable. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device, and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which differential input signals must cross. 8. The VIX extended range (±175mV) is allowed only for the clock, and this VIX extended range is only allowed when the following conditions are met: The single-ended input signals are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and the differential slew rate of CK, CK# is greater than 3 V/ns. Figure 16: VIX for Differential Signals Vdd, Vddq Vdd, Vddq CK#, DQS# CK#, DQS# X Vix Vix Vdd/2, Vddq/2 X X Vdd/2, Vddq/2 Vix X CK, DQS Vix CK, DQS Vss, Vssq Vss, Vssq 45 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Figure 17: Single-Ended Requirements for Differential Signals VDD or VDDQ VSEH (MIN) VDD/2 or VDDQ/2 VSEH CK or DQS VSEL (MAX) VSEL VSS or VSSQ 46 Preliminary 4Gb: x4, x8, x16 DDR3 SRAM Electrical Specifications – DC and AC Figure 18: Definition of Differential AC-Swing and tDVAC tDVAC VIHDIFF(AC) MIN VIHDIFF (MIN) VIHDIFF(DC) MIN CK - CK# DQS - DQS# 0.0 VILDIFF(DC) MAX VILDIFF (MAX) VILDIFF(AC) MAX tDVAC half cycle Table 27: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS - DQS# Below VIL(AC) t DVAC (ps) at |VIHDIFF(AC) to VILDIFF(AC)| Slew Rate (V/ns) 350mV 300mV >4.0 4.0 3.0 2.0 1.9 1.6 1.4 1.2 1.0