ZD25WD40B
ZD25WD40B
Ultra Low Power, 4M-bit
Serial Multi I/O Flash Memory Datasheet
Performance Highlight
Wide Supply Range from 1.65 to 2.0V for Read, Erase and Program
Ultra Low Power consumption for Read, Erase and Program
X1 and X2 Multi I/O Support
High reliability with 100K cycling and 20 Year-retention
1
ZD25WD40B
1.
2.
3.
4.
5.
Contents
Overview.............................................................................................................................................. 4
1.1.
General....................................................................................................................................4
1.2.
Performance............................................................................................................................4
1.3.
Software features.................................................................................................................... 5
1.4.
Hardware features...................................................................................................................5
Description............................................................................................................................................6
2.1.
Pin Definition......................................................................................................................... 7
2.2.
Block Diagram........................................................................................................................7
2.3.
Memory Address Mapping..................................................................................................... 8
Device Operation.................................................................................................................................. 9
3.1.
Mode0 and Mode3..................................................................................................................9
3.2.
IO MODE............................................................................................................................... 9
3.3.
Status Register...................................................................................................................... 10
3.4.
Data Protection..................................................................................................................... 11
Electrical Specifications..................................................................................................................... 14
4.1.
Absolute Maximum Ratings................................................................................................. 14
4.2.
DC Characteristics................................................................................................................15
4.3.
AC Characteristics................................................................................................................ 16
4.4.
AC Characteristics for Program and Erase...........................................................................17
4.5.
Operation Conditions............................................................................................................19
Commands.......................................................................................................................................... 21
5.1.
Commands listing................................................................................................................. 21
5.2.
Write Enable (WREN)..........................................................................................................23
5.3.
Write Disable (WRDI)..........................................................................................................23
5.4.
Write Enable for Volatile Status Register............................................................................ 24
5.5.
Read Status Register (RDSR)............................................................................................... 25
5.6.
Active Status Interrupt (ASI)................................................................................................26
5.7.
Write Status Register (WRSR).............................................................................................. 27
5.8.
Read Data Bytes (READ).....................................................................................................28
5.9.
Read Data Bytes at HigherSpeed (FAST_READ)............................................................... 29
5.10.
Dual Read Mode (DREAD)..................................................................................................30
5.11.
2 X IO Read Mode (2READ)................................................................................................31
5.12.
2 X IO Read PerformerEnhance Mode................................................................................. 32
5.13.
Page Erase (PE).....................................................................................................................33
5.14.
Sector Erase (SE)...................................................................................................................33
5.15.
Block Erase (BE32K)............................................................................................................35
5.16.
Block Erase (BE)...................................................................................................................35
5.17.
Chip Erase (CE).................................................................................................................... 36
5.18.
Page Program (PP)................................................................................................................37
5.19.
Dual Input Page Program (DPP)........................................................................................... 38
5.20.
Erase Security Registers (ERSCUR)..................................................................................... 39
5.21.
Program Security Registers (PRSCUR).................................................................................40
5.22.
Erase Security Registers (RDSCUR)....................................................................................41
5.23.
Deep Power-down (DP)........................................................................................................42
5.24.
Release form Deep Power-Down (RDP), Read Electronic Signature (RES)..........................43
5.25.
Read Electronic Manufacturer ID & Device ID (REMS).......................................................44
5.26.
Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS).....................................45
5.27.
Read Identification (RDID)................................................................................................... 46
5.28.
Program/Erase Suspend/Resume.......................................................................................... 47
2
ZD25WD40B
6.
7.
8.
5.29.
Erase Suspend to Program.................................................................................................... 48
5.30.
Program Resume and Erase Resume..................................................................................... 49
5.31.
No Operation (NOP)............................................................................................................. 49
5.32.
Software Reset (RSTEN/RST).............................................................................................. 50
5.33.
Read Unique ID (RUID)........................................................................................................51
5.34.
Read SFDP Mode (RDSFDP)...............................................................................................52
Ordering Information..........................................................................................................................55
Package Information...........................................................................................................................56
7.1.
8-Lead SOP(150mil).............................................................................................................56
7.2.
8-Lead SOP(208mil).............................................................................................................57
7.3.
8-Lead TSSOP(173mil)........................................................................................................ 58
7.4.
8-Land USON(3x2mm,THICKNESS 0.55MM)..................................................................59
7.5.
8-Land USON(3x2mm,THICKNESS 0.45MM)..................................................................60
7.6.
8-Land USON(1.5x1.5mm).................................................................................................. 61
Revision History................................................................................................................................62
3
ZD25WD40B
1. Overview
1.1. General
Single 1.65V to 2.0V supply
-
1.65V-2.0V for Read, Erase and Program Operations
Industrial Temperature Range -40C to 85C
Serial Peripheral Interface (SPI) Compatible:
-
Mode 0 and Mode 3
Single and Dual IO mode
4M x 1 bit
-
2M x 2 bits
Flexible Architecture for Code and Data Storage
-
Uniform 256-byte
Page Program
-
Uniform 256-byte
Page Erase
-
Uniform 4K-byte
Sector Erase
-
Uniform 32K/64K-byte
-
Full Chip Erase
Block Erase
1.2. Performance
Fast read
-
2 I/O
104MHz with 4 dummy cycles，equivalent to 208M
-
1 I/O
104MHz with 8 dummy cycles
Fast Program and Erase Speed
-
1.3ms
Page program time
-
10ms
Page erase time
-
10ms
4K-byte sector erase time
-
10ms
32K-byte block erase time
-
10ms
64K-byte block erase time
Ultra Low Power Consumption
-
0.1uA
Deep Power Down current
-
9uA
Standby current
-
0.6mA
Active Read current at 33MHz
-
1.8mA
Active Program or Erase current
High Reliability
-
100,000 Program / Erase Cycles
-
20-year Data Retention
4
ZD25WD40B
1.3. Software features
One Time Programmable (OTP) Security Register
3*512-Byte Security Registers With OTP Lock
Software Protection Mode
-
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the memory array that can be
read but not change.
128 bit unique ID for each device
Program/Erase Suspend and Program/Erase Resume
JEDEC Standard Manufacturer and Device ID Read Methodology
1.4. Hardware features
Hardware Protection Mode
-
Hardware Controlled Locking of Protected Sectors by WP Pin
Industry Standard Green Package Options
-
8-PACKAGE
SOP (150mil/208mil)
-
8-PACKAGE
USON (3x2x0.55mm)
-
8-PACKAGE
USON (3x2x0.45mm)
-
8-PACKAGE
USON (1.5x1.5mm)
5
ZD25WD40B
2. Description
The ZD25WD40B is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or
external RAM for execution. The flexible erase architecture of the device, with its page erase granularity it is
ideal for data storage as well, eliminating the need for additional data storage devices.
The erase block sizes of the device have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently.
Because certain code modules and data storage segments must reside by themselves in their own erase
regions, the wasted and unused memory space that occurs with large sectored and large block erase Flash
memory devices can be greatly reduced. This increased memory space efficiency allows additional code
routines and data storage segments to be added while still maintaining the same overall device density.
The device also contains an additional 3*512-byte security registers with OTP lock (One-Time
Programmable), can be used for purposes such as unique device serialization, system-level Electronic Serial
Number (ESN) storage, locked key storage, etc.
Specifically designed for use in many different systems, the device supports read, program, and erase
operations with a wide supply voltage range of 1.65V to 2.0V. No separate voltage is required for
programming and erasing.
6
ZD25WD40B
2.1. Pin Definition
Pin Configurations
CS#
SO
WP#
GND
1
8
2
7
3
6
4
5
Vcc
NC#
SCLK
SI
8-PIN SOP (150mil/200mil) and TSSOP
Pin Descriptions
No.
Symbol
Extension
Remarks
1
CS#
Chip select
2
SO
SIO1
3
4
WP#
GND
SIO2
-
5
SI
SIO0
6
7
SCLK
Nc
-
Serial data output for 1 x I/O
Serial data input and output for 2 x I/O read mode
Write protection active low
Ground of the device
Serial data input for 1x I/O
Serial data input and output for 2 x I/O read mode
Serial interface clock input
Not Connection
8
VCC
-
Power supply of the device
2.2. Block Diagram
Din
Hv PageLatch
High Voltage
Generator
(O3)
R
o
w
SI(IO0)
SCLK
WP#(IO2)
SO(IO1)
SPI
Command &
Control Logic
D
e
c
o
d
e
r
High Voltage
Control
Flash- cell Array
Address
Latch
CS
Coumun Mux
Dout
Sense Amplifier
7
ZD25WD40B
2.3. Memory Address Mapping
The memory array can be erased in three levels of granularity including a full chip erase. The size of the erase
blocks is optimized for both code and data storage applications, allowing both code and data segments to
reside in their own erase regions.
ZD25WD40B Memory Organization
Block64K
……
……
1-0
0
……
3-2
1
……
5-4
2
13 - 12
6
15 - 14
7
Block32K
Sector
Address Range
127
07F000H
07FFFFH
……
……
……
112
070000H
070FFFH
111
06F000H
06FFFFH
……
……
……
96
060000H
060FFFH
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
……
47
02F000H
02FFFFH
……
……
……
32
020000H
020FFFH
31
01F000H
01FFFFH
……
……
……
16
010000H
010FFFH
15
00F000H
00FFFFH
……
……
……
0
000000H
000FFFH
8
ZD25WD40B
3. Device Operation
3.1. Mode0 and Mode3
Before a command is issued, status register should be checked to ensure device is ready for the intended
operation.
When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. When correct
command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS#
rising edge.
Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of
SCLK.The difference of serial peripheral interface mode 0 and mode 3 is shown as Figure 3-1.
For the following instructions: RDID, RDSR, RDSR1, RDSCUR, READ, FAST_READ, DREAD, 2READ,
RDSFDP, RES, REMS, DREMS, the shifted-in instruction sequence is followed by a data-out sequence.
After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI,
WRSR, PE, SE, BE32K, BE, CE, PP, DPP, DP, ERSCUR, PRSCUR,
SUSPEND, RESUME, RSTEN, RST, the CS# must go high exactly at the byte boundary; otherwise, the
instruction will be rejected and not executed.
During the progress of Write Status Register, Program, Erase operation, to access the memory array is
neglected and not affect the current operation of Write Status Register, Program, Erase.
Figure 3-1 Serial Peripheral Interface Modes Supported
CPOL CPHA
shift in
(Serial mode 0) 0
0
SCLK
(Serial mode 3) 1
1
SCLK
SI
SO
shift
out
MSB
MSB
Note:
CPOL indicates clock polarity of serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA
indicates clock phase. The combination of CPOL bit and CPHA bit decides which serial mode is supported.
3.2. IO MODE
Standard SPI
The ZD25WD40B features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select
(CS#), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input
data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK.
Dual SPI
The ZD25WD40B supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast
9
ZD25WD40B
Read”(3BHand BBH) commands. These commands allow data to be transferred to or from the device
at two times the rate of the standard SPI. When using the Dual SPI command the SI and SO pins become
bidirectional I/O pins: IO0 and IO1.
3.3. Status Register
S15
SUS1
S14
CMP
S13
LB3
S12
LB2
S11
LB1
S10
SUS2
S9
Reserved
S8
SRP1
S7
SRP0
S6
BP4
S5
BP3
S4
BP2
S3
BP1
S2
BP0
S1
WEL
S0
WIP
The definition of the status register bits is as below:
WIP bit.
The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register
progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress,
when WIP bit sets 0, means the device is not in program/erase/write status register progress.
WEL bit.
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the
internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status
Register, Program or Erase command isaccepted.
BP4, BP3, BP2, BP1, BP0 bits.
The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase commands. These bits are written with the Write Status Register
(WRSR) command. When the Block Protect (BP4, BP3, BP2, BP1, BP0) bits are set to 1, the relevant memory
area (as defined in Table “Protected Area Sizes”).becomes protected against Page Program (PP), Page Erase
(PE), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP4, BP3, BP2, BP1, and BP0)
bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE)
command is executed, only if the Block Protect (BP4, BP3, BP2, BP1and BP0) are set to “None protected”.
SRP1, SRP0 bits.
The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The
SRP bits control the method of write protection: software protection, hardware protection, power supply
lock-down or one time programmable protection
SRP1
SRP0
WP#
Status Register
0
0
x
Software Protected
0
1
0
Hardware Protected
0
1
1
Hardware Unprotected
1
0
x
1
1
x
Description
The Status Register can be written to after a
Write Enable command, WEL=1.(Default)
WP#=0, the Status Register locked and can not
be write to.
WP#=1, the Status Register is unlocked and can
be written to after a Write Enable command, WEL=1.
Power Supply
Status Register is protected and can not be written to
Lock-Down(1)
again until the next Power-Down, Power-Up cycle.
One Time Program(2)
Status Register is permanently protected and can not be
written to.
10
ZD25WD40B
NOTE:
1. When SRP1, SRP0=(1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
2. This feature is available on special order. Please contact Zetta fordetails.
LB3, LB2, LB1, bits.
The LB3, LB2, LB1, bits are non-volatile One Time Program (OTP) bits in Status Register (S13-S11) that provide
the write protect control and status to the Security Registers. The default state of LB3-LB1are0, the security
registers are unlocked. The LB3-LB1bitscan be set to 1 individually using the Write Register instruction. The
LB3-LB1bits are One Time Programmable, once its set to 1, the Security Registers will become read-only
permanently.
CMP bit
The CMP bit is a non-volatile Read/Write bit in the Status Register(S14). It is used in conjunction the BP4-BP0
bits to provide more flexibility for the array protection. Please see the table “Protected Area Size” for details.
The default setting is CMP=0.
SUS1, SUS2 bit
The SUS1 and SUS2bit are read only bit in the status register (S15and S10) that are set to 1 after interrupting an
program/erase/write status register progress by Program/Erase Suspend (75H or B0H) command (The Erase
Suspend will set the SUS1 to 1,and the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bit are
cleared to 0 by Program/Erase Resume (7AH or 30H) command as well as a power-down, power-up cycle.
3.4. Data Protection
During power transition, there may be some false system level signals which result in inadvertent erasure or
programming. The device is designed to protect itself from these accidental write cycles.
The state machine will be reset as standby mode automatically during power up. In addition, the control
register architecture of the device constrains that the memory contents can only be changed after specific
command sequences have completed successfully.
In the following, there are several features to protect the system from the accidental write cycles during VCC
power-up and power-down or from system noise.
• Power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may
protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and
completed on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL)
before issuing other commands to change data.
• Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1, and BP0) bits define the section of the
memory array that can be read but not change.
• Hardware Protection Mode: WP# going low to protected the BP0~BP4bits and SRP0~1bits
• Deep Power-Down Mode: By entering deep power down mode, the flash device is under protected from
writing all commands except the Release form Deep Power-Down Mode command.
11
ZD25WD40B
Table 3-1. Protected Area Sizes
ZD25WD40B Protected Area Sizes (CMP bit = 0)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
NONE
NONE
NONE
NONE
0
0
0
0
1
7
070000H-07FFFFH
64KB
Upper 1/8
0
0
0
1
0
6 and 7
060000H-07FFFFH
128KB
Upper 1/4
0
0
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
1
0
0
1
0
000000H-00FFFFH
64KB
Lower 1/8
0
1
0
1
0
0 and 1
000000H-01FFFFH
128KB
Lower 1/4
0
1
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
x
1
x
x
0 to 7
000000H-07FFFFH
512KB
ALL
1
0
0
0
1
7
07F000H-07FFFFH
4KB
Upper 1/128
1
0
0
1
0
7
07E000H-07FFFFH
8KB
Upper 1/64
1
0
0
1
1
7
07C000H-07FFFFH
16KB
Upper 1/32
1
0
1
0
x
7
078000H- 07FFFFH
32KB
Upper 1/16
1
0
1
1
0
7
078000H-07FFFFH
32KB
Upper 1/16
1
1
0
0
1
0
000000H-000FFFH
4KB
Lower 1/128
1
1
0
1
0
0
000000H-001FFFH
8KB
Lower 1/64
1
1
0
1
1
0
000000H-003FFFH
16KB
Lower 1/32
1
1
1
0
x
0
000000H-007FFFH
32KB
Lower 1/16
1
1
1
1
0
0
000000H-007FFFH
32KB
Lower 1/16
1
x
1
1
1
0 to 7
000000H-07FFFFH
512KB
ALL
12
ZD25WD40B
ZD25WD40B Protected Area Sizes (CMP bit = 1)
Status bit
Memory Content
BP4
BP3
BP2
BP1
BP0
Blocks
Addresses
Density
Portion
x
x
0
0
0
0 to 7
000000H-07FFFFH
512KB
ALL
0
0
0
0
1
0 to 6
000000H-06FFFFH
448KB
Lower 7/8
0
0
0
1
0
0 to 5
000000H-05FFFFH
384KB
Lower 3/4
0
0
0
1
1
0 to 3
000000H-03FFFFH
256KB
Lower 1/2
0
1
0
0
1
1 to 7
010000H-07FFFFH
448KB
Upper 7/8
0
1
0
1
0
2 to 7
020000H-07FFFFH
384KB
Upper 3/4
0
1
0
1
1
4 to 7
040000H-07FFFFH
256KB
Upper 1/2
0
x
1
x
x
NONE
NONE
NONE
NONE
1
0
0
0
1
0 to 7
000000H-07EFFFH
508KB
Lower 127/128
1
0
0
1
0
0 to 7
000000H-07DFFFH
504KB
Lower 63/64
1
0
0
1
1
0 to 7
000000H-07BFFFH
496KB
Lower 31/32
1
0
1
0
x
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
0
1
1
0
0 to 7
000000H-077FFFH
480KB
Lower 15/16
1
1
0
0
1
0 to 7
001000-07FFFFH
508KB
Upper 127/128
1
1
0
1
0
0 to 7
002000-07FFFFH
504KB
Upper 63/64
1
1
0
1
1
0 to 7
004000-07FFFFH
496KB
Upper 31/32
1
1
1
0
x
0 to 7
008000-07FFFFH
480KB
Upper 15/16
1
1
1
1
0
0 to 7
008000-07FFFFH
480KB
Upper 15/16
1
x
1
1
1
NONE
NONE
NONE
NONE
Note:
1. X=don’t care
2. If any erase or program command specifies a memory that contains protected data portion, this command will be ignored.
13
ZD25WD40B
4. Electrical Specifications
4.1. Absolute Maximum Ratings
Parameters
Value
Storage Temperature
-65°C to +150°C
Operation Temperature
.-40°C to +85°C
Maximum Operation Voltage
2.5V
Voltage on Any Pin with respect to Ground
-0.6V to + 2.5V
DC Output Current
5.0 mA
NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Figure 4-1 Maximum Overshoot Waveform
Maxinum Positive Overshoot Waveform
Maxinum Negative Overshoot Waveform
VCC+0.5V
20ns
0V
VCC
20ns
-0.6V
Table 4-1 Pin Capacitance [1]
Symbol
Parameter
Max.
Units
Test Condition
COUT
Output Capacitance
8
pF
VOUT=GND
CIN
Input Capacitance
6
pF
VIN=GND
Note:
Test Conditions: TA = 25°C, F = 1MHz, Vcc = 3.0V.
Figure 4-2 Input Test Waveforms and Measurement Level
Input timing referencelevel
0.7VCC
0.3VCC
Output timing referencelevel
Ac MersurementLevel
0.5VCC
Note：Inputpulse rise and fall time eara < 5ns
Figure 4-3 Output Loading
25K ohm
DEVICE
UNDER
TEST
VCC
CL
25K ohm
CL=15/30pF Including jig capacitance
14
ZD25WD40B
4.2. DC Characteristics
Table 4-2 DC parameters
Sym.
Parameter
IDPD
Deep power down
current
ISB
Standby current
ICC1
Low power read
current (03h)
ICC2
Read current (0Bh)
ICC3
ICC4
Conditions
1.65V to 2.0V
Min.
CS#=Vcc, all other
inputs at 0V or Vcc
CS#, WP#=VIH
all inputs at CMOS levels
f=33MHz; IOUT=0mA
Typ.
Max.
0.1
0.6
9
Units
uA
uA
0.6
1.2
f=55MHz; IOUT=0mA
f=85MHz; IOUT=0mA
0.9
1.3
1.5
2.0
mA
mA
mA
mA
Program current
CS#=Vcc
1.8
3.0
mA
Erase current
CS#=Vcc
1.8
3.0
mA
ILI
ILO
Input load current
All inputs at CMOS level
1.0
uA
Output leakage
All inputs at CMOS level
1.0
uA
VIL
VIH
Input low voltage
0.3Vcc
V
VOL
VOH
Output low voltage
IOL=100uA
Output high voltage
IOH=-100uA
Input high voltage
0.7Vcc
V
0.2
Vcc-0.2
V
V
Note
1. Typical values measured at 1.8V @ 25°C .
15
ZD25WD40B
4.3. AC Characteristics
Symbol
Alt.
fSCLK
fC
1.65V~2.0V
Parameter
Clock
Frequency
for
the
min
.
max
.
Unit
D.C.
85
MHz
following
instructions: FAST_READ, RDSFDP, PP, SE, BE32K,
BE, CE, DP, RES,
fRSCLK
fR
Clock Frequency for READ instructions
33
MHz
fTSCLK
fT
Clock Frequency for 2READ,DREAD instructions
85
MHz
tCH(1)
tCLH
Clock High Time
tCL(1)
tCLL
Clock Low Time
tCLCH(7)
tCHCL(7)
tSLCH
tCSS
tCHSL
4.5
ns
4.5
ns
Clock Rise Time (peak to peak)
0.1
ns/v
Clock Fall Time (peak to peak)
0.1
ns/v
CS# Active Setup Time (relative to SCLK)
5
ns
CS# Not Active Hold Time (relative to SCLK)
5
ns
(fSCLK) 45% x (1fSCLK)
tDVCH
tDSU
Data In Setup Time
2
ns
tCHDX
tDH
Data In Hold Time
3
ns
tCHSH
CS# Active Hold Time (relative to SCLK)
5
ns
tSHCH
CS# Not Active Setup Time (relative to SCLK)
5
ns
CS# Deselect Time From Read to next Read
15
ns
30
ns
tSHSL
tCSH
CS# Deselect Time From Write,Erase,Program to
Read Status Register
tSHQZ(7)
tDIS
Output Disable Time
6
ns
Clock Low to Output Valid Loading 30pF
7
ns
Clock Low to Output Valid Loading 15pF
6
ns
tCLQV
tV
tCLQX
tHO
Output Hold Time
0
ns
tWHSL(3)
Write Protect Setup Time
20
ns
tSHWL(3)
Write Protect Hold Time
100
ns
tDP
CS# High to Deep Power-down Mode
CS# High To Standby Mode Without Electronic Signature
tRES1
Read
CS# High To Standby Mode Without Electronic Signature
tRES2
tW
tReady
Read
Write Status Register Cycle Time
Reset recovery time(for erase/program operation except
WRSR)
Reset recovery time(for WRSR operation)
8
3
us
8
us
8
us
12
ms
30
us
8
12
ms
Table 4-3 AC parameters
16
ZD25WD40B
4.4. AC Characteristics for Program and Erase
Table 4-4 AC parameters fro program and erase
Sym.
Parameter
1.65V to 2.0V
Min.
Typ.
Max.
Units
TESL(6)
TPSL(6)
Erase Suspend Latency
30
us
Program Suspend Latency
30
us
TPRS(4)
TERS(5)
Latency between Program Resume and next Suspend
0.3
Latency between Erase Resume and next Suspend
0.3
us
us
tPP
tPE
Page program time (up to 256 bytes)
1.3
1.6
ms
Page erase time
10
12
ms
tSE
tBE1
Sector erase time
10
12
ms
Block erase time for 32K bytes
10
12
ms
Block erase time for 64K bytes
10
12
ms
Chip erase time
10
12
ms
tBE2
tCE
Note
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values givenfor TA=25°C. Not 100% tested.
3. Only applicable as a constraint for a WRSR instruction.
4. Program operation may be interrupted as often as system request. The minimum timing of tPRS must be
observed before issuing the next program suspend command. However, in order for an Program operation to make
progress, tPRS ≥ 100us must be included in resume-to-suspend loop(s). Not 100% tested.
5. Erase operation may be interrupted as often as system request. The minimum timing of tERS must be observed
before issuing the next erase suspend command. However, in order for an Erase operation to make progress, tERS
≥ 200us must be included in resume-to-suspend loop(s). Notes. Not 100% tested.
6. Latency time is required to complete Erase/Program Suspend operation.
7. The value guaranteed by characterization, not 100% tested in production.
Figure 4-4 Serial Input Timing
tSHSL
CS#
tCHSL
SCLK
tSLCH
tCLH tCLL
tDVCH
tCHDX
SI
MSB
SO
High - Z
tCHSH
tSHCH
tCHCL
tCLCH
LSB
17
ZD25WD40B
Figure 4-5 Output Timing
CS#
tSHQZ
tCLH
SCLK
tCLQV
tCLQX
tCLQV
tCLQX
tCLL
tQLQH
LSB
tQHQL
SO
SI
Least
significant address bit (LIB) in
18
ZD25WD40B
4.5. Operation Conditions
At Device Power-Up and Power-Down
AC timing illustrated in "Figure AC Timing at Device Power-Up" and "Figure Power-Down Sequence" are for
the supply voltages and the control signals at device power-up and power-down. If the timing in the figures is
ignored, the device will not operatecorrectly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to
be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 4-7 AC Timing at Device Power-Up
VCC
VCC( min)
GND
tVR
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
LSB
MSB
SI
tCLCH
High-Z
SO
Figure 4-8 Power-Up Timing
Vcc(max)
Chip Selectionis not allowed
Vcc(min)
VWI
tVSL
Device is fully accessible
Time
19
ZD25WD40B
Power Up/Down and Voltage Drop
For Power-down to Power-up operation, the VCC of flash device must below VPWD for at least tPWD timing.
Please check the table below for more detail.
Figure 4-9 Power down-up Timing
Vcc(max)
Chip Selection is not allowed
Vcc(min)
tVSL
VPWD(max)
Device is fully
accessible
tPWD
Time
Symbol
Parameter
VPWD
VCC voltage needed to below VPWD for ensuring
initialization will occur
tPWD
tVSL
tVR
VWI
The minimum duration for ensuring initialization will occur
VCC(min.) to device operation
VCC Rise Time
Write Inhibit Voltage
min
300
70
1
1.45
max
unit
1
V
500000
1.55
us
us
us/V
V
20
ZD25WD40B
5.
Commands
5.1. Commands listing
Figure 5-1 Command set
Abbr.
Code
ADR
Bytes
Read Array (fast)
FREAD
0Bh
3
1
1+
n bytes read out until CS# goes high
Read Array (low power)
READ
03h
3
0
1+
n bytes read out until CS# goes high
Read Dual Output
DREAD
3Bh
3
1
1+
n bytes read out by Dual output
Read 2x I/O
2READ
BBh
3
1
1+
n bytes read out by 2 x I/O
Page Erase
PE
81h
3
0
0
erase selected page
Sector Erase (4K bytes)
SE
20h
3
0
0
erase selected sector
Block Erase (32K bytes)
BE32
52h
3
0
0
erase selected 32K block
Block Erase (64K bytes)
BE64
D8h
3
0
0
erase selected 64K block
CE
60h
0
0
0
erase whole chip
C7h
0
0
0
erase whole chip
Commands
DMY
Bytes
Data
Bytes
Function description
Read
Program and Erase
Chip Erase
Page Program
PP
02h
3
0
1+
program selected page
Dual-IN Page Program
2PP
A2h
3
0
1+
program selected page by Dual input
Program/Erase Suspend
PES
75h
0
0
0
suspend program/erase operation
B0h
0
0
0
suspend program/erase operation
7Ah
0
0
0
continue program/erase operation
30h
0
0
0
continue program/erase operation
sets the (WEL) write enable latch bit
Program/Erase Resume
PER
Protection
Write Enable
WREN
06h
0
0
0
Write Disable
WRDI
04h
0
0
0
VWREN
50h
0
0
0
Erase Security Registers
ERSCUR
44h
3
0
0
Erase security registers
Program Security Registers
PRSCUR
42h
3
0
1+
Program security registers
Read Security Registers
RDSCUR
48h
3
1
1+
Read value of security register
RDSR
05h
0
0
1
read out status register
RDSR2
35h
0
0
1
Read out status register-1
ASI
25h
0
1
0
Enable the active status interrupt
WRSR
01h
0
0
2
Write data to status registers
Volatile SR Write Enable
resets the (WEL) write enable
latch bit
Write enable for volatile
status register
Security
Status Register
Read Status Register
Active Status Interrupt
Write Status Register
21
ZD25WD40B
Command set (Cont’d)
Abbr.
Code
ADR
Bytes
DMY
Bytes
RSTEN
66h
0
0
0
Enable reset
Reset
RST
99h
0
0
0
Reset
Read Manufacturer/device
ID
Read Manufacture ID
Dual Read Manufacture ID
RDID
9Fh
0
0
1 to 3
output JEDEC ID: 1-byte manufacturer ID
& 2-byte device ID
REMS
DREMS
90h
92h
3
3
1
1+
1
Read manufacturer ID/device ID data
Dual output read manufacture/device ID
DP
B9h
RDP/RES ABh
0
3
0
0
0
1
enters deep power-down mode
Read electronic ID data
Commands
Data
Bytes
Function
Other Commands
Reset Enable
Deep Power-down
Release Deep Power-down /
Read Electronic ID
Read SFDP
RDSFDP
Release read enhanced
Read unique ID
RUID
5Ah
Read SFDP parameter
FFh
Release from read enhanced
4Bh
4
1+
Read unique ID
NOTE:
1. Dual Output data
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
2. Dual Input Address
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
3. Security Registers Address:
Security Register1: A23-A16=00H, A15-A9=0001000, A8-A0= Byte Address;
Security Register2: A23-A16=00H, A15-A9=0010000, A8-A0= Byte Address;
Security Register3: A23-A16=00H, A15-A9=0011000, A8-A0= Byte Address;
22
ZD25WD40B
5.2. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like
PP,DPP, PE,SE, BE32K,BE, CE, and WRSR,ERSCUR, PRSCUR which are intended to change the device
content, should be set every time after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→ sending WREN instruction code→ CS# goes
high.
5.3. Write Disable (WRDI)
The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→ sending WRDI instruction code→ CS# goes
high.
The WEL bit is reset by following situations:
- Power-up
- Write Disable (WRDI) instructioncompletion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Dual Input Page Program (DPP) instructioncompletion
- Page Erase (PE) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE32K,BE) instruction completion
- Chip Erase (CE) instruction completion
- Erase Security Register (ERSCUR) instruction completion
- Program Security Register (PRSCUR) instruction completion
- Reset (RST) instruction completion
23
ZD25WD40B
Figure 5-3 Write Disable (WRDI) Sequence (Command 04)
CS #
0
1
2
3
4
5
6
7
SCLK
Command
SI
04H
SO
High-Z
5.4. Write Enable for Volatile Status Register
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical
non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write
Enable for Volatile Status Register command must be issued prior to a Write Status Register command. The
Write Enable for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the
Write Status Register command to change the volatile Status Register bit values.
The sequence of issuing Write Enable for Volatile Status Register instruction is: CS# goes low→ sending
Write Enable for Volatile Status Register instruction code→ CS# goes high.
Figure 5-4 Write Enable for Volatile Status Register Sequence (Command 50)
CS #
0
1
2
3
4
5
6
7
SCLK
Command(50H)
SI
SO
High-Z
24
ZD25WD40B
5.5. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time
(even in program/erase/write status register condition). It is recommended to check the Write in Progress
(WIP) bit before sending a new instruction when a program, erase, or write status register operation is in
progress. For command code “05H”, the SO will output Status Register bits S7~S0. The command code
“35H”, theSO will output Status Register bits S15~S8.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status
Register data out on SO.
The SIO[2:1] are "don't care".
Figure 5-5 Read Status Register (RDSR) Sequence (Command 05 or 35)
CS #
0
SCLK
SI
SO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Command
05H or 35H
7
6
5
4
3
2
1
0 7
6
5
4
3
2
1
0
25
ZD25WD40B
5.6.Active Status Interrupt (ASI)
To simplify the readout of the WIP bit, the Active Status Interrupt command (25h) may be used. It is then not
necessary to continuously read the status register, it is sufficient to monitor the value of the SO line. If the SO
line is connected to an interrupt line on the host controller, the host controller may be in sleep mode until the
SO line indicates that the device is ready for the next command.
The WIP bit can be read at any time, including during an internally self-timed program or erase operation.
To enable the Active Status Interrupt command, the CS pin must first be asserted and the opcode of 25h
must be clocked into the device. For SPI Mode0 and Mode3, at least one dummy bit has to be clocked into the
device after the last bit of the opcode has been clocked in. (In most cases, this is most easily done by
sending a dummy byte to the device.) The value of the SI line after the opcode is clocked in is of no
significance to the operation.
The value of WIP is then output on the SO line, and is continuously updated by the device for as long as the
CS pin remains asserted. Additional clocks on the SCLK pin are not required. For SPI Mode3, SCLK must
keep low. If the WIP bit changes from 1 to 0 while the CS pin is asserted, the SO line will change from 1 to 0.
(The WIP bit cannot change from 0 to 1 during an operation, so if the SO line already is 0, it will not change.)
Deasserting the CS pin will terminate the Active Status Interrupt operation and put the SO pin into a
high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data
be read.
The sequence of issuing ASI instruction is: CS# goes low→ sending ASI instruction code→ WIP data out on
SO.
Figure 5-6 Active Status Interrupt (ASI) Sequence (Command 25)
CS #
0 1 2
3
4
5
6
7
8
SCLK
Command
25 H
SI
SO
High-z
RDY / BSY
High-z
5.7. Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write
Enable (WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S10, S1 and S0 of the Status Register.
CS# must be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write
Status Register (WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the
CMP and SRP1 bits will not change. As soon as CS# is driven high, the self-timed Write Status Register
cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status
Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is
26
ZD25WD40B
completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
Protect (SRP1 and SRP0) bits in accordance with the Write Protect (WP#) signal. The Status Register Protect
(SRP1 and SRP0) bits and Write Protect (WP#) signal allow the device to be put in the Hardware Protected
Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode is
entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status
Register data on SI→CS# goes high.
The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected
and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#)
goes high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in
progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and
the Write Enable Latch (WEL) bit is reset.
5.8. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory
can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
27
ZD25WD40B
The sequence of issuing READ instruction is: CS# goes low→ sending READ instruction code→ 3-byte address
on SI→ data out on SO→ to end READ operation can use CS# to high at any time during data out.
Figure 5-8 Read Data Bytes (READ) Sequence (Command 03)
CS#
SCLK
0
1
2
3
4
5
6
7
8
SO
03H
High - Z
28 29 30 31 32 33 34 35 36 37 38 39
24 -bit address
Command
SI
9 10
23 22 21
3
2
1
0
Data Out1
MSB
MSB
7
6
5
4
3
2
Data Out2
1
0
5.9. Read Data Bytes at Higher Speed(FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK,
and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte
can be at any location. The address is automatically increased to the next higher address after each byte data
is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter
rolls over to 0 when the highest address has been reached.
The
sequence of
issuing
FAST_READ instruction
is:
CS#
goes
low→ sending
FAST_READ instruction code→3-byte address on SI→ 1-dummy byte address on SI→data out on SO→
to end FAST_READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without
any impact on the Program/Erase/Write Status Register current cycle.
Figure 5-9 Read at Higher Speed (FAST_READ) Sequence (Command 0B)
28
ZD25WD40B
CS#
0
1
SCLK
2
5
4
3
6
7
8 9 10
Command
SI
28 29 30 31
24- bit address
0BH
23 22 21
3
1
2
0
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Byte
SI
7
6
5
4
3
2
1
0
Data Out1
SO
7
6 5
MSB
4
3
Data Out2
2
1 0
7
6 5
MSB
29
ZD25WD40B
5.10. Dual Read Mode (DREAD)
The DREAD instruction enable double throughput of Serial NOR Flash in read mode. The address is latched
on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK
at a maximum frequency fT. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at
a single DREAD instruction. The address counter rolls over to 0 when the highest address has been reached.
Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing DREAD instruction is: CS# goes low → sending DREAD instruction → 3-byte
address on SI → 8-bit dummy cycle → data out interleave on SIO1 & SIO0 → to end DREAD operation
can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 5-10 Dual Read Mode Sequence (Command 3B)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9
10
Command
SI
28 29 30 31
24- bit address
3BH
23 22 21
3
2 1
0
SO
CS#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
Dummy Clocks
SI
SO
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
MSB
MSB
30
ZD25WD40B
5.11. 2 X IO Read Mode (2READ)
The 2READ instruction enables Double Transfer Rate of Serial NOR Flash in read mode. The address is
latched on rising edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge
of SCLK at a maximum frequency fT. The first address byte can be at any location. The address is
automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has
been reached.
Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of previous
1-bit.
The sequence of issuing 2READ instruction is: CS# goes low→ sending 2READ instruction→ 24-bit address
interleave on SIO1 & SIO0→ 8-bit dummy cycle on SIO1 & SIO0→ data out interleave on SIO1 & SIO0→ to
end 2READ operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any
impact on the Program/Erase/Write Status Register current cycle.
Figure 5-11 2 X IO Read Mode Sequence (Command BB M5-4 ≠ (1,0))
CS#
0
1
2
3
4
5 6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3 1
SCLK
Command
SI
BBH
SO
A23-16
A15-8
A7-0
0
M7-0
CS#
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
SO
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
Byte1
Byte2
Byte3
Byte4
31
ZD25WD40B
5.12. 2 X IO Read Performer Enhance Mode
“BBh” command supports 2 X IO Performance Enhance Mode which can further reduce command overhead
through setting the “Continuous Read Mode” bits (M7-0) after the input 3-byte address (A23-A0). If the
“Continuous Read Mode” bits (M5-4) = (1, 0), then the next 2 X IO Read command (after CS# is raised and
then lowered) does not require the BBH command code.
If the “Continuous Read Mode” bits (M5-4) do not equal (1, 0), the next command requires the first BBH
command code, thus returning to normal operation. A “Continuous Read Mode” Reset command can be used
to reset (M5-4) before issuing normal command.
Figure 5-12 2 X IO Read Performance Enhance Mode ( M5-4 = (1,0) )
CS#
0
1
2
5 6
4
3
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
SCLK
Command
BBH
SI
SO
A23-16
CS#
A15-8
A7-0
M7-0
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCLK
SI
SO
6
4
2
0
6
4
2
0
6
7
5
3
1
7
5
3
1
7
Byte1
Byte2
2
0
6
4
2
0
5 3
1
7
5
3
1
4
Byte4
Byte3
CS#
1
2
3
4
5 6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0 6
4
2
0
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1 7
5
3
1
SCLK
SI
SO
A23-16
A15-8
A7-0
M7-0
Byte1
Byte2
Note: 2 X IO Read Performance Enhance Mode, if M5-4 = 1, 0. If not using performance enhance
recommend to set M5-4 ≠ 1, 0.
32
ZD25WD40B
5.13. Page Erase (PE)
The Page Erase (PE) instruction is for erasing the data of the chosen Page to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Erase (PE).
To perform a Page Erase with the standard page size (256 bytes), an opcode of 81h must be clocked into the
device followed by three address bytes comprised of 2 page address bytes that specify the page in the main
memory to be erased, and 1 dummy byte.
The sequence of issuing PE instruction is: CS# goes low → sending PE instruction code→ 3-byte address on
SI → CS# goes high
Figure 5-13 Page Erase Sequence (Command 81)
CS #
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
SI
81H
24- bit address
23 22
2
1
0
MSB
5.14. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any
address of the sector is a valid address for Sector Erase (SE) instruction.
The CS# must go high exactly at
the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected
and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low → sending SE instruction code→ 3-byte address on
SI → CS# goes high.
The SIO[2:1] are don't care.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write
in progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1
during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL)
bit is reset. If the sector is protected by BP4, BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will
not be executed on the sector.
33
ZD25WD40B
5.15. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is
used for 32K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write
Enable Latch (WEL) bit before sending the Block Erase (BE32K). Any address of the block is a valid address
for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the least significant
bit of address byte has been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low → sending BE32K instruction code → 3-byte
address on SI → CS# goes high.
The SIO[2:1] are don't care.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the
tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is
cleared. If the block is protected by BP4, BP3, BP2, BP1,BP0 bits, the array data will be protected (no change)
and the WELbit still be reset.
34
ZD25WD40B
Figure 5-15 Block Erase 32K(BE32K)
Sequence (Command 52 )
CS #
0
1
2
4
3
5
6
7
8
29 30 31
9
SCLK
Command
SI
24- bit address
52H
23 22
2
1
0
MSB
5.16. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch
(WEL) bit before sending the Block Erase (BE). Any address of the block is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been
latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on
SI→CS# goes high.
The SIO[2:1] are "don't care".
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the
tBE timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP4, BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed
on the block.
Figure 5-16 Block Erase (BE) Sequence (Command D8)
CS #
SCLK
0
1
2
3
4
5
6
7
8
9
Command
SI
D8H
29 30 31
24- bit address
23 22
2
1
0
MSB
5.17. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The
CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→ sending CE instruction code→ CS# goes high.
The SIO[2:1] are "don't care".
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the
tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
35
ZD25WD40B
the chip is protected by BP4,BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It
will be only executed when all Block Protect(BP4, BP3, BP2, BP1, BP0) are set to “None protected”.
Figure 5-17 Chip Erase (CE) Sequence (Command 60 or C7)
CS#
SCLK
0
1
2
3
4
5
6
7
Command
SI
60H or C7H
5.18. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN)
instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP).
The device programs only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to
be programmed, A7-A0 (The eight least significant address bits) should be set to 0. If the eight least
significant address bits (A7-A0) are not all 0, all transmitted data going beyond the end of the current page
are programmed from the start address of the same page (from the address A7-A0 are all 0). If more than
256 bytes are sent to the device, the data of the last 256-byte is programmed at the request page and
previous data will be disregarded.
If less than 256 bytes are sent to the device, the data is programmed at
the requested address of the page without effect on other address of the same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on
SI→ at least 1-byte on data on SI→ CS# goes high.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte
boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be
executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during
the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is
reset. If the page is protected by BP4, BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be
executed.
The SIO[2:1] are "don't care".
36
ZD25WD40B
Figure 5-18 Page Program (PP) Sequence (Command 02)
CS#
0
1
3 4
2
5
6
7 8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
Bit address
02H
SI(IO0)
3
23 22 21
2
7
0
2072
2073
2074
2075
2076
2077
2078
2079
CS#
1 0
Byte1
6 5 4 3 2 1
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Byte2
SI(IO0)
7
6
5
4 3 2 1
Byte3
6 5 4 3 2 1
0 7
Byte256
7
0
6 5 4
3 2 1
0
5.19. Dual Input Page Program (DPP)
The Dual Input Page Program (DPP) instruction is similar to the standard Page Program command and can be
used to program anywhere from a single byte of data up to 256 bytes of data into previously erased memory
locations. The Dual-Input Page Program command allows two bits of data to be clocked into the device on
every clock cycle rather than justone.
A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the
Dual Input Page Program (DPP). The Dual Input Page Programming takes two pins: SIO0, SIO1 as data input,
which can improve programmer performance and the effectiveness of application. The other function
descriptions are as same as standard page program.
The sequence of issuing DPP instruction is: CS# goes low→ sending DPP instruction code→ 3-byte address on
SI→at least 1-byte on data on SIO[1:0]→ CS# goes high.
Figure 5-19 Page Program (DPP) Sequence (Command A2)
CS#
0 1
SCLK
2
3
4
5
6 7
28 29 30 31 32 33 34 35 36 37 38 39
9 10
24-bitaddress
Command
A2H
SI(IO0)
8
3 2 1
23 22 21
Byte1
0
Byte2
6
4
2 0
6
4
2
0
7
5
3
1 7
5
3
1
MSB
SO(IO1)
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Byte3
1048
1049
1050
1051
1052
1053
1054
1055
CS#
Byte4
SI(IO0)
Byte5
Byte6
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
6
4
2
SO(IO1)
7
7
5
3 1
5
3
1 7
5
3
1
7 5
3
1
7
5 3
1
Byte255
Byte256
0 6
7
4
2
0
5
3
1
37
ZD25WD40B
5.20. Erase Security Registers (ERSCUR)
The product provides three512-byte Security Registers which can be erased and programmed individually.
These registers may be used by the system manufacturers to store security and other important information
separately from the main memory array.
The Erase Security Registers command is similar to Sector/Block Erase command, the instruction is used for
512-byte erase operation. A Write Enable (WREN) command must previously have been executed to set the
Write Enable Latch (WEL) bit.
The Erase Security Registers command sequence: CS# goes low → sending ERSCUR instruction
→ sending 24 bit address → CS# goes high.
CS# must be driven high after the eighth bit of the command code has been latched in; otherwise the Erase
Security Registers command is not executed. As soon as CS# is driven high, the self-timed Erase Security
Registers cycle (whose duration is tSE) is initiated. While the Erase Security Registers cycle is in progress, the
Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit
is 1 during the self-timed Erase Security Registers cycle, and is 0 when it is completed. The Security Registers
Lock Bit (LB3-1) in the Status Register can be used to OTP protect the security registers. Once the LB bit is set to
1, the Security Registers will be permanently locked; the Erase Security Registers command will
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Don’t care
Security Register #2
00H
0010
000
Don’t care
Security Register #3
00H
0011
000
Don’t care
Figure 5-20 Erase Security Registers (ERSCUR) Sequence (Command 44)
CS#
SCLK
0
1
2
3
4 5
6
7
8
9
Command
SI
44H
29 30 31
24 bit address
23 22
2
1
0
38
ZD25WD40B
5.21. Program Security Registers (PRSCUR)
The Program Security Registers command is similar to the Page Program command. It allows from 1 to
512bytes Security Registers data to be programmed. A Write Enable (WREN) command must previously have
been executed to set the Write Enable Latch (WEL) bit before sending the Program Security Registers
command.
The Program Security Registers command sequence: CS# goes low → sending PRSCUR instruction
→ sending 24 bit address → sending at least one byte data → CS# goes high.
As soon as CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is
initiated. While the Program Security Registers cycle is in progress, the Status Register may be read to check
the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Program
Security Registers cycle, and is 0 when it is completed.
If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Registers will be permanently locked.
Program Security Registers command will be ignored.
Address
A23-16
A15-12
A5-9
A8-0
Security Register #1
00H
0001
000
Byte Address
Security Register #2
00H
0010
000
Byte Address
Security Register #3
00H
0011
000
Byte Address
Figure 5-21 Program Security Registers (PRSCUR) Sequence (Command 42)
CS#
0
1
2 3
4
5
6
7 8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Bit address
23 22 21
3 2
42H
SI(IO0)
CS#
40 41 42 43 44 45 46 47 48 49 50
51 52 53 54 55
1
0
Byte1
6 5 4 3 2 1
7
0
2072
2073
2074
2075
2076
2077
2078
2079
Command
SCLK
SI(IO0)
7
6
5
Byte2
4 3 2 1
0
7 6
Byte3
5 4 3 2 1
Byte512
0
7
6
5
4 3
2 1
0
39
ZD25WD40B
5.22. Read Security Registers (RDSCUR)
The Read Security Registers command is similar to Fast Read command. The command is followed by a
3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of SCLK. Then
the memory content, at that address, is shifted out on SO, each bit being shifted out, at a Max frequency fC,
during the falling edge of SCLK. The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. Once the A8-A0 address
reaches the last byte of the register (Byte 1FFH), it will reset to 000H, the command is completed by driving
CS# high.
The sequence of issuing RDSCUR instruction is : CS# goes low → sending RDSCUR instruction → sending 24
bit address → 8 bit dummy byte → Security Register data out on SO → CS# goes high.
Address
A23-16
A15-12
A11-9
A8-0
Security Register #1
00H
0001
000
Byte Address
Security Register #2
00H
0010
000
Byte Address
Security Register #3
00H
0011
000
Byte Address
Figure 5-22 Read Security Registers (RDSCUR) Sequence (Command 48)
CS#
0
SCLK
1
2
3
4
5
6
7
8
9 10
24 bit address
Command
SI
28 29 30 31
23 22 21
48H
3
2
1
0
High -Z
SO
CS#
SCLK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Dummy Byte
SI
SO
7
6
5
4
3 2
1
0
Data Out2
Data Out1
7
MSB
6
5
4
3
2
1
0
7
6
5
MSB
40
ZD25WD40B
5.23. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to
entering the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep
Power-down mode requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down
mode, the device is not active and all Write/Program/Erase instruction are ignored. When CS# goes high, it's
only in standby mode not deep power-down mode.
It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→ sending DP instruction code→ CS# goes high.
Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power-down mode
(RDP) and Read Electronic Signature (RES) instruction. (RES instruction to allow the ID been read out).
When Power- down, the deep power-down mode automatically stops, and when power-up, the device
automatically is in standby mode. For RDP instruction the CS# musOnce the DP instruction is set, all
instruction will be ignored except the Release from Deep Power-down mode (RDP) and Read Electronic
Signature (RES) instruction. (RES instruction to allow the ID been read out).
t go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the
instruction will not be executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before
entering the Deep Power-down mode and reducing the current to ISB2.
Figure 5-23 Deep Power-down (DP) Sequence (Command B9)
CS #
tDP
SCLK
Command
SI
Standby mode
Deep power-down mode
B9H
41
ZD25WD40B
5.24. Release form Deep Power-Down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High.
When Chip Select (CS#) is driven high, the device is put in the Stand-by Power mode. If the device was not
previously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the
device was previously in the Deep Power-down mode, though, the transition to the Stand-by Power mode is
delayed by tRES2, and Chip Select (CS#) must remain High for at least tRES2(max). Once in the
Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as
table of ID Definitions.
This is not the same as RDID instruction. It is not recommended to use for new
design. For new design, please use RDID instruction.Even in Deep power-down mode, the RDP and RES
are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's
no effect on the current program/erase/ write cycle in progress.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs
repeatedly if continuously send the additional clock cycles on SCLK while CS# is at low.
If the device
was not previously in Deep Power-down mode, the device transition to standby mode is immediate. If the
device was previously in Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and
CS# must remain to high at least tRES2 (max). Once in the standby mode, the device waits to be selected,
so it can be receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power-Down Mode.
Figure 5-24a Read Electronic Signature (RES) Sequence (Command AB)
CS#
SCLK
0
1
2
4
5 6
7
8
29 30 31 32 33 34 35 36 37 38
9
tRES2
3 Dummy Bytes
Command
SI
SO
3
ABH
23 22
2
1
0
MSB
High-Z
7
MSB
Electronic Signatur eOut
6 5 4 3 2 1 0
Deep Power- down mode
Standby Mode
Figure 5-24b Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
SCLK
0
1
2
3
4
5 6
7
tRES1
Command
SI
ABH
Deep Power - down mode
Stand-by mode
42
ZD25WD40B
5.25. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction returns both the JEDEC assigned manufacturer ID and the device ID. The Device ID
values are listed in "Table ID Definitions".
The REMS instruction is initiated by driving the CS# pin low and sending the instruction code "90h" followed
by two dummy bytes and one address byte (A7~A0). After which the manufacturer ID for Zetta and the device
ID are shifted out on the falling edge of SCLK with the most significant bit (MSB) first. If the least significant bit
(LSB) of the address byte is 0b, the manufacturer ID will be output first, followed by the device ID. If the least
significant bit (LSB) of the address byte is 1b, then the device ID will be output first, followed by the
manufacturer ID. While CS# is low, the manufacturer and device IDs can be read continuously, alternating
from one to the other. The instruction is completed by driving CS# high.
Figure 5-25 Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8 9
10
28 29 30 31
SCLK
2dummy byte and
1 address byte
3 2
23 22 21
Command
SI
90H
SO
1 0
High-Z
CS#
SCLK
SI
SO
Device ID
Manufacture ID
7 6
MSB
5
4
3
2
1
0
7
6
5
4
3
2
1
0
MSB
43
ZD25WD40B
5.26. Dual I/O Read Electronic Manufacturer ID & Device ID (DREMS)
The DREMS instruction is similar to the REMS command and returns the JEDEC assigned manufacturer ID
which takes two pins: SIO0, SIO1 as address input and ID output I/O
The instruction is initiated by driving the CS# pin low and shift the instruction code "92h" followed by two
dummy bytes and one bytes address (A7~A0). After which, the Manufacturer ID for Zetta and the Device ID
are shifted out on the falling edge of SCLK with most significant bit (MSB) first. If the least significant bit (LSB) of
the one-byte address is initially set to 1b, then the device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the
other. The instruction is completed by driving CS# high.
Figure 5-26 DUAL I/O Read Electronic Manufacturer & Device ID (DREMS) Sequence (Command 92)
44
ZD25WD40B
5.27. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The
Zetta Manufacturer ID and Device ID are list as “as "Table . ID Definitions”.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code →24-bits ID
data out on SO→ to end RDID operation can use CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at
standby stage.
Figure 5-27 Read Identification(RDID) Sequence (Command 9F)
CS#
0
SCLK
1
2
3 4
5
6 7 8
9 10 11 12 13 14 15
9FH
SI
SO
7
MSB
CS#
6
Manufacturer ID
5 4 3 2 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SCLK
SI
MemoryType ID
7 6 5 4 3 2 1
MSB
SO
Table ID Definitions
ZD25WD40B
RDID
manufacturer ID
command
BA
0
7 6
MSB
Capacity ID
5 4 3 2 1
memory type
60
RES
electronic ID
command
12
0
memory density
13
REMS
manufacturer ID
device ID
command
BA
12
5.28. Program/Erase Suspend/Resume
The Suspend instruction interrupts a Page Program, Sector Erase, or Block Erase operation to allow access to
the memory array. After the program or erase operation has entered the suspended state, the memory array
can be read except for the page being programmed or the sector or block being erased.
Readable Area of Memory While a Program or Erase Operation is Suspended
Suspended Operation
Readable Region of Memory Array
Page Program
All but the Page being programmed
Page Erase
All but the Page being erased
Sector Erase(4KB)
All but the 4KB Sector being erased
Block Erase(32KB)
Block Erase(64KB)
All but the 32KB Block being erased
All but the 64KB Block being erased
45
ZD25WD40B
When the Serial NOR Flash receives the Suspend instruction, there is a latency of tPSL or tESL before the
Write Enable Latch (WEL) bit clears to “0” and the SUS2 or SUS1 sets to “1”, after which the device is ready to
accept one of the commands listed in "Table Acceptable Commands During Program/Erase Suspend after
tPSL/tESL" (e.g. FAST READ). Refer to " AC Characteristics" for tPSL and tESL timings. "Table Acceptable
Commands During Suspend (tPSL/tESL not required)" lists the commands for which the tPSL and tESL
latencies do not apply. For example, RDSR, RDSCUR, RSTEN, and RST can be issued at any time after the
Suspend instruction.
Status Register bit 15 (SUS2) and bit 10 (SUS1) can be read to check the suspend status. The SUS2 (Program
Suspend Bit) sets to “1” when a program operation is suspended. The SUS1 (Erase Suspend Bit) sets to “1”
when an erase operation is suspended. The SUS2 or SUS1 clears to “0” when the program or erase operation
is resumed.
Acceptable Commands During Program/Erase Suspend after tPSL/tESL
Command name
Command Code
Suspend Type
Program Suspend
Erase Suspend
READ
03H
•
•
FAST READ
0BH
•
•
DREAD
3BH
•
•
2READ
BBH
•
•
RDSFDP
5AH
•
•
RDID
9FH
•
•
REMS
90H
•
•
DREMS
92H
•
•
RDSCUR
48H
•
•
SBL
77H
•
•
WREN
06H
•
RESUME
7AH OR 30H
•
•
PP
02H
•
DPP
A2H
•
Acceptable Commands During Suspend（tPSL/tESL not required）
Command name
WRDI
RDSR
RDSR2
ASI
RES
RSTEN
RST
NOP
Command Code
04H
05H
35H
25H
ABH
66H
99H
00H
Suspend Type
Program Suspend
Erase Suspend
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
46
ZD25WD40B
Figure 5-28 Resume to Suspend Latency
tPRS / tERS
Resume Command
Suspend Command
CS#
tPRS: Program Resume to another Suspend
tERS: Erase Resume to another Suspend
5.29. Erase Suspend to Program
The “Erase Suspend to Program” feature allows Page Programming while an erase operation is suspended.
Page Programming is permitted in any unprotected memory except within the sector of a suspended Sector
Erase operation or within the block of a suspended Block Erase operation. The Write Enable (WREN)
instruction must be issued before any Page Program instruction.
A Page Program operation initiated within a suspended erase cannot itself be suspended and must be allowed
to finish before the suspended erase can be resumed. The Status Register can be polled to determine the
status of the Page Program operation. The WEL and WIP bits of the Status Register will remain “1” while the
Page Program operation is in progress and will both clear to “0” when the Page Program operation completes.
Figure 5-29 Suspend to Read/Program Latency
Resume Command
tPSL / tESL
Read/Program command
CS#
tPSL: Program latency
tESL: Erase latency
Notes:
1. Please note that Program only available after the Erase-Suspend operation
2. To check suspend ready information, please read status register bit15 (SUS2) and bit10(SUS1)
5.30. Program Resume and Erase Resume
The Resume instruction resumes a suspended Page Program, Sector Erase, or Block Erase operation. Before
issuing the Resume instruction to restart a suspended erase operation, make sure that there is no Page
Program operation in progress.
Immediately after the Serial NOR Flash receives the Resume instruction, the WEL and WIP bits are set to “1”
and the SUS2 or SUS1 is cleared to “0”. The program or erase operation will continue until finished ("Resume
to Read Latency") or until another Suspend instruction is received. A resume-to-suspend latency of tPRS or
tERS must be observed before issuing another Suspend instruction ("Resume to Suspend Latency").
Figure 5-30 Resume to Read Latency
Resume Command
tSE /tBE / tPP
Read Command
CS#
47
ZD25WD40B
5.31. No Operation (NOP)
The "No Operation" command is only able to terminate the Reset Enable (RSTEN) command and will not
affect any other command.
The SIO[2:1] are don't care.
5.32. Software Reset (RSTEN/RST)
The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command and Reset (RST)
command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which
makes the device return to the default status as power on.
To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed first to perform
the Reset operation. If there is any other command to interrupt after the Reset-Enable command, the
Reset-Enable will be invalid. The SIO[2:1] are "don't care".
If the Reset command is executed during program or erase operation, the operation will be disabled, the data
under processing could be damaged or lost.
Figure 5-32a Software Reset
Recovery
CS#
99H
66H
tReady
Mode
Stand-by Mode
Figure 5-32b Reset Sequence
CS#
0
1 2 3
4
5
6 7
0
1 2 3
4
5
6 7
SCLK
Command
SI
66H
Command
99H
SO
48
ZD25WD40B
5.33. Read Unique ID (RUID)
The Read Unique ID command accesses a factory-set read-only 128bit number that is unique to each
ZD25Dxx device. The Unique ID can be used in conjunction with user software methods to help prevent
copying or cloning of a system.
The Read Unique ID command sequence: CS# goes low → sending Read Unique ID command →Dummy
Byte1 →Dummy Byte2 →Dummy Byte3 → Dummy Byte4 → 128bit Unique ID Out → CS# goes high.
The command sequence is show below.
Figure 5-33
Read Unique ID (RUID) Sequence (Command 4B)
CS#
0
1
2
3 4
5
6
7
8
9 10
28 29 30 31
SCLK
3 bytes dummy
Command
SI
SO
4BH
High-Z
CS#
32 33 34 35 36 37 38 39 40 41 42 43
164 165 166
SCLK
Dummy Byte
SI
128 bit unique serial number
SO
127 126 125 124
MSB
3
2
1
0
49
ZD25WD40B
5.34. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the
functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. These
parameter tables can be interrogated by host system software to enable adjustments needed to
accommodate divergent features from multiple vendors. The concept is similar to the one found in the
Introduction of JEDEC Standard, JESD68 on CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→ send RDSFDP
instruction (5Ah)→send 3 address bytes on SI pin→ send 1 dummy byte on SI pin→ read SFDP code on
SO→ to end RDSFDP operation can use CS# to high at any time during data out. The lower byte (A7~A0) of
the address is the valid address which is corresponded to the Add in the Figure 5-42.
SFDP is a JEDEC Standard, JESD216B.
Figure 5-34 Read Serial Flash Discoverable Parameter(RDSFDP) Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31
SCLK
Command
SI
5AH
SO
3 2
1
0
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCLK
SI
23 22 21
High-Z
SO
CS#
24-bit address
Command
7
6
5 4
3
2
1
0
7
6
5
4 3
2
1
0
7 6
5
50
ZD25WD40B
Figure 5-35 Serial Flash Discoverable Parameter (SFDP) Table
Table Signature and Parameter Identification Data Values
Description
Data
Data
07:00
53H
53H
01H
15:08
46H
46H
02H
23:16
44H
44H
03H
31:24
50H
50H
Start from 00H
04H
07:00
06H
06H
SFDP Major Revision Number
Start from 01H
05H
15:08
01H
01H
Number of Parameters Headers
Start from 00H
06H
23:16
01H
01H
07H
31:24
FFH
FFH
08H
07:00
00H
00H
Start from 0x00H
09H
15:08
06H
06H
Start from 0x01H
0AH
23:16
01H
01H
0BH
31:24
09H
09H
0CH
07:00
30H
30H
0DH
15:08
00H
00H
0EH
23:16
00H
00H
0FH
31:24
FFH
FFH
10H
07:00
BAH
BAH
Start from 0x00H
11H
15:08
00H
00H
Start from 0x01H
12H
23:16
01H
01H
13H
31:24
03H
03H
SFDP Signature
SFDP
Minor Revision Number
Unused
Comment
Fixed:50444653H
Contains 0xFFH and can never be
Add(H)
DW Add
(Byte)
(Bit)
00H
changed
ID number (JEDEC)
00H: It indicates a JEDEC specified
header
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Parameter Table Pointer (PTP)
How many DWORDs in the
Parameter table
First address of JEDEC Flash
Parameter table
Unused
Contains 0xFFH and can never be
changed
ID Number
It is indicates Zetta
(ZettaDevice Manufacturer ID)
manufacturer ID
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
How many DWORDs in the
(in double word)
Parameter table
Parameter Table Pointer (PTP)
First address of Zetta Flash
14H
07:00
90H
90H
Parameter table
15H
15:08
00H
00H
16H
23:16
00H
00H
17H
31:24
FFH
FFH
Unused
Contains 0xFFH and can never be
changed
51
ZD25WD40B
Table Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add(H)
(Byte)
DW Add
(Bit
)
Data
01:00
01b
02
1b
03
0b
Data
00: Reserved; 01: 4KB erase;
Block/Sector Erase Size
10: Reserved;
11: not support 4KB erase
Write Granularity
Write Enable Instruction
Requested for Writing to Volatile
Status Registers
0: 1Byte, 1: 64Byte or larger
0: Nonvolatile status bit
1:
Volatile status bit
(BP status register bit)
0: Use 50H Opcode,
Write Enable Opcode Select for
Writing to Volatile Status Registers
30H
E5H
1: Use 06H Opcode,
Note: If target flash status register is
04
0b
07:05
111b
15:08
20H
16
1b
18:17
00b
19
0b
Nonvolatile, then bits3 and 4 must
be set to 00b.
Contains 111b and can never be
Unused
changed
4KB Erase Opcode
(1-1- 2) Fast Read
31H
0=Not support, 1=Support
Address Bytes Number used in
00: 3Byte only, 01: 3 or 4Byte,
addressing flash array
10: 4Byte only, 11: Reserved
Double Transfer Rate (DTR)
clocking
0=Not support, 1=Support
32H
(1-2- 2) FastRead
0=Not support, 1=Support
20
1b
(1-4- 4) Fast Read
0=Not support, 1=Support
21
0b
(1-1- 4) Fast Read
0=Not support, 1=Support
22
0b
23
1b
33H
31:24
FFH
37H:34H
31:00
Unused
Unused
Flash Memory Density
(1-4-
4) Fast Read Number of Wait
states
(1-4-
Clocks) not support
4) Fast Read Number of
Mode Bits
(1-4(1-1-
4) Fast Read Number of Wait
Mode Bits
(1-1-
0 0000b: Wait states (Dummy
4) Fast Read Opcode
3BH
FFH
00000b
00H
07:05
000b
15:08
FFH
20:16
00000b
FFH
00H
3AH
000b:Mode Bits not support
91H
001FFFFFH
38H
39H
Clocks) not support
4) Fast Read Number of
04:00
000b:Mode Bits not support
4) Fast Read Opcode
states
(1-1-
0 0000b: Wait states (Dummy
20H
23:21
000b
31:24
FFH
FFH
52
ZD25WD40B
Description
(1-1- 2) Fast Read Number of Wait
states
(1-1- 2) Fast Read Number
of Mode Bits
Comment
(1-2- 2) Fast Read Number
of Mode Bits
Clocks) not support
(Bit)
04:00
000b: Mode Bits not support
3DH
0 0000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
3FH
0=not support
0=not support
Data
1=support
1=support
40H
Unused
Data
01000b
08H
07:05
000b
15:08
3BH
20:16
00000b
3EH
Unused
(4-4- 4) Fast Read
(Byte)
3CH
(1-2- 2) Fast Read Opcode
(2-2- 2) Fast Read
DW Add
0 0000b: Wait states (Dummy
(1-1- 2) Fast Read Opcode
(1-2- 2) Fast Read Number
of Wait states
Add(H)
3BH
80H
23:21
100b
31:24
BBH
00
0b
03:01
111b
04
0b
07:05
111b
BBH
EEH
Unused
43H:41H
31:08
0xFFH
0xFFH
Unused
45H:44H
15:00
0xFFH
0xFFH
20:16
00000b
(2-2- 2) Fast Read Number
of Wait states
(2-2- 2) Fast Read Number
of Mode Bits
0 0000b: Wait states (Dummy
Clocks) not support
000b: Mode Bits not support
(2-2- 2) Fast Read Opcode
Unused
(4-4- 4) Fast Read Number of Wait
states
(4-4- 4) Fast Read Number
of Mode Bits
Clocks) not support
this sector type don’t exist
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size=2^N bytes 0x00b:
this sector type don’t exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size=2^N bytes 0x00b:
this sector type don’t exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector Type 4 erase Opcode
000b
47H
31:24
FFH
FFH
49H:48H
15:00
0xFFH
0xFFH
20:16
00000b
Sector/block size=2^N bytes 0x00b:
this sector type don’t exist
00H
4AH
000b: Mode Bits not support
Sector/block size=2^N bytes 0x00b:
00H
23:21
0 0000b: Wait states (Dummy
(4-4- 4) Fast Read Opcode
Sector Type 1 Size
46H
23:21
000b
4BH
31:24
FFH
FFH
4CH
07:00
0CH
0CH
4DH
15:08
20H
20H
4EH
23:16
0FH
0FH
4FH
31:24
52H
52H
50H
07:00
10H
10H
51H
15:08
D8H
D8H
52H
23:16
00H
00H
53H
31:24
FFH
FFH
53
ZD25WD40B
Table Parameter Table (1): Zetta Flash Parameter Tables
Description
Comment
Add(H)
DW Add
(Byte)
(Bit)
91H:90H
93H:92H
Data
Data
15:00
3600H
3600H
31:16
1650H
1650H
2000H=2.000V
Vcc Supply Maximum Voltage
2700H=2.700V
3600H=3.600V
1650H=1.650V
Vcc Supply Minimum Voltage
2250H=2.250V
2350H=2.350V
2700H=2.700V
HW Reset# pin
0=not support
1=support
00
0b
HW Hold# pin
0=not support
1=support
01
0b
0=not support 1=support
02
1b
0=not support 1=support
03
1b
Deep Power Down Mode
SW Reset
SW Reset Opcode
Should be issue Reset Enable(66H)
before Reset cmd.
95H:94H
11:04
1001 1001b
(99H)
799CH
Program Suspend/Resume
0=not support
1=support
12
1b
Erase Suspend/Resume
0=not support
1=support
13
1b
14
1b
15
0b
96H
23:16
FFH
FFH
97H
31:24
00H
00H
00
0b
01
0b
09:02
FFH
10
0b
1=support
11
1b
1=support
12
0b
13
0b
Unused
15:14
11b
Unused
31:16
FFFFH
Unused
Wrap
Around Read mode
0=not support 1=support
Wrap - Around Read mode Opcode
08H:support 8B wra-paround read
Wrap - Around Read data length
16H:8B&16B
32H:8B&16B&32B
64H:8B&16B&32B&64B
Individualblock lock
Individual block lock bit
(Volatile/Nonvolatile)
0=not support
1=support
0=Volatile
1=Nonvolatile
Individual block lock Opcode
Individual blocklock Volatile
protect bit default protect status
0=protect
Secured OTP
0=not support
Read Lock
0=not support
Permanent Lock
0=not support
1=unprotect
1=support
9BH:98H
CBFCH
FFFFH
54
ZD25WD40B
6. Ordering Information
ZD 25XX XX X X X
X X
Packaging Type
T:Tube
R:Tape & Reel
Y:Tray
Green Code
G: Low-halogen, Lead(Pb)-free
P: Lead (Pb) - free
Temperature Range
I: Industrial(-40℃~85℃)
E: Extended (-25℃~85℃)
J:Industrial Plus (-40℃~105℃)
Package Type
S: 208mil SOP8
T: 150mil SOP8
U:USON8(3*2mm)
E:USON8(3*3mm,0.65mm)
N:USON8(3*3mm,0.5mm)
O:173mil TSSOP8
Version
A: A Version
B: B Version
C: C Version
Device Density
20: 2Mbit
40: 4Mbit
80: 8Mbit
16: 16Mbit
Base Part Number
1.8V Serial 4Kbyte Uniform-sector Flash
Zetta
Memory
Figure 1, Ordering Information
ZD25WD40B
7.
Package Information
7.1-Lead SOP(150mil)
θ
8
5
E1
E
L
1
L1
h
4
C
D
A3
A2 A
A1
SEATING PLANE
0.10
b
e
Dimensions
Symbol
A
A1
A2
A3
b
C
D
E
E1
Min
-
0.10
1.30
0.6
0.39
0.20
4.80
5.80
3.80
Nom
-
-
1.40
0.65
-
-
4.90
5.90
3.90
Max
1.75
0.225
1.50
0.7
0.47
0.24
5.00
6.20
4.00
Min
-
Nom
-
Unit
mm
Inch
Max
0.004 0.051 0.024 0.015 0.008 0.189
-
0.055 0.026
-
-
0.193
0.069 0.009 0.059 0.028 0.019 0.009 0.197
0.228 0.150
e
1.27
BSC
0.050
0.236 0.154 BSC
0.244 0.158
h
θ
0.25
0
-
-
0.80
0.50
8
0.020
0.010
0
-
-
0.020
8
L
L1
0.50
-
0.031
1.05
0.041
56
ZD25WD40B
TITLE
8-Lead SOP(150mil)
DRAWING NO.
REV
A
REF
JEDEC MS-012
57
ZD25WD40B
7.2-Lead SOP(208mil)
θ
8
5
E1
E
L1
L
1
4
C
D
A3
A2
A
A1
SEATING PLANE
0.10
b
e
Dimensions
Symbol
A
A1
A2
A3
b
Min
1.75
0.05
1.70
0.55
0.38
Nom
1.9
0.1
1.80
0.60
0.43
Unit
mm
Inch
Max
2.05
0.15
1.90
0.65
0.48
Min
0.069
0.002
0.067
0.022
0.015
Nom
0.075
0.004
0.071
0.024
0.017
Max
0.081
0.006
0.075
0.026
0.019
TITLE
8-Lead SOP(208mil)
DRAWING NO.
C
0.203
REF
0.008
REF
D
E
E1
5.13
7.70
5.18
5.23
7.90
5.28
5.33
8.10
5.38
0.202
0.303
0.204
0.206
0.311
0.208
0.210
0.319
0.212
REV
A
e
1.27
REF
0.050
REF
L
L1
θ
0.50
1.21
0
0.65
1.31
-
0.80
1.41
8
0.020
0.048
0
0.026
0.052
-
0.031
0.056
8
REF
58
ZD25WD40B
7.3-Lead TSSOP(173mil)
8
5
E1 E
“A”
1
4
C
D
b
A3
e
A2
A
0.25
GAUGE PLANE
L
A1
θ
L1
SEATING PLANE
DETAIL “A”
0.10
Dimensions
Symbol
A
A1
A2
A3
b
C
D
E
E1
Min
-
0.05
0.90
0.39
0.20
0.13
2.90
6.20
4.30
Nom
-
-
1.00
0.44
-
-
3.00
6.40
4.40
Max
1.20
0.15
1.05
0.49
0.28
0.17
3.10
6.60
4.50
Min
-
0.002
0.035
0.015
0.008
0.005
0.114
0.244
0.169
Nom
-
-
0.039
0.017
-
-
0.118
0.252
0.173
Max
0.047
0.006
0.041
0.019
0.011
0.007
0.122
0.260
0.177
Unit
mm
Inch
TITLE
8-lead TSSOP
DRAWING NO.
REV
A
e
0.65
BSC
0.026
BSC
L
0.45
0.75
0.018
0.030
L1
1.00
REF
0.039
REF
θ
0
8
0
8
REF
JEDEC MO-153
59
ZD25WD40B
7.4-Land USON(3x2mm,thickness 0.55mm)
D
b
e
L
L1
D1
E1
E
PIN1 I.D.
L3
1
TOP VIEW
BOTTOM VIEW
A2
A
A3
A1
SEATING PLANE
SIDE VIEW
0.05
Dimensions
Symbol
A
A1
A2
A3
Min
0.50
0.00
-
-
0.20
1.90
1.55
2.90
0.15
Nom
0.55
0.02
0.40
0.15
0.25
2.00
1.60
3.00
0.20
Max
0.60
0.05
-
-
0.30
2.10
1.65
3.10
Min
0.015
0.00
-
-
0.007
0.074
0.061
Nom
0.018
---
0.012
0.005
0.010
0.079
Max
0.019
0.001
-
-
0.012
0.082
Unit
mm
Inch
TITLE
DFN8L(0203X0.55-0.5)
b
DRAWING NO.
D
D1
E
L1
L3
0.30
-
0.40
0.35
0.10
0.45
0.25
0.40
-
0.50
0.114
0.005
0.011
-
0.012
0.063
0.118
0.008
0.064
0.122
0.009
REV
A
E1
e
0.50
0.02
L
0.013 0.004
0.016
0.015
0.020
-
REF
JEDEC MO-252
60
ZD25WD40B
7.5-Land USON(2x3mm, thickness 0.50mm)
61
ZD25WD40B
7.6. Package USON8 (1.5x1.5mm)
62
ZD25WD40B
8.
Revision History
Rev.
Date
Description
V1.0
2020-12-01
Preliminary datasheet
V1.1
2021-08-01
Package information update
62
工商网监
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