SILICON CONTENT
TECHNOLOGY
SCT12A0
December 2017
2.7V-14V Vin, 30W Fully Integrated Synchronous Boost Converter
FEATURES
DESCRIPTION
Wide Input Voltage Range: 2.7V-14.0V
Wide Output Voltage Range: 4.5V-14.6V
Fully Integrated High-side/Low-side Power
MOSFETs：13mΩ/11mΩ
Up to 12A Switch Current and Programmable
Peak Current Limit
Typical Shut-down Current: 1uA
Programmable Switching Frequency: 200kHz2.2MHz
Output Overvoltage Protection at 15.4V
Feedback Overvoltage Protection at 110% of
Reference Voltage
Selectable PFM or Forced PWM Mode
Programmable Soft Start
Thermal Shutdown Protection: 150°C
Available in DFN-20 3.5mmx4.5mm Package
APPLICATIONS
Bluetooth Audio
Power Banks
POS System
E-Cigarette
USB Power Delivery
The SCT12A0 is a high efficiency synchronous boost
converter with fully integrated a 13mΩ high-side
MOSFET and an 11mΩ low-side MOSFET,
supporting 2.7V to 14V input voltage range and up to
12-A switch current. The switch current limit can be
adjustable with an external resistor.
The SCT12A0 adapts constant off-time peak current
control to provide fast transient. An external
compensation network allows flexibility setting loop
dynamics to achieve optimal transient performance at
different load conditions. Using MODE pin selects
either Pulse Frequency Modulation (PFM) operation
or forced Pulse Width Modulation (PWM) operation.
The switching frequency in PWM mode is adjustable
from 200KHz to 2.2MHz by an external resistor. The
device also features programmable soft-start time
with an external capacitor.
The SCT12A0 monitors both output voltage and
feedback voltage to protect overvoltage condition. It
features cycle-by-cycle peak current limit and thermal
shutdown protection when the device over loads.
The device is available in a low-profile package DFN20L 3.5mmx4.5mmx0.75mm with enhanced thermal
power pad.
TYPICAL APPLICATION
Efficiency, Vout=9V
100%
Efficiency
90%
80%
Efficiency
70%
60%
VIN=3.0V PWM
50%
VIN=3.6V PWM
40%
VIN=4.2V PWM
VIN=3.0V PFM
30%
VIN=3.6V PFM
20%
VIN=4.2V PFM
10%
0%
0.01
0.10
1.00
10.00
Output Current (A)
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1
SCT12A0
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DEVICE ORDER INFORMATION
PART NUMBER
PACKAGE MARKING
PACKAGE DISCRIPTION
SCT12A0
12A0
20-Lead 3.5mm×4.5mm Plastic DFN
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
MIN
MAX
UNIT
BOOT
-0.3
23.5
V
VIN, SW, VOUT, FSW
-0.3
18
AGND
Top View: 20-Lead Plastic DFN 3.5mmx4.5mm
VCC
Over operating free-air temperature unless otherwise
PIN CONFIGURATION
noted(1)
ILIM
EN
FSW
COMP
SW
V
FB
VOUT
SW
PGND
5.5
V
Operating junction temperature TJ (2)
-40
125
C
Storage temperature TSTG
-65
150
C
(1)
(2)
SW
VOUT
SW
VOUT
BOOT
MODE
VIN
NC
NC
-0.3
SS
VCC, LIM，FB， EN, SS, COMP,
MODE
Stresses beyond those listed under Absolut Maximum Rating may cause device permanent damage. The device is not guaranteed to
function outside of its Recommended Operation Conditions.
The IC includes over temperature protection to protect the device during overload conditions. Junction temperature will exceed 150°C
when over temperature protection is active. Continuous operation above the specified maximum operating junction temperature will
reduce lifetime
PIN FUNCTIONS
NAME
VCC
1
EN
2
FSW
SW
2
NO.
3
4,5,6,7
BOOT
8
VIN
9
SS
10
NC
11, 12
MODE
13
VOUT
14,15,16
PIN FUNCTION
Internal linear regulator output. Connect a 1uF or larger ceramic capacitor to
ground. VCC cannot to be externally driven. No additional components or loading
is recommended on this pin.
Enable logic input. A 500KΩ resistor connects this pin to ground inside. Floating
disables the device.
Place a resistor from this pin to SW to sets the switching frequency.
Switching node of the boost converter.
Power supply for the high-side power MOSFET gate driver. Must connect a 0.1uF
or greater ceramic capacitor between BOOT pin and SW node.
Power supply input. Must be locally bypassed with a 0.1uF capacitor as close to
the pin as possible.
Place a ceramic cap from this pin to ground to program soft-start time. An internal
5uA current source pulls SS pin to VCC.
Not connected inside. Connect to ground pad under IC on PCB for thermal
dissipation and impendence reduction of C6 ground loop.
Operation mode selection. 270KΩ internal resistor connects this pin to VCC.
Floating or logic high enables PFM mode. Logic low enables forced PWM mode.
Boost converter output. Connect a 1uF decoupling capacitor as close to VOUT pins
and power ground pad as possible to reduce the ringing voltage of SW.
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SCT12A0
Feedback Input. Connect a resistor divider from VOUT to FB to set up output
voltage. The device regulates FB to the internal reference value of 1.2V typical.
Output of the error amplifier and switching converter loop compensation point.
Inductor peak current limit set point input. A resistor connecting this pin to ground
sets current limit through low-side power FET.
FB
17
COMP
18
ILIM
19
AGND
20
Analog ground. Analog ground should be used as the common ground for all small
signal analog inputs and compensation components. No electrical connection to
PGND inside.
PGND
21
Power ground. Must be soldered directly to ground planes using multiple vias
directly under the IC for improved thermal performance and electrical contact.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range unless otherwise noted
PARAMETER
VIN
VOUT
TJ
DEFINITION
Input voltage range
Output voltage range
Operating junction temperature
MIN
MAX
UNIT
2.7
4.5
-40
14
14.6
125
V
V
°C
MIN
MAX
UNIT
-2
+2
kV
-0.5
+0.5
kV
ESD RATINGS
PARAMETER
Human Body Model (HBM), per ANSI-JEDEC-JS-0012014 specification, all pins (1)
Charged Device Model (CDM), per ANSI-JEDEC-JS-0022014specification, all pins (1)
VESD
(1)
DEFINITION
HBM and CDM stressing are done in accordance with the ANSI/ESDA/JEDEC JS-001-2014 specification
THERMAL INFORMATION
PARAMETER
RθJA
RθJC
THERMAL METRIC
Junction to ambient thermal resistance (1)
Junction to case thermal resistance
(1)
DFN-20L
38
39
UNIT
°C/W
(1) SCT provides RθJA and RθJC numbers only as reference to estimate junction temperatures of the devices. RθJA and RθJC are not a
characteristic of package itself, but of many other system level characteristics such as the design and layout of the printed circuit
board (PCB) on which the SCT12A0 is mounted, thermal pad size, and external environmental factors. The PCB board is a heat sink
that is soldered to the leads and thermal pad of the SCT12A0. Changing the design or configuration of the PCB board changes the
efficiency of the heat sink and therefore the actual RθJA and RθJC.
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SCT12A0
ELECTRICAL CHARACTERISTICS
VIN=3.6V, TJ=-40°C~125°C, typical values are tested under 25°C.
SYMBOL
PARAMETER
TEST CONDITION
MIN
Power Supply and Output
VIN
Operating input voltage
VOUT
Output voltage range
VIN_UVLO
Input UVLO
Hysteresis
ISD
Shutdown current
IQ
VCC
MAX
UNIT
2.7
14
V
4.5V
14.6
V
2.6
200
2.7
V
mV
1
3
uA
150
uA
uA
V
1.220
1.228
100
V
V
nA
VIN rising
Quiescent current from VIN
Quiescent current from VOUT
Internal linear regulator
TYP
EN=0, No load. Measured on
VIN pin
EN=2V, No load, No switching.
Measured on VIN pin.
1
120
4.8
IVCC=5mA, VIN=6V
Reference and Control Loop
FPWM mode
PSM mode
VFB=1.2V
1.170
1.192
1.202
1.210
VREF
Reference voltage of FB
IFB
FB pin leakage current
GEA
VCOMP=1.5V
190
uS
VFB=VREF-200mV, VCOMP=1.5V
20
uA
ICOMP_SNK
Error amplifier trans-conductance
Error amplifier maximum source
current
Error amplifier maximum sink current
VFB=VREF+200mV, VCOMP=1.5V
20
uA
VCOMP_H
COMP high clamp
VFB=1V， RILIM=100KΩ
1.5
V
VCOMP_L
COMP low clamp
VFB=1.5V, RILIM=100KΩ,PFM
0.6
V
Power MOSFETs
RDSON_H
High side FET on-resistance
13
mΩ
RDSON_L
11
mΩ
ICOMP_SRC
Low side FET on-resistance
Current Limit
ILIM
Peak current limit
RILIM=100kΩ
Enable and Mode
Enable high threshold
VEN
Enable low threshold
REN
Enable pull down resistance
RMODE
MODE high threshold
MODE low threshold
MODE pull-up resistance
ISS
Soft-start charging current
VMODE
10.5
12
13
A
1.2
V
V
kΩ
4
270
V
V
kΩ
5
uA
VCC=5V
0.4
800
VCC=5V
1.5
Switching Frequency
FSW
Switching frequency
RFSW=301k, VOUT=12V
500
tON_MIN
Minimum on-time
RFSW=301k, VOUT=12V
150
200
ns
TOFF_MIN
Minimum off-time
RFSW=301k, VFB=0V
100
150
ns
Output overvoltage threshold
Hysteresis
Feedback overvoltage with respect to
reference voltage
VOUT rising
15.4
250
110
105
kHz
Protection
VOVP_VOUT
VOVP_VFB
4
VFB rising
VFB falling
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V
mV
%
%
SCT12A0
SYMBOL
PARAMETER
TEST CONDITION
TSD
Thermal shutdown threshold
Hysteresis
TJ rising
MIN
TYP
MAX
UNIT
150
20
°C
°C
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
78%
76%
74%
72%
70%
Efficiency
Efficiency
TYPICAL CHARACTERISTICS
VIN=3V
VIN=3.6V
VIN=4.2V
VIN=5V
0.01
0.10
1.00
10.00
VOUT=5V
VOUT=9V
VOUT=12V
0.01
Output Current (A)
Figure 1. Efficiency, Vout=9V, fsw=560KHz, PFM
0.10
1.00
10.00
Output Current (A)
Figure 2. Efficiency, Vin=3.6V, fsw=560KHz, PFM
100%
100%
90%
90%
80%
80%
70%
Efficiency
70%
Efficiency
100%
98%
96%
94%
92%
90%
88%
86%
84%
82%
80%
78%
76%
74%
72%
70%
60%
50%
40%
VIN=3.6V
VOUT=5V
VOUT=9V
30%
VIN=4.2V
20%
50%
40%
VIN=3V
30%
60%
VOUT=12V
20%
VIN=5V
10%
10%
0
1
2
3
4
5
Output Current (A)
Figure 3. Efficiency, Vout=9V, fsw=560KHz, PWM
0
1
2
3
4
5
Output Current (A)
Figure 4. Efficiency, Vin=3.6V, fsw=560KHz, PWM
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5
SCT12A0
2500
Switch Peak Current Limit
16
Frequency (KHz)
2000
1500
1000
500
14
12
10
8
6
4
2
0
0
0
100
200
300
400
500
600
700
800
50
900
100
150
Resistance (K Ohm)
250
300
350
Resistance (K Ohm)
Figure 5. Switching Frequency vs FSW Resistance
Figure 6. Inductor Peak Current Limit vs RLIM Resistance
160
Quiescent Current (uA)
600
590
Frequency (KHz)
200
580
570
560
140
120
100
80
60
40
20
0
550
-40
-20
0
20
40
60
80
(OC)
100
80
100
120
Temperature
Figure 7. Frequency vs Temperature
140
-40
-20
0
20
40
60
80
100
120
140
Temperature (OC)
Figure 8. Quiescent Current vs Temperature
1.5
1.4
Shutdown Current (uA)
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
-20
0
20
40
60
120
140
Temperature (OC)
Figure 9. Shutdown Current vs Temperature
6
Figure 10. Feedback Reference Voltage vs Temperature
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SCT12A0
Figure 11. Load Regulation (Vin=3.6V, Vout=9V)
Figure 12. Line Regulation
FUNCTIONAL BLOCK DIAGRAM
UVLO
VIN
9
VCC
BOOT
SW
SW
SW
SW
1
8
4
5
6
7
OTP
UVLO
BOOT
Regulator
LDO
Thermal
Sensor
14
VOUT
15
VOUT
16
VOUT
21
PGND
Q2
VOUT
Q1
NC
NC
11
Dead Time and
PWM Control
Logic
12
OVP
270K
VCC
R
S
Q
VCC
OVP
Q
ILSD Sense
5uA
+
+
13
Mode
SelectIon
GM
+
+
MODE
17
FB
10
SS
18
COMP
+
1.2V
1/N
UVLO OVP OTP
30pF
V/I
3
+
FSW
ON/OFF and Protection
VIN
800K
1.2V
2
19
20
EN
ILIM
AGND
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7
SCT12A0
OPERATION
Overview
The SCT12A0 device is a fully integrated synchronous boost converter, which regulates output voltage higher than
input voltage. The constant off-time peak current mode control provides fast transient with pseudo fixed switching
frequency. When low-side MOSFET Q1 turns on, input voltage forces the inductor current rise. When sensed
voltage on low-side MOSFET peak current rises above the voltage of COMP, the device turns off low-side MOSFET
and inductor current goes through body diode of high-side MOSFET Q2 during dead time. After dead time duration,
the device turns on high-side MOSFET Q2 and the inductor current decreases. Based on Vin and Vout voltage, the
device predicts required off-time and turns off high-side MOSFET Q2. This repeats on cycle-by-cycle based.
The negative voltage feedback loop regulates the FB voltage to a 1.2V reference with an internal trans-conductance
error amplifier. The feedback loop stability and transient response are optimized through an external loop
compensation network connected to the COMP pin.
The mode selection offers flexibility of design between forced Pulse Width Modulation (PWM) and Pulse Frequency
Modulation (PFM) operations. When MODE pin is connected to VCC or floats, the SCT12A0 works at PFM mode
to further increase the efficiency in light load condition. If MODE pin is connected to ground, the device works in
forced PWM mode with low output voltage ripple.
The quiescent current of SCT12A0 is 110uA typical under no-load condition and not switching. Disabling the device,
the typical supply shutdown current is 1μA.
A resistor connected between SW pin and the FSW pin sets the switching frequency. The wide switching frequency
range of 200 kHz to 2.2 MHz offers optimization on efficiency or size of filter components.
The SCT12A0 device features adjustable soft-start time, cycle-by-cycle low-side FET current limit, over-voltage
protection, and over-temperature protection.
The SCT12A0 uses two separate ground pins to avoid ground bouncing due to the high switching current through
the N-channel power MOSFET. AGND pin sets the reference for all control functions. The source of the power
MOSFET connects to PGND pin. Both grounds must be connected to the thermal pad on the PCB at the closest
point.
VIN Power
The SCT12A0 is designed to operate from an input voltage supply range between 2.7 V to 14V. If the input supply
is located more than a few inches from the converter, additional bulk capacitance may be required in addition to the
ceramic bypass capacitors. A typical choice is an electrolytic or tantalum capacitor with a value of 47μF.
VCC Power
The internal VCC LDO provides the bias power supply for internal circuitries. A ceramic capacitor of no less than
1uF is required to bypass from VCC pin to ground. During starting up, input of VCC LDO is from VIN pin. Once the
output voltage at VOUT pin exceeds VIN voltage, VCC LDO switches its input to VOUT pin. This allows higher
voltage headroom of VCC at lower input voltage. The maximum current capability of VCC LDO is 130mA typical.
No additional components or loading are recommended on this pin.
Under Voltage Lockout UVLO
The SCT12A0 features UVLO protection for voltage rails of VIN, VCC and BOOT-SW from the converter malfunction
and the battery over discharging. The default VIN rising threshold is 2.6V typical at startup and falling threshold is
2.4V typical at shutdown. The internal VCC LDO dropout voltage is about 100mV and the device is disabled when
VCC falling trips 2.1V typical threshold. The internal charge pump from BOOT to SW powers the gate driver to highside MOSFET Q2. The BOOT UVLO circuit monitors the capacitor voltage between BOOT pin and SW pin. When
the voltage of BOOT-SW falls below a preset threshold 3V typical, high-side MOSFET Q2 turns off. As a result, the
device works as a non-synchronous boost converter.
Enable and Start-up
8
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SCT12A0
When applying a voltage higher than the EN high threshold (maximum 1.2V), the SCT12A0 enables all functions
and starts converter operation. To disable converter operation, EN voltage needs fall below its lower threshold
(minimum 0.4V). An internal 800KΩ resistor connects EN pin to the ground. Floating EN pin automatically disables
the device.
The SCT12A0 features programmable soft start to prevent inrush current during power-up. SS pin sources an
internal 5μA current charging an external soft-start capacitor CSS when EN pin exceeds turn-on threshold. The
device uses the lower voltage between the internal voltage reference 1.2V and the SS pin voltage as the reference
input voltage of error amplifier and regulates the output. The soft-start completes when SS pin voltage exceeds the
internal 1.2V reference. Use equation 1 to calculate the soft-start time (10% to 90%). When EN pin is pulled low to
disable the device, the SS pin will be discharged to ground.
t SS =
where
CSS ∗ VREF
ISS
(1)
tSS is the soft start time
VREF is the internal reference voltage of 1.2V
CSS is the capacitance connecting to SS pin
ISS is the source current of 5uA to SS pin
Adjustable Switching Frequency
The SCT612A0 features adjustable switching frequency from 200kHz to 2.2MHz. To set the switching frequency,
an external resistor between SW pin and FSW pin is a must to guarantee the proper operation. Use Equation 2 or
the curves in Figure 5 to determine the resistance for a given switching frequency. To reduce the solution size, one
would typically set the switching frequency as higher as possible, but need to consider the tradeoff of the thermal
dissipation and minimum on time of low-side power MOSFET.
6∗(
𝑅𝐹𝑅𝐸𝑄 =
where:
1
𝑓𝑆𝑊
− 𝑇𝐷𝐸𝐿𝐴𝑌 ∗
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁
)
(2)
𝐶𝐹𝑅𝐸𝑄
fSW is the desired switching frequency
TDELAY = 90 ns
CFREQ = 34 pF
VIN is the input voltage
VOUT is the output voltage
Adjustable Peak Current Limit
The SCT12A0 boost converter implements cycle-by-cycle peak current limit function with sensing the internal lowside power MOSFET Q1 during over current condition. While the Q1 is turned on, its conduction current is monitored
by the internal sensing circuitry. Once the low-side MOSFET Q1 current exceeds the limit, it turns off immediately.
An external resistor connecting ILIM pin to ground sets the low-side MOSFET Q1 peak current limit threshold. Use
Equation 3 or Figure 6 to calculate the peak current limit.
𝐼𝐿𝐼𝑀 =
1200
𝑅𝐿𝐼𝑀
(3)
where:
ILIM is the peak current limit
RLIM is the resistance between ILIM pin to ground.
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SCT12A0
This current limit function is realized by detecting the current flowing through the low-side MOSFET. The current
limit feature loses function in the output hard short circuit conditions. At normal operation, when the output hard
shorts to ground, there is a direct path to short the input voltage through high-side MOSFET Q2 or its body diode
even the Q2 is turned off. This could damage the circuit components and cause catastrophic failure at load circuit.
Once VIN is present, VOUT is moved to VIN level due to the direct path from input to output even when the device
is shut down or the load is not ready. The presence of unwanted output voltage before system start up sequence
could cause system latch off or malfunction.
To address the above issue, users need design external circuits for protection or choose SCT12A1 from Silicon
Content Technology, which provides an option to insert an external P-channel MOSFET to disconnect output from
input in application. Refer SCT12A1 data sheet for details of load disconnection feature.
Over Voltage Protection and Minimum On-time
The SCT12A0 features both VOUT pin over voltage protection and the FB pin over voltage protection. If the VOUT
pin is above 15.4V typical or FB pin voltage exceeds 1.32V typical, the device stops switching immediately until the
VOUT pin drops below 15.2 V or FB pin voltage drops below 1.26V. The OVP function prevents the connected
output circuitry from un-predictive overvoltage. Featured feedback overvoltage protection prevents dynamic voltage
spike to damage the circuitry at load during fast loading transient.
The low-side MOSFET has minimum on-time 150ns typical limitation. While the device is operating at minimum on
time and further increasing Vin pushed output voltage beyond regulation point. With output and feedback over
voltage protection, the converter skips pulse with turning off high-side MOSFET and prevents output running higher
to damage the load.
Forced PWM and PFM Modes
Connecting MODE pin to ground, the SCT12A0 forces the device operating at forced Pulse Width Modulation
(PWM) mode with pseudo-fixed switching frequency regardless loading current. Operating in PWM mode can avoid
the possible audible noise caused by lower frequency in PFM mode at light load. When the load current approaches
zero, the high-side MOSFET current crosses zero and sinks current from output to maintain the constant output.
Hence power efficiency in light load is much lower than heavy load.
Floating MODE pin or connecting MODE pin to VCC, the SCT12A0 works at Pulse Frequency Modulation (PFM)
mode to improve the power efficiency in light load. As the load current decreasing, the COMP pin voltage decreases
as resulting the inductor current down. With the load current further decreasing, the COMP pin voltage decreases
and be clamped to a voltage corresponding to the ILIM/12. The converter extends the off time of high-side MOSFET
Q2 to reduce the average delivered current to output. The switching frequency is lower and varied depending on
loading condition. In PFM mode, the peak inductor current is fixed at around 1A and the output voltage is regulated
0.7% higher than the setting output voltage. When the inductor current decreased to zero, zero-cross detection
circuitry on high-side MOSFET Q2 forces the Q2 off until the beginning of the next switching cycle. The boost
converter does not sink current from the load at light load.
Thermal Shutdown
Once the junction temperature in the SCT12A0 exceeds 150OC, the thermal sensing circuit stops switching until the
junction temperature falling below 130C, and the device restarts. Thermal shutdown prevents the damage on device
during excessive heat and power dissipation condition.
10
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SCT12A0
APPLICATION INFORMATION
Typical Application
L1 1.5uH
VIN=2.7V-8.4V
C4 0.1uF
R2
270k
C2
2x 22uF
SW
VOUT=9V
BOOT
FSW
VOUT
VIN
C6
1uF
ON
EN
OFF
C7
100uF
R3
383k
SCT12A0
C1
0.1uF
MODE
FB
VCC
SS
C3
1uF
COMP
ILIM
C5
47nF
R5
16.9k
PGND
R4
59k
AGND
R1
100k
47pF
Optional
C9
C8
4.7nF
Figure 13. One Cell Battery Input, 9V/3A (30W) Output
Design Parameters
Design Parameters
Example Value
Input Voltage
3.0V to 4.2V
Output Voltage
9V
Output Current
3A
Output voltage ripple (peak to peak)
100mV
Switching Frequency
560 kHz
Operation Mode
PFM
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SCT12A0
Switching Frequency
The resistor connected from FSW to SW sets switching frequency of the converter. The resistor value required for
a desired frequency can be calculated using equation 2. High frequency can reduce the inductor and output
capacitor size with the tradeoff of more thermal dissipation and lower efficiency.
6∗(
𝑅𝐹𝑅𝐸𝑄 =
1
𝑓𝑆𝑊
− 𝑇𝐷𝐸𝐿𝐴𝑌 ∗
𝑉𝑂𝑈𝑇
𝑉𝐼𝑁
)
Table 1. RFSW Value for Common Switching Frequencies
(Vin=3.6V, Vout=9V, Room Temperature)
𝐶𝐹𝑅𝐸𝑄
where:
Fsw
RFSW
fSW is the desired switching frequency
200 KHz
750KΩ
TDELAY = 90 ns
350 KHz
422 KΩ
CFREQ = 34 pF
520 KHz
270 KΩ
VIN is the input voltage
730 KHz
196 KΩ
VOUT is the output voltage
1000 KHz
127 KΩ
2000 KHz
48.7 KΩ
Peak Current Limit
Using the correct external resistor at ILIM pin sets the peak input current. Table 2 shows the resistor value for
inductor peak current limit. For a typical current limit of 12A, the resistor value is 100KΩ. The minimum current limit
must be higher than the required peak switch current at lowest input voltage and the highest output power not to hit
the current limit and still regulate the output voltage.
𝐼𝐿𝐼𝑀 =
Table 2. RLIM Value for Inductor Peak Current
(Vin=3.6V, Vout=9V, L=1.5uH, Room Temperature)
1200
𝑅𝐿𝐼𝑀
where:
ILIM
RLIM
ILIM is the peak current limit
12 A
100 KΩ
RLIM is the resistance of ILIM pin to ground
8A
154 KΩ
6.3A
200 KΩ
4.4A
301 KΩ
Output Voltage
The output voltage is set by an external resistor divider R3 and R4 in typical application schematic. A minimum
current of typical 20uA flowing through feedback resistor divider gives good accuracy and noise covering. The value
of R3 can be calculated by equation 4.
(𝑉𝑂𝑈𝑇 − 𝑉𝑅𝐸𝐹 ) × 𝑅4
𝑅3 =
𝑉𝑅𝐸𝐹
Table 3. Feedback Resistor R3 R4Value for Output Voltage
(Room Temperature)
(4)
where:
VREF is the feedback reference voltage,
typical 1.2V
12
VOUT
R3
R4
5 V
187 KΩ
59 KΩ
9 V
383 KΩ
59 KΩ
12 V
536 KΩ
59 KΩ
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Inductor Selection
The performance of inductor affects the power supply’s steady state operation, transient behavior, loop stability,
and boost converter efficiency. The inductor value, DC resistance, and saturation current influences both efficiency
and the magnitude of the output voltage ripple. Larger inductance value reduces inductor current ripple and
therefore leads to lower output voltage ripple. For a fixed DC resistance, a larger value inductor yields higher
efficiency via reduced RMS and core losses. However, a larger inductor within a given inductor family will generally
have a greater series resistance, thereby counteracting this efficiency advantage.
Inductor values can have ±20% or even ±30% tolerance with no current bias. When the inductor current approaches
saturation level, its inductance can decrease 20% to 35% from the value at 0-A current depending on how the
inductor vendor defines saturation. When selecting an inductor, choose its rated current especially the saturation
current larger than its peak current during the operation.
To calculate the current in the worst case, use the minimum input voltage, maximum output voltage, maxim load
current and minimum switching frequency of the application, while considering the inductance with -30% tolerance
and low-power conversion efficiency.
For a boot converter, calculate the inductor DC current as in equation 5
𝐼𝐿𝐷𝐶 =
Where
𝑉𝑂𝑈𝑇 × 𝐼𝑂𝑈𝑇
𝑉𝐼𝑁 × 𝜂
(5)
VOUT is the output voltage of the boost converter
IOUT is the output current of the boost converter
VIN is the input voltage of the boost converter
η is the power conversion efficiency
Calculate the inductor current peak-to-peak ripple, ILPP, as in equation 6.
𝐼𝐿𝑃𝑃 =
Where
1
𝐿×(
1
𝑉𝑂𝑈𝑇 −𝑉𝐼𝑁
+
1
𝑉𝐼𝑁
(6)
) × 𝑓𝑆𝑊
ILPP is the inductor peak-to-peak current
L is the inductance of inductor
fSW is the switching frequency
VOUT is the output voltage
VIN is the input voltage
Therefore the peak switching current of inductor, ILPEAK, is calculated as in equation 7.
𝐼𝐿𝑃𝐸𝐴𝐾 = 𝐼𝐿𝐷𝐶 +
𝐼𝐿𝑃𝑃
2
(7)
Set the current limit of the SCT12A0 higher than the peak current I LPEAK and select the inductor with the saturation
current higher than the current limit.
The inductor’s DC resistance (DCR) and the core loss significantly affect the efficiency of power conversion. Core
loss is related to the core material and different inductors have different core loss. For a certain inductor, larger
current ripple generates higher DCR and ESR conduction losses and higher core loss. Usually, a data sheet of an
inductor does not provide the ESR and core loss information. If needed, consult the inductor vendor for detailed
information. There is a tradeoff among the inductor’s inductance, DCR and ESR resistance, and its footprint.
Shielded inductors typically have higher DCR than unshielded inductors. Table 4 lists recommended inductors for
the SCT12A0. Verify whether the recommended inductor can support the user's target application with the previous
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13
SCT12A0
calculations and bench evaluation. In this application, the WB's inductor CDMC8D28NP-1R2MC is used on
SCT12A0 evaluation board.
Table 4. Recommended Inductors
Part Number
L
(uH)
DCR Max
(mΩ)
Saturation Current/Heat
Rating Current (A)
Size Max
(LxWxH mm)
Vendor
WE-HCI SMD 7443552150
1.5
5.3
17 / 14
10.5 x 10.2 x 4.0
WurthElektronix
CDMC8D28NP-1R2MC
1.2
7.0
12.2 / 12.
9.5 x 8.7 x 3.0
Sumida
Input Capacitor Selection
For good input voltage filtering, choose low-ESR ceramic capacitors. A 0.1μF ceramic bypass capacitor is
recommended to be placed as close as possible to the VIN pin of the SCT12A0. A ceramic capacitor of more than
1.0μF is required at the VCC pin to get a stable operation of the internal LDO.
For the power stage, because of the inductor current ripple, the input voltage changes if there is parasite inductance
and resistance between the power supply and the inductor. It is recommended to have enough input capacitance
to make the input voltage ripple less than 100mV. Generally, 2x 22μF input capacitance is recommended for most
applications. Choose the right capacitor value carefully considering high-capacitance ceramic capacitors DC bias
effect, which has a strong influence on the final effective capacitance.
Output Capacitor Selection
For small output voltage ripple, choose a low-ESR output capacitor like a ceramic capacitor. Typically, 3～4x 22μF
ceramic output capacitors work for most applications. Higher capacitor values can be used to improve the load
transient response. Due to a capacitor’s derating under DC bias, the bias can significantly reduce capacitance.
Ceramic capacitors can lose most of their capacitance at rated voltage. Therefore, leave margin on the voltage
rating to ensure adequate effective capacitance. From the required output voltage ripple, use the equation 8 and 9
to calculate the minimum required effective capacitance, COUT.
𝑉𝑟𝑖𝑝𝑝𝑙𝑒_𝐶 =
(𝑉𝑂𝑈𝑇 − 𝑉𝐼𝑁_𝑀𝐼𝑁 ) × 𝐼𝑂𝑈𝑇
𝑉𝑂𝑈𝑇 × 𝑓𝑆𝑊 × 𝐶𝑂𝑈𝑇
(8)
𝑉𝑟𝑖𝑝𝑝𝑙𝑒_𝐸𝑆𝑅 = 𝐼𝐿𝑝𝑒𝑎𝑘 × 𝐸𝑆𝑅
where
(9)
Vripple_C is output voltage ripple caused by charging and discharging of the output capacitor.
Vripple_ESR is output voltage ripple caused by ESR of the output capacitor.
VIN_MIN is the minimum input voltage of boost converter.
VOUT is the output voltage.
IOUT is the output current.
ILpeak is the peak current of the inductor.
ƒSW is the converter switching frequency.
ESR is the ESR resistance of the output capacitors.
Loop Stability
An external loop compensation network comprises resister R5, ceramic capacitors C8 and C9 connected to the
COMP pin to optimize the loop response of the converter. The power stage small signal loop response of constant
off time with peak current control can be modeled by equation 10.
14
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𝑆
𝑆
𝑅𝑙𝑜𝑎𝑑 × (1 − 𝐷) (1 + 2𝜋×𝑓𝐸𝑆𝑅𝑍)(1 + 2𝜋×𝑓𝑅𝐻𝑃𝑍)
𝐺𝑃𝑆 (𝑆) =
×
𝑆
2 × 𝑅𝑆𝐸𝑁𝑆𝐸
1+
(10)
2𝜋×𝑓𝑃
where
D is the switching duty cycle.
Rload is the output load resistance.
RSENSE is the equivalent internal current sense resistor, which is 0.08 Ω.
𝑓𝑃 =
1
(11)
2𝜋 × 𝑅𝑙𝑜𝑎𝑑 × 𝐶𝑂
where
CO is the output capacitance
𝑓𝑃𝐸𝑆𝑅𝑍 =
1
2𝜋 × 𝐸𝑆𝑅 × 𝐶𝑂
(12)
where
ESR is the equivalent series resistance of the output capacitor.
𝑓𝑃𝐸𝑆𝑅𝑍 =
𝑅𝑙𝑜𝑎𝑑 × (1 − 𝐷)2
2𝜋 × 𝐿
(13)
The COMP pin is the output of the internal trans-conductance amplifier. Equation 14 shows the small signal transfer
function of compensation network.
𝐺𝐸𝐴 × 𝑅𝐸𝐴 × 𝑉𝑅𝐸𝐹
𝐺𝐶 (𝑆) =
×
𝑉𝑂𝑈𝑇
(1 +
where
(1 +
𝑆
2𝜋×𝑓𝐶𝑂𝑀𝑍
𝑆
2𝜋×𝑓𝐶𝑂𝑀𝑃1
)(1 +
)
𝑆
2𝜋×𝑓𝐶𝑂𝑀𝑃2
)
(14)
GEA is the amplifier’s trans-conductance
REA is the amplifier’s output resistance
VREF is the reference voltage at the FB pin
VOUT is the output voltage
ƒCOMP1, ƒCOMP2 are the poles' frequency of the compensation network.
ƒCOMZ is the zero's frequency of the compensation network.
The next step is to choose the loop crossover frequency, ƒ C . The higher frequency that the loop gain stays above
zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no
higher than the lower of either 1/10 of the switching frequency, ƒSW , or 1/5 of the RHPZ frequency, ƒRHPZ.
Then set the value of R5, C8, and C9 in typical application circuit by following these equations.
𝑅5 =
2𝜋 × 𝑉𝑂𝑈𝑇 × 𝑅𝑆𝐸𝑁𝑆𝐸 × 𝑓𝐶 × 𝐶𝑂
(1 − 𝐷) × 𝑉𝑅𝐸𝐹 × 𝐺𝐸𝐴
(15)
where
ƒC is the selected crossover frequency.
𝐶8 =
𝑅𝑙𝑜𝑎𝑑 × 𝐶𝑂
2 × 𝑅5
𝐶9 =
𝐸𝑆𝑅 × 𝐶𝑂
𝑅5
(16)
(17)
If the calculated value of C9 is less than 10pF, it can be left open. Designing the loop for greater than 45°of phase
margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.
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SCT12A0
Application Waveforms
Figure 14. Switching Waveforms and Output Ripple in PWM
Figure 15. Switching Waveforms and Output Ripple in DCM
Figure 16. Switching Waveforms in PFM
Figure 17. Power Up
IOUT
Figure 18. Power Down
16
Figure 19. Load Transient (Vout=9V, Iout=2A to 3A,
SR=250mA/us)
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Layout Guideline
The regulator could suffer from instability and noise problems without careful layout of PCB. Radiation of highfrequency noise induces EMI, so proper layout of the high-frequency switching path is essential. Minimize the length
and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to
minimize coupling. The input capacitor needs to be close to the VIN pin and GND pin to reduce the input supply
ripple. The placement and ground trace for C6 are critical for the performance of SW ringing voltage. Place capacitor
C6 as close to VOUT pin and power ground pad as possible to reduce high frequency ringing voltage on SW pin.
Short NC pins to power ground pad directly to reduce the ground trace impedance of C6.
The layout should also be done with well consideration of the thermal. The center thermal pad should always be
soldered to the board for mechanical strength and reliability, using multiple thermal vias underneath the thermal
pad. The bottom layer is a large ground plane connected to the PGND plane and AGND plane on top layer by vias.
Since thermal pad is electrical power ground of the device, improper soldering thermal pad to ground plate on PCB
will cause SW higher ringing and overshoot besides downgrading thermal performance. it is recommended 8mil
diameter drill holes of thermal vias, but a smaller via offers less risk of solder volume loss. On applications where
solder volume loss thru the vias is of concern, plugging or tenting can be used to achieve a repeatable process.
AGND
L1
VCC
AGND
EN
ILIM
FSW
COMP
SW
VIN
SW
FB
SW
VOUT
SW
VOUT
SW
VOUT
BOOT
VOUT
MODE
VIN
NC
NC
SS
PGND
Figure 19. PCB Layout Example Bottom Layer
Thermal Considerations
The maximum IC junction temperature should be restricted to 125°C under normal operating conditions. Calculate
the maximum allowable dissipation, PD(max) , and keep the actual power dissipation less than or equal to P D(max) .
The maximum-power-dissipation limit is determined using Equation 18.
𝑃𝐷(𝑀𝐴𝑋) =
125 − 𝑇𝐶𝐴
𝑅θJA
(18)
where
TA is the maximum ambient temperature for the application.
RθJA is the junction-to-ambient thermal resistance given in the Thermal Information table.
SCT12A0 DFN package includes a thermal pad that improves the thermal capabilities of the package. The real
junction-to-ambient thermal resistance RθJA of the package greatly depends on the PCB type, layout, thermal pad
connection and environmental factor. Using thick PCB copper and soldering the thermal pad to a large ground plate
enhance the thermal performance. Using more vias connects the ground plate on the top layer and bottom layer
around the IC without solder mask also improves the thermal capability.
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SCT12A0
PACKAGE INFORMATION
TOP VIEW
BOTTOM VIEW
SYMBOL
SIDE VIEW
NOTE:
1.
2.
3.
4.
5.
6.
18
Drawing proposed to be made a JEDEC package outline
MO-220 variation.
Drawing not to scale.
All linear dimensions are in millimeters.
Thermal pad shall be soldered on the board.
Dimensions of exposed pad on bottom of package do not
include mold flash.
Contact PCB board fabrication for minimum solder mask
web tolerances between the pins.
A
A1
b
c
D
D2
D3
e
e1
e2
Nd
E
E2
E3
E4
L
h
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Unit: Millimeter
MIN
TYP
MAX
0.85
0.90
0.95
0
0.02
0.05
0.18
0.25
0.30
0.18
0.20
0.25
4.40
4.50
4.60
3.10
3.20
3.30
3.85REF
0.50BSC
0.75BSC
0.25BSC
3.50BSC
3.40
3.50
3.60
2.10
2.20
2.30
0.35REF
0.75REF
0.35
0.40
0.45
0.20
0.25
0.30
All Rights Reserved
SCT12A0
TAPE AND REEL INFORMATION
Orderable Device
SCT12A0DHKR
Reel Width
12
Package Type
DFN 3.5mmx4.5mm
A
Ø329±1
Pins
20
SPQ
3000
REEL DIMENSIONS
B
C
12.8±1
Ø100±1
D
Ø13.3±0.3
t
2.0±0.3
TAPE DIMENSIONS
W
(mm)
A0
(mm)
B0
(mm)
K0
(mm)
t
(mm)
P
(mm)
12±0.30
3.80±0.10
4.80±0.10
1.18±0.10
0.30±0.05
8±0.10
E
(mm)
F
(mm)
P2
(mm)
D
(mm)
D1
(mm)
P0
(mm)
10P0
(mm)
1.75±0.10
5.50±0.10
2.00±0.10
1.55±0.10
1.50MIN
4.00±0.10
40.0±0.20
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19
SCT12A0
TYPICAL APPLICATION
12V Output, Synchronous Boost Converter
Efficiency, Vin=3.6V
L1 1.5uH
VIN=3.0~4.2V
C4 0.1uF
R2
SW
FSW
270K
ON
C1
0.1uF
OFF
VOUT=12V
IOUT=3A
BOOT
VOUT
VIN
C6
1uF
EN
C7
4x 22uF
SCT12A0
MODE
VCC
FB
SS
COMP
ILIM
C3
1uF
C5
47nF
R5
17.4K
PGND AGND
R1
100K
Efficiency
C2
2x 22uF
R3
536K C10
1000pF
Optional
R4
59K
C9
47pF
C8
4700pF
100%
90%
80%
70%
60%
50%
40%
30%
20%
10%
0%
PWM
PFM
0.01
0.10
1.00
Output Current (A)
10.00
RELATED PARTS
PART NUMBERS
SCT12A1
DESCRIPTION
COMMENTS
30W Fully-integrated
Synchronous Boost
Converter with Load
Disconnection
Vin=2.7V-14V, 12A switch current
Load disconnection control to an external PMOS with
high-side current sensing to protect
Damage of circuit components and cause
catastrophic failure at load during hard short.
Presence of unwanted output voltage before start
up sequence causing system to latch off or
malfunction.
L1 1.5uH
VIN=2.7~4.2V
C4 0.1uF
C2
2x 22uF
R2
SW
FDMC612PZ
BOOT
FSW
VOUT
VOUT=9V
IOUT=3A
270K
VIN
ON
C1
0.1uF
C6
1uF
R3
383K
EN
OFF
SCT12A1
FB
PGATE
MODE
ENPGATEZ
VCC
SS
COMP
ILIM
C3
1uF
PGND
C5
47nF
C10
2x 22uF
C7
2x 22uF
R5
16.9K
AGND
R1
100K
R4
59K
C9
47pF
C8
4700pF
Figure 20. SCT12A1 Typical Application
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee the third
party Intellectual Property rights are not infringed upon when integrating Silicon Content Technology (SCT) products into any
application. SCT will not assume any legal responsibility for any said applications.
20
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