GX28E01P-100

GX28E01-100 1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine GENERAL DESCRIPTION FEATURES The GX28E01-100 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the ISO/IEC 10118-3 Secure Hash Algorithm (SHA-1). The 1024-bit EEPROM array is configured as four pages of 256 bits with a 64-bit scratchpad to perform write operations. All memory pages can be write protected, and one page can be put in EPROM-emulation mode, where bits can only be changed from a 1 to a 0 state. Each GX28E01100 has its own guaranteed unique 64-bit ROM registration number that is factory lasered into the chip. The GX28E01-100 communicates over the single-contact 1-Wire® bus. The communication follows the standard Dallas Semiconductor 1-Wire protocol with the registration number acting as node address in the case of a multi-device 1-Wire network. APPLICATIONS Printer Cartridge Configuration and Monitoring Medical Sensor Authentication and Calibration System Intellectual Property Protection TYPICAL OPERATING CIRCUIT ● 1024 bits of EEPROM memory partitioned into four pages of 256 bits ● On-chip 512-bit SHA-1 engine to compute 160-bit Message Authentication Codes (MAC) and to generate secrets ● Write access requires knowledge of the secret and the capability of computing and transmitting a 160-bit MAC as authorization ● User-programmable page write-protection for page 0, page 3 or all four pages together ● User-programmable OTP EPROM emulation mode for page 1 ("write to 0") ● Communicates to host with a single digital signal at 15.3k bits or 125k bits per second using 1-Wire protocol ● Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise ● Reads and writes over a wide voltage range of 2.8V to 5.25V from -40°C to +85°C ORDERING INFORMATION PART GX28E01P-100 TEMP RANGE -40°C to 85°C PIN-PACKAGE 6-pin DFN VCC RPUP + Indicates lead-free compliance. Ordering Information and Pin Configuration continued at the end of the data sheet. µC IO GX28E01 GND PIN CONFIGURATION Commands, Registers, and Modes are capitalized for clarity. 1-Wire is a registered trademark of Dallas Semiconductor Corp. 1 of 16 GND 1 6 NC IO 2 5 NC NC 3 4 NC DFN Top view GX28E01-100 ABSOLUTE MAXIMUM RATINGS IO Voltage to GND IO Sink Current Operating Temperature Range Junction Temperature Storage Temperature Range Soldering Temperature -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C See IPC/JEDEC J-STD-020A Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C; see Note 1.) PARAMETER IO PIN GENERAL DATA 1-Wire Pullup Voltage 1-Wire Pullup Resistance Input Capacitance Input Load Current High-to-Low Switching Threshold Input Low Voltage Low-to-High Switching Threshold Switching Hysteresis Output Low Voltage SYMBOL CONDITIONS MIN VPUP RPUP CIO IL (Note 2) (Notes 2, 3) (Notes 4, 5) IO pin at VPUP 2.8 0.3 0.05 VTL (Notes 5, 6, 7) 0.46 VIL (Notes 2, 8) VTH (Notes 5, 6, 9) 1.0 (Notes 5, 6, 10) At 4mA Current Load (Note 11) Standard speed, RPUP = 2.2kΩ Recovery Time Overdrive speed, RPUP = 2.2kΩ tREC (Notes 2, 12) Overdrive speed, directly prior to reset pulse; RPUP = 2.2kΩ Rising-Edge Hold-off Time Standard speed tREH (Notes 5, 13) Overdrive speed Time slot Duration Standard speed tSLOT (Note 2, 14) Overdrive speed IO PIN, 1-WIRE RESET, PRESENCE DETECT CYCLE Standard speed Reset Low Time (Note 2) tRSTL Overdrive speed Presence Detect High Standard speed tPDH Time Overdrive speed Presence Detect Low Standard speed tPDL Time Overdrive speed Presence Detect Sample Standard speed tMSP Time (Notes 2, 15) Overdrive speed IO PIN, 1-Wire WRITE Standard speed Write-0 Low Time tW0L Overdrive speed, VPUP > 4.5V (Notes 2, 16, 17) Overdrive speed Write-1 Low Time Standard speed tW1L (Notes 2, 17) Overdrive speed IO PIN, 1-Wire READ Standard speed Read Low Time tRL (Notes 2, 18) Overdrive speed Standard speed Read Sample Time tMSR (Notes 2, 18) Overdrive speed VHY VOL 2 of 15 0.21 TYP MAX UNITS 5.25 2.2 1000 6.7 VPUP 1.8V 0.5 VPUP 1.1V 1.70 0.4 V kΩ pF µA 5 2 V V V V V µs 5 0.5 5.0 Not applicable (0) 65 8 µs µs 480 48 15 2 60 8 60 6 640 80 60 6 240 24 75 10 60 5 6 1 1 120 15.5 15.5 15 2 5 1 tRL + δ tRL + δ 15 - δ 2-δ 15 2 µs µs µs µs µs µs µs µs GX28E01-100 PARAMETER EEPROM Programming Current Programming Time Write/Erase Cycles (Endurance) (Notes 21, 22) Data Retention (Notes 23, 24, 25) SHA-1 ENGINE SHA Computation Current (Notes 5, 19) SHA Computation Time (Note 5) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: Note 19: Note 20: Note 21: Note 22: Note 23: Note 24: Note 25: SYMBOL IPROG tPROG NCY tDR CONDITIONS MIN TYP MAX UNITS 0.8 10 mA ms (Notes 5, 19) (Note 20) At 25°C At 85°C (worst case) 200k 50k --- At 85°C (worst case) 40 years ILCSHA See full version of data sheet. mA tCSHA See full version of data sheet. ms Specifications at TA = -40°C are guaranteed by design only and not production-tested. System requirement. Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required. Maximum value represents the internal parasite capacitance when VPUP is first applied. If RPUP = 2.2kΩ, 2.5µs after VPUP has been applied the parasite capacitance will not affect normal communications. Guaranteed by design, characterization and/or simulation only. Not production tested. VTL, VTH, and VHY are a function of the internal supply voltage, which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY. Voltage below which, during a falling edge on IO, a logic 0 is detected. The voltage on IO needs to be less than or equal to VIL(MAX) at all times the master is driving IO to a logic-0 level. Voltage above which, during a rising edge on IO, a logic 1 is detected. After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'. The I-V characteristic is linear for voltages less than 1V. Applies to a single device attached to a 1-Wire line. The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge. Defines maximum possible bit rate. Equal to tW0L(min) + tREC(min). Interval after tRSTL during which a bus master is guaranteed to sample a logic-0 on IO if there is a GX28E01-100 present. Minimum limit is tPDH(max); maximum limit is tPDH(min) + tPDL(min). Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below. ε in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1Lmax + tF - ε and tW 0Lmax + tF - ε respectively. δ in Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLmax + tF. Current drawn from IO during EEPROM programming or SHA-1 computation interval. See full version of data sheet. Write-cycle endurance is degraded as TA increases. Not 100% production-tested; guaranteed by reliability monitor sampling. Data retention is degraded as TA increases. Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. EEPROM writes may become non-functional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write-capability after 10 years at 125°C or 40 years at 85°C. 3 of 15 GX28E01-100 LEGACY VALUES STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX 61µs (undef.) 7µs (undef.) 480µs (undef.) 48µs 80µs 15µs 60µs 2µs 6µs 60µs 240µs 8µs 24µs 60µs 120µs 6µs 16µs PARAMETER tSLOT (incl. tREC) tRSTL tPDH tPDL tW0L 1) GX28E01-100 VALUES STANDARD SPEED OVERDRIVE SPEED MIN MAX MIN MAX 1) 1) (undef.) (undef.) 65µs 8µs 480µs 640µs 48µs 80µs 15µs 60µs 2µs 6µs 60µs 240µs 8µs 24µs 60µs 120µs 6µs 15.5µs Intentional change, longer recovery time requirement due to modified 1-Wire front end. PIN DESCRIPTION NAME IO GND NC FUNCTION 1-Wire bus interface. Open drain, requires external pull-up resistor. Ground reference Not connected DESCRIPTION The GX28E01-100 combines 1024 bits of EEPROM organized as four 256-bit pages, a 64-bit secret, a register page, a 512-bit SHA-1 engine, a 64-bit ROM registration number in a single chip. Data is transferred serially through the 1-Wire protocol, which requires only a single data lead and a ground return. The GX28E01-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the memory, the register page, or when installing a new secret. Data is first written to the scratchpad from where it can be read back. After the data has been verified, a copy scratchpad command transfers the data to its final memory location, provided that the GX28E01-100 receives a matching 160-bit MAC. The computation of the MAC involves the secret and additional data stored in the GX28E01-100 including the device’s registration number. Only a new secret can be loaded without providing a MAC. The SHA-1 engine is also activated to compute 160-bit MACs when performing an authenticated read of a memory page and when computing a new secret, instead of loading it. The GX28E01-100 understands a unique command "Refresh Scratchpad." Proper use of a refresh sequence after a copy scratchpad operation reduces the number of weak bit failures if the device is used in a touch environment (see the Writing with Verification section). The refresh sequence also provides a means to restore functionality in a device with bits in a weak state. The device's 64-bit ROM registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment, where multiple devices reside on a common 1-Wire bus and operate independently of each other. Applications of the GX28E01-100 include printer cartridge configuration and monitoring, medical sensor authentication and calibration, and system intellectual property protection. OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the GX28E01-100. The GX28E01-100 has six main data components: 1) 64-bit lasered ROM, 2) 64-bit scratchpad, 3) four 256-bit pages of EEPROM, 4) register page, 5) 64-bit secrets memory, and 6) a 512-bit SHA-1 (Secure Hash Algorithm) engine. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM function commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume Communication, 6) Overdrive-Skip ROM, or 7) Overdrive-Match ROM. Upon completion of an overdrive ROM command byte executed at standard speed, the device enters overdrive mode where all subsequent communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 10. After a ROM function command is successfully executed, the memory and SHA-1 functions become accessible and the master can provide any one of the 9 available function commands. The function protocols are described in * Figure 8 . All data is read and written least significant bit first. * For Figure 8 see the full version of the data sheet. 4 of 15 GX28E01-100 Figure 1. Block Diagram PARASITE POWER 1-Wire net 1-Wire Function Control 64-bit Lasered ROM 512-bit Secure Hash Algorithm Engine Memory and SHA Function Control Unit CRC16 Generator 64-bit Scratchpad Data Memory 4 Pages of 256 bits each Secrets Memory 64 bits Register Page Figure 2. Hierarchical Structure for 1-Wire Protocol GX28E01-100 Command Level: 1-Wire ROM Function Commands (see Figure 10) Device-specific Memory Function Commands (see Figure 8) Available Commands: Data Field Affected: Read ROM Match ROM Search ROM Skip ROM Resume Overdrive Skip Overdrive Match 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag RC-Flag RC-Flag RC-Flag, OD-Flag 64-bit Reg. #, RC-Flag, OD-Flag For details see the full version of the data sheet. 5 of 15 GX28E01-100 64-BIT LASERED ROM Each GX28E01-100 has a unique ROM Registration Number that is 64 bits long, as shown in Figure 3. The first eight bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last eight bits are a CRC (Cyclic Redundancy Check) of the first 56 bits. The 1-Wire CRC is generated using a polynomial generator 8 5 4 consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X + X + X + 1. Additional information about the Dallas 1-Wire CRC is available in Application Note 27. The shift register bits are initialized to zero. Then starting with the LSB of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC should return the shift register to all zeros. Figure 3. 64-Bit LASERED ROM MSB LSB 8-Bit CRC Code MSB 8-Bit Family Code 48-Bit Serial Number LSB MSB LSB MSB * LSB Figure 4. 1-Wire CRC Generator 8 5 4 Polynomial = X + X + X + 1 st nd 1 STAGE X 0 rd 2 STAGE X 1 th 3 STAGE X 2 th 4 STAGE X 3 th 5 STAGE X 4 th 6 STAGE X 5 th 7 STAGE X 6 8 STAGE X 7 X 8 INPUT DATA MEMORY The GX28E01-100 has four memory areas: data memory, secrets memory, register page with special function registers and user-bytes, and a volatile scratchpad. The data memory is organized as four pages of 32 bytes. Secret and scratchpad are 8 bytes each. The scratchpad acts as a buffer when writing to the data memory, loading the initial secret or when writing to the register page. For further details (including Figures 5 and 6) refer to the full version of the data sheet. * For the actual Family Code refer to the full version of the data sheet. 6 of 15 GX28E01-100 ADDRESS REGISTERS AND TRANSFER STATUS The GX28E01-100 employs three address registers: TA1, TA2, and E/S (Figure 7). These registers are common to many other 1-Wire devices but operate slightly differently with the GX28E01-100. Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer-status register, used to verify data integrity with write commands. Since the scratchpad of the GX28E01100 is designed to accept data in blocks of eight bytes only, the lower three bits of TA1 are forced to 0 and the lower three bits of the E/S register (ending offset) always read 1. This indicates that all the data in the scratchpad is used for a subsequent copying into main memory or secret. Bit 5 of the E/S register, called PF or partial byte flag, is a logic-1 if the number of data bits sent by the master is not an integer multiple of eight or if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad clears the PF bit. Bits 3, 4, and 6 have no function; they always read 1. The partial flag supports the master checking the data integrity after a write command. The highest valued bit of the E/S register is called the AA or authorization accepted flag, which indicates that the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag. Figure 7. Address Registers Bit # 7 6 5 4 3 2 1 0 Target Address (TA1) T7 T6 T5 T4 T3 T2 (0) T1 (0) T0 (0) Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8 Ending Address with Data Status (E/S) (Read Only) AA 1 PF 1 1 E2 (1) E1 (1) E0 (1) WRITING WITH VERIFICATION To write data to the GX28E01-100, the scratchpad has to be used as intermediate storage. First the master issues the write scratchpad command, which specifies the desired target address and the data to be written to the scratchpad. Note that writes to data memory must be performed on 8-byte boundaries with the three LSBs of the target address T2–T0 equal to 000b. Therefore, if T2–T0 are sent with non-zero values, the device sets these bits to zero and uses the modified address as the target address. The master should always send eight complete data bytes. After the eight bytes of data have been transmitted, the master can elect to receive an inverted CRC16 of the write scratchpad command, the address as sent by the master, and the data as sent by the master. The master can compare the CRC to the value it has calculated itself in order to determine if the communication was successful. After the scratchpad has been written, the master should always perform a read scratchpad to verify that the intended data was in fact written. During a read scratchpad, the GX28E01-100 repeats the target address TA1 and TA2 and sends the contents of the E/S register. The partial flag (bit 5 of the E/S register) is set to 1 if the last data byte the GX28E01-100 received during a write scratchpad or refresh scratchpad command was incomplete, or if there was a loss of power since data was last written to the scratchpad. The authorization-accepted (AA) flag (bit 7 of the E/S register) is normally cleared by a write scratchpad or refresh scratchpad; therefore, if it is set to 1, it indicates that the GX28E01-100 did not understand the proceeding write (or refresh) scratchpad command. In either of these cases, the master should rewrite the scratchpad. After the master receives the E/S register, the scratchpad data is received. The descriptions of write scratchpad and refresh scratchpad provide clarification of what changes can occur to the scratchpad data under certain conditions. An inverted CRC of the read scratchpad command, target address, E/S register, and scratchpad data follows the scratchpad data. As with the write scratchpad command, this CRC can be compared to the value the master has calculated itself in order to determine if the communication was successful. After the master has verified the data, it can send the copy scratchpad to copy the scratchpad to memory. Alternatively, the load first secret or compute next secret command can be issued to change the secret. See the descriptions of these commands for more information. 7 of 15 GX28E01-100 MEMORY AND SHA FUNCTION COMMANDS This section describes the commands and flow charts to use the memory and SHA-1 engine of the device. It includes Tables 1 to 4 and Figure 8. Please refer to the full version of the data sheet. SHA-1 COMPUTATION ALGORITHM This description of the SHA computation is adapted from the Secure Hash Standard SHA-1 document that can be downloaded from the NIST website (www.itl.nist.gov/fipspubs/fip180-1.htm). Further details are found in the full version of the data sheet. 1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances the GX28E01100 is a slave device. The bus master is typically a microcontroller. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots, which are initiated on the falling edge of sync pulses from the bus master. HARDWARE CONFIGURATION The 1-Wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must have open-drain or tri-state outputs. The 1-Wire port of the GX28E01-100 is open drain with an internal circuit equivalent to that shown in Figure 9. A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The GX28E01-100 supports both a Standard and Overdrive communication speed of 15.3kbps (max) and 125kbps (max), respectively. Note that legacy 1Wire products support a standard communication speed of 16.3kbps and Overdrive of 142kbps. The slightly reduced rates for the GX28E01-100 are a result of additional recovery times, which in turn were driven by a 1-Wire physical interface enhancement to improve noise immunity. The value of the pullup resistor primarily depends on the network size and load conditions. The GX28E01-100 requires a pullup resistor of 2.2kΩ (max) at any speed. The idle state for the 1-Wire bus is high. If for any reason a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume. If this does not occur and the bus is left low for more than 16µs (Overdrive speed) or more than 120µs (standard speed), one or more devices on the bus may be reset. Figure 9. Hardware Configuration BUS MASTER VPUP GX28E01 1-Wire PORT RPUP RX DATA RX TX IL TX RX = RECEIVE Open Drain Port Pin TX = TRANSMIT 8 of 15 100 Ω MOSFET GX28E01-100 TRANSACTION SEQUENCE The protocol for accessing the GX28E01-100 through the 1-Wire port is as follows:     Initialization ROM Function Command Memory/SHA Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the GX28E01-100 is on the bus and is ready to operate. For more details, see the 1-Wire Signaling section. 1-Wire ROM FUNCTION COMMANDS Once the bus master has detected a presence, it can issue one of the seven ROM function commands that the GX28E01-100 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to the flow chart in Figure 10). READ ROM [33h] This command allows the bus master to read the GX28E01-100’s 8-bit family code, unique 48-bit serial number, and 8-bit CRC. This command can only be used if there is a single slave on the bus. If more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC. MATCH ROM [55h] The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific GX28E01-100 on a multidrop bus. Only the GX28E01-100 that exactly matches the 64-bit ROM sequence, including the external address, responds to the following Memory/Control Function command. All other slaves wait for a reset pulse. This command can be used with a single or multiple devices on the bus. SEARCH ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1-Wire bus or their device ID numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the device ID numbers of all slave devices. For each bit of the device ID number, starting with the least significant bit, the bus master issues a triplet of time slots. On the first slot, each slave device participating in the search outputs the true value of its device ID number bit. On the second slot, each slave device participating in the search outputs the complemented value of its device ID number bit. On the third slot, the master writes the true value of the bit to be selected. All slave devices that do not match the bit written by the master stop participating in the search. If both of the read bits are zero, the master knows that slave devices exist with both states of the bit. By choosing which state to write, the bus master branches in the ROM code tree. After one complete pass, the bus master knows the device ID number of a single device. Additional passes identify the device ID numbers of the remaining devices. Refer to Application Note 187: 1-Wire Search Algorithm for a detailed discussion, including an example. SKIP ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and, for example, a read command is issued following the Skip ROM command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). 9 of 15 GX28E01-100 Figure 10-1. ROM Functions Flow Chart Bus Master TX Reset Pulse From Figure 10, 2nd Part From Memory Functions Flow Chart (Figure 8) N OD Reset Pulse ? OD = 0 Y Bus Master TX ROM Function Command 33h Read ROM Command ? Y GX28E01 TX Presence Pulse N 55h Match ROM Command ? F0h Search ROM Command ? N Y Y RC = 0 RC = 0 GX28E01 TX Family Code (1 Byte) Master TX Bit 0 To Figure 10 nd CCh 2 Part Skip ROM Command ? N Y RC = 0 RC = 0 GX28E01 TX Bit 0 GX28E01 TX Bit 0 Master TX Bit 0 N Bit 0 Match ? N Bit 0 Match ? Y GX28E01 TX Serial Number (6 Bytes) N Y GX28E01 TX Bit 1 Master TX Bit 1 GX28E01 TX Bit 1 Master TX Bit 1 N Bit 1 Match ? N Bit 1 Match ? Y Y GX28E01 TX Bit 63 GX28E01 TX CRC Byte Master TX Bit 63 GX28E01 TX Bit 63 Master TX Bit 63 N Bit 63 Match ? N Bit 63 Match ? Y Y RC = 1 RC = 1 To Memory Functions Flow Chart (Figure 8) 10 of 15 To Figure 10 2nd Part From Figure 10 nd 2 Part GX28E01-100 Figure 10-2. ROM Functions Flow Chart (continued) To Figure 10, 1st Part From Figure 10 st 1 Part A5h Resume Command ? 3Ch Overdrive Skip ROM ? N Y N Y 69h Overdrive Match ROM ? N Y RC = 0 ; OD = 1 RC = 0 ; OD = 1 N RC = 1 ? Master TX Bit 0 Y Master TX Reset ? N Y Bit 0 Match ? N Y Master TX Bit 1 Master TX Reset ? Y Bit 1 Match ? N Y N Master TX Bit 63 Bit 63 Match ? Y RC = 1 From Figure 10 1st Part To Figure 10 st 1 Part 11 of 15 N GX28E01-100 RESUME [A5h] To maximize the data throughput in a multidrop environment, the Resume function is available. This function checks the status of the RC bit and, if it is set, directly transfers control to the Memory functions, similar to a Skip ROM command. The only way to set the RC bit is through successfully executing the Match ROM, Search ROM, or Overdrive Match ROM command. Once the RC bit is set, the device can repeatedly be accessed through the Resume Command function. Accessing another device on the bus clears the RC bit, preventing two or more devices from simultaneously responding to the Resume Command function. OVERDRIVE SKIP ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the GX28E01-100 in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0). When issued on a multidrop bus, this command sets all Overdrive-supporting devices into Overdrive mode. To subsequently address a specific Overdrive-supporting device, a reset pulse at Overdrive speed has to be issued followed by a Match ROM or Search ROM command sequence. This speeds up the time for the search process. If more than one slave supporting Overdrive is present on the bus and the Overdrive Skip ROM command is followed by a Read command, data collision occurs on the bus as multiple slaves transmit simultaneously (open-drain pulldowns produce a wired-AND result). OVERDRIVE MATCH ROM [69h] The Overdrive Match ROM command followed by a 64-bit ROM sequence transmitted at Overdrive Speed allows the bus master to address a specific GX28E01-100 on a multidrop bus and to simultaneously set it in Overdrive mode. Only the GX28E01-100 that exactly matches the 64-bit ROM sequence responds to the subsequent Memory or SHA Function command. Slaves already in Overdrive mode from a previous Overdrive Skip or successful Overdrive Match command remain in Overdrive mode. All overdrive-capable slaves return to standard speed at the next Reset Pulse of minimum 480µs duration. The Overdrive Match ROM command can be used with a single or multiple devices on the bus. 1-Wire SIGNALING The GX28E01-100 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except for the Presence pulse, the bus master initiates all falling edges. The GX28E01-100 can communicate at two different speeds, standard speed, and Overdrive Speed. If not explicitly set into the Overdrive mode, the GX28E01-100 communicates at standard speed. While in Overdrive Mode the fast timing applies to all waveforms. To get from idle to active, the voltage on the 1-Wire line needs to fall from VPUP below the threshold VTL. To get from active to idle, the voltage needs to rise from VILMAX past the threshold VTH. The time it takes for the voltage to make this rise is seen in Figure 11 as 'ε' and its duration depends on the pullup resistor (RPUP) used and the capacitance of the 1-Wire network attached. The voltage VILMAX is relevant for the GX28E01-100 when determining a logical level, not triggering any events. Figure 11 shows the initialization sequence required to begin any communication with the GX28E01-100. A Reset Pulse followed by a Presence Pulse indicates the GX28E01-100 is ready to receive data, given the correct ROM and Memory/Control Function command. If the bus master uses slew-rate control on the falling edge, it must pull down the line for tRSTL + tF to compensate for the edge. A tRSTL duration of 480µs or longer exits the Overdrive Mode, returning the device to standard speed. If the GX28E01-100 is in Overdrive Mode and tRSTL is no longer than 80µs, the device remains in Overdrive Mode. If the device is in Overdrive Mode and tRSTL is between 80µs and 480µs, the device will reset, but the communication speed is undetermined. 12 of 15 GX28E01-100 Figure 11. Initialization Procedure: Reset and Presence Pulse MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE” tMSP ε VPUP VIHMASTER VTH VTL VILMAX 0V tF tRSTL RESISTOR tPDH MASTER tPDL tRSTH tREC GX28E01 After the bus master has released the line it goes into receive mode. Now the 1-Wire bus is pulled to VPUP through the pullup resistor, or in case of a DS2482-x00 or DS2480B driver, by active circuitry. When the threshold VTH is crossed, the GX28E01-100 waits for tPDH and then transmits a Presence Pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP. The tRSTH window must be at least the sum of tPDHMAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is expired, the GX28E01-100 is ready for data communication. In a mixed population network, tRSTH should be extended to minimum 480µs at standard speed and 48µs at Overdrive speed to accommodate other 1-Wire devices. Read/Write Time Slots Data communication with the GX28E01-100 takes place in time slots, which carry a single bit each. Write-time slots transport data from bus master to slave. Read-time slots transfer data from slave to master. Figure 12 illustrates the definitions of the write- and read-time slots. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the GX28E01-100 starts its internal timing generator that determines when the data line is sampled during a write-time slot and how long data is valid during a read-time slot. Figure 12. Read/Write Timing Diagram Write-One Time Slot tW1L VPUP VIHMASTER VTH VTL VILMAX 0V ε tF RESISTOR tSLOT MASTER 13 of 15 GX28E01-100 Figure 12. Read/Write Timing Diagram (continued) Write-Zero Time Slot tW 0L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR ε tREC MASTER Read-Data Time Slot tMSR tRL VPUP VIHMASTER VTH Master Sampling Window VTL VILMAX 0V δ tF tREC tSLOT RESISTOR MASTER GX28E01 Master-to-Slave For a write-one time slot, the voltage on the data line must have crossed the VTH threshold before the write-one low time tW1LMAX is expired. For a write-zero time slot, the voltage on the data line must stay below the VTH threshold until the write-zero low time tW0LMIN is expired. For the most reliable communication, the voltage on the data line should not exceed VILMAX during the entire tW0L or tW1L window. After the VTH threshold has been crossed, the GX28E01-100 needs a recovery time tREC before it is ready for the next time slot. Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired. During the tRL window, when responding with a 0, the GX28E01-100 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. When responding with a 1, the GX28E01-100 does not hold the data line low at all, and the voltage starts rising as soon as tRL is over. The sum of tRL + δ (rise time) on one side and the internal timing generator of the GX28E01-100 on the other side define the master sampling window (tMSRMIN to tMSRMAX) in which the master must perform a read from the data line. For the most reliable communication, tRL should be as short as permissible, and the master should read close to but no later than tMSRMAX. After reading from the data line, the master must wait until tSLOT is expired. This guarantees sufficient recovery time tREC for the GX28E01-100 to get ready for the next time slot. Note that tREC specified herein applies only to a single GX28E01-100 attached to a 1-Wire line. For multidevice configurations, tREC needs to be extended to accommodate the additional 1-Wire device input capacitance. Alternatively, an interface that performs active pullup during the 1-Wire recovery time such as the DS2482-x00 or DS2480B 1-Wire line drivers can be used. 14 of 15 GX28E01-100 IMPROVED NETWORK BEHAVIOR (SWITCHPOINT HYSTERESIS) In a 1-Wire environment, line termination is possible only during transients controlled by the bus master (1-Wire driver). 1-Wire networks, therefore, are susceptible to noise of various origins. Depending on the physical size and topology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the 1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search ROM command coming to a dead end or cause a device-specific function command to abort. For better performance in network applications, the GX28E01-100 uses a new 1-Wire front end, which makes it less sensitive to noise. The 1-Wire front end of the GX28E01-100 differs from traditional slave devices in three characteristics. 1) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot. This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed. 2) There is a hysteresis at the low-to-high switching threshold VTH. If a negative glitch crosses VTH but does not go below VTH - VHY, it will not be recognized (Figure 13, Case A). The hysteresis is effective at any 1-Wire speed. 3) There is a time window specified by the rising edge hold-off time tREH during which glitches are ignored, even if they extend below VTH - VHY threshold (Figure 13, Case B, tGL < tREH). Deep voltage droops or glitches that appear late after crossing the VTH threshold and extend beyond the tREH window cannot be filtered out and are taken as the beginning of a new time slot (Figure 13, Case C, tGL ≥ tREH). Devices that have the parameters VHY, and tREH specified in their electrical characteristics use the improved 1-Wire front end. Figure 13. Noise Suppression Scheme tREH VPUP tREH VTH VHY Case A Case B Case C 0V tGL tGL CRC GENERATION With the GX28E01-100 there are two different types of CRCs. One CRC is an 8-bit type. It is computed at the factory and is stored in the most significant byte of the 64-bit ROM. The equivalent polynomial function of this CRC 8 5 4 is X + X + X + 1. To determine whether the ROM data has been read without error the bus master can compute the CRC value from the first 56 bits of the 64-bit ROM and compare it to the value read from the GX28E01-100. This 8-bit CRC is received in the true form (noninverted) when reading the ROM. The other CRC is a 16-bit type, which is used for error detection with Memory and SHA-1 function commands. For PACKAGING DFN6 15 of 15 GX28E01-100 16 of 15