ALC5672-VB
Multi-Channel Audio Hub/CODEC with Gen.3 Voice DSP
and SounzRealTM Post-Processing for Mobile Devices
DATASHEET
Rev. 0.91
21 January 2014
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC5672-VB
Datasheet
COPYRIGHT
©2014 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC5672 Audio Codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide.
ii
Rev. 0.91
ALC5672-VB
Datasheet
REVISION HISTORY
Revision
0.9
0.91
Release Date
2014/1/13
2014/1/21
Summary
First release for ALC5672-VB
Modify TDM function
iii
Rev. 0.91
ALC5672-VB
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION .............................................................................................................................................. 1
2.
FEATURES ......................................................................................................................................................................... 2
3.
POWER/GROUND OPERATION CONDITIONS ......................................................................................................... 4
4.
SYSTEM APPLICATION ................................................................................................................................................. 4
5.
FUNCTION BLOCK AND MIXER PATH ..................................................................................................................... 5
5.1.
5.2.
5.3.
FUNCTION BLOCK ........................................................................................................................................................ 5
AUDIO MIXER PATH..................................................................................................................................................... 6
DIGITAL MIXER PATH .................................................................................................................................................. 7
6.
PIN ASSIGNMENTS ......................................................................................................................................................... 8
7.
PIN DESCRIPTIONS......................................................................................................................................................... 9
7.1.
7.2.
7.3.
7.4.
8.
FUNCTION DESCRIPTION .......................................................................................................................................... 12
8.1.
9.
DIGITAL I/O PINS ......................................................................................................................................................... 9
ANALOG I/O PINS ...................................................................................................................................................... 10
FILTER/REFERENCE.................................................................................................................................................... 11
POWER/GROUND ........................................................................................................................................................ 11
SYSTEM CONNECTION ................................................................................................................................................ 12
POWER ............................................................................................................................................................................. 13
9.1.
POWER SUPPLY ON/OFF SEQUENCE ........................................................................................................................... 14
9.2.
RESET ........................................................................................................................................................................ 16
9.2.1. Power-On Reset (POR) ........................................................................................................................................ 16
9.2.2. Software Reset ...................................................................................................................................................... 16
9.3.
CLOCKING .................................................................................................................................................................. 17
9.3.1. Phase-Locked Loop .............................................................................................................................................. 18
9.3.2. I2C and Two I2S/PCM Interface ........................................................................................................................... 19
9.4.
DIGITAL DATA INTERFACE ........................................................................................................................................ 22
9.4.1. Two I2S/PCM Interface ......................................................................................................................................... 22
9.5.
AUDIO DATA PATH .................................................................................................................................................... 27
9.5.1. 2 Analog ADCs with 6-Channel Record Path ...................................................................................................... 27
9.5.2. 4 DACs with 4-Channel Playback Path................................................................................................................ 28
9.5.3. Mixers ................................................................................................................................................................... 29
9.6.
ANALOG AUDIO INPUT PORT ..................................................................................................................................... 30
9.7.
ANALOG AUDIO OUTPUT PORT .................................................................................................................................. 31
9.8.
MULTI-FUNCTION PINS .............................................................................................................................................. 32
9.9.
DRC AND AGC FUNCTION ........................................................................................................................................ 35
9.10.
SOUNZREALTM POST-PROCESSING ............................................................................................................................. 41
9.11.
EQUALIZER BLOCK .................................................................................................................................................... 41
9.12.
WIND NOISE REDUCTION FILTER ............................................................................................................................... 41
9.13.
I2C CONTROL INTERFACE .......................................................................................................................................... 44
9.13.1.
Address Setting ................................................................................................................................................ 44
9.13.2.
Complete Data Transfer .................................................................................................................................. 44
9.14.
GPIO, INTERRUPT AND JACK DETECTION .................................................................................................................. 46
9.15.
PUSH BUTTON DETECTION ......................................................................................................................................... 49
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Rev. 0.91
ALC5672-VB
Datasheet
9.16.
9.17.
9.18.
10.
POWER MANAGEMENT............................................................................................................................................... 51
GEN.3 VOICE DSP FUNCTION .................................................................................................................................... 52
MULTI-JACK JACK DETECTION PIN (JD1) .................................................................................................................. 54
REGISTERS LIST....................................................................................................................................................... 55
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
10.8.
10.9.
10.10.
10.11.
10.12.
10.13.
10.14.
10.15.
10.16.
10.17.
10.18.
10.19.
10.20.
10.21.
10.22.
10.23.
10.24.
10.25.
10.26.
10.27.
10.28.
10.29.
10.30.
10.31.
10.32.
10.33.
10.34.
10.35.
10.36.
10.37.
10.38.
10.39.
10.40.
10.41.
10.42.
10.43.
10.44.
10.45.
10.46.
10.47.
10.48.
10.49.
10.50.
REGISTER MAP .......................................................................................................................................................... 55
MX-00H: S/W RESET & DEVICE ID ........................................................................................................................... 59
MX-02H: HEADPHONE OUTPUT CONTROL................................................................................................................. 59
MX-03H: LINE OUTPUT CONTROL ........................................................................................................................... 60
MX-0AH: IN1 PORT CONTROL - 1 ............................................................................................................................. 62
MX-0BH: IN1 PORT CONTROL - 2 ............................................................................................................................. 62
MX-0CH: IN1 PORT CONTROL - 3 ............................................................................................................................. 63
MX-0EH: IN2 INPUT CONTROL ................................................................................................................................. 63
MX-0FH: INL & INR VOLUME CONTROL ................................................................................................................. 64
MX-19H: DACL1/R1 DIGITAL VOLUME .............................................................................................................. 65
MX-1AH: DACL2/R2 DIGITAL VOLUME ............................................................................................................. 65
MX-1BH: DACL2/R2 MUTE/UN-MUTE CONTROL............................................................................................... 67
MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ........................................................................................ 68
MX-1DH: MONO ADC DIGITAL VOLUME CONTROL ............................................................................................ 69
MX-1EH: ADC DIGITAL BOOST GAIN CONTROL.................................................................................................. 70
MX-1FH: STEREO2 ADC DIGITAL VOLUME CONTROL......................................................................................... 71
MX-20H: MONO ADC DIGITAL BOOST GAIN CONTROL ....................................................................................... 72
MX-26H: STEREO2 ADC DIGITAL MIXER CONTROL ............................................................................................ 72
MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ............................................................................................ 73
MX-28H: MONO ADC DIGITAL MIXER CONTROL ................................................................................................ 74
MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL ................................................................................ 75
MX-2AH: STEREO DAC DIGITAL MIXER CONTROL ............................................................................................. 75
MX-2BH: MONO DAC DIGITAL MIXER CONTROL ............................................................................................... 76
MX-2CH: DAC DIGITAL MIXER CONTROL........................................................................................................... 77
MX-2DH: VOICE DSP PATH CONTROL 1 .............................................................................................................. 78
MX-2EH: VOICE DSP VOLUME CONTROL ............................................................................................................ 79
MX-2FH: INTERFACE DAC/ADC DATA CONTROL ............................................................................................... 80
MX-31H: SPEAKER CONTROL 1 ............................................................................................................................ 80
MX-3BH: RECMIXL CONTROL 1 ........................................................................................................................ 81
MX-3CH: RECMIXL CONTROL 2 ........................................................................................................................ 81
MX-3DH: RECMIXR CONTROL 1 ........................................................................................................................ 82
MX-3EH: RECMIXR CONTROL 2 ........................................................................................................................ 82
MX-45H: HPOMIX CONTROL .............................................................................................................................. 83
MX-4FH: OUTMIXL CONTROL ........................................................................................................................... 83
MX-52H: OUTMIXR CONTROL ........................................................................................................................... 84
MX-53H: LOUTMIX CONTROL ........................................................................................................................... 84
MX-61H: POWER MANAGEMENT CONTROL 1 ....................................................................................................... 85
MX-62H: POWER MANAGEMENT CONTROL 2 ....................................................................................................... 86
MX-63H: POWER MANAGEMENT CONTROL 3 ....................................................................................................... 86
MX-64H: POWER MANAGEMENT CONTROL 4 ....................................................................................................... 87
MX-65H: POWER MANAGEMENT CONTROL 5 ....................................................................................................... 88
MX-66H: POWER MANAGEMENT CONTROL 6 ....................................................................................................... 89
MX-6AH: PRIVATE REGISTER INDEX .................................................................................................................... 89
MX-6CH: PRIVATE REGISTER DATA ..................................................................................................................... 89
MX-70H: I2S1 DIGITAL INTERFACE CONTROL ..................................................................................................... 90
MX-71H: I2S2 DIGITAL INTERFACE CONTROL ..................................................................................................... 90
MX-73H: ADC/DAC CLOCK CONTROL................................................................................................................ 91
MX-74H: ADC/DAC HPF CONTROL .................................................................................................................... 92
MX-75H: DIGITAL MICROPHONE CONTROL 1 ....................................................................................................... 93
MX-76H: DIGITAL MICROPHONE CONTROL 2 ....................................................................................................... 94
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Rev. 0.91
ALC5672-VB
Datasheet
10.51.
10.52.
10.53.
10.54.
10.55.
10.56.
10.57.
10.58.
10.59.
10.60.
10.61.
10.62.
10.63.
10.64.
10.65.
10.66.
10.67.
10.68.
10.69.
10.70.
10.71.
10.72.
10.73.
10.74.
10.75.
10.76.
10.77.
10.78.
10.79.
10.80.
10.81.
10.82.
10.83.
10.84.
10.85.
10.86.
10.87.
10.88.
10.89.
10.90.
10.91.
10.92.
10.93.
10.94.
10.95.
10.96.
10.97.
10.98.
10.99.
10.100.
10.101.
10.102.
10.103.
10.104.
10.105.
MX-77H: TDM INTERFACE CONTROL 1 ............................................................................................................... 95
MX-78H: TDM INTERFACE CONTROL 2 ............................................................................................................... 96
MX-79H: TDM INTERFACE CONTROL 3 ............................................................................................................... 97
MX-7FH: CLOCK CONTROL 1 ............................................................................................................................... 98
MX-80H: GLOBAL CLOCK CONTROL .................................................................................................................... 98
MX-81H: PLL CONTROL 1 .................................................................................................................................... 99
MX-82H: PLL CONTROL 2 .................................................................................................................................... 99
MX-83H: ASRC CONTROL 1 .............................................................................................................................. 100
MX-84H: ASRC CONTROL 2 .............................................................................................................................. 101
MX-85H: ASRC CONTROL 3 .............................................................................................................................. 102
MX-8AH: ASRC CONTROL 4 .............................................................................................................................. 103
MX-8CH: ASRC CONTROL 5 .............................................................................................................................. 103
MX-8EH: HP AMP CONTROL 1 ........................................................................................................................... 104
MX-8FH: HP AMP CONTROL 2 ........................................................................................................................... 104
MX-93H: MICBIAS CONTROL ........................................................................................................................... 105
MX-94H: JD1 CONTROL ..................................................................................................................................... 105
MX-AEH: ADC PATH EQ CONTROL 1................................................................................................................ 106
MX-AFH: ADC PATH EQ CONTROL 2 ................................................................................................................ 107
MX-B0H: DAC PATH EQ CONTROL 1 ................................................................................................................ 108
MX-B1H: EQ CONTROL 2 ................................................................................................................................... 109
MX-B2H: DRC CONTROL 1 ................................................................................................................................ 110
MX-B3H: DRC CONTROL 2 ................................................................................................................................ 110
MX-B4H: DRC CONTROL 3 ................................................................................................................................ 111
MX-B5H: DRC CONTROL 4 ................................................................................................................................ 112
MX-B6H: DRC CONTROL 5 ................................................................................................................................ 113
MX-B7H: DRC CONTROL 6 ................................................................................................................................ 114
MX-BBH: JACK DETECTION CONTROL 1 ............................................................................................................ 114
MX-BDH: IRQ CONTROL 1 ................................................................................................................................ 115
MX-BEH: IRQ CONTROL 2 ................................................................................................................................. 116
MX-BFH: IRQ CONTROL 3 ................................................................................................................................. 117
MX-C0H: GPIO CONTROL 1 ............................................................................................................................... 117
MX-C1H: GPIO CONTROL 2 ............................................................................................................................... 118
MX-C2H: GPIO CONTROL 3 ............................................................................................................................... 119
MX-CFH: SOUNZREALTM BASSBACK CONTROL ................................................................................................ 120
MX-D0H: SOUNZREALTM TRUTREBLE CONTROL 1 ............................................................................................ 120
MX-D1H: SOUNZREALTM TRUTREBLE CONTROL 2 ............................................................................................ 121
MX-D3H: STEREO1 ADC WIND FILTER CONTROL 1 .......................................................................................... 121
MX-D4H: STEREO1 ADC WIND FILTER CONTROL 2 .......................................................................................... 122
MX-D9H: SOFT VOLUME & ZCD CONTROL 1 .................................................................................................... 123
MX-DAH: SOFT VOLUME & ZCD CONTROL 2 ................................................................................................... 124
MX-DBH: INLINE COMMAND CONTROL 1 .......................................................................................................... 124
MX-DCH: INLINE COMMAND CONTROL 2 .......................................................................................................... 125
MX-DDH: INLINE COMMAND CONTROL 3 .......................................................................................................... 126
MX-E0H: VOICE DSP CONTROL 1 ...................................................................................................................... 126
MX-E1H: VOICE DSP CONTROL 2 ...................................................................................................................... 127
MX-E2H: VOICE DSP CONTROL 3 ...................................................................................................................... 127
MX-E3H: VOICE DSP CONTROL 4 ...................................................................................................................... 127
MX-E4H: VOICE DSP CONTROL 5 ...................................................................................................................... 128
MX-E5H: VOICE DSP CONTROL 6 ...................................................................................................................... 128
MX-ECH: MONO ADC WIND FILTER CONTROL 1 .............................................................................................. 128
MX-EDH: MONO ADC WIND FILTER CONTROL 2 .............................................................................................. 129
MX-EEH: STEREO2 ADC WIND FILTER CONTROL 1 .......................................................................................... 129
MX-EFH: STEREO2 ADC WIND FILTER CONTROL 2 .......................................................................................... 131
MX-F8H: JACK DETECTION CONTROL ................................................................................................................ 131
MX-F9H: JACK DETECTION CONTROL ................................................................................................................ 132
vi
Rev. 0.91
ALC5672-VB
Datasheet
10.106.
10.107.
10.108.
10.109.
10.110.
10.111.
10.112.
10.113.
10.114.
10.115.
10.116.
10.117.
10.118.
10.119.
10.120.
10.121.
10.122.
10.123.
10.124.
10.125.
10.126.
10.127.
10.128.
10.129.
10.130.
10.131.
10.132.
10.133.
10.134.
10.135.
10.136.
10.137.
10.138.
10.139.
10.140.
10.141.
10.142.
10.143.
10.144.
10.145.
10.146.
10.147.
10.148.
10.149.
10.150.
10.151.
10.152.
10.153.
10.154.
10.155.
10.156.
10.157.
10.158.
10.159.
10.160.
MX-FAH: GENERAL CONTROL 1 ........................................................................................................................ 132
MX-FBH: GENERAL CONTROL 2......................................................................................................................... 133
MX-FCH: GENERAL CONTROL 3......................................................................................................................... 134
PR-3DH: ADC/DAC RESET CONTROL ............................................................................................................. 134
PR-A4H: DAC_L EQ (LPF:A1) .......................................................................................................................... 135
PR-A5H: DAC_L EQ (LPF:H0).......................................................................................................................... 135
PR-A6H: DAC_R EQ (LPF:A1) .......................................................................................................................... 135
PR-A7H: DAC_R EQ (LPF:H0) ......................................................................................................................... 135
PR-AEH: DAC_L EQ (BPF2:A1) ....................................................................................................................... 136
PR-AFH: DAC_L EQ (BPF2:A2) ........................................................................................................................ 136
PR-B0H: DAC_L EQ (BPF2:H0) ....................................................................................................................... 136
PR-B1H: DAC_R EQ (BPF2:A1) ........................................................................................................................ 136
PR-B2H: DAC_R EQ (BPF2:A2) ........................................................................................................................ 137
PR-B3H: DAC_R EQ (BPF2:H0) ....................................................................................................................... 137
PR-B4H: DAC_L EQ (BPF3:A1) ........................................................................................................................ 137
PR-B5H: DAC_L EQ (BPF3:A2) ........................................................................................................................ 137
PR-B6H: DAC_L EQ (BPF3:H0) ....................................................................................................................... 138
PR-B7H: DAC_R EQ (BPF3:A1) ........................................................................................................................ 138
PR-B8H: DAC_R EQ (BPF3:A2) ........................................................................................................................ 138
PR-B9H: DAC_R EQ (BPF3:H0) ....................................................................................................................... 138
PR-BAH: DAC_L EQ (BPF4:A1) ....................................................................................................................... 139
PR-BBH: DAC_L EQ (BPF4:A2) ....................................................................................................................... 139
PR-BCH: DAC_L EQ (BPF4:H0) ....................................................................................................................... 139
PR-BDH: DAC_R EQ (BPF4:A1) ....................................................................................................................... 139
PR-BEH: DAC_R EQ (BPF4:A2) ....................................................................................................................... 140
PR-BFH: DAC_R EQ (BPF4:H0) ....................................................................................................................... 140
PR-C0H: DAC_L EQ (HPF1:A1) ........................................................................................................................ 140
PR-C1H: DAC_L EQ (HPF1:H0) ....................................................................................................................... 140
PR-C2H: DAC_R EQ (HPF1:A1) ........................................................................................................................ 141
PR-C3H: DAC_R EQ (HPF1:H0) ....................................................................................................................... 141
PR-C4H: DAC_L EQ (HPF2:A1) ........................................................................................................................ 141
PR-C5H: DAC_L EQ (HPF2:A2) ........................................................................................................................ 141
PR-C6H: DAC_L EQ (HPF2:H0) ....................................................................................................................... 142
PR-C7H: DAC_R EQ (HPF2:A1) ........................................................................................................................ 142
PR-C8H: DAC_R EQ (HPF2:A2) ........................................................................................................................ 142
PR-C9H: DAC_R EQ (HPF2:H0) ....................................................................................................................... 142
PR-CAH: DAC_L EQ PRE-VOLUME CONTROL .................................................................................................. 143
PR-CBH: DAC_R EQ PRE-VOLUME CONTROL .................................................................................................. 143
PR-CCH: DAC_L EQ POST-VOLUME CONTROL ................................................................................................ 143
PR-CDH: DAC_R EQ POST-VOLUME CONTROL ................................................................................................ 144
PR-CEH: ADC EQ (LPF:A1) .............................................................................................................................. 144
PR-CFH: ADC EQ (LPF:H0) .............................................................................................................................. 144
PR-D0H: ADC EQ (BPF1:A1) ............................................................................................................................ 144
PR-D1H: ADC EQ (BPF1:A2) ............................................................................................................................ 145
PR-D2H: ADC EQ (BPF1:H0) ............................................................................................................................ 145
PR-D3H: ADC EQ (BPF2:A1) ............................................................................................................................ 145
PR-D4H: ADC EQ (BPF2:A2) ............................................................................................................................ 145
PR-D5H: ADC EQ (BPF2:H0) ............................................................................................................................ 146
PR-D6H: ADC EQ (BPF3:A1) ............................................................................................................................ 146
PR-D7H: ADC EQ (BPF3:A2) ............................................................................................................................ 146
PR-D8H: ADC EQ (BPF3:H0) ............................................................................................................................ 146
PR-D9H: ADC EQ (BPF4:A1) ............................................................................................................................ 147
PR-DAH: ADC EQ (BPF4:A2) ........................................................................................................................... 147
PR-DBH: ADC EQ (BPF4:H0) ........................................................................................................................... 147
PR-DCH: ADC EQ (HPF1:A1) ........................................................................................................................... 147
vii
Rev. 0.91
ALC5672-VB
Datasheet
10.161.
10.162.
10.163.
10.164.
10.165.
10.166.
10.167.
10.168.
10.169.
10.170.
10.171.
10.172.
10.173.
10.174.
10.175.
10.176.
10.177.
10.178.
10.179.
10.180.
10.181.
10.182.
10.183.
10.184.
11.
PR-DDH: ADC EQ (HPF1:H0)........................................................................................................................... 148
PR-E1H: ADC EQ PRE-VOLUME CONTROL ........................................................................................................ 148
PR-E2H: ADC EQ POST-VOLUME CONTROL ...................................................................................................... 148
PR-E5H: DAC_L BIQUAD EQ (BPF1:H0-1) ....................................................................................................... 148
PR-E6H: DAC_L BIQUAD EQ (BPF1:H0-2) ....................................................................................................... 149
PR-E7H: DAC_L BIQUAD EQ (BPF1:B1-1)........................................................................................................ 149
PR-E8H: DAC_L BIQUAD EQ (BPF1:B1-2)........................................................................................................ 149
PR-E9H: DAC_L BIQUAD EQ (BPF1:B2-1)........................................................................................................ 149
PR-EAH: DAC_L BIQUAD EQ (BPF1:B2-2)....................................................................................................... 150
PR-EBH: DAC_L BIQUAD EQ (BPF1:A1-1) ....................................................................................................... 150
PR-ECH: DAC_L BIQUAD EQ (BPF1:A1-2) ....................................................................................................... 150
PR-EDH: DAC_L BIQUAD EQ (BPF1:A2-1) ...................................................................................................... 150
PR-EEH: DAC_L BIQUAD EQ (BPF1:A2-2) ....................................................................................................... 151
PR-EFH: DAC_R BIQUAD EQ (BPF1:H0-1) ....................................................................................................... 151
PR-F0H: DAC_R BIQUAD EQ (BPF1:H0-2) ....................................................................................................... 151
PR-F1H: DAC_R BIQUAD EQ (BPF1:B1-1)........................................................................................................ 151
PR-F2H: DAC_R BIQUAD EQ (BPF1:B1-2)........................................................................................................ 152
PR-F3H: DAC_R BIQUAD EQ (BPF1:B2-1)........................................................................................................ 152
PR-F4H: DAC_R BIQUAD EQ (BPF1:B2-2)........................................................................................................ 152
PR-F5H: DAC_R BIQUAD EQ (BPF1:A1-1) ....................................................................................................... 152
PR-F6H: DAC_R BIQUAD EQ (BPF1:A1-2) ....................................................................................................... 153
PR-F7H: DAC_R BIQUAD EQ (BPF1:A2-1) ....................................................................................................... 153
PR-F8H: DAC_R BIQUAD EQ (BPF1:A2-2) ....................................................................................................... 153
MX-FEH: VENDOR ID ........................................................................................................................................ 153
ELECTRICAL CHARACTERISTICS.................................................................................................................... 154
11.1.
DC CHARACTERISTICS ............................................................................................................................................. 154
11.1.1.
Absolute Maximum Ratings ........................................................................................................................... 154
11.1.2.
Recommended Operating Conditions ............................................................................................................ 154
11.1.3.
Static Characteristics..................................................................................................................................... 154
11.2.
ANALOG PERFORMANCE CHARACTERISTICS ............................................................................................................ 155
11.3.
SIGNAL TIMING ........................................................................................................................................................ 157
11.3.1.
I2C Control Interface ..................................................................................................................................... 157
11.3.2.
I2S/PCM Interface Master Mode ................................................................................................................... 158
11.3.3.
I2S/PCM Interface Slave Mode ...................................................................................................................... 159
11.3.4.
Digital Microphone Interface ........................................................................................................................ 160
12.
APPLICATION CIRCUITS ..................................................................................................................................... 161
13.
PACKAGE INFORMATION ................................................................................................................................... 163
13.1.
13.2.
14.
MECHANICAL DIMENSIONS ...................................................................................................................................... 163
PACKAGE THERMAL INFORMATION ......................................................................................................................... 164
ORDERING INFORMATION ................................................................................................................................. 165
viii
Rev. 0.91
ALC5672-VB
Datasheet
List of Tables
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 21.
TABLE 22.
TABLE 23.
TABLE 24.
TABLE 25.
TABLE 26.
TABLE 27.
TABLE 28.
TABLE 29.
TABLE 30.
TABLE 31.
TABLE 32.
TABLE 33.
TABLE 34.
TABLE 35.
TABLE 36.
TABLE 37.
TABLE 38.
TABLE 39.
TABLE 40.
TABLE 41.
TABLE 42.
TABLE 43.
TABLE 44.
TABLE 45.
TABLE 46.
TABLE 47.
TABLE 48.
TABLE 49.
TABLE 50.
TABLE 51.
TABLE 52.
DIGITAL I/O PINS .......................................................................................................................................................... 9
ANALOG I/O PINS ........................................................................................................................................................ 10
FILTER/REFERENCE ..................................................................................................................................................... 11
POWER/GROUND ......................................................................................................................................................... 11
POWER SUPPLY FOR BEST PERFORMANCE................................................................................................................... 13
POWER SUPPLY CONDITION FOR POWER DOWN LEAKAGE.......................................................................................... 13
RESET OPERATION ...................................................................................................................................................... 16
POWER-ON RESET VOLTAGE....................................................................................................................................... 16
CLOCK SETTING TABLE FOR 48K (UNIT: MHZ) .......................................................................................................... 18
CLOCK SETTING TABLE FOR 44.1K (UNIT: MHZ) ..................................................................................................... 18
THE RELATIVE OF SYSCLK/BCLK/LRCK ............................................................................................................... 19
REGISTER SETTINGS FOR ASRC FUNCTION ON SLAVE MODE ................................................................................... 21
SAMPLE RATE WITH FILTER COEFFICIENT FOR WIND FILTER..................................................................................... 42
ADDRESS SETTING (0X38H) ...................................................................................................................................... 44
WRITE WORD PROTOCOL ........................................................................................................................................ 45
READ WORD PROTOCOL .......................................................................................................................................... 45
REGISTER MAP .......................................................................................................................................................... 55
MX-00H: S/W RESET ................................................................................................................................................ 59
MX-02H: HEADPHONE OUTPUT CONTROL ................................................................................................................ 59
MX-03H: LINE OUTPUT CONTROL ........................................................................................................................... 60
MX-0DH: IN1 INPUT CONTROL - 1 ........................................................................................................................... 62
MX-0BH: IN1 INPUT CONTROL - 2 ............................................................................................................................ 62
MX-0CH: IN1 INPUT CONTROL - 3 ............................................................................................................................ 63
MX-0EH: IN2 INPUT CONTROL ................................................................................................................................. 63
MX-0FH: INL & INR VOLUME CONTROL................................................................................................................. 64
MX-19H: DACL1/R1 DIGITAL VOLUME .................................................................................................................. 65
MX-1AH: DACL2/R2 DIGITAL VOLUME.................................................................................................................. 65
MX-1BH: DACL2/R2 MUTE/UN-MUTE CONTROL ................................................................................................... 67
MX-1CH: STEREO1 ADC DIGITAL VOLUME CONTROL ............................................................................................ 68
MX-1DH: MONO ADC DIGITAL VOLUME CONTROL ................................................................................................ 69
MX-1EH: ADC DIGITAL BOOST GAIN CONTROL ...................................................................................................... 70
MX-1FH: STEREO2 ADC DIGITAL VOLUME CONTROL ............................................................................................. 71
MX-20H: MONO ADC DIGITAL BOOST GAIN CONTROL ........................................................................................... 72
MX-26H: STEREO2 ADC DIGITAL MIXER CONTROL ................................................................................................ 72
MX-27H: STEREO1 ADC DIGITAL MIXER CONTROL ................................................................................................ 73
MX-28H: MONO ADC DIGITAL MIXER CONTROL .................................................................................................... 74
MX-29H: STEREO ADC TO DAC DIGITAL MIXER CONTROL .................................................................................... 75
MX-2AH: STEREO DAC DIGITAL MIXER CONTROL ................................................................................................. 75
MX-2BH: MONO DAC DIGITAL MIXER CONTROL.................................................................................................... 76
MX-2CH: DAC DIGITAL MIXER CONTROL ............................................................................................................... 77
MX-2DH: VOICE DSP PATH CONTROL 1 .................................................................................................................. 78
MX-2EH: VOICE DSP VOLUME CONTROL ................................................................................................................ 79
MX-2FH: INTERFACE DAC/ADC DATA CONTROL ................................................................................................... 80
MX-31H: SPEAKER CONTROL 1 ................................................................................................................................ 80
MX-3BH: RECMIXL CONTROL 1 ............................................................................................................................ 81
MX-3CH: RECMIXL CONTROL 2 ............................................................................................................................ 81
MX-3DH: RECMIXR CONTROL 1 ............................................................................................................................ 82
MX-3EH: RECMIXR CONTROL 2 ............................................................................................................................ 82
MX-45H: HPOMIX CONTROL .................................................................................................................................. 83
MX-4FH: OUTMIXL CONTROL ............................................................................................................................... 83
MX-52H: OUTMIXR CONTROL 3 ............................................................................................................................ 84
MX-53H: LOUTMIX CONTROL ............................................................................................................................... 84
ix
Rev. 0.91
ALC5672-VB
Datasheet
TABLE 53. MX-61H: POWER MANAGEMENT CONTROL 1 ........................................................................................................... 85
TABLE 54. MX-62H: POWER MANAGEMENT CONTROL 2 ........................................................................................................... 86
TABLE 55. MX-63H: POWER MANAGEMENT CONTROL 3 ........................................................................................................... 86
TABLE 56. MX-64H: POWER MANAGEMENT CONTROL 4 ........................................................................................................... 87
TABLE 57. MX-65H: POWER MANAGEMENT CONTROL 5 ........................................................................................................... 88
TABLE 58. MX-66H: POWER MANAGEMENT CONTROL 6 ........................................................................................................... 89
TABLE 59. MX-6AH: PRIVATE REGISTER INDEX ........................................................................................................................ 89
TABLE 60. MX-6CH: PRIVATE REGISTER DATA ......................................................................................................................... 89
TABLE61. MX-70H: I2S1 DIGITAL INTERFACE CONTROL .......................................................................................................... 90
TABLE 61. MX-71H: I2S2 DIGITAL INTERFACE CONTROL.......................................................................................................... 90
TABLE 62. MX-73H: ADC/DAC CLOCK CONTROL .................................................................................................................... 91
TABLE 63. MX-74H: ADC/DAC HPF CONTROL ........................................................................................................................ 92
TABLE 64. MX-75H: DIGITAL MICROPHONE CONTROL 1 ........................................................................................................... 93
TABLE 65. MX-76H: DIGITAL MICROPHONE CONTROL 2 ........................................................................................................... 94
TABLE 66. MX-77H: TDM INTERFACE CONTROL 1 .................................................................................................................... 95
TABLE 67. MX-78H: TDM INTERFACE CONTROL 2 .................................................................................................................... 96
TABLE 68. MX-79H: TDM INTERFACE CONTROL 3 .................................................................................................................... 97
TABLE 69. MX-7FH: CLOCK CONTROL 1.................................................................................................................................... 98
TABLE 70. MX-80H: GLOBAL CLOCK CONTROL ........................................................................................................................ 98
TABLE 71. MX-81H: PLL CONTROL 1 ........................................................................................................................................ 99
TABLE 72. MX-82H: PLL CONTROL 2 ........................................................................................................................................ 99
TABLE 73. MX-83H: ASRC CONTROL 1 ................................................................................................................................... 100
TABLE 74. MX-84H: ASRC CONTROL 2 ................................................................................................................................... 101
TABLE 75. MX-85H: ASRC CONTROL 3 ................................................................................................................................... 102
TABLE 76. MX-8AH: ASRC CONTROL 4 .................................................................................................................................. 103
TABLE 77. MX-8CH: ASRC CONTROL 5 .................................................................................................................................. 103
TABLE 78. MX-8EH: HP AMP CONTROL 1 ............................................................................................................................... 104
TABLE 79. MX-8FH: HP AMP CONTROL 2 ............................................................................................................................... 104
TABLE 80. MX-93H: MICBIAS CONTROL ............................................................................................................................... 105
TABLE 81. MX-94H: JD1 CONTROL ......................................................................................................................................... 105
TABLE 82. MX-AEH: ADC PATH EQ CONTROL 1 .................................................................................................................... 106
TABLE 83. MX-AFH: ADC PATH EQ CONTROL 2 .................................................................................................................... 107
TABLE 84. MX-B0H: DAC PATH EQ CONTROL 1 .................................................................................................................... 108
TABLE 85. MX-B1H: EQ CONTROL 2 ....................................................................................................................................... 109
TABLE 86. MX-B2H: DRC CONTROL 1 .................................................................................................................................... 110
TABLE 87. MX-B3H: DRC CONTROL 2 .................................................................................................................................... 110
TABLE 88. MX-B4H: DRC CONTROL 3 .................................................................................................................................... 111
TABLE 89. MX-B5H: DRC CONTROL 4 .................................................................................................................................... 112
TABLE 90. MX-B6H: DRC CONTROL 5 .................................................................................................................................... 113
TABLE 91. MX-B7H: DRC CONTROL 6 .................................................................................................................................... 114
TABLE 92. MX-BBH: JACK DETECTION CONTROL 1 ................................................................................................................ 114
TABLE 93. MX-BDH: IRQ CONTROL 1 ..................................................................................................................................... 115
TABLE 94. MX-BEH: IRQ CONTROL 2 ..................................................................................................................................... 116
TABLE 95. MX-BFH: IRQ CONTROL 3 ..................................................................................................................................... 117
TABLE 96. MX-C0H: GPIO CONTROL 1 ................................................................................................................................... 118
TABLE 97. MX-C1H: GPIO CONTROL 2 ................................................................................................................................... 118
TABLE 98. MX-C2H: GPIO CONTROL 3 ................................................................................................................................... 119
TABLE 99. MX-CFH: SOUNZREALTM BASSBACK CONTROL..................................................................................................... 120
TABLE 100. MX-D0H: SOUNZREALTM TRUTREBLE CONTROL 1 .............................................................................................. 120
TABLE 101. MX-D1H: SOUNZREALTM L TRUTREBLE CONTROL 2 ............................................................................................ 121
TABLE 102. MX-D3H: STEREO1 ADC WIND FILTER CONTROL 1 ............................................................................................ 121
TABLE 103. MX-D4H: STEREO1 ADC WIND FILTER CONTROL 2 ............................................................................................ 122
TABLE 104. MX-D9H: SOFT VOLUME & ZCD CONTROL 1 ...................................................................................................... 123
TABLE 105. MX-DAH: SOFT VOLUME & ZCD CONTROL 2...................................................................................................... 124
TABLE 106. MX-DBH: INLINE COMMAND CONTROL 1 ............................................................................................................ 124
x
Rev. 0.91
ALC5672-VB
Datasheet
TABLE 107.
TABLE 108.
TABLE 109.
TABLE 110.
TABLE 111.
TABLE 112.
TABLE 113.
TABLE 114.
TABLE 115.
TABLE 116.
TABLE 117.
TABLE 118.
TABLE 119.
TABLE 120.
TABLE 121.
TABLE 122.
TABLE 123.
TABLE 124.
TABLE 125.
TABLE 126.
TABLE 127.
TABLE 128.
TABLE 129.
TABLE 130.
TABLE 131.
TABLE 132.
TABLE 133.
TABLE 134.
TABLE 135.
TABLE 136.
TABLE 137.
TABLE 138.
TABLE 139.
TABLE 140.
TABLE 141.
TABLE 142.
TABLE 143.
TABLE 144.
TABLE 145.
TABLE 146.
TABLE 147.
TABLE 148.
TABLE 149.
TABLE 150.
TABLE 151.
TABLE 152.
TABLE 153.
TABLE 154.
TABLE 155.
TABLE 156.
TABLE 157.
TABLE 158.
TABLE 159.
TABLE 160.
TABLE 161.
MX-DCH: INLINE COMMAND CONTROL 2 ............................................................................................................ 125
MX-DDH: INLINE COMMAND CONTROL 3 ............................................................................................................ 126
MX-E0H: VOICE DSP CONTROL 1 ........................................................................................................................ 126
MX-E1H: VOICE DSP CONTROL 2 ........................................................................................................................ 127
MX-E2H: VOICE DSP CONTROL 3 ........................................................................................................................ 127
MX-E3H: VOICE DSP CONTROL 4 ........................................................................................................................ 127
MX-E4H: VOICE DSP CONTROL 5 ........................................................................................................................ 128
MX-E5H: VOICE DSP CONTROL 6 ........................................................................................................................ 128
MX-ECH: MONO ADC WIND FILTER CONTROL 1 ................................................................................................ 128
MX-EDH: MONO ADC WIND FILTER CONTROL 2 ................................................................................................ 129
MX-EEH: STEREO2 ADC WIND FILTER CONTROL 1 ............................................................................................ 129
MX-EFH: STEREO2 ADC WIND FILTER CONTROL 2 ............................................................................................. 131
MX-F8H: JACK DETECTION CONTROL .................................................................................................................. 131
MX-F9H: JACK DETECTION CONTROL .................................................................................................................. 132
MX-FAH: GENERAL CONTROL 1........................................................................................................................... 132
MX-FBH: GENERAL CONTROL 2 ........................................................................................................................... 133
MX-FCH: GENERAL CONTROL 3 ........................................................................................................................... 134
PR-3DH: ADC/DAC RESET CONTROL................................................................................................................ 134
PR-A4H: DAC_L EQ (LPF2:A1) .......................................................................................................................... 135
PR-A5H: DAC_L EQ (LPF2:H0) .......................................................................................................................... 135
PR-A6H: DAC_R EQ (LPF2:A1) .......................................................................................................................... 135
PR-A7H: DAC_R EQ (LPF:H0) ........................................................................................................................... 135
PR-AEH: DAC_L EQ (BPF2:A1).......................................................................................................................... 136
PR-AFH: DAC_L EQ (BPF2:A2) .......................................................................................................................... 136
PR-B0H: DAC_L EQ (BPF2:H0) .......................................................................................................................... 136
PR-B1H: DAC_R EQ (BPF2:A1) .......................................................................................................................... 136
PR-B2H: DAC_R EQ (BPF2:A2) .......................................................................................................................... 137
PR-B3H: DAC_R EQ (BPF2:H0) ......................................................................................................................... 137
PR-B4H: DAC_L EQ (BPF3:A1) .......................................................................................................................... 137
PR-B5H: DAC_L EQ (BPF3:A2) .......................................................................................................................... 137
PR-B6H: DAC_L EQ (BPF3:H0) .......................................................................................................................... 138
PR-B7H: DAC_R EQ (BPF3:A1) .......................................................................................................................... 138
PR-B8H: DAC_R EQ (BPF3:A2) .......................................................................................................................... 138
PR-B9H: DAC_R EQ (BPF3:H0) ......................................................................................................................... 138
PR-BAH: DAC_L EQ (BPF4:A1) ......................................................................................................................... 139
PR-BBH: DAC_L EQ (BPF4:A2).......................................................................................................................... 139
PR-BCH: DAC_L EQ (BPF4:H0) ......................................................................................................................... 139
PR-BDH: DAC_R EQ (BPF4:A1) ......................................................................................................................... 139
PR-BEH: DAC_R EQ (BPF4:A2).......................................................................................................................... 140
PR-BFH: DAC_R EQ (BPF4:H0) ......................................................................................................................... 140
PR-C0H: DAC_L EQ (HPF1:A1) .......................................................................................................................... 140
PR-C1H: DAC_L EQ (HPF1:H0) ......................................................................................................................... 140
PR-C2H: DAC_R EQ (HPF1:A1) .......................................................................................................................... 141
PR-C3H: DAC_R EQ (HPF1:H0) ......................................................................................................................... 141
PR-C4H: DAC_L EQ (HPF2:A1) .......................................................................................................................... 141
PR-C5H: DAC_L EQ (HPF2:A2) .......................................................................................................................... 141
PR-C6H: DAC_L EQ (HPF2:H0) ......................................................................................................................... 142
PR-C7H: DAC_R EQ (HPF2:A1) .......................................................................................................................... 142
PR-C8H: DAC_R EQ (HPF2:A2) .......................................................................................................................... 142
PR-C9H: DAC_R EQ (HPF2:H0) ......................................................................................................................... 142
PR-CAH: DAC_L EQ PRE-VOLUME CONTROL .................................................................................................... 143
PR-CBH: DAC_R EQ PRE-VOLUME CONTROL .................................................................................................... 143
PR-CCH: DAC_L EQ POST-VOLUME CONTROL ................................................................................................... 143
PR-CDH: DAC_R EQ POST-VOLUME CONTROL .................................................................................................. 144
PR-CEH: ADC EQ (LPF:A1) ................................................................................................................................ 144
xi
Rev. 0.91
ALC5672-VB
Datasheet
TABLE 162.
TABLE 163.
TABLE 164.
TABLE 165.
TABLE 166.
TABLE 167.
TABLE 168.
TABLE 169.
TABLE 170.
TABLE 171.
TABLE 172.
TABLE 173.
TABLE 174.
TABLE 175.
TABLE 176.
TABLE 177.
TABLE 178.
TABLE 179.
TABLE 180.
TABLE 181.
TABLE 182.
TABLE 183.
TABLE 184.
TABLE 185.
TABLE 186.
TABLE 187.
TABLE 188.
TABLE 189.
TABLE 190.
TABLE 191.
TABLE 192.
TABLE 193.
TABLE 194.
TABLE 195.
TABLE 196.
TABLE 197.
TABLE 198.
TABLE 199.
TABLE 200.
TABLE 201.
TABLE 202.
TABLE 203.
TABLE 204.
TABLE 205.
TABLE 206.
TABLE 207.
TABLE 208.
TABLE 209.
PR-CFH: ADC EQ (LPF:H0) ................................................................................................................................ 144
PR-D0H: ADC EQ (BPF1:A1) .............................................................................................................................. 144
PR-D1H: ADC EQ (BPF1:A2) .............................................................................................................................. 145
PR-D2H: ADC EQ (BPF1:H0) .............................................................................................................................. 145
PR-D3H: ADC EQ (BPF2:A1) .............................................................................................................................. 145
PR-D4H: ADC EQ (BPF2:A2) .............................................................................................................................. 145
PR-D5H: ADC EQ (BPF2:H0) .............................................................................................................................. 146
PR-D6H: ADC EQ (BPF3:A1) .............................................................................................................................. 146
PR-D7H: ADC EQ (BPF3:A2) .............................................................................................................................. 146
PR-D8H: ADC EQ (BPF3:H0) .............................................................................................................................. 146
PR-D9H: ADC EQ (BPF4:A1) .............................................................................................................................. 147
PR-DAH: ADC EQ (BPF4:A2).............................................................................................................................. 147
PR-DBH: ADC EQ (BPF4:H0) ............................................................................................................................. 147
PR-DCH: ADC EQ (HPF1:A1).............................................................................................................................. 147
PR-DDH: ADC EQ (HPF1:H0) ............................................................................................................................. 148
PR-E1H: ADC EQ PRE-VOLUME CONTROL .......................................................................................................... 148
PR-E2H: ADC EQ POST-VOLUME CONTROL ........................................................................................................ 148
PR-E5H: DAC_L BIQUAD EQ (BPF1:H0-1).......................................................................................................... 148
PR-E6H: DAC_L BIQUAD EQ (BPF1:H0-2).......................................................................................................... 149
PR-E7H: DAC_L BIQUAD EQ (BPF1:B1-1) .......................................................................................................... 149
PR-E8H: DAC_L BIQUAD EQ (BPF1:B1-2) .......................................................................................................... 149
PR-E9H: DAC_L BIQUAD EQ (BPF1:B2-1) .......................................................................................................... 149
PR-EAH: DAC_L BIQUAD EQ (BPF1:B2-2) ......................................................................................................... 150
PR-EBH: DAC_L BIQUAD EQ (BPF1:A1-1) ......................................................................................................... 150
PR-ECH: DAC_L BIQUAD EQ (BPF1:A1-2) ......................................................................................................... 150
PR-EDH: DAC_L BIQUAD EQ (BPF1:A2-1)......................................................................................................... 150
PR-EEH: DAC_L BIQUAD EQ (BPF1:A2-2) ......................................................................................................... 151
PR-EFH: DAC_R BIQUAD EQ (BPF1:H0-1) ......................................................................................................... 151
PR-F0H: DAC_R BIQUAD EQ (BPF1:H0-2).......................................................................................................... 151
PR-F1H: DAC_R BIQUAD EQ (BPF1:B1-1) .......................................................................................................... 151
PR-F2H: DAC_R BIQUAD EQ (BPF1:B1-2) .......................................................................................................... 152
PR-F3H: DAC_R BIQUAD EQ (BPF1:B2-1) .......................................................................................................... 152
PR-F4H: DAC_R BIQUAD EQ (BPF1:B2-2) .......................................................................................................... 152
PR-F5H: DAC_R BIQUAD EQ (BPF1:A1-1).......................................................................................................... 152
PR-F6H: DAC_R BIQUAD EQ (BPF1:A1-2).......................................................................................................... 153
PR-F7H: DAC_R BIQUAD EQ (BPF1:A2-1).......................................................................................................... 153
PR-F8H: DAC_R BIQUAD EQ (BPF1:A2-2).......................................................................................................... 153
MX-FEH: VENDOR ID........................................................................................................................................... 153
ABSOLUTE MAXIMUM RATINGS ............................................................................................................................ 154
RECOMMENDED OPERATING CONDITIONS............................................................................................................. 154
STATIC CHARACTERISTICS .................................................................................................................................... 154
ANALOG PERFORMANCE CHARACTERISTICS ......................................................................................................... 155
I2C TIMING ............................................................................................................................................................ 157
TIMING OF I2S/PCM MASTER MODE ..................................................................................................................... 158
I2S/PCM SLAVE MODE TIMING ............................................................................................................................. 159
DIGITAL MICROPHONE INTERFACE TIMING ........................................................................................................... 160
THERMAL INFORMATION ....................................................................................................................................... 164
ORDERING INFORMATION ...................................................................................................................................... 165
xii
Rev. 0.91
ALC5672-VB
Datasheet
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
FIGURE 9.
FIGURE 10.
FIGURE 11.
FIGURE 12.
FIGURE 13.
FIGURE 14.
FIGURE 15.
FIGURE 16.
FIGURE 17.
FIGURE 18.
FIGURE 19.
FIGURE 20.
FIGURE 21.
FIGURE 22.
FIGURE 23.
FIGURE 24.
FIGURE 25.
FIGURE 26.
FIGURE 27.
FIGURE 28.
FIGURE 29.
FIGURE 30.
FIGURE 31.
FIGURE 32.
FIGURE 33.
FIGURE 34.
FIGURE 35.
FIGURE 36.
FIGURE 37.
FIGURE 38.
FIGURE 39.
AUDIO MIXER PATH ................................................................................................................................................... 5
AUDIO MIXER PATH ................................................................................................................................................... 6
DIGITAL MIXER PATH ................................................................................................................................................ 7
PIN ASSIGNMENTS ...................................................................................................................................................... 8
GENERAL SYSTEM CONNECTION .............................................................................................................................. 12
POWER ON/OFF TIMING ........................................................................................................................................... 15
AUDIO CLOCK TREE ................................................................................................................................................. 17
SYSTEM CONNECTION FOR ASRC FUNCTION ........................................................................................................... 20
MONO PCM DATA MODE A FORMAT (BCLK POLARITY=0) ................................................................................ 22
MONO PCM DATA MODE B FORMAT (BCLK POLARITY=0) .............................................................................. 23
PCM STEREO DATA MODE A FORMAT (BCLK POLARITY=0) ............................................................................ 23
TDM MODE-1 PCM DATA MODE A FORMAT (BCLK POLARITY=0) ................................................................. 23
PCM STEREO DATA MODE B FORMAT (BCLK POLARITY=0) ............................................................................ 24
TDM MODE-1 PCM DATA MODE B FORMAT (BCLK POLARITY=0) ................................................................... 24
TDM MODE-2 PCM DATA MODE B FORMAT (BCLK POLARITY=0) ................................................................... 24
I2S DATA FORMAT (BCLK POLARITY=0)............................................................................................................. 25
I2S TDM DATA FORMAT (BCLK POLARITY=0) ................................................................................................... 25
LEFT-JUSTIFIED DATA FORMAT (BCLK POLARITY=0) ........................................................................................ 25
LEFT-JUSTIFIED TDM DATA FORMAT (BCLK POLARITY=0) ............................................................................... 26
4-CHANNEL RECORDING PATH ................................................................................................................................ 27
4-CHANNEL PLAYBACK PATH .................................................................................................................................. 28
STEREO BTL SPEAKER OUTPUT ............................................................................................................................... 31
DAC DRC FUNCTION BLOCK .................................................................................................................................. 35
ADC AGC FUNCTION BLOCK .................................................................................................................................. 35
PLAYBACK DRC OUTPUT CURVE ............................................................................................................................ 36
RECORD DRC OUTPUT CURVE - 1............................................................................................................................ 37
RECORD DRC OUTPUT CURVE - 2............................................................................................................................ 38
DRC/AGC FOR PLAYBACK/RECORDING MODE ....................................................................................................... 39
DRC/AGC FOR NOISE GATE MODE ......................................................................................................................... 40
DATA TRANSFER OVER I2C CONTROL INTERFACE ................................................................................................... 44
GPIO FUNCTION BLOCK .......................................................................................................................................... 46
IRQ FUNCTION BLOCK............................................................................................................................................. 47
POWER MANAGEMENT ............................................................................................................................................. 51
I2C CONTROL INTERFACE ....................................................................................................................................... 157
TIMING OF I2S/PCM MASTER MODE ...................................................................................................................... 158
I2S/PCM SLAVE MODE TIMING ............................................................................................................................. 159
DIGITAL MICROPHONE INTERFACE TIMING............................................................................................................ 160
APPLICATION CIRCUIT ........................................................................................................................................... 162
PACKAGE DIMENSION ............................................................................................................................................ 163
xiii
Rev. 0.91
ALC5672-VB
Datasheet
1.
General Description
The ALC5672 is a high performance, low power, dual I2S interface audio CODEC with embedded low
power/high performance Voice DSP. Dual I2S interface can connect to different devices and let the
ALC5672 to be an Audio Hub. Each device can pass through the Audio Hub and then perform as input or
output application. Asynchronous Sample Rate Converter (ASRC) provides independent and
asynchronous connections to different processors, such as an application processor, baseband processor or
wireless transceiver(BT).
Stereo Class-D speaker amplifiers provide 1.5W per channel into 8Ω or 2.8W per channel into 4Ω with a
5V supply, with high THD+N performance, excellent PSRR and low EMI. A mono differential earpiece
amplifier is also provided, providing output from any DAC or Analog-in.
The ALC5672 features a Class-G type ultra low power cap-free headphone amplifier. It is a high
efficiency audio amplifier with an integrated Class-G voltage converter that enhances efficiency at low
output power. It consumes only around 5mW power during playback, providing mobile system longer
battery life under headphone listening mode.
The integrated multi-section DRC(Dynamic Range Controller) and 14-band parametric Equalizer provide
further digital sound processing capability of audio playback paths. The multi-section DRC in ALC5672
continuously monitors the DAC output level. When the power level is low, it increases the input signal
gain to make it sound louder. At the same time, if a peaking signal is detected, it autonomously reduces
the applied gain to avoid hard clipping. It ensures the maximum/consistent signal amplitude without
producing audio clipping and speaker damage. The 14-band parametric Equalizer contains each channel
has 7 independent filters with programmable gain, center frequency and bandwidth to tailor the frequency
characteristics of embedded speaker system according to user preferences.
For microphone recording, the DRC in ALC5672 can be used as AGC(Auto Gain Controller) to maintain
a constant recording volume. Besides, a dynamic wind reduction filter is built in on recording path. The
filter can detect the level of wind noise and on/off dynamically to keep the recording quality. The
ALC5672 also integrates independent 6-band parametric Equalizer for recording path. They can use to
compensate microphone device frequency response.
ALC5672 embedded a low power, high performance voice processor. The 140MIPS voice processor
provides advanced voice processing features, including exceptional noise suppression, echo cancellation
and advanced Beam-Forming under low power consumption. The voice processor is optimized for
advanced voice processing to improve voice quality for voice communication and recording in noisy
environments.
SounzRealTM post-processing technology is configurable to provide better listening experience. BassBack
EXPTM bring LFE(low frequency effect) to listeners without subwoofer needed. TruTreble EXPTM adds
processed harmonic tones at high frequency, bringing more melody and details for music listening.
1
Rev. 0.9
ALC5672-VB
Datasheet
2.
Features
Digital Super Wideband Voice DSP
Voice communication enhancement (AEC, NS…etc.)
Advanced Beam-Forming (Voice Tracking)
Stereo Far field pick-up recording (48KHz Sample Rate)
SounzRealTM post-processing
TruTreble
BassBack
Parametric 14 bands equalizer (EQ) – each 7 bands for L/R playback path independent control
Parametric 6 bands equalizer (EQ) for recording path
Advanced DRC with multi-section compressor function for playback/recording path
Sound detection wake up technology
Wind noise reduction filter
One 24bit/8kHz ~ 192kHz I2S/PCM/TDM digital interface
One 24bit/8kHz ~ 192kHz I2S/PCM digital interface
Digital asynchronous sampling rate converter (ASRC) function
I2C control interface
3 stereo digital microphone interfaces
4 Digital-to-Analog Converter with 100dBA SNR
2 Analog-to-Digital Converter with 94dBA SNR
2 single-ended analog microphone inputs with pre-amplifiers (+20/24/30/35/40/44/50/52dB) and low
noise microphone bias
MIC input to ADC with 50dB Boost, SNR>66dBA, THD+N 48KHz * 25Bit * 8CH) (Only support for I2S-1)
BCLK clock rate only support 50FS/100FS/150FS/200FS (FS is sample rate)
I2S mode
Normal I2S mode (Support for all I2S port)
Left justified mode (Support for all I2S port)
TDM mode-1 (Max. BCLK Rate is 12.288MHz => 48KHz * 32Bit * 8CH) (Only support for
I2S-1)
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
X
1
2
3
4
5
6
7
8
MSB
Figure 9.
9
1
0
1
1
1
2
1
3
1
4
1
5
1
X
6
LSB
Mono PCM Data Mode A Format (BCLK POLARITY=0)
22
Rev. 0.91
ALC5672-VB
Datasheet
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
6
1
2
3
4
5
6
7
8
1
1
1
0
9
1
2
1
3
1
4
1
5
MSB
Figure 10.
1
1
6
LSB
Mono PCM Data Mode B Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
2
3
n-1 n
MSB
1
LSB MSB
n-1 n
LSB
Right-Channel
Left-Channel
Figure 11.
3
2
PCM Stereo Data Mode A Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
DACDAT /
ADCDAT
1 2
MSB
Channel Length:
16/20/24/32Bit
Figure 12.
------
n 1 2
LSB MSB
Channel-1
------
n 1 2
LSB MSB
Channel-2
------
n
1 2
LSB
MSB
Channel-3
n
1 2
LSB
MSB
------
Channel-8
TDM Mode-1 PCM Data Mode A Format (BCLK POLARITY=0)
23
Rev. 0.91
ALC5672-VB
Datasheet
1/Fs
LRCK
BLCK
DACDAT/
ADCDAT
1
3
2
1
n-1 n
MSB
n-1 n
LSB MSB
LSB
Left-Channel
Figure 13.
3
2
Right-Channel
PCM Stereo Data Mode B Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
DACDAT /
ADCDAT
1 2
MSB
Channel Length:
16/20/24/32Bit
------
n 1 2
LSB MSB
Channel-1
------
n 1 2
LSB MSB
------
n
1 2
LSB
MSB
Channel-3
Channel-2
------
n 1 2
LSB MSB
Channel-8
Figure 14. TDM Mode-1 PCM Data Mode B Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
Channel
Length
DACDAT /
ADCDAT
Channel Length:
16/20/24Bit
Data Length:
16/20/24Bit
1 2
MSB
------
n 1 2
LSB MSB
Channel-1
------
n
1 2
LSB
MSB
------
x 1 2
LSB
Channel-8
Channel-2
n x x
MSB
Don’t Care
Figure 15. TDM Mode-2 PCM Data Mode B Format (BCLK POLARITY=0)
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1/ Fs
Left Channel
Right Channel
LRCK
BLCK
DACDAT/
ADCDAT
1
n-1 n
2
1
LSB
MSB
2
n-1 n
LSB
MSB
2
Figure 16. I S Data Format (BCLK POLARITY=0)
1/ Fs
LRCK
BLCK
DACDAT /
ADCDAT
1 2
Channel Length:
16/20/24/32Bit
------
MSB
n
1 2
LSB
MSB
n 1 2
------
LSB MSB
Channel-7
Channel-1
Data Length:
16/20/24Bit
------
n
1 2
LSB
MSB
Channel-2
------
n 1 2 3
LSB
Channel-8
2
Figure 17. I S TDM Data Format (BCLK POLARITY=0)
1/ Fs
Left Channel
Right Channel
LRCK
BLCK
DACDAT/
ADCDAT
1
MSB
2
n-1
n
1
LSB
MSB
2
n-1 n
LSB
Figure 18. Left-Justified Data Format (BCLK POLARITY=0)
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1/ Fs
LRCK
BLCK
DACDAT /
ADCDAT
Channel Length:
16/20/24/32Bit
Data Length:
16/20/24Bit
1 2
MSB
------
n
1 2
LSB
MSB
Channel-1
------
n 1 2
LSB MSB
Channel-7
------
n
1 2
LSB
MSB
Channel-2
------
n 1 2 3
LSB
Channel-8
Figure 19. Left-Justified TDM Data Format (BCLK POLARITY=0)
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9.5. Audio Data Path
The ALC5672 provides 4-channel analog DACs for playback and 2-channel analog ADCs for recording.
9.5.1.
2 Analog ADCs with 6-Channel Record Path
There are two analog ADCs and with up to 6-channel recording path. You can use two analog
microphones pass to analog ADCs and four digital microphones to reach 6-channel recording. Or use
three digital microphone interfaces to reach 6-channel recording. These 6-channel data can through I2S1
interface for recording. The I2S1 interface supports TDM interface and up to 8-CH, 24-bit/CH recording.
The full scale input of analog ADC is around 0.55Vrms. In order to save power, the left and right analog
ADC can be powered down separately by setting pow_adc_l (MX-61[2]) and pow_adc_r (MX-61[1]).
And the volume control of the stereo ADC is also separately controlled by ad_gain_l (MX-1C[14:8]) and
ad_gain_r (MX-1C[6:0]).
DMIC1_L
DMIC1_L
DMIC1_L
DMIC2_L
DMIC2_L
DMIC2_L
DMIC3_L
DMIC3_L
DAC_MIXL
DMIC3_L
DAC_MIXL
Mono_DAC_MIXL
CH1
IF_ADC1_L
DAC_MIXL
CH3
IF_ADC2_L
Mono_DAC_MIXL
Analog ADC_L
Analog ADC_L
DMIC1_R
DMIC1_R
DMIC1_R
DMIC2_R
DMIC2_R
DMIC2_R
DMIC3_R
DMIC3_R
DMIC3_R
DAC_MIXR
Mono_DAC_MIXR
CH2
DAC_MIXR
Analog ADC_R
IF_ADC1_R
IF_ADC3_L
CH6
IF_ADC3_L
DAC_MIXR
CH4
Mono_DAC_MIXR
IF_ADC2_R
DAC_MIXR
Analog ADC_R
IF_ADC1_L
CH5
DAC_MIXL
Analog ADC_L
Analog ADC_R
IF_ADC1_R
IF_ADC2_L
IF_ADC2_R
IF_ADC3_L
IF_ADC3_R
TDM Format
Figure 20. 4-Channel Recording Path
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9.5.2.
4 DACs with 4-Channel Playback Path
There are four analog DACs and with up to 4-channel playback path. Two I2S interfaces provide four
channels data to analog DACs. And analog DAC can output audio signal to speaker output, headphone
output or line output. That also can use I2S1 TDM interface to support 4-channel playback.
The full scale output of analog DAC is around 1Vrms at line output port. In order to save power, the four
analog DACs can be powered down separately by setting pow_dac_l_1 (MX-61[12]), pow_dac_r_1
(MX-61[11]), pow_dac_l_2 (MX-61[7]) and pow_dac_r_2 (MX-61[6]). And the digital volume control
of the four DACs are also separately controlled by vol_dac1_l (MX-19[15:8]), vol_dac1_r (MX-19[7:0]),
vol_mono_dacl (MX-1A[15:8] and vol_mono_dacr (MX-1A[7:0]).
L
L
CH1
IF1_DAC
Analog DACL1
IF1_DAC
I2S1
R
L
IF2_DAC
Analog DACL1
CH2
Analog DACR1
CH3
Analog DACL2
CH4
Analog DACR2
R
CH2
Analog DACR1
CH3
Analog DACL2
L
I2S1
TDM
I2S2
R
CH1
I2S1
TDM
CH4
Analog DACR2
R
Figure 21. 4-Channel Playback Path
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9.5.3.
Mixers
The ALC5672 has digital and analog mixers build-in.
Output mixer - OUTMIXL/R
The stereo analog mixer can do mixing for DAC output and analog input. The mixer output is mainly
for line output. Each input path has it’s mute control to the mixer block in MX-53. pow_outmixl and
pow_outmixr can be used to power on/off OUTMIXL/R
Record mixer – RECMIXL/R
The stereo analog mixer can do mixing for analog input and OUTMIX output. The mixer output is for
ADC input. Each input path has it’s mute control to the mixer block in MX-3B ~ MX-3E.
pow_recmixl and pow_recmixr can be used to power on/off RECMIXL/R.
HP mixer – HPMIXL/R
The stereo analog mixer can do mixing for headphone volume and DAC output. The mixer output
directly output to external headphone device. Each input path has it’s mute control to the mixer block
in MX-45.
Digital mixer
There are twelve digital mixers in ALC5672. Six digital mixers are assigned for ADC recording.
These six mixers can mix analog line input, analog microphone input and digital microphone input
then output to I2S interface to other device. Another four digital mixers are assigned for DAC
playback. These mixers can mix digital data from I2S interface or ADC data from external analog
signal. The mixed data is output to analog DAC and output port to drive external device. The other
two mixers are used for DA-AD processing. The incoming data from two I2S interfaces (DACDAT)
uses these two mixers to do mixing and output to I2S interface (ADCDAT).
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9.6. Analog Audio Input Port
The ALC5672 has two type analog input ports: microphone input and line input.
IN1P_RING2/IN1N_SLEEVE
The port is a microphone type input port. The input port only can be configured as single-ended mode.
The microphone input port has its microphone bias and microphone boost. The low noise microphone
bias can improve recording performance and enhance recording quality. Build-in short current
detection scheme can be used for switch detection. Multi-steps microphone boost gain set by sel_bst1
(MX-0D[15:12]) is easy to use for microphone application. Pow_bst1 can be used to power down the
MIC1 boost and pow_micbias1 can be used to power down the microphone bias 1.
IN2P/N
The IN2P/N is a dual type input port: microphone input and line input. Microphone input can be
configured to differential input or single-ended input by MX-0E[7]. Multi-steps microphone boost
gain set by sel_bst2 (MX-0E[15:12]) is easy to use for microphone application. Pow_bst2 can be used
to power down the MIC2 boost.
If as line input, it has volume control for tuning by MX-0F[12:8] and MX-0F[4:0].
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9.7. Analog Audio Output Port
The ALC5672 supports three type output ports:
SPO_L/R_P/N
The speaker output of ALC5672 is a stereo BTL output with Class-D type amplifier.
The power of speaker amplifier is an individual power pin and higher than AVDD. So the input and
output of speaker amplifier has a gain ratio to enlarge or reduce the income analog signal. The ratio
gain is auto tuning.
The input source of the speaker output port can be selected from Stereo_DAC_MIXL/R or
Mono_DAC_MIXL/R.
SPKVDDL
Stereo_DAC_MIXL
LP
Gate Drive
Mono_DAC_MIXL
SPOLP
SPKGND
SPKVDDL
Stereo_DAC_MIXL
LN
SPOLN
Gate Drive
Mono_DAC_MIXL
SPKGND
SPKVDDR
Stereo_DAC_MIXR
RP
Gate Drive
Mono_DAC_MIXR
SPORP
SPKGND
SPKVDDR
Stereo_DAC_MIXR
LN
Gate Drive
Mono_DAC_MIXR
SPORN
SPKGND
Figure 22. Stereo BTL Speaker Output
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HPO_L/R
The headphone output of ALC5672 is a stereo output with cap-free type headphone amplifier. It does
not need to connect external capacitor and can connect to earphone device directly. The headphone
output source can mix from output mixer (HPMIX) and DAC by setting MX-45. The front stage of
headphone output has volume control and gain control. The volume range is from +12dB to -46.5dB
with 1.5dB/step by MX-02.
En_l_hp and en_r_hp (MX-63[7/6]) can be used to power on/off Headphone Amplifier, and
pow_hpo_voll and pow_hpo_volr (MX-66[11/10]) can be used to power on/off headphone volume
control. In addition, pow_pump_hp (MX-8E[3]) can be used to power on/off charge pump circuit for
Headphone Amplifier.
Line_OUT_L/R
The output type is line type output. The output is a stereo single ended output or mono differential.
The input can be selected from OUTMIX or DAC output by setting MX-53[15:12]. The front stage of
LOUT output has gain control for attenuation. The gain control is 0dB or -6dB by MX-53[11].
9.8. Multi-Function Pins
There are eight multi-function pins in ALC5672. For different functions of each pin are controlled by
register. You need to set the right register settings for each multi-function pins by your application.
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GPIO1/IRQ – Pin 41
The pin default is GPIO function. It can change to IRQ output, write MX-C0[15] to 1’b will switch to
IRQ function.
GPIO2/DMIC_SCL – Pin 42
The pin default is GPIO function. It can change to DMIC clock output, write MX-C0[14] to 1’b will
switch to DMIC clock output function.
IN2P/INL/DMIC1_DAT – Pin 4
The pin can as analog microphone positive input or as line input. If as analog microphone input function
needs to power on the power – MX-64[13] & MX64[4]. If as analog input function needs to power on the
power – MX-66[9] & MX66[8].
Digital microphone input function:
1. Power down analog microphone input and line input.
2. Mute IN2 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR).
3. Change IN2P pin share function, set MX-75[1:0] to 01’b.
4. Turn on digital microphone function – MX-75[14] = 1’b
IN2N/INR/DMIC2_DAT/JD2 – Pin 5
There are four functions share this pin. For each function switching shows below:
Analog microphone input function, power on MX-64[13] & MX-64[4] and power off other functions.
Analog line input function, power on MX-66[9] & MX-66[8] and power off other functions.
Digital microphone input function:
1. Power down analog microphone input, line input and JD2 function
2. Mute IN2 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR).
3. Change IN2N pin share function, set MX-75[10] to 1’b.
4. Turn on digital microphone function – MX-75[14] = 1’b
Jack detection function:
1. Power down analog microphone input, line input and digital microphone function.
2. Mute IN2 to each analog mixer - (RECMIXLR/OUTMIXLR/HPMIXLR).
3. Turn on JD2 power – MX-64[1] = 1’b
BCLK2/GPIO3 – Pin 31
MX-C0[8] use to control pin31 is BCLK2 function or GPIO function.
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LRCK2/GPIO4 – Pin 30
MX-C0[8] use to control pin31 is LRCK2 function or GPIO function.
DACDAT2/GPIO5/DMIC3_SDA – Pin 32
MX-C0[8] use to control pin31 is LRCK2 function or GPIO function.
MX-C0[7] use to control pin31 is GPIO function or DMIC_SDA3 function.
ADCDAT2/GPIO6/DMIC1_SDA – Pin 33
MX-C0[8] use to control pin31 is LRCK2 function or GPIO function.
MX-C0[6] use to control pin31 is GPIO function or DMIC_SDA1 function.
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9.9. DRC and AGC Function
The Dynamic Range Controller (DRC) dynamically adjusts the input signal and let the output signal
achieve the target level. The ALC5672 supports playback DRC for DAC path, and the DRC can also be
used as AGC(Auto Gain Controller) for ADC path. The control register is at MX-B4[15:14]. The function
block is shown as below. The signal input pass through the Pre-Gain first, then DRC volume and
Post-Gain then output. The Pre-Gain is use to enlarge the input signal. The DRC volume is use to
attenuate the signal after detected by DRC. The Post-Gain is use to fine tune the signal after pass DRC
tuning.
0 ~ 28.5dB, 1.5/step
MXB5[4:0]
-95.625 ~ 0dB
0.375/step
-11.625 ~ 12dB, 0.375/step
MXB5[13:8]
Pre-Gain
DRC
Volume
Post-Gain
I2C Interface
DAC
DRC
1. Limiter level
2. Attack / Release time
3. Zero data
Figure 23. DAC DRC Function Block
Analog
Pre-Boost
ADC
0 ~ 28.5dB, 1.5/step
MXB5[4:0]
-95.625 ~ 0dB
0.375/step
-11.625 ~ 12dB, 0.375/step
MXB5[13:8]
Pre-Gain
AGC
Volume
Post-Gain
I2S Interface
AGC
1. Limiter level
2. Attack / Release time
3. Noise gate
Figure 24.
ADC AGC Function Block
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DRC Output Curve - Playback Mode:
The Figure 24. shows DRC output curve for DAC playback application.
Alc_thmax(MX-B7[5:0]):
The parameter limits the maximum output level when 0dB full scale input. The limit range is
from 0dBFS to -23.625dBFS.
Ratio_1(MX-B5[6:5]):
The parameter determines the slope begin from start point. There are 4 slopes can be selected.
Alc_thmax2(MX-B7[11:6]):
The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS.
Ratio_2(MX-B5[15:14]):
The parameter determines the slope begin from first knee. There are 4 slopes can be selected.
The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thmin to calculate.
Alc_thmin(MX-B2[5:0]):
The parameter determines the third knee from previous curve. The range is from -60dBFS to -94.5dBFS.
Ratio_3(MX-B5[1:0]):
The slope is determined by third knee and end point. The end point is determined by boost gain on
MX-B3[11:6] register.
Vout (db)
Segment1
Segment2
Segment_thmin
0
alc_thmax=-6db (REG.)
-6
ratio_1=¼ (REG.)
Start Point
-12
-18
2nd Knee
st
-24
1:
1
Bo
o
-30
-36
ration_2=½ (REG.)
1st Knee
-42
-48
3rd Knee
-54
-60
ration_3 (H/W)
-66
-72
-78
-84
boost_gain = 12db (REG.) -90
End Point
-95.625
-90
-84
-78 -72
-66
-60
-54
-48 -42
alc_thmin = -60db (REG.)
-36 -30
-24
Knee (H/W)
-18
-12
-6
0
Vin (db)
alc_thmax2 = -12db (REG.)
Figure 25. Playback DRC Output Curve
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DRC Output Curve - Record Mode 1:
The Figure 25. shows DRC output curve for ADC record application.
Alc_thmax(MX-B7[5:0]):
The parameter limits the maximum output level when 0dB full scale input. The limit range is
from 0dBFS to -23.625dBFS.
Ratio_1(MX-B5[6:5]):
The parameter determines the slope begin from start point. There are 4 slopes can be selected.
Alc_thmax2(MX-B7[11:6]):
The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS.
Ratio_2(MX-B5[15:14]):
The parameter determines the slope begin from first knee. There are 4 slopes can be selected.
The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thnoise to calculate.
Alc_thnoise(MX-B6[4:0]):
The parameter determines the third knee from previous curve. The range is from -24dBFS to -70.5dBFS.
Noise_gate_ratio(MX-B5[1:0]):
The parameter determines the slope begin from third knee. There are 4 slopes can be selected.
The end point is determined by third knee and noise_gate_ratio.
Vout (db)
Segment1
Segment2
Segment_noise_gate
0
alc_thmax=-6db (REG.)
Start Point
-12
ratio_1=¼ (REG.)
-6
-18
Bo
o
st
2nd Knee
1:
1
-24
-30
-36
3rd Knee
ratio_2=½ (REG.)
1st Knee
-42
-48
-54
noise_gate_ratio=2
(REG.)
-60
-66
-72
-78
-84
boost_gain = 12db (REG.) -90
-95.625
End Point
-90
-84
-78 -72
-66
-60
-54
-48 -42
alc_thnoise = -48db (REG.)
-36
-30
-24
-18
Knee (H/W)
-12
-6
0
Vin (db)
alc_thmax2 = -12db (REG.)
Figure 26. Record DRC Output Curve - 1
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DRC Output Curve - Record Mode 2:
The Figure 26. shows another DRC output curve for ADC record application.
Alc_thmax(MX-B7[5:0]):
The parameter limits the maximum output level when 0dB full scale input. The limit range is
from 0dBFS to -23.625dBFS.
Ratio_1(MX-B5[6:5]):
The parameter determines the slope begin from start point. There are 4 slopes can be selected.
Alc_thmax2(MX-B7[11:6]):
The parameter determines the first knee from ratio_1 curve. The range is from 0dBFS to -45dBFS.
Ratio_2(MX-B5[15:14]):
The parameter determines the slope begin from first knee. There are 4 slopes can be selected.
The second knee is calculated by internal circuit. It bases on ratio_2 and alc_thnoise to calculate.
Alc_thnoise(MX-B6[4:0]):
The parameter determines the third knee from previous curve. The range is from -24dBFS to -70.5dBFS.
From third knee to fourth knee is a noise drop function by enable noise gate drop mode at MX-B5[4]. The
drop level is determined by boost_gain (MX-B3[11:6]) and alc_noise_gate_exp (MX-B6[15:12]).
Noise_gate_ratio(MX-B5[1:0]):
The parameter determines the slope begin from fourth knee. There are 4 slopes can be selected. The end
point is determined by fourth knee and noise_gate_ratio.
Vout (db)
Segment1
Segment2
Segment_noise_gate
0
alc_thmax=-6db (REG.)
-6
Start Point
ratio_1=¼ (REG.)
-12
-18
2nd Knee
-24
-30
3rd Knee
-36
ratio_2=½ (REG.)
1st Knee
boost_gain = 12db
-42
Drop_all = 12 + 6 =18db
-48
alc_noise_gate_exp = 6db
-54
4th Knee
-60
noise_gate_ratio=2
(REG.)
-66
-72
-78
-84
boost_gain = 12db (REG.) -90
End Point
-95.625
-90
-84
-78 -72
-66
-60
-54
-48 -42
alc_thnoise = -48db (REG.)
-36
-30
-24
Knee (H/W)
-18
-12
-6
0
Vin (db)
alc_thmax2 = -12db (REG.)
Figure 27. Record DRC Output Curve - 2
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Playback/Recording Mode:
For DAC playback or ADC recording mode, when the input signal exceeds target threshold, the signal
will decrease “DRC/AGC Digital Volume” (0.375dB/step at every zero-crossing) until drop to target
level then keep the digital volume. When input signal is below the target threshold, the signal will step-up
“DRC/AGC Digital Volume” (0.375dB/step every zero-crossing) until return to original level. If want to
return to the target level, need to set the pre-gain to achieve.
Fine tune parameters:
Limiter Threshold: 0 ~ -46.5dB, 1.5dB/step, MX-B7[5:0]
Attack Rate: T=(4*2^n)/sample rate, n = MX-B4[12:8]
Recovery Rate: T=(4*2^n)/sample rate, n = MX-B4[4:0]
Input signal
Target Level
Volume
0dB
Attack Rate
Recovery Rate
Output signal
Figure 28. DRC/AGC for Playback/Recording Mode
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Noise Gate Mode:
The Noise Gate Function is use to reduce the noise floor for DAC path or ADC path. When input signal is
below noise gate level, the input signal will be reduced by DRC/AGC volume in order to suppress the
background noise. The reducing level can be set by register. And when input signal is above noise gate,
the input signal will be boosted to target level.
Fine tune parameters:
Noise Gate Threshold: -36 ~ -82.5dB, 1.5dB/step, MX-B6[4:0]
Noise Gate Attack Rate: T=(4*2^n)/sample rate, n = PR-06[4:0]
Noise Gate Recovery Rate: T=(4*2^n)/sample rate, n = PR-02[12:8]
Reducing Noise Level: 0 ~ 45dB, 3dB/step, MX-B6[15:12]
Input signal
Target Level
Noise Gate
Volume
0dB
Attack Rate
Recovery Rate
Attack Rate
Recovery Rate
Noise Reduction
Output signal
Target Level
Noise Gate
Figure 29. DRC/AGC for Noise Gate Mode
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9.10. SounzRealTM Post-Processing
The Realtek’s SounzRealTM post-processing is composed of:
TruTreble
BassBack
9.11. Equalizer Block
The equalizer block cascades 7 bands of equalizer to each channel to tailor the frequency characteristics
of embedded speaker system according to user preferences and to emulate environment sound. The 7
bands equalizer includes two high pass filters, three band pass filters, one low pass filter and one biquad
filter. One high pass filter cascaded in the front end is used to drop low frequency tone, The tone has a
large amplitude and may damage a mini speaker. The high pass filter can be used to adjust Treble
strength with gain control. One low pass filter with gain control can adjust the Bass strength. Three bands
of band pass filters are used to emulate environment sounds, e.g., ‘Pub’, ‘Live’, ‘Rock’,… etc.. The gain,
center frequency and bandwidth of each filter are all programmable. One biquad filter can switch to
high-pass, low-pass or band-pass filter by register settings.
9.12. Wind Noise Reduction Filter
The wind filter is implemented by a high pass filter equalizer. The wind filter is mainly for ADC
recording used. The cut-off freqnecy of wind filter is programmable and is varied accroding to different
sample rate. The filter is used to remove DC offset at normal condition, and to remove wind noise at
application mode.
There are three wind filters for three ADC filters:
Stereo 1 ADC Wind Filter => MX-D3 & MX-D4
Mono ADC Wind Filter => MX-EC & MX-ED
Stereo 2 ADC Wind Filter => MX-EE & MX-EF
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Wind filter setting procedure (For Stereo 1 ADC Filter):
Step1: Disable wind filter – MX-D3[15]
Step2: Select filter coarse coefficient – MX-D3[14:12] and MX-D3[10:8]
Step3: Select filter fine coefficient – MX-D4[13:8] and MX-D4[5:0]
Step4: Enable wind filter – MX-D3[15]
The following table (Table 13.) is shown the Fc with sample rate selection.
For the formula of Fc calculation is also shown as:
Fc = (Fs * tan-1(a/(2-a))) / π
Where:
Sample rate = 8K/12K/16K (MX-D3[14:12] and [10:8]), a = 2-6 + n * 2-6 (n is MX-D4[13:8] & MX-D4[5:0])
Sample rate = 24K/32K (MX-D3[14:12] and [10:8]), a = 2-7 + n * 2-7 (n is MX-D4[13:8] & MX-D4[5:0])
Sample rate = 44.1K/48L (MX-D3[14:12] and [10:8]), a = 2-8 + n * 2-8 (n is MX-D4[13:8] & MX-D4[5:0])
Sample rate = 88.2K/96L (MX-D3[14:12] and [10:8]), a = 2-9 + n * 2-9 (n is MX-D4[13:8] & MX-D4[5:0])
Sample rate = 176.4K/192L (MX-D3[14:12] and [10:8]), a = 2-10 + n * 2-10 (n is MX-D4[13:8] & MX-D4[5:0])
PR-6E[11:6]
n
000000’b, 0
000001’b, 1
000010’b, 2
000011’b, 3
000100’b, 4
000101’b, 5
000110’b, 6
000111’b, 7
001000’b, 8
001001’b, 9
001010’b, 10
001011’b, 11
001100’b, 12
001101’b, 13
001110’b, 14
001111’b, 15
010000’b, 16
010001’b, 17
010010’b, 18
010011’b, 19
010100’b, 20
010101’b, 21
010110’b, 22
010111’b, 23
011000’b, 24
011001’b, 25
011010’b, 26
011011’b, 27
Table 13. Sample Rate with filter coefficient for Wind Filter
L & R Channel Sample Rate Setting
8K
16K
32K
44.1K
20.0
40.1
39.9
27.4
40.4
80.8
80.2
55.0
61.1
122.2
120.7
82.7
82.1
164.2
161.6
110.5
103.4
206.9
202.8
138.4
125.1
250.2
244.4
166.4
147.1
294.3
286.2
194.5
169.5
339.0
328.4
222.7
192.2
384.4
371.0
251.1
215.2
430.5
413.8
279.5
238.7
477.4
457.0
308.1
262.4
524.9
500.5
336.8
286.6
573.2
544.4
365.6
311.1
622.3
588.6
394.5
336.0
672.1
633.2
423.5
361.3
722.6
678.1
452.6
386.9
773.9
723.3
481.9
413.0
826.0
768.9
511.2
439.4
878.9
814.9
540.7
466.2
932.5
861.2
570.3
493.5
987.0
907.8
600.0
521.1
1042.2
954.9
629.8
549.1
1098.2
1002.2
659.7
577.5
1155.0
1050.0
689.8
606.3
1212.7
1098.1
719.9
635.5
1271.1
1146.6
750.2
665.1
1330.3
1195.5
780.6
695.2
1390.4
1244.7
811.1
42
48K
29.8
59.9
90.0
120.3
150.6
181.1
211.7
242.5
273.3
304.3
335.4
366.6
397.9
429.4
460.9
492.6
524.5
556.4
588.5
620.7
653.0
685.5
718.1
750.8
783.6
816.6
849.6
882.9
Rev. 0.91
ALC5672-VB
Datasheet
PR-6E[11:6]
n
011100’b, 28
011101’b, 29
011110’b, 30
011111’b, 31
100000’b, 32
100001’b, 33
100010’b, 34
100011’b, 35
100100’b, 36
100101’b, 37
100110’b, 38
100111’b, 39
101000’b, 40
101001’b, 41
101010’b, 42
101011’b, 43
101100’b, 44
101101’b, 45
101110’b, 46
101111’b, 47
110000’b, 48
110001’b, 49
110010’b, 50
110011’b, 51
110100’b, 52
110101’b, 53
110110’b, 54
110111’b, 55
111000’b, 56
111001’b, 57
111010’b, 58
111011’b, 59
111100’b, 60
111101’b, 61
111110’b, 62
111111’b, 63
8K
725.6
756.4
787.6
819.3
851.3
883.7
916.6
949.8
983.3
1017.3
1051.6
1086.3
1121.4
1156.8
1192.6
1228.7
1265.1
1301.8
1338.8
1376.1
1413.7
1451.5
1489.6
1528.0
1566.5
1605.3
1644.2
1683.3
1722.5
1761.9
1801.4
1841.0
1880.7
1920.4
1960.2
2000.0
L & R Channel Sample Rate Setting
16K
32K
44.1K
1451.2
1294.3
841.8
1512.9
1344.3
872.5
1575.3
1394.7
903.4
1638.6
1445.4
934.4
1702.7
1496.5
965.5
1767.5
1548.0
996.8
1822.3
1599.9
1028.1
1899.6
1652.2
1059.6
1966.7
1704.9
1091.2
2034.7
1757.9
1122.9
2103.3
1811.4
1154.8
2172.7
1865.2
1186.7
2242.9
1919.5
1218.8
2313.7
1974.1
1251.0
2385.2
2029.1
1283.4
2457.4
2084.6
1315.8
2530.2
2140.4
1348.4
2603.6
2196.6
1381.1
2677.7
2253.3
1414.0
2752.3
2310.3
1447.0
2827.5
2367.7
1480.0
2903.1
2425.5
1513.3
2979.3
2483.8
1546.6
3056.0
2542.4
1580.1
3133.1
2601.5
1613.7
3210.6
2660.9
1647.4
3288.4
2720.8
1681.3
3366.6
2781.0
1715.3
3445.1
2841.7
1749.4
3523.9
2902.7
1783.6
3602.9
2964.2
1818.0
3682.1
3026.1
1852.5
3761.4
3088.3
1887.1
3840.8
3151.0
1921.9
3920.4
3214.1
1956.8
4000.0
3277.5
1991.8
43
48K
916.2
949.7
983.3
1017.0
1050.9
1084.9
1119.0
1153.3
1187.7
1222.2
1256.9
1291.7
1326.6
1361.7
1396.9
1432.2
1467.7
1503.3
1539.0
1574.9
1610.9
1647.1
1683.4
1719.8
1756.4
1793.1
1830.0
1867.0
1904.1
1941.4
1978.8
2016.3
2054.0
2091.9
2129.9
2168.0
Rev. 0.91
ALC5672-VB
Datasheet
9.13. I2C Control Interface
I2C is a 2-wire (SCL/SDA) half-duplex serial communication interface, supporting only slave mode. SCL
is used for clock and SDA is for data. SCL clock supports up to 400KHz rate and SDA data is a open
drain structure. The input has built-in spike filter and can remove less than 50ns spike at SCL and SDA.
9.13.1. Address Setting
Table 14.
(MSB)
0
0
1
Address Setting (0x38h)
BIT
1
1
0
0
(LSB)
R/W
9.13.2. Complete Data Transfer
Data Transfer over I2C Control Interface
2
Figure 30. Data Transfer Over I C Control Interface
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ALC5672-VB
Datasheet
Write WORD Protocol
Table 15. Write WORD Protocol
1
7
S
Device Address
1
1
Wr A
8
1
8
1
8
1
1
Register Address
A
Data Byte High
A
Data Byte Low
A
P
Read WORD Protocol
Table 16. Read WORD Protocol
1
7
S
Device Address
1
1
Wr A
8
1
Register Address
A
7
S
1
Device Address Rd A
S: Start Condition
Slave Address: 7-bit Device Address
8
1
8
Data Byte High
A
Data Byte Low
1
1
NA P
A: 0 for ACK, 1 for NACK
Data Byte: 16-bit Mixer data
: Master-to-Slave
: Slave-to-Master
Wr: 0 for Write Command
Rd: 1 for Read Command
Command Code: 8-bit Register Address
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ALC5672-VB
Datasheet
9.14. GPIO, Interrupt and Jack Detection
The ALC5672 supports six GPIOs – GPIO1/GPIO2/GPIO3/GPIO4/GPIO5/GPIO6. For GPIO function,
the GPIO can be configured to input or output. For input type, the internal circuit can read pin status and
report to register table. For output type, the internal circuit can drive this pin to high or low to control
external device. In GPIO function, the pin polarity can be controlled by register at output type.
MX-C1[0]
MX-C1[3]
MX-C1[1]
MX-C1[4]
GPIO1
High
GPIO2
High
EN_OBUF
Low
EN_OBUF
Low
MX-BF[8]
MX-BF[7]
EN_IBUF
EN_IBUF
MX-C1[2]
MX-C1[5]
MX-C1[6]
MX-C1[9]
MX-C1[7]
MX-C1[10]
GPIO3
High
GPIO4
High
EN_OBUF
Low
EN_OBUF
Low
MX-BF[6]
MX-BF[5]
EN_IBUF
EN_IBUF
MX-C1[8]
MX-C1[11]
MX-C1[12]
MX-C2[0]
MX-C1[13]
MX-C2[1]
GPIO5
High
GPIO6
High
EN_OBUF
Low
Low
MX-
MX-BF[9]
EN_OBUF
BF[10]
EN_IBUF
EN_IBUF
MX-C1[14]
MX-C2[2]
Figure 31. GPIO Function Block
For the jack detection function, there are four GPIOs (GPIO3/4/5/6) can be configured as jack detection
pins and also have JD1 and JD2 can as jack detection pin. For GPIO jack detection pin source selection is
controlled by MX-BB[15:13]. It’s JD status is sta_gpio_jd1 – MX-BF[4]. For JD1, it can detect two ports.
Which JD statuses are sta_jd1_1 – MX-BF[12] & sta_jd1_2 – MX-BF[13]. For JD2, it can detect one port.
Which JD status is sta_jd2 – MX-BF[14].
MX-BB[15:13]
GPIO3
GPIO4
Sta_gpio_jd1
GPIO5
GPIO6
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Rev. 0.91
ALC5672-VB
Datasheet
For IRQ function as shown at Figure 24, the IRQ output source can be selected from JD1 Status, JD2
Status, GPIO JD Status, InLine Command Status and MICBIAS1 Over-Current Status. When either status
is trigged, the GPIO will output a flag as interrupt signal.
MX-BB[15:13]
MX-BD[13]
MX-BD[14]
GPIO3
MX-BD[15]
GPIO4
Sticky Control
GPIO5
GPIO6
MX-BD[7]
MX-BD[8]
MX-BD[9]
Sticky Control
Sta_jd1_1_internal
MX-BD[4]
MX-BD[5]
MX-BD[6]
Sticky Control
Sta_jd1_2_internal
MX-BD[1]
MX-BD[2]
MX-BD[3]
OR Gate
Sticky Control
IRQ
Sta_jd2_internal
MX-BE[11]
MX-BE[13]
MX-BE[15]
Sticky Control
Sta_micbias1_ovcd_internal
MX-BF[0]
MX-BF[1]
MX-BF[3]
Sticky Control
Sta_inline_command_internal
Figure 32. IRQ Function Block
47
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ALC5672-VB
Datasheet
In general, the IRQ output needs to combine with JD function. When JD is trigger, IRQ will output a flag
to host to notice S/W driver. The S/W driver will do some settings by system design. The behavior flow
chard as following:
Initial Settings
(For JD and IRQ)
Device Plug-In
JD Triggered
IRQ Flag Output to Host
S/W Driver Settings
Clear JD Status for Next
JD Trigger
The MICBIAS supports short current detection function. When MICBIAS circuit detects over-current
happen, MICBIAS circuit will generate an over-current flag. The flag can generate an interrupt signal to
notice host and let S/W do follow-up processes.
The jack detect function can be used to turn-on or turn-off the related output ports. When jack detect pin
is trigged, the selected output ports will be turn-on or turn-off. For example on HP and SPK auto switch
when JD is trigger.
Setting procedure:
1. Select JD status source: use sta_jd1_1 as JD source. MX-F8[2:0] = 001’b & MX-F9[11:9] = 001’b
2. Set JD status polarity for HP and SPK
MX-BB[11:10] = 10’b, JD status low to trigger HPO
MX-BB[9:6] = 1111’b, JD status high to trigger SPK
3. When JD status is low, HP_OUT is un-mute and SPK is mute.
When JD status is low go high, HP is mute and SPK is un-mute.
Note: For HP and SPK port switch function, driver need to turn-on DAC to HP path and DAC to SPK
path first.
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ALC5672-VB
Datasheet
9.15. Push Button Detection
The ALC5672 has built-in push button detection circuit inside. It can supports up to three push buttons.
Each button support three behaviors and shows on register (MX-DBh) – one click, double click and hold.
The push button event will also cause an interrupt to IRQ output to notice external host.
Ring2
U
U
C
C
D
MIC
D
R2
R1
R3
Sleeve
Sleeve
Ring
Tip
Ring2
Push Button Resistance
Up button, R2
Center button, R1
Down button, R3
Resistance Range
150 ~ 280 Ohm
0 ~ 50 Ohm
550 ~ 650 Ohm
Recommend Value
220 Ohm
20 Ohm
620 Ohm
Button Behavior
One click
Double click
Hold
One click
Double click
Hold
One click
Double click
Hold
Register Status
MX-DBh[15]
MX-DBh[14]
MX-DBh[13]
MX-DBh[12]
MX-DBh[11]
MX-DBh[10]
MX-DBh[9]
MX-DBh[8]
MX-DBh[7]
Push Button Detection Status:
Button #
Up button
Center button
Down button
49
Rev. 0.91
ALC5672-VB
Datasheet
Push Button Detection Flow Chart:
Initial Settings
(Power-On)
Push Button Trigger
(Press push button)
IRQ Output
(Codec issue a interrupt)
Status?
(Codec driver check codec register
status)
Configuration
(Codec driver set settings by push
button event)
Clear Status for Next
Push Button Trigger
50
Rev. 0.91
ALC5672-VB
Datasheet
9.16. Power Management
ALC5672 detailed Power Management control registers are supported in MX-61h, 62h, 63h, 64h, 65h and
66h. Each particular block will only be active when each bit MX-61h, 62h, 63h, 64h, 65h and 66h is set to
enable.
MX-61
I2S-1 Power
DACL1/R1
Power
I2S-2 Power
DACL2/R2
Power
ADCL/R
Power
MX-62
DAC Digital
Filter
ADC Digital
Filter
DSP Power
MX-63
Analog MBias
Power
Analog Vref
Power
Headphone
Amp Power
LOUT Mixer
Power
MX-64
MIC BST1
Power
MIC BST2
Power
JD Power
MICBIAS1
Power
PLL
Power
MX-65
OUTMIXL
Power
OUTMIXR
Power
RECMIXL
Power
RECMIXR
Power
INLVOL
Power
INRVOL
Power
MX-66
HPMIXL
Power
HPMIXR
Power
Figure 33. Power Management
51
Rev. 0.91
ALC5672-VB
Datasheet
9.17. Gen.3 Voice DSP Function
The on-chip Voice Processor provides microphone beam-forming with voice tracking to allow for
acoustic echo cancellation, far-field pickup, stationary and non-stationary noise suppression, and voice
recognition rate enhancement.
Data Input/Output
Command Control
Data Interface
Control Interface
PLL/Clock Gen
Master Clock
Voice Provessor
Dual-Core DSP
SRAM
ROM
Accelerators
Power Management
VDD / VSS
Acoustic Echo Cancellation:
The voice DSP suppresses echo effectively under all occasions, and the performance of which could be
easily optimized for different types of acoustics set-up and applications for tablet computers. The AEC
performs robustly under prolonged double talk periods and provides a face-to-face like conversation in
full-duplex without any cut-off, drop-out, howling, voice level pumping, and annoying echoes.
52
Rev. 0.91
ALC5672-VB
Datasheet
Noise Suppression:
The advanced noise suppression is specifically designed for tablets to benefit users that invoke voice
communication applications on these devices. Ambient noise pickup is reduced by the advanced
microphone array beam-forming which could run in 2- or 3- microphone configurations. The technology
further reduces both stationary noise and non-stationary noises, and enhances user experiences in video
and voice chats. Noise reduction is available on both downstream and upstream signals and is highly
effectively against hums, fan-noises, tones, background babbles, and a variety of unwanted interferences.
48kHz Stereo Recording with Far-Field Pickup
The vioce DSP provides specific pure 48kHz audio recording with FFP technology. It can suppress
stationary noise for each channel with 24kHz bandwidth. Far-Field Pickup technology is also considered
in this mode for long distance audio catch up with high signal to noise ratio. The dual feature sculpture
the tablet computer to be a real stereo recording device with stationary noise suppression for long distance
range.
Voice Recognition Rate Enhancement
The advanced voice processing could be configured to run in Voice Recognition Rate Enhancement mode
which would perform beam-forming, acoustic echo cancellation and other processing in a way that helps
to improve recognition rates in poor signal-to-noise conditions for the common commercial voice
recognition engines.
Advanced Beam-Forming
The advanced beam-forming algorithm performs Voice Tracking which could follow the incidence angle
of the talkers’ voice and hence reduces background noise pick-up and reverberations. It also allows for
exceptional widened talking angle in handheld mode to accommodate for a wide variety of user holding
positions, and avoids any annoying voice drop-outs and fade-outs.
53
Rev. 0.91
ALC5672-VB
Datasheet
9.18. Multi-Jack Jack Detection Pin (JD1)
The JD1 pin supports up to two ports jack detection. When supports two ports jack detection, the external
pull-high voltage is 3.3V. When supports one ports jack detection, the external pull-high voltage is 1.8V.
The application schematic as shows below:
3.3V
1.8V
VDD
0.5
R
CP1
R
Vt1=1.485V
VDD
VDD
CP2
Port-1
CP2
Vt2=1.95V
Port-2
Vt2=0.9V
Port-1
VDD
R
0.5
R
VDD
CP3
Vt3=2.7V
Mode-0
Mode-1
MX-94h: JD1 Control
Name
reserved
Sel_mode_jd1
Bits
15:2
1:0
Read/Write
R/W
R/W
Reset State Description
0’h
Reserved
0’h
JD1 Mode Control
00’b: Mode-0, two port jack detection
01’b: Mode-1, one port jack detection
Others: Reserved
MX-BFh: JD1 Status
Name
sta_jd1_2
(Port-2)
Bits
13
Read/Write
R
sta_jd1_1
(Port-1)
12
R
Reset State Description
0’h
Status of JD1_2 Jack detection .
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
0’h
Status of JD1_1 Jack detection .
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
54
Rev. 0.9
ALC5672-VB
Datasheet
10. Registers List
ALC5672 register map as shown as following and accessing unimplemented registers, will return a 0.
10.1. Register Map
Type
Reset
Digital
Gain/Volume
Name
S/W Reset
HPOUT
LOUT
IN1
IN1
IN1
IN2
INL/INR
DACL1/R1
DACL2/R2-1
DACL2/R2-2
ADC
ADC
ADC
ADC
Digital Mixer
Speaker
Input Mixer
Output Mixer
Power
Management
ADC
ADC
ADC
ADC
ADC
DAC
DAC
DAC
Voice DSP
Voice DSP
Copy Mode
Table 17. Register Map
Description
S/W Reset & Device ID
Headphone Output Volume & Mute/Un-Mute
Line Output Volume & Mute/Un-Mute
IN1 Control 1
IN1 Control 2
IN1 Control 3
IN2 Mode and Gain Boost Control
INL/INR Volume Control
DACL1/R1 Digital Volume Control
DACL2/R2 Digital Volume Control
DACL2/R2 Digital Mute/Un-Mute Control
Stereo1 ADCL/R Digital Volume & Mute/Un-Mute
Control
Mono ADCL/R Digital Path Volume Control
ADC Boost Gain for DMIC
Stereo2 ADCL/R Digital Volume & Mute/Un-Mute
Control
ADC Boost Gain for DMIC
Stereo2 ADC Digital Mixer Control
Stereo1 ADC Digital Mixer Control
Mono ADC Digital Mixer Control
ADC to DAC Digital Mixer Control
DAC Stereo Digital Mixer Control
DAC Mono Digital Mixer Control
DAC Stereo to Mono Mixer Control
Voice DSP Path Control
Voice DSP Volume Control
ADC/DAC Data Copy Mode Control
Speaker Control 1
RECMIXL Gain Control
RECMIXL Gain & Selection Control
RECMIXR Gain Control
RECMIXR Gain & Selection Control
HPOMIX Gain & Selection Control
OUTMIXL Selection Control
OUTMIXR Selection Control
LOUTMIX Gain & Selection Control
RECMIXL-1
RECMIXL-2
RECMIXR-1
RECMIXR-2
HPOMIX
OUTMIXL
OUTMIXR
LOUTMIX
ManagementI2S & DAC & ADC Power Control
1
ManagementDigital Filter & DSP & SPK Power Control
2
ManagementVREF & MBias & LOUTMIX & HP Power Control
3
55
Register Address
MX-00h
MX-02h
MX-03h
MX-0Ah
MX-0Bh
MX-0Ch
MX-0Eh
MX-0Fh
MX-19h
MX-1Ah
MX-1Bh
Reset State
0x0004’h
0x8888’h
0x8888’h
0x0001’h
0x0827’h
0x0000’h
0x0000’h
0x0808’h
0xAFAF’h
0xAFAF’h
0x0000’h
MX-1Ch
0x2F2F’h
MX-1Dh
MX-1Eh
0x2F2F’h
0x0000’h
MX-1Fh
0x2F2F’h
MX-20h
MX-26h
MX-27h
MX-28h
MX-29h
MX-2Ah
MX-2Bh
MX-2Ch
MX-2Dh
MX-2Eh
MX-2Fh
MX-31h
MX-3Bh
MX-3Ch
MX-3Dh
MX-3Eh
MX-45h
MX-4Fh
MX-52h
MX-53h
0x0000’h
0x7860’h
0x7860’h
0x7871’h
0x8080’h
0x5656’h
0x5454’h
0xAAA0’h
0x0000’h
0x2F2F’h
0x1002’h
0x5F00’h
0x0000’h
0x007F’h
0x0000’h
0x007F’h
0x600F’h
0x0073’h
0x00D3’h
0xF000’h
MX-61h
0x0000’h
MX-62h
0x0000’h
MX-63h
0x00C0’h
Rev. 0.91
ALC5672-VB
Datasheet
Type
PR Register
Digital
Interface
Name
Management4
Management5
Management6
PR Index
PR Data
I2S1 Port Ctrl
I2S2 Port Ctrl
ADC/DAC
Clock
ADC/DAC
HPF
Digital MIC
TDM
Global Clock
Clock
Clock
PLL
PLL
ASRC
ASRC
ASRC
ASRC
ASRC
HP Amp
HP
MICBIAS
JD1
MICBIAS
JD1
ADC EQ
ADC EQ
DAC EQ
DAC EQ
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ
Description
Register Address Reset State
MICBST & MICBIAS & PLL & JD Power Control
MX-64h
0x0000’h
OUTMIX & RECMIX Power Control
MX-65h
0x0000’h
MX-66h
0x0000’h
MX-6Ah
Mx-6Ch
MX-70h
MX-71h
0x0000’h
0x0000’h
0x8000’h
0x8000’h
ADC/DAC Clock Control
MX-73h
0x1114’h
ADC/DAC HPF Control
MX-74h
0x0E00’h
Digital Microphone Control
Digital Microphone Control
TDM Interface Control
TDM Interface Control
TDM Interface Control
DSP Clock Control
Global Clock Control
PLL Control 1
PLL Control 2
ASRC Control 1
ASRC Control 2
ASRC Control 3
ASRC Control 4
ASRC Control 5
HP Output De-Pop Control 1
HP Output De-Pop Control 2
MICBIAS Control
JD1 Control
ADC EQ Control 1
ADC EQ Control 2
DAC EQ Control 1
DAC EQ Control 2
DAC_L EQ (LPF: a1)
DAC_L EQ (LPF: H0)
DAC_R EQ (LPF: a1)
DAC_R EQ (LPF: H0)
DAC_L EQ (BPF2: a1)
DAC_L EQ (BPF2: a2)
DAC_L EQ (BPF2: H0)
DAC_R EQ (BPF2: a1)
DAC_R EQ (BPF2: a2)
DAC_R EQ (BPF2: H0)
DAC_L EQ (BPF3: a1)
DAC_L EQ (BPF3: a2)
DAC_L EQ (BPF3: H0)
DAC_R EQ (BPF3: a1)
DAC_R EQ (BPF3: a2)
MX-75h
MX-76h
MX-77h
MX-78h
MX-79h
MX-7Fh
MX-80h
MX-81h
MX-82h
MX-83h
MX-84h
MX-85h
MX-8Ah
MX-8Ch
MX-8Eh
MX-8Fh
MX-93h
MX-94h
MX-AE
MX-AF
MX-B0h
MX-B1h
PR-A4h
PR-A5h
PR-A6h
PR-A7h
PR-AEh
PR-AFh
PR-B0h
PR-B1h
PR-B2h
PR-B3h
PR-B4h
PR-B5h
PR-B6h
PR-B7h
PR-B8h
0x1505’h
0x0015’h
0x0C00’h
0x4000’h
0x0123’h
0x1100’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0007’h
0x0004’h
0x1100’h
0x0000’h
0x0000h
0x6000’h
0x0000’h
0x6000’h
0x0000’h
0x1C10’h
0x01F4’h
0x1C10’h
0x01F4’h
0xC882’h
0x1C10’h
0x01F4’h
0xC882’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
MICBIAS & OUTVOL & HPOVOL & INVOL Power
Control
PR Register Index
PR Register Data
I2S-1 Interface Control
I2S-2 Interface Control
56
Rev. 0.91
ALC5672-VB
Datasheet
Type
Name
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
Description
DAC_R EQ (BPF3: H0)
DAC_L EQ (BPF4: a1)
DAC_L EQ (BPF4: a2)
DAC_L EQ (BPF4: H0)
DAC_R EQ (BPF4: a1)
DAC_R EQ (BPF4: a2)
DAC_R EQ (BPF4: H0)
DAC_L EQ (HPF1: a1)
DAC_L EQ (HPF1: H0)
DAC_R EQ (HPF1: a1)
DAC_R EQ (HPF1: H0)
DAC_L EQ (HPF2: a1)
DAC_L EQ (HPF2: a2)
DAC_L EQ (HPF2: H0)
DAC_R EQ (HPF2: a1)
DAC_R EQ (HPF2: a2)
DAC_R EQ (HPF2: H0)
DAC_L EQ Pre-Volume Control
DAC_R EQ Pre-Volume Control
DAC_L EQ Post-Volume Control
DAC_R EQ Post-Volume Control
ADC EQ (LPF: a1)
ADC EQ (LPF: H0)
ADC EQ (BPF1: a1)
ADC EQ (BPF1: a2)
ADC EQ (BPF1: H0)
ADC EQ (BPF2: a1)
ADC EQ (BPF2: a2)
ADC EQ (BPF2: H0)
ADC EQ (BPF3: a1)
ADC EQ (BPF3: a2)
ADC EQ (BPF3: H0)
ADC EQ (BPF4: a1)
ADC EQ (BPF4: a2)
ADC EQ (BPF4: H0)
ADC EQ (HPF1: a1)
ADC EQ (HPF1: H0)
ADC EQ Pre-Volume Control
ADC EQ Post-Volume Control
DAC_L Biquad EQ (BPF1: h0-1)
DAC_L Biquad EQ (BPF1: h0-2)
DAC_L Biquad EQ (BPF1: b1-1)
DAC_L Biquad EQ (BPF1: b1-2)
DAC_L Biquad EQ (BPF1: b2-1)
DAC_L Biquad EQ (BPF1: b2-2)
DAC_L Biquad EQ (BPF1: a1-1)
DAC_L Biquad EQ (BPF1: a1-2)
DAC_L Biquad EQ (BPF1: a2-1)
DAC_L Biquad EQ (BPF1: a2-2)
DAC_R Biquad EQ (BPF1: h0-1)
DAC_R Biquad EQ (BPF1: h0-2)
57
Register Address
PR-B9h
PR-BAh
PR-BBh
PR-BCh
PR-BDh
PR-BEh
PR-BFh
PR-C0h
PR-C1h
PR-C2h
PR-C3h
PR-C4h
PR-C5h
PR-C6h
PR-C7h
PR-C8h
PR-C9h
PR-CAh
PR-CBh
PR-CCh
PR-CDh
PR-CEh
PR-CFh
PR-D0h
PR-D1h
PR-D2h
PR-D3h
PR-D4h
PR-D5h
PR-D6h
PR-D7h
PR-D8h
PR-D9h
PR-DAh
PR-DBh
PR-DCh
PR-DDh
PR-E1h
PR-E2h
PR-E5h
PR-E6h
PR-E7h
PR-E8h
PR-E9h
PR-EAh
PR-EBh
PR-ECh
PR-EDh
PR-EEh
PR-EFh
PR-F0h
Reset State
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0x1C10’h
0x01F4’h
0x1C10’h
0x01F4’h
0x2000’h
0x0000’h
0x1FF1’h
0x2000’h
0x0000’h
0x1FF1’h
0x0800’h
0x0800’h
0x0800’h
0x0800’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0xE904’h
0x1C10’h
0x01F4’h
0x1C10’h
0x01F4’h
0x0800’h
0x0800’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
Rev. 0.91
ALC5672-VB
Datasheet
Type
Name
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
EQ-Parameter
DRC/AGC
DRC/AGC
DRC/AGC
DRC/AGC
DRC/AGC
DRC/AGC
DRC/AGC
JD
Jack Detection JD
JD
IRQ
IRQ
IRQ
IRQ
GPIO
GPIO
GPIO
GPIO
SounzRealTM BassBack
Post-Processin TruTreble
g
TruTreble
Stereo1
Stereo1
Mono
Wind Filter
Mono
Stereo2
Stereo2
Description
DAC_R Biquad EQ (BPF1: b1-1)
DAC_R Biquad EQ (BPF1: b1-2)
DAC_R Biquad EQ (BPF1: b2-1)
DAC_R Biquad EQ (BPF1: b2-2)
DAC_R Biquad EQ (BPF1: a1-1)
DAC_R Biquad EQ (BPF1: a1-2)
DAC_R Biquad EQ (BPF1: a2-1)
DAC_R Biquad EQ (BPF1: a2-2)
DRC/AGC Control 1
DRC/AGC Control 2
DRC/AGC Control 3
DRC/AGC Control 4
DRC/AGC Control 5
DRC/AGC Control 6
Jack Detection Control
Jack Detection Control
Jack Detection Control
IRQ Control 1
IRQ Control 2
IRQ Control 3
GPIO Control 1
GPIO Control 2
GPIO Control 3
BassBack Control
TruTreble Control 1
TruTreble Control 2
Stereo1 ADC Wind Filter Control 1
Stereo1 ADC Wind Filter Control 2
Mono ADC Wind Filter Control 1
Mono ADC Wind Filter Control 2
Stereo2 ADC Wind Filter Control 1
Stereo2 ADC Wind Filter Control 2
Soft Volume and ZCD Control 1
SVOL & ZCD SVOL & ZCD
Soft Volume and ZCD Control 2
Inline Command Control 1
InLine
Inline Command Control 2
Command
Inline Command Control 3
Voice DSP Control 1
Voice DSP Control 2
Voice DSP Control 3
Voice DSP
Voice DSP Control 4
Voice DSP Control 5
Voice DSP Control 6
General Control 1
General Control 2
General
Control
General Control 3
ADC/DAC RESET Control
Vendor ID
ID
Vendor ID
58
Register Address
PR-F1h
PR-F2h
PR-F3h
PR-F4h
PR-F5h
PR-F6h
PR-F7h
PR-F8h
MX-B2h
MX-B3h
MX-B4h
MX-B5h
MX-B6h
MX-B7h
MX-BBh
MX-F8h
MX-F9h
MX-BDh
MX-BEh
MX-BFh
MX-C0h
MX-C2h
MX-C3h
MX-CFh
MX-D0h
MX-D1h
MX-D3h
MX-D4h
MX-ECh
MX-EDh
MX-EEh
MX-EFh
MX-D9h
MX-DAh
MX-DBh
MX-DCh
MX-DDh
MX-E0h
MX-E1h
MX-E2h
MX-E3h
MX-E4h
MX-E5h
MX-FAh
MX-FBh
MX-FCh
PR-3D
MX-FEh
Reset State
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x001F’h
0x2206’h
0x1F00’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0013’h
0x0680’h
0x1C17’h
0xAA20’h
0x0000’h
0xAA20’h
0x0000’h
0xAA20’h
0x0000’h
0x0809’h
0x0000’h
0x0001’h
0x0049’h
0x0003’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x0000’h
0x8010’h
0x0033’h
0x0080’h
0x2808’h
0x10EC’h
Rev. 0.91
ALC5672-VB
Datasheet
10.2. MX-00h: S/W Reset & Device ID
Default: 0004’h
Table 18. MX-00h: S/W Reset
Port Name
Bits
Read/Write Reset State Description
15:3
R
0’h
Reserved
Reserved
2:1
R
2’h
Device_id
ALC5672
0
R
0’h
Reserved
Reserved
Note: Writes to this register will reset all registers to their default values.
10.3. MX-02h: Headphone Output Control
Default: 8888’h
Name
mu_hpo_l
Bits
15
Table 19. MX-02h: Headphone Output Control
Read/Write Reset State Description
R/W
1’h
Mute Control for Left Headphone Output Port (HPOL)
0’b: Un-Mute
1’b: Mute
Reserved
14
R
0’h
Reserved
vol_hpol
13:8
R/W
8’h
Left Headphone Channel Volume Control (HPOVOLL)
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
mu_hpo_r
7
R/W
1’h
Mute Control Right Headphone Output Port (HPOR)
0’b: Un-Mute
1’b: Mute
Reserved
6
R
0’h
Reserved
Vol_hpor
5:0
R/W
8’h
Right Headphone Channel Volume Control (HPOVOLR)
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
59
Rev. 0.91
ALC5672-VB
Datasheet
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0
0
12
16
10
-12
32
20
-36
1
1
10.5
17
11
-13.5
33
21
-37.5
2
2
9
18
12
-15
34
22
-39
3
3
7.5
19
13
-16.5
35
23
-40.5
4
4
6
20
14
-18
36
24
-42
5
5
4.5
21
15
-19.5
37
25
-43.5
6
6
3
22
16
-21
38
26
-45
7
7
1.5
23
17
-22.5
39
27
-46.5
8
8
0
24
18
-24
9
9
-1.5
25
19
-25.5
10
A
-3
26
1A
-27
11
B
-4.5
27
1B
-28.5
12
C
-6
28
1C
-30
13
D
-7.5
29
1D
-31.5
14
E
-9
30
1E
-33
15
F
-10.5
31
1F
-34.5
10.4. MX-03h: LINE Output Control
Default: 8888’h
Name
Mu_lout_l
Bits
15
En_dfo1
14
Vol_outl
13:8
Table 20. MX-03h: LINE Output Control
Read/Write Reset State Description
R/W
1’h
Mute Control for Left Line Output Port(LOUTL)
0’b: Un-Mute
1’b: Mute
R/W
0’h
LOUT Differential Mode Control
0’b: Disable (Single-ended mode)
1’b: Enable (Differential mode)
R/W
08’h
Left Output Volume Control (OUTVOLL)
00’h: +12dB
…
08’h: 0dB
…
Mu_lout_r
7
R/W
1’h
Reserved
6
R
0’h
27’h: -46.5dB, with 1.5dB/step
Mute Control for Right Line Output Port (LOUTR)
0’b: Un-Mute
1’b: Mute
Reserved
60
Rev. 0.91
ALC5672-VB
Datasheet
Name
Vol_outr
Bits
5:0
Read/Write
R/W
Reset State Description
08’h
Right Output Volume Control
00’h: +12dB
…
08’h: 0dB
…
27’h: -46.5dB, with 1.5dB/step
Volume Table
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0
0
12
16
10
-12
32
20
-36
1
1
10.5
17
11
-13.5
33
21
-37.5
2
2
9
18
12
-15
34
22
-39
3
3
7.5
19
13
-16.5
35
23
-40.5
4
4
6
20
14
-18
36
24
-42
5
5
4.5
21
15
-19.5
37
25
-43.5
6
6
3
22
16
-21
38
26
-45
7
7
1.5
23
17
-22.5
39
27
-46.5
8
8
0
24
18
-24
9
9
-1.5
25
19
-25.5
10
A
-3
26
1A
-27
11
B
-4.5
27
1B
-28.5
12
C
-6
28
1C
-30
13
D
-7.5
29
1D
-31.5
14
E
-9
30
1E
-33
15
F
-10.5
31
1F
-34.5
61
Rev. 0.91
ALC5672-VB
Datasheet
10.5. MX-0Ah: IN1 Port Control - 1
Default: 0001’h
Name
Sel_bst1
Bits
15:12
reserved
11:3
En_bst1
2
Table 21. MX-0Dh: IN1 Input Control - 1
Read/Write
Reset State Description
R/W
0’h
IN1 Boost Control (BST1)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved
R/W
0’h
Reserved
R/W
0’h
IN1 Port Enable Control
0’b: Disable
1’b: Enable
reserved
1:0
R/W
1’h
Reserved
10.6. MX-0Bh: IN1 Port Control - 2
Default: 0827’h
Name
Reserved
Bits
15:13
Table 22. MX-0Bh: IN1 Input Control - 2
Read/Write
Reset State Description
R
0’h
Reserved
Manual_tri_in1
12
R/W
0’h
Capless_gat_en
11
R/W
1’h
10:8
R/W
0’h
Reserved
7
R/W
1’h
IN1 Port Mode Control
reserved
Reg_mode
Manual Trigger For IN1 Port
0’b: Low trigger
1’b: High trigger
Capless Power Gating with IN1 Control
0’b: Register control
1’b: Auto mode
0’b: Auto mode
1’b: Manual mode
reserved
6:0
R/W
27’h
Reserved
62
Rev. 0.91
ALC5672-VB
Datasheet
10.7. MX-0Ch: IN1 Port Control - 3
Default: 0000’h
Name
Reserved
Bits
15:3
In1_result
2:0
Table 23. MX-0Ch: IN1 Input Control - 3
Read/Write
Reset State Description
R
0’h
Reserved
R
0’h
IN1 Port Final Status
001’b: Type1
010’b: Type2
100’b: Type3
10.8. MX-0Eh: IN2 Input Control
Default: 0000’h
Name
Sel_bst2
Bits
15:12
Reserved
11:8
En_in2_df
7
Table 24. MX-0Eh: IN2 Input Control
Read/Write
Reset State Description
R/W
0’h
IN2 Boost Control (BST2)
0000’b: Bypass
0001’b: +20dB
0010’b: +24dB
0011’b: +30dB
0100’b: +35dB
0101’b: +40dB
0110’b: +44dB
0111’b: +50dB
1000’b: +52dB
Others : Reserved
R/W
0’h
Reserved
R/W
0’h
IN2 Input Mode Control
0’b: Single Ended Mode
1’b: Differential Mode
Reserved
6:0
R
0’h
Reserved
63
Rev. 0.91
ALC5672-VB
Datasheet
10.9. MX-0Fh: INL & INR Volume Control
Default: 0808’h
Name
reserved
Bits
15:13
Vol_inl
12:8
Table 25. MX-0Fh: INL & INR Volume Control
Read/Write
Reset State Description
R
0’h
Reserved
R/W
8’h
INL Channel Volume Control
00’h: +12dB
…
08’h: 0dB
…
Reserved
7:5
R
0’h
Vol_inr
4:0
R/W
8’h
1F’h: -34.5dB, with 1.5dB/step
Reserved
INR Channel Volume Control
00’h: +12dB
…
08’h: 0dB
…
1F’h: -34.5dB, with 1.5dB/step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain
0
0
12
16
10
-12
1
1
10.5
17
11
-13.5
2
2
9
18
12
-15
3
3
7.5
19
13
-16.5
4
4
6
20
14
-18
5
5
4.5
21
15
-19.5
6
6
3
22
16
-21
7
7
1.5
23
17
-22.5
8
8
0
24
18
-24
9
9
-1.5
25
19
-25.5
10
A
-3
26
1A
-27
11
B
-4.5
27
1B
-28.5
12
C
-6
28
1C
-30
13
D
-7.5
29
1D
-31.5
14
E
-9
30
1E
-33
15
F
-10.5
31
1F
-34.5
64
Rev. 0.91
ALC5672-VB
Datasheet
10.10. MX-19h: DACL1/R1 Digital Volume
Default: AFAF’h
Name
vol_dac1_l
Bits
15:8
Table 26. MX-19h: DACL1/R1 Digital Volume
Read/Write Reset State Description
R/W
AF’h
DAC1 Left Channel Digital Volume
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
vol_dac1_r
7:0
R/W
AF’h
DAC1 Right Channel Digital Volume
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
10.11. MX-1Ah: DACL2/R2 Digital Volume
Default: AFAF’h
Name
vol_dac2_l
Bits
15:8
Table 27. MX-1Ah: DACL2/R2 Digital Volume
Read/Write Reset State Description
R/W
AF’h
DAC2 Left Channel Digital Volume
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
vol_dac2_r
7:0
R/W
AF’h
DAC2 Right Channel Digital Volume
00’h: -65.625dB
…
AF’h: 0dB, with 0.375dB/Step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0
0
-65.625
53
35
-45.75
106
6A
-25.875
159
9F
-6
212
D4
1
1
-65.25
54
36
-45.375
107
6B
-25.5
160
A0
-5.625
213
D5
2
2
-64.875
55
37
-45
108
6C
-25.125
161
A1
-5.25
214
D6
3
3
-64.5
56
38
-44.625
109
6D
-24.75
162
A2
-4.875
215
D7
4
4
-64.125
57
39
-44.25
110
6E
-24.375
163
A3
-4.5
216
D8
5
5
-63.75
58
3A
-43.875
111
6F
-24
164
A4
-4.125
217
D9
6
6
-63.375
59
3B
-43.5
112
70
-23.625
165
A5
-3.75
218
DA
7
7
-63
60
3C
-43.125
113
71
-23.25
166
A6
-3.375
219
DB
65
Rev. 0.91
ALC5672-VB
Datasheet
8
8
-62.625
61
3D
-42.75
114
72
-22.875
167
A7
-3
220
DC
9
9
-62.25
62
3E
-42.375
115
73
-22.5
168
A8
-2.625
221
DD
10
A
-61.875
63
3F
-42
116
74
-22.125
169
A9
-2.25
222
DE
11
B
-61.5
64
40
-41.625
117
75
-21.75
170
AA
-1.875
223
DF
12
C
-61.125
65
41
-41.25
118
76
-21.375
171
AB
-1.5
224
E0
13
D
-60.75
66
42
-40.875
119
77
-21
172
AC
-1.125
225
E1
14
E
-60.375
67
43
-40.5
120
78
-20.625
173
AD
-0.75
226
E2
15
F
-60
68
44
-40.125
121
79
-20.25
174
AE
-0.375
227
E3
16
10
-59.625
69
45
-39.75
122
7A
-19.875
175
AF
0
228
E4
17
11
-59.25
70
46
-39.375
123
7B
-19.5
176
B0
229
E5
18
12
-58.875
71
47
-39
124
7C
-19.125
177
B1
230
E6
19
13
-58.5
72
48
-38.625
125
7D
-18.75
178
B2
231
E7
20
14
-58.125
73
49
-38.25
126
7E
-18.375
179
B3
232
E8
21
15
-57.75
74
4A
-37.875
127
7F
-18
180
B4
233
E9
22
16
-57.375
75
4B
-37.5
128
80
-17.625
181
B5
234
EA
23
17
-57
76
4C
-37.125
129
81
-17.25
182
B6
235
EB
24
18
-56.625
77
4D
-36.75
130
82
-16.875
183
B7
236
EC
25
19
-56.25
78
4E
-36.375
131
83
-16.5
184
B8
237
ED
26
1A
-55.875
79
4F
-36
132
84
-16.125
185
B9
238
EE
27
1B
-55.5
80
50
-35.625
133
85
-15.75
186
BA
239
EF
28
1C
-55.125
81
51
-35.25
134
86
-15.375
187
BB
240
F0
29
1D
-54.75
82
52
-34.875
135
87
-15
188
BC
241
F1
30
1E
-54.375
83
53
-34.5
136
88
-14.625
189
BD
242
F2
31
1F
-54
84
54
-34.125
137
89
-14.25
190
BE
243
F3
32
20
-53.625
85
55
-33.75
138
8A
-13.875
191
BF
244
F4
33
21
-53.25
86
56
-33.375
139
8B
-13.5
192
C0
245
F5
34
22
-52.875
87
57
-33
140
8C
-13.125
193
C1
246
F6
35
23
-52.5
88
58
-32.625
141
8D
-12.75
194
C2
247
F7
36
24
-52.125
89
59
-32.25
142
8E
-12.375
195
C3
248
F8
37
25
-51.75
90
5A
-31.875
143
8F
-12
196
C4
249
F9
38
26
-51.375
91
5B
-31.5
144
90
-11.625
197
C5
250
FA
39
27
-51
92
5C
-31.125
145
91
-11.25
198
C6
251
FB
40
28
-50.625
93
5D
-30.75
146
92
-10.875
199
C7
252
FC
41
29
-50.25
94
5E
-30.375
147
93
-10.5
200
C8
253
FD
42
2A
-49.875
95
5F
-30
148
94
-10.125
201
C9
254
FE
43
2B
-49.5
96
60
-29.625
149
95
-9.75
202
CA
255
FF
66
Rev. 0.91
ALC5672-VB
Datasheet
44
2C
-49.125
97
61
-29.25
150
96
-9.375
203
CB
45
2D
-48.75
98
62
-28.875
151
97
-9
204
CC
46
2E
-48.375
99
63
-28.5
152
98
-8.625
205
CD
47
2F
-48
100
64
-28.125
153
99
-8.25
206
CE
48
30
-47.625
101
65
-27.75
154
9A
-7.875
207
CF
49
31
-47.25
102
66
-27.375
155
9B
-7.5
208
D0
50
32
-46.875
103
67
-27
156
9C
-7.125
209
D1
51
33
-46.5
104
68
-26.625
157
9D
-6.75
210
D2
52
34
-46.125
105
69
-26.25
158
9E
-6.375
211
D3
10.12. MX-1Bh: DACL2/R2 Mute/Un-Mute Control
Default: 0000’h
Name
reserved
Mu_dac2_l
Bits
15:14
13
Table 28. MX-1Bh: DACL2/R2 Mute/Un-Mute Control
Read/Write
Reset State Description
R
0’h
Reserved
R/W
0’h
Mute Control for Left DAC2 Volume
0’b: Un-Mute
1’b: Mute
Mu_dac2_r
12
R/W
0’h
Mute Control for Right DAC2 Volume
0’b: Un-Mute
1’b: Mute
reserved
11:7
R
0’h
Reserved
Sel_dacl2
6:4
R/W
1’h
Select DACL2 Data Source
000’b: IF1_DAC2_L
001’b: IF2_DAC_L
010’b: Reserved
011’b: TxDC_DAC_L
Others: Reserved
reserved
3
R
0’h
Reserved
67
Rev. 0.91
ALC5672-VB
Datasheet
Sel_dacr2
2:0
R/W
1’h
Select DACR2 Data Source
000’b: IF1_DAC2_R
001’b: IF2_DAC_R
010’b: Reserved
011’b: TxDC_DAC_R
100’b: TxDP_DAC_L
Others: Reserved
10.13. MX-1Ch: Stereo1 ADC Digital Volume Control
Default: 2F2F’h
Name
Mu_adc_vol_l
Table 29. MX-1Ch: Stereo1 ADC Digital Volume Control
Bits
Read/Write
Reset State Description
15
R/W
0’h
Mute Control for Stereo1 ADC Left Volume Channel
0’b: Un-Mute
1’b: Mute
Ad_gain_l
14:8
R/W
2F’h
Stereo1 ADC Left Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Mu_adc_vol_r
7
R/W
0’h
Mute Control for Stereo1 ADC Right Volume Channel
0’b: Un-Mute
1’b: Mute
Ad_gain_r
6:0
R/W
2F’h
Stereo1 ADC Right Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
68
Rev. 0.91
ALC5672-VB
Datasheet
10.14. MX-1Dh: Mono ADC Digital Volume Control
Default: 2F2F’h
Name
reserved
Bits
15
Mono_ad_gain_l
14:8
Table 30. MX-1Dh: Mono ADC Digital Volume Control
Read/Write
Reset State Description
R
0’h
Reserved
R/W
2F’h
Mono ADC Left Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
reserved
Mono_ad_gain_r
7
R
0’h
Reserved
6:0
R/W
2F’h
Mono ADC Right Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Volume Table:
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
-17.625
-7.875
1.875
11.625
0
0
26
1A
52
34
78
4E
-17.25
-7.5
2.25
12
1
1
27
1B
53
35
79
4F
2
2
-16.875
28
1C
-7.125
54
36
2.625
80
50
12.375
-16.5
-6.75
3
12.75
3
3
29
1D
55
37
81
51
4
4
-16.125
30
1E
-6.375
56
38
3.375
82
52
13.125
-15.75
-6
3.75
13.5
5
5
31
1F
57
39
83
53
-15.375
-5.625
4.125
13.875
6
6
32
20
58
3A
84
54
-15
-5.25
4.5
14.25
7
7
33
21
59
3B
85
55
-14.625
-4.875
4.875
14.625
8
8
34
22
60
3C
86
56
9
9
-14.25
35
23
-4.5
61
3D
5.25
87
57
15
-13.875
-4.125
5.625
15.375
10
A
36
24
62
3E
88
58
-13.5
-3.75
6
15.75
11
B
37
25
63
3F
89
59
-13.125
-3.375
6.375
16.125
12
C
38
26
64
40
90
5A
-12.75
-3
6.75
16.5
13
D
39
27
65
41
91
5B
14
E
-12.375
40
28
-2.625
66
42
7.125
92
5C
16.875
-12
-2.25
7.5
17.25
15
F
41
29
67
43
93
5D
16
10
-11.625
42
2A
-1.875
68
44
7.875
94
5E
17.625
-11.25
-1.5
8.25
18
17
11
43
2B
69
45
95
5F
-10.875
-1.125
8.625
18.375
18
12
44
2C
70
46
96
60
-10.5
-0.75
9
18.75
19
13
45
2D
71
47
97
61
-10.125
-0.375
9.375
19.125
20
14
46
2E
72
48
98
62
21
15
-9.75
47
2F
0
73
49
9.75
99
63
19.5
69
DEC HEX Boost Gain
21.375
104 68
21.75
105 69
106 6A
22.125
22.5
107 6B
108 6C
22.875
23.25
109 6D
23.625
110 6E
24
111 6F
24.375
112 70
113 71
24.75
25.125
114 72
25.5
115 73
25.875
116 74
26.25
117 75
118 76
26.625
27
119 77
120 78
27.375
27.75
121 79
28.125
122 7A
28.5
123 7B
28.875
124 7C
125 7D
29.25
Rev. 0.91
ALC5672-VB
Datasheet
22
23
24
25
16
17
18
19
-9.375
-9
-8.625
-8.25
48
49
50
51
30
31
32
33
0.375
0.75
1.125
1.5
74
75
76
77
4A
4B
4C
4D
10.125
10.5
10.875
11.25
100
101
102
103
64
65
66
67
19.875
20.25
20.625
21
126
127
7E
7F
29.625
30
10.15. MX-1Eh: ADC Digital Boost Gain Control
Default: 0000’h
Name
Stereo1_ad_boost_
Bits
15:14
Table 31. MX-1Eh: ADC Digital Boost Gain Control
Read/Write
Reset State Description
R/W
0’h
Stereo1 ADC Left Channel Digital Boost Gain
gain_l
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
Stereo1_ad_boost_
13:12
R/W
0’h
gain_r
Stereo1 ADC Right Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
Stereo1_ad_comp_
11:10
R/W
0’h
gain
Stereo1 ADC Compensation Gain
00’b: 0dB
01’b: 1dB
10’b: 2dB
11’b: 3dB
Stereo2_ad_boost_
9:8
R/W
0’h
gain_l
Stereo2 ADC Left Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
Stereo2_ad_boost_
gain_r
7:6
R/W
0’h
Stereo2 ADC Right Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
70
Rev. 0.91
ALC5672-VB
Datasheet
Stereo2_ad_comp_
5:4
R/W
0’h
gain
Stereo2 ADC Compensation Gain
00’b: 0dB
01’b: 1dB
10’b: 2dB
11’b: 3dB
reserved
3:0
R/W
0’h
Reserved
10.16. MX-1Fh: Stereo2 ADC Digital Volume Control
Default: 2F2F’h
Name
Mu_adc2_vol_l
Bits
15
Table 32. MX-1Fh: Stereo2 ADC Digital Volume Control
Read/Write
Reset State Description
R/W
0’h
Mute Control for Stereo2 ADC Left Volume Channel
0’b: Un-Mute
1’b: Mute
Ad2_gain_l
14:8
R/W
2F’h
Stereo2 ADC Left Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
Mu_adc2_vol_r
7
R/W
0’h
Mute Control for Stereo2 ADC Right Volume Channel
0’b: Un-Mute
1’b: Mute
Ad2_gain_r
6:0
R/W
2F’h
Stereo2 ADC Right Channel Volume Control
00’h: -17.625dB
…
2F’h: 0dB
…
7F’h: +30dB, with 0.375dB/Step
71
Rev. 0.91
ALC5672-VB
Datasheet
10.17. MX-20h: Mono ADC Digital Boost Gain Control
Default: 0000’h
Table 33. MX-20h: Mono ADC Digital Boost Gain Control
Name
Bits
Read/Write
Reset State Description
mono_ad_boost_ga 15:14
R/W
0’h
Mono ADC Left Channel Digital Boost Gain
in_l
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
mono_ad_boost_ga 13:12
R/W
0’h
in_r
Mono ADC Right Channel Digital Boost Gain
00’b: 0dB
01’b: 12dB
10’b: 24dB
11’b: 36dB
mono_ad_comp_ga 11:10
R/W
0’h
in
Mono ADC Compensation Gain
00’b: 0dB
01’b: 1dB
10’b: 2dB
11’b: 3dB
Reserved
9:0
R
0’h
Reserved
10.18. MX-26h: Stereo2 ADC Digital Mixer Control
Default: 7860’h
Name
Sel_stereo2_lr_mix
Bits
15
mu_stereo2_adcl1
14
mu_stereo2_adcl2
13
sel_stereo2_adc1
12
Table 34. MX-26h: Stereo2 ADC Digital Mixer Control
Read/Write
Reset State Description
R/W
0’h
Mixing Control for Stereo2 ADC Left channel
0’b: L
1’b: L+R
R/W
1’h
Mute Source1 to Stereo2 ADC Left Channel
0’b:UnMute
1’b:Mute
R/W
1’h
Mute Source2 to Stereo2 ADC Left Channel
0’b:UnMute
1’b:Mute
R/W
1’h
Select Stereo2 ADC L/R Channel Source 1
0’b: DAC_MIXL / DAC_MIXR
1’b: ADC1
72
Rev. 0.91
ALC5672-VB
Datasheet
sel_stereo2_adc2
11
R/W
1’h
Reserved
Sel_stereo2_dmic
10
9:8
R/W
R/W
0’h
0’h
reserved
mu_stereo2_adcr1
7
6
R
R/W
0’h
1’h
mu_stereo2_adcr2
5
R/W
1’h
4:0
R
0’h
reserved
Select Stereo2 ADC L/R Channel Source 2
0’b: DAC_MIXL / DAC_MIXR
1’b: DMIC1/DMIC2/DMIC3
Reserved
Select Stereo2 DMIC Source
00’b: DMIC1
01’b: DMIC2
10’b: DMIC3
11’b: Reserved
Reserved
Mute Source1 to Stereo2 ADC Right Channel
0’b:UnMute
1’b:Mute
Mute Source2 to Stereo2 ADC Right Channel
0’b:UnMute
1’b:Mute
reserved
10.19. MX-27h: Stereo1 ADC Digital Mixer Control
Default: 7860’h
Name
reserved
mu_stereo1_adcl1
Bits
15
14
mu_stereo1_adcl2
13
sel_stereo1_adc1
12
sel_stereo1_adc2
11
reserved
Sel_stereo1_dmic
10
9:8
reserved
mu_stereo1_adcr1
7
6
mu_stereo1_adcr2
5
Table 35. MX-27h: Stereo1 ADC Digital Mixer Control
Read/Write
Reset State Description
R
0’h
Reserved
R/W
1’h
Mute Source 1 to Stereo1 ADC Left Channel
0’b:UnMute
1’b:Mute
R/W
1’h
Mute Source 2 to Stereo1 ADC Left Channel
0’b:UnMute
1’b:Mute
R/W
1’h
Select Stereo1 ADC L/R Channel Source 1
0’b: DAC_MIXL / DAC_MIXR
1’b: ADC1
R/W
1’h
Select Stereo1 ADC L/R Channel Source 2
0’b: DAC_MIXL / DAC_MIXR
1’b: DMIC1/DMIC2/DMIC3
R/W
0’h
Reserved
R/W
0’h
Select Stereo1 DMIC Source
00’b: DMIC1
01’b: DMIC2
10’b: DMIC3
11’b: Reserved
R
0’h
Reserved
R/W
1’h
Mute Source 1 to Stereo1 ADC Right Channel
0’b:UnMute
1’b:Mute
R/W
1’h
Mute Source 2 to Stereo1 ADC Right Channel
0’b:UnMute
1’b:Mute
73
Rev. 0.91
ALC5672-VB
Datasheet
reserved
4:0
R
0’h
reserved
10.20. MX-28h: Mono ADC Digital Mixer Control
Default: 7871’h
Name
reserved
mu_mono_adcl1
Bits
15
14
mu_mono_adcl2
13
sel_mono_adcl1
12
sel_mono_adcl2
11
reserved
Sel_mono_dmic_l
10
9:8
reserved
mu_mono_adcr1
7
6
mu_mono_adcr2
5
sel_mono_adcr1
4
sel_mono_adcr2
3
reserved
Sel_mono_dmic_r
2
1:0
Table 36. MX-28h: Mono ADC Digital Mixer Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
1’h
Mute Source 1 to Mono ADC Left channel
0’b:UnMute
1’b:Mute
R/W
1’h
Mute Source 2 to Mono ADC Left channel
0’b:UnMute
1’b:Mute
R/W
1’h
Select Mono ADC Left channel source 1
0’b: Mono_DAC_Mixer_L
1’b: ADC1
R/W
1’h
Select Mono ADC Left channel source 2
0’b: Mono_DAC_Mixer_L
1’b: DMIC1_L or DMIC2_L or DMIC3_L
R/W
0’h
Reserved
R/W
0’h
Select Mono Left Channel DMIC Source
00’b: DMIC1_L
01’b: DMIC2_L
10’b: DMIC3_L
11’b: Reserved
R
0’h
Reserved
R/W
1’h
Mute Source 1 to Mono ADC Right channel
0’b:UnMute
1’b:Mute
R/W
1’h
Mute Source 2 to Mono ADC Right channel
0’b:UnMute
1’b:Mute
R/W
1’h
Select Mono ADC Right channel source 1
0’b: Mono_DAC_Mixer_R
1’b: ADC2
R/W
0’h
Select Mono ADC Right channel source 2
0’b: Mono_DAC_Mixer_R
1’b: DMIC1_R or DMIC2_R or DMIC3_R
R/W
0’h
Reserved
R/W
1’h
Select Mono Right Channel DMIC Source
00’b: DMIC1_R
01’b: DMIC2_R
10’b: DMIC3_R
11’b: Reserved
74
Rev. 0.91
ALC5672-VB
Datasheet
10.21. MX-29h: Stereo ADC to DAC Digital Mixer Control
Default: 8080’h
Table 37. MX-29h: Stereo ADC to DAC Digital Mixer Control
Name
Bits Read/Write Reset State Description
Mu_stereo1_adc_mix 15
R/W
1’h
Mute Stereo1 ADC to DAC1 Left Channel
er_l
0’b:UnMute
1’b:Mute
Mu_dac1_l
14
R/W
0’h
Mute IF1 DAC Left Channel
0’b:UnMute
1’b:Mute
reserved
13:12
R
0’h
Reserved
Sel_dacr1
11:10
R/W
0’h
DACR1 Source Selection
00’b: IF1_DAC1_R
01’b: IF2_DAC_R
10’b: Reserved
11’b: Reserved
Sel_dacl1
9:8
R/W
0’h
DACL1 Source Selection
00’b: IF1_DAC1_L
01’b: IF2_DAC_L
10’b: Reserved
11’b: Reserved
Mu_stereo1_adc_mix
7
R/W
1’h
Mute Stereo1 ADC to DAC1 Right Channel
er_r
0’b:UnMute
1’b:Mute
Mu_dac1_r
6
R/W
0’h
Mute IF1 DAC Right Channel
0’b:UnMute
1’b:Mute
reserved
5:0
R
0’h
reserved
10.22. MX-2Ah: Stereo DAC Digital Mixer Control
Default: 5656’h
Name
Bits
reserved
15
mu_stereo_dacl1_mix 14
l
gain_dacl1_to_stereo
_l
13
mu_stereo_dacl2_mix
l
12
gain_dacl2_to_stereo
_l
11
Table 38. MX-2Ah: Stereo DAC Digital Mixer Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
1’h
Mute Stereo DAC1 Left channel
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for DACL1 to Stereo Left Mixer
0’b: 0dB
1’b: -6dB
R/W
1’h
Mute Stereo DAC2 Left channel
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for DACL2 to Stereo Left Mixer
0’b: 0dB
1’b: -6dB
75
Rev. 0.91
ALC5672-VB
Datasheet
Name
reserved
mu_stereo_dacr1_mi
xl
Bits
10
9
Read/Write
R/W
R/W
gain_dacr1_to_stereo
_l
8
R/W
reserved
mu_stereo_dacr1_mi
xr
7
6
R
R/W
gain_dacr1_to_stereo
_r
5
R/W
mu_stereo_dacr2_mi
xr
4
R/W
gain_dacr2_to_stereo
_r
3
R/W
Reserved
mu_stereo_dacl1_mix
r
2
1
R/W
R/W
gain_dacl1_to_stereo
_r
0
R/W
Reset State Description
1’h
Reserved
1’h
Mute Stereo DAC1 Right channel to Left Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACR1 to Stereo Left Mixer
0’b: 0dB
1’b: -6dB
0’h
reserved
1’h
Mute Stereo DAC1 Right channel
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACR1 to Stereo Right Mixer
0’b: 0dB
1’b: -6dB
1’h
Mute Stereo DAC2 Right channel
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACR2 to Stereo Right Mixer
0’b: 0dB
1’b: -6dB
1’h
Reserved
1’h
Mute Stereo DAC1 Left channel to Right Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACL1 to Stereo Right Mixer
0’b: 0dB
1’b: -6dB
10.23. MX-2Bh: Mono DAC Digital Mixer Control
Default: 5454’h
Name
Bits
reserved
15
mu_mono_dacl1_mix 14
l
gain_mono_l_dacl1
13
mu_mono_dacl2_mix
l
12
gain_mono_l_dacl2
11
Table 39. MX-2Bh: Mono DAC Digital Mixer Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
1’h
Mute DAC1 Left channel to Mono DAC Left Mixer
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for DAC1 Left channel to Mono DAC Left
Mixer
0’b: 0dB
1’b: -6dB
R/W
1’h
Mute DAC2 Left channel to Mono DAC Left Mixer
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for DAC2 Left channel to Mono DAC Left
Mixer
0’b: 0dB
1’b: -6dB
76
Rev. 0.91
ALC5672-VB
Datasheet
Name
Bits
mu_mono_dacr2_mix 10
l
gain_mono_l_dacr2
9
Read/Write
R/W
R/W
reserved
8:7
mu_mono_dacr1_mix 6
r
R
R/W
gain_mono_r_dacr1
5
R/W
mu_mono_dacr2_mix
r
4
R/W
gain_mono_r_dacr2
3
R/W
mu_mono_dacl2_mix
r
2
R/W
gain_mono_r_dacl2
1
R/W
reserved
0
R
Reset State Description
1’h
Mute DAC2 Right channel to Mono DAC Left Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DAC2 Right channel to Mono DAC Left
Mixer
0’b: 0dB
1’b: -6dB
0’h
reserved
1’h
Mute DAC1 Right channel to Mono DAC Right Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DAC1 Right channel to Mono DAC Right
Mixer
0’b: 0dB
1’b: -6dB
1’h
Mute DAC2 Right channel to Mono DAC Right Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DAC2 Right channel to Mono DAC Right
Mixer
0’b: 0dB
1’b: -6dB
1’h
Mute DAC2 Left channel to Mono DAC Right Mixer
0’b:UnMute
1’b:Mute
0’h
Gain Control for DAC2 Left channel to Mono DAC Right
Mixer
0’b: 0dB
1’b: -6dB
0’h
reserved
10.24. MX-2Ch: DAC Digital Mixer Control
Default: AAA0’h
Name
Bits
Mu_stereomixl_to_da 15
cmixl
gain_stereomixl_to_d
acmixl
14
Mu_dacl2_to_dacmix
l
13
gain_dacl2_to_dacmi
xl
12
Table 40. MX-2Ch: DAC Digital Mixer Control
Read/Write Reset State Description
R/W
1’h
Mute Stereo_DAC_Mixer_L to DAC_MIXL
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for Stereo_DAC_Mixer_L to DAC_MIXL
0’b: 0dB
1’b: -6dB
R/W
1’h
Mute DACL2 to DAC_MIXL
0’b:UnMute
1’b:Mute
R/W
0’h
Gain Control for DACL2 to DAC_MIXL
0’b: 0dB
1’b: -6dB
77
Rev. 0.91
ALC5672-VB
Datasheet
Name
Bits
Mu_stereomixr_to_da 11
cmixr
Read/Write
R/W
gain_stereomixr_to_d
acmixr
10
R/W
Mu_dacr2_to_dacmix
r
9
R/W
gain_dacr2_to_dacmi
xr
8
R/W
Mu_dacr2_to_dacmix
l
7
R/W
gain_dacr2_to_dacmi
xl
6
R/W
Mu_dacl2_to_dacmix
r
5
R/W
gain_dacl2_to_dacmi
xr
4
R/W
3:0
R
reserved
Reset State Description
1’h
Mute Stereo_DAC_Mixer_R to DAC_MIXR
0’b:UnMute
1’b:Mute
0’h
Gain Control for Stereo_DAC_Mixer_R to DAC_MIXR
0’b: 0dB
1’b: -6dB
1’h
Mute DACR2 to DAC_MIXR
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACR2 to DAC_MIXR
0’b: 0dB
1’b: -6dB
1’h
Mute DACR2 to DAC_MIXL
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACR2 to DAC_MIXL
0’b: 0dB
1’b: -6dB
1’h
Mute DACL2 to DAC_MIXR
0’b:UnMute
1’b:Mute
0’h
Gain Control for DACL2 to DAC_MIXR
0’b: 0dB
1’b: -6dB
0’h
Reserved
10.25. MX-2Dh: Voice DSP Path Control 1
Default: 0000’h
Name
Sel_rxdp_in
Sel_src_to_rxdp
Reserved
Table 41. MX-2Dh: Voice DSP Path Control 1
Bits Read/Write Reset State Description
15:13
R/W
0’h
RxDP Input Selection
000’b: IF2_DAC_L/R
001’b: IF1_DAC2_L/R
010’b: Stereo1_ADC_Mixer_L/R
011’b: Stereo2_ADC_Mixer_L/R
100’b: Mono_ADC_Mixer_L
101’b: Mono_ADC_Mixer_R
110’b: DACL1/R1 (After EQ/ALC/ SounzRealTM)
111’b: Reserved
12:11
R/W
0’h
Select SRC to RxDP
00’b: Bypass
01’b: /2
10’b: /3
11’b: Reserved
10
R
0’h
Reserved
78
Rev. 0.91
ALC5672-VB
Datasheet
Name
Sel_txdp_data
Bits
9:8
Read/Write
R/W
Sel_txdc_data
7:6
R/W
Sel_src_to_txdp
5:4
R/W
Sel_tdm_txdp_slot
3:2
R/W
Sel_dsp_ul_bypass
1
R/W
Sel_dsp_dl_bypass
0
R/W
Reset State Description
0’h
TxDP Output Data Swap
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
0’h
TxDC Output Data Swap
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
0’h
Select SRC to TxDP
00’b: Bypass (Stereo signal)
01’b: /2 (Mono signal)
10’b: /3 (Mono signal)
11’b: Reserved
0’h
TXDP TDM Channel Slot Selection to Stereo Channel
00’b: Slot 0/1
01’b: Slot 2/3
10’b: Slot 4/5
11’b: Slot 6/7
0’h
Select DSP Uplink Bypass
0’b: Pass DSP
1’b: Bypass DSP
0’h
Select DSP Downlink Bypass
0’b: Pass DSP
1’b: Bypass DSP
10.26. MX-2Eh: Voice DSP Volume Control
Default: 2F2F’h
Name
Reserved
Vol_txdp_l
Bits
15
14:8
Reserved
Vol_txdp_r
7
6:0
Table 42. MX-2Eh: Voice DSP Volume Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
2F’h
Mono ADC left channel digital volume in 0.375 dB step
00’h: -17.625dB
2F’h: 0dB
7F’h: 30dB, 0.375dB/Step
R
0’h
Reserved
R/W
2F’h
Mono ADC right channel digital volume in 0.375 dB step
00’h: -17.625dB
2F’h: 0dB
7F’h: 30dB, 0.375dB/Step
79
Rev. 0.91
ALC5672-VB
Datasheet
10.27. MX-2Fh: Interface DAC/ADC Data Control
Default: 1002’h
Table 43. MX-2Fh: Interface DAC/ADC Data Control
Name
Bits Read/Write Reset State Description
Sel_if1_adc2_data_in 15
R/W
0’h
Select Interface1 ADC2 Data Input
0’b: IF_ADC2
1’b: Reserved
Sel_if2_adc_data_in 14:12
R/W
1’h
Select Interface2 ADC Data Input
000’b: IF_ADC1
001’b: IF_ADC2
010’b: Reserved
011’b: TxDC_DAC
100’b: TxDP_ADC
101’b: Reserved
110’b: Reserved
111’b: Reserved
sel_if2_dac_data
11:10
R/W
0’h
Select Interface2 DAC Data Swap
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
sel_if2_adc_data
9:8
R/W
0’h
Select Interface2 ADC Data Swap
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
reserved
7:0
R
2’h
Reserved
10.28. MX-31h: Speaker Control 1
Default: 5F00’h
Name
sel_spk_l
Bits
15
mu_spk_l
14
sel_spk_r
13
mu_spk_r
12
Table 44. MX-31h: Speaker Control 1
Read/Write Reset State Description
R/W
0’h
Select Speaker Left channel source
0’b: Mono_DAC_MIXL
1’b: Stereo_DAC_MIXL
R/W
1’h
Mute Speaker Left channel data
0’b: UnMute
1’b: Mute
R/W
0’h
Select Speaker Right channel source
0’b: Mono_DAC_MIXR
1’b: Stereo_DAC_MIXR
R/W
1’h
Mute Speaker Right channel data
0’b: UnMute
1’b: Mute
80
Rev. 0.91
ALC5672-VB
Datasheet
Name
Reserved
Bits
11:0
Read/Write
R
Reset State Description
F00’h
Reserved
10.29. MX-3Bh: RECMIXL Control 1
Default: 0000’h
Name
reserved
gain_inl_recmixl
reserved
gain_bst2_recmixl
reserved
Table 45. MX-3Bh: RECMIXL Control 1
Bits Read/Write Reset State Description
15:13
R/W
0’h
Reserved
12:10
R/W
0’h
Gain Control for INL1 to REC Left Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
9:7
R/W
0’h
Reserved
6:4
R/W
0’h
Gain Control for Boost 2 to REC Left Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
3:0
R
0’h
reserved
-6dB
-15dB
-6dB
-15dB
10.30. MX-3Ch: RECMIXL Control 2
Default: 007F’h
Name
gain_bst1_recmixl
reserved
Mu_inl_recmixl
reserved
Mu_bst2_recmixl
reserved
Mu_bst1_recmixl
reserved
Table 46. MX-3Ch: RECMIXL Control 2
Bits Read/Write Reset State Description
15:13
R/W
0’h
Gain Control for Boost 1 to REC Left Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
12:6
R
1’h
Reserved
5
R/W
1’h
INL1 to RECMIXL Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
4
R/W
1’h
Reserved
3
R/W
1’h
MIC BST2 to RECMIXL Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
2
R/W
1’h
Reserved
1
R/W
1’h
MIC BST1 to RECMIXL Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
0
R/W
1’h
Reserved
81
-6dB
-15dB
Rev. 0.91
ALC5672-VB
Datasheet
10.31. MX-3Dh: RECMIXR Control 1
Default: 0000’h
Name
reserved
gain_inr_recmixr
reserved
gain_bst2_recmixr
reserved
Table 47. MX-3Dh: RECMIXR Control 1
Bits Read/Write Reset State Description
15:13
R/W
0’h
Reserved
12:10
R/W
0’h
Gain Control for INR1 to REC Right Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
9:7
R/W
0’h
Reserved
6:4
R/W
0’h
Gain Control for Boost 2 to REC Right Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
3:0
R
0’h
reserved
-6dB
-15dB
-6dB
-15dB
10.32. MX-3Eh: RECMIXR Control 2
Default: 007F’h
Name
gain_bst1_recmixr
reserved
Mu_inr_recmixr
reserved
Mu_bst2_recmixr
reserved
Mu_bst1_recmixr
reserved
Table 48. MX-3Eh: RECMIXR Control 2
Bits Read/Write Reset State Description
15:13
R/W
0’h
Gain Control for Boost 1 to REC Right Mixer
000’b:
0dB
001’b:
-3dB
010’b:
011’b:
-9dB
100’b:
-12dB
101’b:
110’b: -18dB
12:6
R
1’h
Reserved
5
R/W
1’h
INR1 to RECMIXR Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
4
R/W
1’h
Reserved
3
R/W
1’h
MIC BST2 to RECMIXR Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
2
R/W
1’h
Reserved
1
R/W
1’h
MIC BST1 to RECMIXR Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
0
R/W
1’h
Reserved
82
-6dB
-15dB
Rev. 0.91
ALC5672-VB
Datasheet
10.33. MX-45h: HPOMIX Control
Default: E00F’h
Name
reserved
Mu_hpvol_hpo
Bits
15
14
Mu_dac1_hpo
13
En_bst_hp
12
reserved
Mu_inr1_hpmixr
11:4
3
Mu_dacr1_hpomixr
2
Mu_inl1_hpomixl
1
Mu_dacl1_hpomixl
0
Table 49. MX-45h: HPOMIX Control
Read/Write Reset State Description
R
1‘h
Reserved
R/W
1’h
HPOVOL to HPO Mute Control
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
DAC1 to HPO Mute Control
0’b: Un-Mute
1’b: Mute (- dB)
R/W
0’h
HPO Gain Control
0’b: 0dB
1’b: -6dB
R
0’h
Reserved
R/W
1’h
INR to HPMIXR Mute Control
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
DACR1 to HPMIXR Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
R/W
1’h
INL to HPMIXL Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
R/W
1’h
DACL1 to HPMIXL Mute Control
0’b : Un-Mute
1’b: Mute (- dB)
10.34. MX-4Fh: OUTMIXL Control
Default: 0073’h
Name
Reserved
Mu_bst1_outmixl1
Mu_inl_outmixl1
Reserved
Mu_dacl2_outmixl1
Bits
15:6
5
4
3:2
1
Table 50. MX-4Fh: OUTMIXL Control
Read/Write Reset State Description
R
1’h
reserved
R/W
1’h
Mute Control for BST1 to OUTMIXL1
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
Mute Control for INL1 to OUTMIXL1
0’b: Un-Mute
1’b: Mute (- dB)
R
0’h
reserved
R/W
1’h
Mute Control for DACL2 to OUTMIXL1
0’b: Un-Mute
1’b: Mute (- dB)
83
Rev. 0.91
ALC5672-VB
Datasheet
Name
Mu_dacl1_outmixl1
Bits
0
Read/Write
R/W
Reset State Description
1’h
Mute Control for DACL1 to OUTMIXL1
0’b: Un-Mute
1’b: Mute (- dB)
10.35. MX-52h: OUTMIXR Control
Default: 00D3’h
Name
reserved
Mu_bst2_outmixr1
Bits
15:7
6
reserved
Mu_inr_outmixr1
5
4
reserved
Mu_dacr2_outmixr1
3:2
1
Mu_dacr1_outmixr1
0
Table 51. MX-52h: OUTMIXR Control 3
Read/Write Reset State Description
R
1’h
reserved
R/W
1’h
Mute Control for BST2 to OUTMIXR1
0’b: Un-Mute
1’b: Mute (- dB)
R
0’h
reserved
R/W
1’h
Mute Control for INR1 to OUTMIXR1
0’b: Un-Mute
1’b: Mute (- dB)
R
0’h
reserved
R/W
1’h
Mute Control for DACR2 to OUTMIXR1
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
Mute Control for DACR1 to OUTMIXR1
0’b: Un-Mute
1’b: Mute (- dB)
10.36. MX-53h: LOUTMIX Control
Default: F000’h
Name
mu_dacl1_lout1
Bits
15
mu_dacr1_lout1
14
mu_outmixl1_lout1
13
mu_outmixr1_lout1
12
Table 52. MX-53h: LOUTMIX Control
Read/Write Reset State Description
R/W
1’h
Mute DACL1 to LOUT1 Mixer
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
Mute DACR1 to LOUT1 Mixer
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
Mute Output Left Volume 1 to LOUT1 Mixer
0’b: Un-Mute
1’b: Mute (- dB)
R/W
1’h
Mute Output Right Volume 1 to LOUT1 Mixer
0’b: Un-Mute
1’b: Mute (- dB)
84
Rev. 0.91
ALC5672-VB
Datasheet
Name
bst_lout1
Bits
11
Read/Write
R/W
reserved
10:0
R
Reset State Description
0’h
Gain Control for ALL path to LOUT1 Mixer
0’b: 0dB
1’b: -6dB
0’h
Reserved
10.37. MX-61h: Power Management Control 1
Default: 0000’h
Name
En_i2s1
Bits
15
En_i2s2
14
reserved
Pow_dac_l_1
13
12
Pow_dac_r_1
11
reserved
Pow_dac_l_2
10:8
7
Pow_dac_r_2
6
reserved
Pow_adc_l
5:3
2
Pow_adc_r
1
reserved
0
Table 53. MX-61h: Power Management Control 1
Read/Write Reset State Description
R/W
0’h
I2S1 Digital Interface Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
I2S2 Digital Interface Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Reserved
R/W
0’h
Analog DACL1 Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Analog DACR1 Power Control
0’b: Power Down
1’b: Power On
R
0’h
Reserved
R/W
0’h
Analog DACL2 Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Analog DACR2 Power Control
0’b: Power Down
1’b: Power On
R
0’h
Reserved
R/W
0’h
Analog ADCL Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Analog ADCR Power Control
0’b: Power Down
1’b: Power On
R
0’h
Reserved
85
Rev. 0.91
ALC5672-VB
Datasheet
10.38. MX-62h: Power Management Control 2
Default: 0000’h
Name
Bits
Pow_adc_stereo_filte 15
r
Pow_adc_monol_filte
r
14
Pow_adc_monor_filte
r
13
Pow_i2s_dsp
12
pow_dac_stereo1_filt
er
11
pow_dac_monol_filte
r
10
pow_dac_monor_filte
r
9
pow_adc_stereo2_filt
er
8
Pow_spk
7
reserved
6:0
Table 54. MX-62h: Power Management Control 2
Read/Write Reset State Description
R/W
0’h
Stereo1 ADC Digital Filter Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Mono ADC_L Digital Filter Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Mono ADC_R Digital Filter Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
I2S Interface for DSP Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
Power on DAC stereo1 filter
0’b: Power Down
1’b: Power On
R/W
0’h
Power on DAC mono left filter
0’b: Power Down
1’b: Power On
R/W
0’h
Power on DAC mono right filter
0’b: Power Down
1’b: Power On
R/W
0’h
Power on ADC stereo2 filter
0’b: Power Down
1’b: Power On
R/W
0’h
Power on Speaker
0’b: Power down
1’b: Power on
R
0’h
Reserved
10.39. MX-63h: Power Management Control 3
Default: 00C0’h
Name
Pow_vref1
Bits
15
En_fastb1
14
Table 55. MX-63h: Power Management Control 3
Read/Write Reset State Description
R/W
0’h
VREF1 Power Control
0’b: Power Down
1’b: Power On
R/W
0’h
VREF1 Fast Mode Control
0’b: Fast VREF
1’b: Slow VREF, (For good analog performance)
86
Rev. 0.91
ALC5672-VB
Datasheet
Name
Pow_main_bias
Bits
13
Read/Write
R/W
Pow_lout
12
R/W
Pow_bg_bias
11
R/W
reserved
En_l_hp
10:8
7
R
R/W
En_r_hp
6
R/W
En_amp_hp
5
R/W
Pow_vref2
4
R/W
En_fastb2
3
R/W
Dvo_ldo
2:0
R/W
Reset State Description
0’h
MBIAS Power Control
0’b: Power Down
1’b: Power On
0’h
LOUTMIX Power Control
0’b: Power Down
1’b: Power On
0’h
MBIAS Bandgap Power Control
0’b: Power Down
1’b: Power On
0’h
Reserved
1’h
Left Headphone Amp Power Control
0’b: Power Down
1’b: Power On
1’h
Right Headphone Amp Power Control
0’b: Power Down
1’b: Power On
0’h
Improve HP Amp Driving
0’b: Disable
1’b: Enable
0’h
VREF2 Power Control
0’b: Power Down
1’b: Power On
0’h
VREF2 Fast Mode Control
0’b: Fast VREF
1’b: Slow VREF, (For good analog performance)
3’h
Selection of the LDO output
000’b: Reserved
001’b: Reserved
010’b: 1.0V
011’b: 1.2V
100’b: 1.25V
101’b: 1.3V
110’b: 1.35V
111’b: 1.4V
10.40. MX-64h: Power Management Control 4
Default: 0000’h
Name
Pow_bst1_1
Bits
15
reserved
Pow_bst2_1
14
13
Table 56. MX-64h: Power Management Control 4
Read/Write Reset State Description
R/W
0’h
MIC BST1 Power Control 1
0’b: Power Down
1’b: Power On
R/W
0’h
reserved
R/W
0’h
MIC BST2 Power Control 1
0’b: Power Down
1’b: Power On
87
Rev. 0.91
ALC5672-VB
Datasheet
Name
reserved
Pow_micbias1_1
Bits
12
11
Read/Write
R/W
R/W
reserved
Pow_pll
10
9
R/W
R/W
reserved
Pow_bst1_2
8:7
6
R
R/W
reserved
Pow_bst2_2
5
4
R
R/W
reserved
Pow_jd1
3
2
R
R/W
Pow_jd2
1
R/W
reserved
0
R
Reset State Description
0’h
reserved
0’h
MICBIAS1 Power Control 1
0’b: Power Down
1’b: Power On
0’h
reserved
0’h
PLL Power Control
0’b: Power Down
1’b: Power On
0’h
Reserved
0’h
MIC BST1 Power Control 2
0’b: Power Down
1’b: Power On
0’h
Reserved
0’h
MIC BST2 Power Control 2
0’b: Power Down
1’b: Power On
0’h
Reserved
0’h
JD1 Power Control
0’b: Power Down
1’b: Power On
0’h
JD2 Power Control
0’b: Power Down
1’b: Power On
0’h
Reserved
10.41. MX-65h: Power Management Control 5
Default: 0000’h
Name
Pow_outmixl
Pow_outmixr
reserved
Pow_recmixl
Pow_recmixr
reserved
Table 57. MX-65h: Power Management Control 5
Bits Read/Write Reset State Description
15
R/W
0’h
OUTMIXL & VOL Power Control
0’b: Power Down
1’b: Power On
14
R/W
0’h
OUTMIXR & VOL Power Control
0’b: Power Down
1’b: Power On
13:12
R
0’h
Reserved
11
R/W
0’h
RECMIXL Power Control
0’b: Power Down
1’b: Power On
10
R/W
0’h
RECMIXR Power Control
0’b: Power Down
1’b: Power On
9:0
R
0’h
Reserved
88
Rev. 0.91
ALC5672-VB
Datasheet
10.42. MX-66h: Power Management Control 6
Default: 0000’h
Name
reserved
Pow_hpovoll
Pow_hpovolr
Pow_inlvol
Pow_inrvol
reserved
Pow_mic_in_det
reserved
Pow_micbias1_2
Table 58. MX-66h: Power Management Control 6
Bits Read/Write Reset State Description
15:12
R
0’h
Reserved
11
R/W
0’h
HPMIXL & VOL Power Control
0’b: Power Down
1’b: Power On
10
R/W
0’h
HPMIXR & VOL Power Control
0’b: Power Down
1’b: Power On
9
R/W
0’h
INLVOL Power Control
0’b: Power Down
1’b: Power On
8
R/W
0’h
INRVOL Power Control
0’b: Power Down
1’b: Power On
7:6
R
0’h
Reserved
5
R/W
0’h
MIC_IN_DET Power Control
0’b: Power Down
1’b: Power On
4:1
R
0’h
Reserved
0
R/W
0’h
MICBIAS1 Power Control 2
0’b: Power Down
1’b: Power On
10.43. MX-6Ah: Private Register Index
Default: 0000’h
Name
reserved
Pr_index
Bits
15:8
7:0
Table 59. MX-6Ah: Private Register Index
Read/Write Reset State Description
R
0’h
reserved
R/W
0’h
PR Register Index
10.44. MX-6Ch: Private Register Data
Default: 0000’h
Name
Pr_data
Bits
15:0
Table 60. MX-6Ch: Private Register Data
Read/Write Reset State Description
R/W
0’h
PR Register Data
89
Rev. 0.91
ALC5672-VB
Datasheet
10.45. MX-70h: I2S1 Digital Interface Control
Default: 8000’h
Name
Sel_i2s1_ms
reserved
en_i2s1_out_comp
en_i2s1_in_comp
Inv_i2s1_bclk
reserved
sel_i2s1_len
sel_i2s1_format
Table61. MX-70h: I2S1 Digital Interface Control
Bits Read/Write Reset State Description
15
R/W
1’h
I2S1 Digital Interface Mode Control
0’b: Master Mode
1’b: Slave Mode
14:12
R
0’h
Reserved
11:10
R/W
0’h
I2S1 Output Data Compress (For ADCDAT1 Output)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
9:8
R/W
0’h
I2S1 Input Data Compress (For DACDAT1 Input)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
7
R/W
0’h
I2S1 BCLK Polarity Control
0’b: Normal
1’b: Invert
6:4
R
0’h
Reserved
3:2
R/W
0’h
I2S1 Data Length Selection
00’b: 16 bits
01’b: 20 bits
10’b: 24 bits
11’b: 8 bits
1:0
R/W
0’h
I2S1 PCM Data Format Selection
00’b: I2S format
01’b: Left justified
10’b: PCM Mode A (LRCK One Plus at Master Mode)
11’b: PCM Mode B (LRCK One Plus at Master Mode)
10.46. MX-71h: I2S2 Digital Interface Control
Default: 8000’h
Name
Sel_i2s2_ms
reserved
Table 61. MX-71h: I2S2 Digital Interface Control
Read/Write Reset State Description
R/W
1’h
I2S2 Digital Interface Mode Control
0’b: Master Mode
1’b: Slave Mode
14:12
R
0’h
Reserved
Bits
15
90
Rev. 0.91
ALC5672-VB
Datasheet
Name
en_i2s2_out_comp
en_i2s2_in_comp
Bits Read/Write
11:10
R/W
9:8
R/W
7
R/W
reserved
sel_i2s2_len
6:4
3:2
R
R/W
sel_i2s2_format
1:0
R/W
inv_i2s2_bclk
Reset State Description
0’h
I2S2 Output Data Compress (For ADCDAT2 Output)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
0’h
I2S2 Input Data Compress (For DACDAT2 Input)
00’b: OFF
01’b: µ law
10’b: A law
11’b: Reserved
0’h
I2S2 BCLK Polarity Control
0’b: Normal
1’b: Invert
0’h
Reserved
0’h
I2S2 Data Length Selection
00’b: 16 bits
01’b: 20 bits
10’b: 24 bits
11’b: 8bits
0’h
I2S2 PCM Data Format Selection
00’b: I2S format
01’b: Left justified
10’b: PCM Mode A (LRCK One Plus at Master Mode)
11’b: PCM Mode B (LRCK One Plus at Master Mode)
10.47. MX-73h: ADC/DAC Clock Control
Default: 1114’h
Name
reserved
sel_i2s_pre_div1
sel_i2s_bclk_ms2
Table 62. MX-73h: ADC/DAC Clock Control
Bits Read/Write Reset State Description
Reserved
15
R
0’h
14:12
R/W
1’h
I2S Clock Pre-Divider 1
000’b: ÷ 1
001’b: ÷ 2
010’b: ÷ 3
011’b: ÷ 4
100’b: ÷ 6
101’b: ÷ 8
110’b: ÷ 12
111’b: ÷ 16
I2S2 Master Mode Clock Relative of BCLK and LRCK
11
R/W
0’h
0’b: 16Bits (32FS)
1’b: 32Bits (64FS)
91
Rev. 0.91
ALC5672-VB
Datasheet
Name
sel_i2s_pre_div2
Bits
10:8
Read/Write
R/W
reserved
sel_dac_osr
7:4
3:2
R/W
R/W
sel_adc_osr
1:0
R/W
Reset State Description
1’h
I2S Pre-Divider 2
000’b: ÷ 1
001’b: ÷ 2
010’b: ÷ 3
011’b: ÷ 4
100’b: ÷ 6
101’b: ÷ 8
110’b: ÷ 12
111’b: ÷ 16
Reserved
1’h
1’h
Stereo DAC Over Sample Rate Select
00’b: 128Fs
01’b: 64Fs
10’b: 32Fs
11’b: Reserved
0’h
Stereo ADC Over Sample Rate Select
00’b: 128Fs
01’b: 64Fs
10’b: 32Fs
11’b: Reserved
10.48. MX-74h: ADC/DAC HPF Control
Default: 0E00’h
Name
reserved
Dehpf_en
Adhpf_en
Mono_adhpf_en
Reserved
Table 63. MX-74h: ADC/DAC HPF Control
Bits Read/Write Reset State Description
15:12
R
0’h
Reserved
11
R/W
1’h
Enable Stereo/Mono DAC High Pass Filter
0’b: Disable
1’b: Enable
10
R/W
1’h
Enable Stereo1/2 ADC High Pass Filter
0’b: Disable
1’b: Enable
9
R/W
1’h
Enable Mono ADC High Pass Filter
0’b: Disable
1’b: Enable
8:0
R
0’h
Reserved
92
Rev. 0.91
ALC5672-VB
Datasheet
10.49. MX-75h: Digital Microphone Control 1
Default: 1505’h
Name
en_dmic1
Bits
15
en_dmic2
14
sel_dmic_l_edge_ster
eo1
13
sel_dmic_r_edge_ster
eo1
12
reserved
Dmic2_data_pin_shar
e
11
10
sel_dmic_l_edge_ster
eo2
9
sel_dmic_r_edge_ster
eo2
8
sel_dmic_clk
7:5
en_dmic3
4
sel_dmic_l_edge_mo
no
3
sel_dmic_r_edge_mo
no
2
Table 64. MX-75h: Digital Microphone Control 1
Read/Write Reset State Description
R/W
0’h
Enable DMIC1 Interface
0’b: Disable
1’b: Enable (Output DMIC clock)
R/W
0’h
Enable DMIC2 Interface
0’b: Disable
1’b: Enable (Output DMIC clock)
R/W
0’h
Stereo1 ADC Filter DMIC Left Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
Stereo1 ADC Filter DMIC Right Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
0’h
Reserved
R/W
1’h
Select the Pin share of DMIC2_DATA
0’b:GPIO8
1’b:IN3N
R/W
0’h
Stereo2 ADC Filter DMIC Left Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
Stereo2 ADC Filter DMIC Right Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
0’h
DMIC Clock Rate Control
000’b: 256*fs/2
001’b: 256*fs/3
010’b: 256*fs/4
011’b: 256*fs/6
100’b: 256*fs/8
101’b: 256*fs/12
R/W
0’h
Enable DMIC3 Interface
0’b: Disable
1’b: Enable (Output DMIC clock)
R/W
0’h
Mono ADC Filter DMIC Left Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
Mono ADC Filter DMIC Right Channel
(Synchronous Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
93
Source Control
Source Control
Source Control
Source Control
Source Control
Source Control
Rev. 0.91
ALC5672-VB
Datasheet
Name
dmic1_data_pin_shar
e
Bits
1:0
Read/Write
R/W
Reset State Description
1’h
Select the Pin share of DMIC1_DATA
00’b: GPIO6
01’b: IN2P
10’b: Reserved
11’b: Reserved
10.50. MX-76h: Digital Microphone Control 2
Default: 0015’h
Name
Bits
Reserved
15:8
Dmic3_data_pin_shar 7:6
e
sel_dmic3_lpf_l_edge
5
sel_dmic3_lpf_r_edg
e
4
sel_dmic2_lpf_l_edge
3
sel_dmic2_lpf_r_edg
e
2
sel_dmic1_lpf_l_edge
1
sel_dmic1_lpf_r_edg
e
0
Table 65. MX-76h: Digital Microphone Control 2
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
Select the Pin share of DMIC3_DATA
00’b: Reserved
01’b: Reserved
10’b: GPIO5 (DACDAT2)
11’b: Reserved
R/W
0’h
DMIC3 Data Left Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
DMIC3 Data Right Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
0’h
DMIC2 Data Left Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
DMIC2 Data Right Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
0’h
DMIC1 Data Left Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
R/W
1’h
DMIC1 Data Right Channel Source Control (Asynchronous
Mode)
0’b: Latch from falling edge
1’b: Latch from rising edge
94
Rev. 0.91
ALC5672-VB
Datasheet
10.51. MX-77h: TDM Interface Control 1
Default: 0C00’h
Name
reserved
mode_sel
Tdmslot_sel
Channel_length
rx_adc_data_sel
reserved
sel_i2s_rx_ch2
sel_i2s_rx_ch4
sel_i2s_rx_ch6
sel_i2s_rx_ch8
Table 66. MX-77h: TDM Interface Control 1
Bits Read/Write Reset State Description
15
R/W
0’h
Reserved
14
R/W
0’h
I2S / TDM Mode Control
0’b: Normal I2S Mode
1’b: TDM Mode
13:12
R/W
0’h
TDM Channel Number Select
00’b: 2ch
01’b: 4ch
10’b: 6ch
11’b: 8ch
TDM Channel Length
11:10
R/W
3’h
00’b: 16bit (For Slave Mode and Master Mode)
01’b: 20bit (For Slave Mode)
10’b: 24bit (For Slave Mode)
11’b: 32bit (For Slave Mode and Master Mode)
9
R/W
0’h
ADC Data to ADCDAT Data Location
0’b: 1L/1R/2L/2R/3L/3R/4L/4R
1’b: 2L/2R/1L/1R/4L/4R/3L/3R
8
R
0’h
Reserved
7:6
R/W
0’h
Data Swap for Slot0/1 in ADCDAT1
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
5:4
R/W
0’h
Data Swap for Slot2/3 in ADCDAT1
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
3:2
R/W
0’h
Data Swap for Slot4/5 in ADCDAT1
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
1:0
R/W
0’h
Data Swap for Slot6/7 in ADCDAT1
00’b: L/R
01’b: R/L
10’b: L/L
11’b: R/R
95
Rev. 0.91
ALC5672-VB
Datasheet
10.52. MX-78h: TDM Interface Control 2
Default: 4000’h
Table 67. MX-78h: TDM Interface Control 2
Name
Bits Read/Write Reset State Description
sel_i2s_lrck_polarity
15
R/W
0’h
TDM Interface LRCK Polarity Inverter
0’b: Normal
1’b: Invert
reserved
14:12
R/W
4’h
Reserved
lrck_pulse_sel
11
R/W
0’h
LRCK Pulse Width Select (Master Mode Only)
0’b: One BCLK width
1’b: One channel slot width
reserved
10:8
R/W
0’h
Reserved
mute_tdm2_outl
7
R/W
0’h
IF1_ADC1 Left Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm2_outr
6
R/W
0’h
IF1_ADC1 Right Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm4_outl
5
R/W
0’h
IF1_ADC2 Left Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm4_outr
4
R/W
0’h
IF1_ADC2 Right Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm6_outl
3
R/W
0’h
IF1_ADC3 Left Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm6_outr
2
R/W
0’h
IF1_ADC3 Right Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm8_outl
1
R/W
0’h
IF1_ADC4 Left Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
mute_tdm8_outr
0
R/W
0’h
IF1_ADC4 Right Data Mute/Un-mute Control
0’b : Un-Mute
1’b : Mute
96
Rev. 0.91
ALC5672-VB
Datasheet
10.53. MX-79h: TDM Interface Control 3
Default: 0123’h
Name
Reserved
sel_i2s_tx_l_ch2
Reserved
sel_i2s_tx_r_ch2
Reserved
sel_i2s_tx_l_ch4
Reserved
sel_i2s_tx_r_ch4
Table 68. MX-79h: TDM Interface Control 3
Bits Read/Write Reset State Description
15
R
0’h
Reserved
14:12
R/W
0’h
IF1_DAC1_L Data Selection
000’b: Slot0
001’b: Slot1
010’b: Slot2
011’b: Slot3
100’b: Slot4
101’b: Slot5
110’b: Slot6
111’b: Slot7
11
R
0’h
Reserved
10:8
R/W
1’h
IF1_DAC1_R Data Selection
000’b: Slot0
001’b: Slot1
010’b: Slot2
011’b: Slot3
100’b: Slot4
101’b: Slot5
110’b: Slot6
111’b: Slot7
7
R
0’h
Reserved
IF1_DAC2_L Data Selection
6:4
R/W
2’h
000’b: Slot0
001’b: Slot1
010’b: Slot2
011’b: Slot3
100’b: Slot4
101’b: Slot5
110’b: Slot6
111’b: Slot7
3
R
0’h
Reserved
2:0
R/W
3’h
IF1_DAC2_R Data Selection
000’b: Slot0
001’b: Slot1
010’b: Slot2
011’b: Slot3
100’b: Slot4
101’b: Slot5
110’b: Slot6
111’b: Slot7
97
Rev. 0.91
ALC5672-VB
Datasheet
10.54. MX-7Fh: Clock Control 1
Default: 1100’h
Name
Reserved
sel_dsp_asrc0
Bits
15:4
3:0
Table 69. MX-7Fh: Clock Control 1
Read/Write Reset State Description
R
110’h
Reserved
R/W
0’h
Select the Clock Source for DSP
0000’b: clk_sys
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
10.55. MX-80h: Global Clock Control
Default: 0000’h
Name
sel_sysclk1
sel_pll_sour
reserved
sel_pll_pre_div
reserved
Table 70. MX-80h: Global Clock Control
Bits Read/Write Reset State Description
15:14
R/W
0’h
System Clock Source MUX Control
00’b: MCLK
01’b: PLL
10’b: Internal Clock
11’b: Reserved
13:11
R/W
0’h
PLL Source Selection
000’b: From MCLK
001’b: From BCLK1
010’b: From BCLK2
Others: Reserved
10:4
R
0’h
Reserved
3
R/W
0’h
PLL Pre-Divider
0’b: ÷ 1
1’b: ÷ 2
2:0
R
0’h
Reserved
98
Rev. 0.91
ALC5672-VB
Datasheet
10.56. MX-81h: PLL Control 1
Default: 0000’h
Name
Pll_n_code
Bits
15:7
Reserved
Pll_k_code
6:5
4:0
Table 71. MX-81h: PLL Control 1
Read/Write Reset State Description
R/W
0’h
PLL N[8:0] Code
000000000’b: Div 2
000000001’b: Div 3
…
111111111’b: Div 513
R
0’h
Reserved
R/W
0’h
PLL K[4:0] Code
00000’b: Div 2
00001’b: Div 3
…
11111’b: Div 33
10.57. MX-82h: PLL Control 2
Default: 0000’h
Name
Pll_m_code
Pll_m_bypass
Reserved
Table 72. MX-82h: PLL Control 2
Bits Read/Write Reset State Description
15:12
R/W
0’h
PLL M[3:0] Code
0000’b: Div 2
0001’b: Div 3
…
1111’b: Div 17
11
R/W
0’h
Bypass PLL M Code
0’b : No bypass
1’b : Bypass
10:0
R
0’h
Reserved
99
Rev. 0.91
ALC5672-VB
Datasheet
10.58. MX-83h: ASRC Control 1
Default: 0000’h
Table 73. MX-83h: ASRC Control 1
Name
Bits Read/Write Reset State Description
Reserved
15:13
R
0’h
Reserved
En_i2s2_asrc
12
R/W
0’h
Enable I2S2 ASRC Function
0’b: Disable
1’b: Enable
En_i2s1_asrc
11
R/W
0’h
Enable I2S1 ASRC Function
0’b: Disable
1’b: Enable
Sel_stereo_dac_mode 10
R/W
0’h
Enable DAC ASRC for Stereo DAC
0’b : Disable
1’b : Enable
Sel_mono_dac_l_mo
9
R/W
0’h
Enable DAC ASRC for mono left path
de
0’b : Disable
1’b : Enable
Sel_mono_dac_r_mo
8
R/W
0’h
Enable DAC ASRC for mono right path
de
0’b : Disable
1’b : Enable
en_dmic_asrc_stereo
7
R/W
0’h
Enable DMIC ASRC for stereo1 path
1
0’b : Disable
1’b : Enable
en_dmic_asrc_stereo
6
R/W
0’h
Enable DMIC ASRC for stereo2 path
2
0’b : Disable
1’b : Enable
en_dmic_asrc_monol
5
R/W
0’h
Enable DMIC ASRC for mono left path
0’b : Disable
1’b : Enable
en_dmic_asrc_monor
4
R/W
0’h
Enable DMIC ASRC for mono right path
0’b : Disable
1’b : Enable
en_adc_asrc_stereo1
3
R/W
0’h
Enable ADC ASRC for stereo1 path
0’b : Disable
1’b : Enable
en_adc_asrc_stereo2
2
R/W
0’h
Enable ADC ASRC for stereo2 path
0’b : Disable
1’b : Enable
en_adc_asrc_monol
1
R/W
0’h
Enable ADC ASRC for mono left path
0’b : Disable
1’b : Enable
en_adc_asrc_monor
0
R/W
0’h
Enable ADC ASRC for mono right path
0’b : Disable
1’b : Enable
100
Rev. 0.91
ALC5672-VB
Datasheet
10.59. MX-84h: ASRC Control 2
Default: 0000’h
Table 74. MX-84h: ASRC Control 2
Name
Bits Read/Write Reset State Description
sel_da_filter_stereo_a 15:12
R/W
0’h
Select the ASRC Clock Source for DA Stereo Filter
src
0000’b : CLK_sys
0001’b : clk_i2s1_asrc
0010’b : clk_i2s2_asrc
0011’b : Reserved
0100’b : Reserved
0101’b : clk_sys2
Others: Reserved
Select the ASRC Clock Source for DA Mono Left Filter
sel_da_filter_monol_ 11:8
R/W
0’h
0000’b: clk_sysy_div_out
asrc
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
Select the ASRC Clock Source for DA Mono Right Filter
sel_da_filter_monor_ 7:4
R/W
0’h
0000’b: clk_sysy_div_out
asrc
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
Select the ASRC Clock Source for AD Stereo1 Filter
sel_ad_filter_stereo1_ 3:0
R/W
0’h
0000’b: clk_sysy_div_out
asrc
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
101
Rev. 0.91
ALC5672-VB
Datasheet
10.60. MX-85h: ASRC Control 3
Default: 0000’h
Table 75. MX-85h: ASRC Control 3
Name
Bits Read/Write Reset State Description
sel_up_filter_asrc
15:12
R/W
0’h
Select the ASRC Clock Source for Up Sample Rate Filter
0000’b: clk_sysy_div_out
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
sel_down_filter_asrc 11:8
R/W
0’h
Select the ASRC Clock Source for Down Sample Rate Filter
0000’b: clk_sysy_div_out
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
sel_ad_filter_monol_ 7:4
R/W
0’h
Select the ASRC Clock Source for AD Mono Left Filter
asrc
0000’b: clk_sysy_div_out
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
sel_ad_filter_monor_ 3:0
R/W
0’h
Select the ASRC Clock Source for AD Mono Right Filter
asrc
0000’b: clk_sysy_div_out
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
102
Rev. 0.91
ALC5672-VB
Datasheet
10.61. MX-8Ah: ASRC Control 4
Default: 0000’h
Name
i2s1_asrc_prediv
sel_i2s1_asrc
i2s2_asrc_prediv
sel_i2s2_asrc
reserved
Table 76. MX-8Ah: ASRC Control 4
Bits Read/Write Reset State Description
15:14
R/W
0’h
Set the I2S1 Clock Division for ASRC Mode
00’b: div1
01’b: div2
10’b: div3
11’b: reserved
13:12
R/W
0’h
Select the ASRC source of ASRC
00’b: ASRC1
01’b: ASRC2
10’b: Reserved
11’b: Reserved
11:10
R/W
0’h
Set the I2S2 Clock Division for ASRC Mode
00’b: div1
01’b: div2
10’b: div3
11’b: Reserved
9:8
R/W
0’h
Select the ASRC Source of I2S2
00’b: ASRC1
01’b: ASRC2
10’b: Reserved
11’b: Reserved
7:0
R/W
0’h
Reserved
10.62. MX-8Ch: ASRC Control 5
Default: 0007’h
Table 77. MX-8Ch: ASRC Control 5
Bits Read/Write Reset State Description
sel_ad_filter_stereo2_asrc 15:12
R/W
0’h
Select the ASRC Clock Source for AD Stereo2 Filter
0000’b: clk_sysy_div_out
0001’b: clk_i2s1_asrc
0010’b: clk_i2s2_asrc
0011’b: Reserved
0100’b: Reserved
0101’b: clk_sys2
Others: Reserved
Reserved
reserved
11:0
R/W
7’h
Name
103
Rev. 0.91
ALC5672-VB
Datasheet
10.63. MX-8Eh: HP Amp Control 1
Default: 0004’h
Name
Smttrig_hp
reserved
En_smt_l_hp
En_smt_r_hp
Pdn_hp
Softgen_rstn
Softgen_rstp
En_out_hp
Pow_pump_hp
En_softgen_hp
reserved
Pow_capless
Table 78. MX-8Eh: HP Amp Control 1
Bits Read/Write Reset State Description
Enable Softgen Trigger for Soft Mute Depop
15
R/W
0’h
0’b: Disable
1’b: Enable
Reserved
14:10
R/W
0’h
Enable HP_L Mute/Un-Mute Depop
9
R/W
0’h
0’b: Disbale
1’b: Enable
Enable HP_R Mute/Un-Mute Depop
8
R/W
0’h
0’b: Disbale
1’b: Enable
Capless Depop Power Down Control
7
R/W
0’h
0’b: Disbale
1’b: Enable
Reset Softgen to Initialize SOFTP=1
6
R/W
0’h
0’b: Disbale
1’b: Reset
Reset Softgen to Initialize SOFTP=0
5
R/W
0’h
0’b: Disbale
1’b: Reset
Enable Headphone Output
4
R/W
0’h
0’b: Disable
1’b: Enable
Charge Pump Power Control
3
R/W
0’h
0’b: Power Down
1’b: Power On
Power On Soft Generator
2
R/W
1’h
0’b: Power down
1’b: Power on
Reserved
1
R/W
0’h
HP Amp All Power On Control
0
R/W
0’h
0’b: Power Down
1’b: Power On
10.64. MX-8Fh: HP Amp Control 2
Default: 1100’h
Name
reserved
Depop_mode_hp
reserved
Table 79. MX-8Fh: HP Amp Control 2
Bits Read/Write Reset State Description
Reserved
15:14
R
0’h
Select HP Depop Mode
13
R/W
0’h
0’b: Depop mode 1
1’b: Depop mode 2
Reserved
12:7
R/W
22’h
104
Rev. 0.91
ALC5672-VB
Datasheet
Name
En_depop_mode1
Bits
6
Read/Write
R/W
reserved
5:0
R/W
Reset State Description
HP Depop Mode 1 Control
0’h
0’b: Disbale
1’b: Enable
Reserved
0’h
10.65. MX-93h: MICBIAS Control
Default: 0000’h
Name
Sel_micbias1
reserved
Pow_mic1_ovcd
Mic1_ovcd_th_sel
reserved
Ckn_micbias
Pow_clk_int
Sel_irq_debounce
reserved
Table 80. MX-93h: MICBIAS Control
Read/Write Reset State Description
R/W
0’h
MICBIAS1 Output Voltage Control
0’b: 0.9 * MICVDD
1’b: 0.75 * MICVDD
14:12
R/W
0’h
Reserved
11
R/W
0’h
MICBIAS1 Short Current Detector Control
0’b: Disable
1’b: Enable
10:9
R/W
0’h
MICBIAS1 Short Current Detector Threshold
00’b: 640uA
01’b: 1280uA
1x’b: 1920uA
Note: tolerance is 200uA
8:6
R/W
0’h
reserved
5
R/W
0’h
MICBIAS Clock Power
0’b: Disable
1’b: Enable
4
R/W
0’h
Internal Clock Power
0’b: Disable
1’b: Enable
3
R/W
0’h
Select IRQ De-bounce Clock
0’b: MCLK
1’b: Internal clock
2:0
R
0’h
reserved
Bits
15
10.66. MX-94h: JD1 Control
Default: 0000’h
Name
reserved
Sel_mode_jd1
Table 81. MX-94h: JD1 Control
Bits Read/Write Reset State Description
15:2
R/W
0’h
Reserved
1:0
R/W
0’h
JD1 Mode Control
00’b: Mode-0, two port jack detection
01’b: Mode-1, one port jack detection
Others: Reserved
105
Rev. 0.91
ALC5672-VB
Datasheet
10.67. MX-AEh: ADC Path EQ Control 1
Default: 6000’h
Name
Reserved
ad_eq_param_update
Bits
15
Table 82. MX-AEh: ADC Path EQ Control 1
Read/Write Reset State Description
R
0’h
Reserved
14
R/W
1’h
Reserved
Ad_eq_hpf1_status
13:6
5
R/W
R
80’h
0’h
Ad_eq_bpf4_status
4
R
0’h
Ad_eq_bpf3_status
3
R
0’h
Ad_eq_bpf2_status
2
R
0’h
Ad_eq_bpf1_status
1
R
0’h
Ad_eq_lpf_status
0
R
0’h
ADC Path EQ Parameter Update Control
0’b: Busy (Waiting for cross)
1’b: Stand-by
Write “1” to update parameter
Reserved
ADC Path EQ High Pass Filter (HPF1) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
ADC Path EQ Band-4 (BP4) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
ADC Path EQ Band-3 (BP3) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
ADC Path EQ Band-2 (BP2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
ADC Path EQ Band-1 (BP1) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
ADC Path EQ Low Pass Filter (LPF) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
106
Rev. 0.91
ALC5672-VB
Datasheet
10.68. MX-AFh: ADC Path EQ Control 2
Default: 0000’h
Name
reserved
Bits
15:9
Table 83. MX-AFh: ADC Path EQ Control 2
Read/Write Reset State Description
R
0’h
Reserved
ad_eq_lpf_tpy
8
R/W
0’h
ad_eq_hpf1_tpy
7
R/W
0’h
Reserved
6
R
0’h
ad_eq_hpf1_en
5
R/W
0’h
ad_eq_bpf4_en
4
R/W
0’h
Ad_eq_bpf3_en
3
R/W
0’h
Ad_eq_bpf2_en
2
R/W
0’h
Ad_eq_bpf1_en
1
R/W
0’h
Ad_eq_lpf_en
0
R/W
0’h
ADC Path 1st EQ Low Pass Filter Mode Control (LPF)
0’b: Low frequency shelving filter
1’b: 1st order Butterworth LPF (-20dB per decade)
ADC Path 1st EQ High Pass Filter1 Mode Control (HPF1)
0’b: High frequency shelving filter
1’b: 1st order Butterworth HPF (-20dB per decade)
Reserved
ADC Path EQ 1st High Pass Filter (HPF1) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
ADC Path 2nd EQ Band-4 (BP4) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
ADC Path 2nd EQ Band-3 (BP3) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
ADC Path 2nd EQ Band-2 (BP2) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
ADC Path 2nd EQ Band-1 (BP1) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
ADC Path 1st EQ Low Pass Filter (LPF) Filter Control.
0’b: Disabled and reset
1’b: Enabled.
107
Rev. 0.91
ALC5672-VB
Datasheet
10.69. MX-B0h: DAC Path EQ Control 1
Default: 6000’h
Name
reserved
Da_eq_param_update
Bits
15
Table 84. MX-B0h: DAC Path EQ Control 1
Read/Write Reset State Description
R
0’h
Reserved
14
R/W
1’h
reserved
Da_eq_lpf1_status
13:8
7
R/W
R
20’h
0’h
Da_eq_hpf2_status
6
R
0’h
Da_eq_hpf1_status
5
R
0’h
Da_eq_bpf4_status
4
R
0’h
Da_eq_bpf3_status
3
R
0’h
Da_eq_bpf2_status
2
R
0’h
Eq_biquad_wclr
1
R
0’h
Reserved
0
R
0’h
DAC Path EQ parameter update control
0’b: Busy (Waiting for cross)
1’b: Stand-by
Write “1” to update parameter
Reserved
DAC Path EQ Low Pass Filter (LPF2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ High Pass Filter (HPF2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ High Pass Filter (HPF1) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ Band-4 (BP4) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ Band-3 (BP3) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ Band-2 (BP2) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
DAC Path EQ Band-1 (Biquad Type) Status.
0’b: Normal
1’b: Overflow.
This bit is set if overflow had ever occurred.
Write 1 to clear it.
Reserved
108
Rev. 0.91
ALC5672-VB
Datasheet
10.70. MX-B1h: EQ Control 2
Default: 0000’h
Name
reserved
Table 85. MX-B1h: EQ Control 2
Bits Read/Write Reset State Description
15:14
R
0’h
Reserved
Da_eq_lpf1_tpy_r
13
R/W
0’h
Da_eq_lpf1_tpy_l
12
R/W
0’h
11:10
R
0’h
Da_eq_hpf1_tpy_r
9
R/W
0’h
Da_eq_hpf1_tpy_l
8
R/W
0’h
Da_eq_lpf1_en
7
R/W
0’h
Da_eq_hpf2_en
6
R/W
0’h
Da_eq_hpf1_en
5
R/W
0’h
Da_eq_bpf4_en
4
R/W
0’h
Da_eq_bpf3_en
3
R/W
0’h
Da_eq_bpf2_en
2
R/W
0’h
Eq_biquad_en
1
R/W
0’h
Reserved
0
R
0’h
Reserved
DAC Path Right Channel 1st EQ Low Pass Filter Mode
Control (LPF2)
0’b: Low frequency shelving filter
1’b: 1st order Butterworth LPF (-20dB per decade)
DAC Path Left Channel 1st EQ Low Pass Filter Mode Control
(LPF2)
0’b: Low frequency shelving filter
1’b: 1st order Butterworth LPF (-20dB per decade)
Reserved
DAC Path Right Channel 1st EQ High Pass Filter1 Mode
Control
0’b: High frequency shelving filter
1’b: 1st order Butterworth HPF (-20dB per decade)
DAC Path Left Channel 1st EQ High Pass Filter1 Mode
Control
0’b: High frequency shelving filter
1’b: 1st order Butterworth HPF (-20dB per decade)
DAC Path 1st EQ Low Pass Filter (LPF2) Filter Control.
0’b: Disabled and reset
1’b: Enabled.
DAC Path EQ 2nd High Pass Butterworth Filter (HPF)
Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
DAC Path EQ 1st High Pass Filter (HPF1) Control.
0’b: Disabled (bypass) and reset
1’b: Enabled
DAC Path 2nd EQ Band-4 (BP4) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
DAC Path 2nd EQ Band-3 (BP3) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
DAC Path 2nd EQ Band-2 (BP2) shelving Filter Control.
0’b: Disabled and reset
1’b: Enabled.
DAC Path 2nd EQ Band-1 (Biquad Type) shelving Filter
Control.
0’b: Disabled and reset
1’b: Enabled.
Reserved
109
Rev. 0.91
ALC5672-VB
Datasheet
10.71. MX-B2h: DRC Control 1
Default: 0000’h
Name
Reserved
Alc_thmin_fast_rc_e
n
Alc_thmin
Bits
15:7
Table 86. MX-B2h: DRC Control 1
Read/Write Reset State Description
R
0’h
Reserved
6
R/W
0’h
5:0
R/W
0’h
DRC THMIN Mode Fast Recover Control
0’b: Disable fast recover
1’b: Enable fast recover
DRC THMIN Mode Threshold Level Control
00’h: -60dB
01’h: -60.75dB
02’h: -61.5dB
…
2E’h: -94.5dB, 0.75dB/Step
10.72. MX-B3h: DRC Control 2
Default: 001F’h
Name
reserved
Bits
15
Table 87. MX-B3h: DRC Control 2
Read/Write Reset State Description
R
0’h
Reserved
Alc_noise_gate_ht
14:12
R/W
0’h
alc_ft_boost
11:6
R/W
0’h
alc_bk_gain_r
5:0
R/W
1f’h
ALC Noise Gate Hold Time Control
000’b: 0 sample
001’b: 128 samples
010’b: 256 samples
…
111’b: 896 samples
ALC Digital Pre-BOOST (0.75dB/step)
00’h= 0dB
01’h= 0.75dB
02’h= 1.5dB
03’h= 2.25dB
…
27’h= 29.25dBFS
Others: Reserved
ALC Right Channel Digital Post-BOOST (0.375dB/step)
00’h= -11.625dB
…
3F’h= 12dB
110
Rev. 0.91
ALC5672-VB
Datasheet
10.73. MX-B4h: DRC Control 3
Default: 2206’h
Name
sel_drc_agc
Bits
15:14
Table 88. MX-B4h: DRC Control 3
Read/Write Reset State Description
R/W
0’h
DRC Enable Control
00’b: Disable DRC
01’b: Enable DRC to DAC Path
10’b: Disable DRC
11’b: Enable DRC to ADC Path
update_drc_agc_para
13
R
1’h
m
sel_drc_agc_atk
Update DRC Parameter
Write 1’b to update all DRC parameter
12:8
R/W
2’h
Select DRC attack rate (0.375dB/TU)
00’h: 83 uSec
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved
Drc_agc_rate_sel
7:5
R/W
0’h
DRC Rate Control for Sample Rate Change
001’b: 48kHz
010’b: 96kHz
011’b: 192kHz
101’b: 44.1kHz
110’b: 88.2kHz
111’b: 176.4kHz
Others: Reserved
sel_rc_rate
4:0
R/W
6’h
Select DRC recovery rate (0.375dB/TU)
00’h: 83 uSec
01’h: 0.167 mSec
…
10’h: 5.46 Sec
Others: Reserved
attack time=(4*2^n)/Sample_Rate, n=MX-B4[12:8], default=0.33mS
recovery time=(4*2^n)/Sample_Rate, n= MX-B4 [4:0], default=5.3mS
When change I2S’s sample rate, the DRC/AGC rate control is need to be changed same with I2S’s sample rate. When
change the DRC/AGC rate, the parameter of DRC/AGC isn’t need be modified.
When I2S’s sample rate is below 48kHz, that need to set the DRC/AGC rate to 48kHz and re-calculate the DRC/AGC’s
parameter by I2S’s sample rate.
111
Rev. 0.91
ALC5672-VB
Datasheet
10.74. MX-B5h: DRC Control 4
Default: 1F00’h
Name
Alc_drc_ratio_sel2
Bits
15:14
sel_drc_agc_post_bst
13:8
Table 89. MX-B5h: DRC Control 4
Read/Write Reset State Description
R/W
0’h
DRC Compression-2 Ratio Selection
00’b: 1:1
01’b: 1:2
10’b: 1:4
11’b: 1:8
R/W
1f’h
DRC Digital Post-Boost Gain (0.375dB/step)
00’h= -11.625dB
…
3F’h= 12dB
Others: Reserved
En_drc_agc_compres
7
R/W
0’h
s
DRC Compression Function Control
0’b: Disable
1’b: Enable
Sel_ratio
6:5
R/W
0’h
DRC Compression Ratio Selection
00’b: 1:1
01’b: 1:2
10’b: 1:4
11’b: 1:8
Alc_noise_gate_drop
_en
4
R/W
0’h
Reserved
3:2
R
0’h
noise_gate_ratio_sel
1:0
R/W
0’h
Gain table:
DRC Noise Gate Drop Mode Control
0’b: Disable
1’b: Enable
Reserved
DRC Expansion Ratio Control when Noise Gate is Enabled
00’b: 1:1
01’b: 2:1
10’b: 4:1
11’b: 8:1
DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain DEC HEX Boost Gain
0
0
-11.625
16
10
-5.625
32
20
0.375
48
30
6.375
64
40
1
1
-11.25
17
11
-5.25
33
21
0.75
49
31
6.75
65
41
2
2
-10.875
18
12
-4.875
34
22
1.125
50
32
7.125
66
42
3
3
-10.5
19
13
-4.5
35
23
1.5
51
33
7.5
67
43
4
4
-10.125
20
14
-4.125
36
24
1.875
52
34
7.875
68
44
5
5
-9.75
21
15
-3.75
37
25
2.25
53
35
8.25
69
45
6
6
-9.375
22
16
-3.375
38
26
2.625
54
36
8.625
70
46
112
Rev. 0.91
ALC5672-VB
Datasheet
7
7
-9
23
17
-3
39
27
3
55
37
9
71
47
8
8
-8.625
24
18
-2.625
40
28
3.375
56
38
9.375
72
48
9
9
-8.25
25
19
-2.25
41
29
3.75
57
39
9.75
73
49
10
A
-7.875
26
1A
-1.875
42
2A
4.125
58
3A
10.125
74
4A
11
B
-7.5
27
1B
-1.5
43
2B
4.5
59
3B
10.5
75
4B
12
C
-7.125
28
1C
-1.125
44
2C
4.875
60
3C
10.875
76
4C
13
D
-6.75
29
1D
-0.75
45
2D
5.25
61
3D
11.25
14
E
-6.375
30
1E
-0.375
46
2E
5.625
62
3E
11.625
15
F
-6
31
1F
0
47
2F
6
63
3F
12
10.75. MX-B6h: DRC Control 5
Default: 0000’h
Name
Noise_gate_boost
Bits
15:12
Table 90. MX-B6h: DRC Control 5
Read/Write Reset State Description
R/W
0’h
Select Compensation Gain When Signal is Below Noise Gate
0’h: 0dB
1’h: 3dB
2’h: 6dB
…
E’h: 42dB
F’h: 45dB
Reserved
en_drc_agc_noise_ga
11:7
R
0’h
Reserved
6
R/W
0’h
Enable Noise Gate function
te
0’b: Diaable
1’b: Enable
En_drc_agc_noise_ga
5
R/W
0’h
te_hold
Enable Noise Gate Hold Data Function
0’b: Disable
1’b: Enable
sel_drc_agc_noise_th
4:0
R/W
0’h
Noise Gate Threshold (-1.5dB/step)
00’h: -24dBFS
01’h: -25.5dBFS
………………..
1F’h: -70.5 dBFS
113
Rev. 0.91
ALC5672-VB
Datasheet
10.76. MX-B7h: DRC Control 6
Default: 0000’h
Name
Reserved
alc_thmax2
Bits
15:12
11:6
alc_thmax
5:0
Table 91. MX-B7h: DRC Control 6
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
DRC Limiter Threshold 2 Control (0.75dB/step)
00’h= 0dBFS
01’h= -0.75dBFS
02’h= -1.5dBFS
03’h= -2.25dBFS
………………..
1F’h= -45dBFS
R/W
0’h
DRC Limiter Threshold Control (0.375dB/step)
00’h= 0dBFS
01’h= -0.375dBFS
02’h= -0.75dBFS
03’h= -1.125dBFS
………………..
1F’h= -23.625dBFS
10.77. MX-BBh: Jack Detection Control 1
Default: 0000’h
Name
sel_gpio_jd1
Bits
15:13
reserved
en_jd_hpo
12
11
polarity_jd_tri_hpo
10
en_jd_spk_l
9
Table 92. MX-BBh: Jack Detection Control 1
Read/Write Reset State Description
R/W
0’h
GPIO Jack Detect – 1 Source Selection
000’b: OFF
001’b: GPIO3
010’b: GPIO4
011’b: GPIO5
100’b: GPIO6
101’b: Reserved
110’b: Reserved
111’b: Reserved
R
0’h
reserved
R/W
0’h
Enable jack detect trigger HPOUT
0’b: Disable
1’b: Enable
R/W
0’h
Select jack detect polarity trigger HPOUT
0’b: Low trigger
1’b: High trigger
R/W
0’h
Enable jack detect trigger SPK_L
0’b: Disable
1’b: Enable
114
Rev. 0.91
ALC5672-VB
Datasheet
Name
polarity_jd_tri_spk_l
Bits
8
Read/Write
R/W
en_jd_spk_r
7
R/W
polarity_jd_tri_spk_r
6
R/W
5:4
3
R/W
R/W
2
R/W
1:0
R
Reserved
en_jd_lout1
polarity_jd_tri_lout1
Reserved
Reset State Description
0’h
Select jack detect polarity trigger SPK_L
0’b: Low trigger
1’b: High trigger
0’h
Enable jack detect trigger SPK_R
0’b: Disable
1’b: Enable
0’h
Select jack detect polarity trigger SPK_R
0’b: Low trigger
1’b: High trigger
0’h
Reserved
0’h
Enable jack detect trigger LOUT1
0’b: Disable
1’b: Enable
0’h
Select jack detect polarity trigger LOUT1
0’b: Low trigger
1’b: High trigger
0’h
Reserved
10.78. MX-BDh: IRQ Control 1
Default: 0000’h
Name
en_irq_gpio_jd1
Bits
15
en_gpio_jd1_sticky
14
inv_gpio_jd1
13
reserved
en_irq_jd1_1
12:10
9
en_jd1_1_sticky
8
inv_jd1_1
7
Table 93. MX-BDh: IRQ Control 1
Read/Write Reset State Description
R/W
0’h
IRQ Output Source Configure of GPIO Jack Detection 1
Status
0’b: bypass
1’b: Normal
R/W
0’h
Sticky Control for GPIO Jack Detect 1
0’b: Disable
1’b: Enable
R/W
0’h
GPIO Jack Detection 1 Status Polarity
0’b: Normal
1’b: Output Invert
R/W
0’h
Reserved
R/W
0’h
IRQ Output Source Configure of JD1_1 Jack Detection
Status
0’b: bypass
1’b: Normal
R/W
0’h
Sticky Control for JD1_1 Jack Detect
0’b: Disable
1’b: Enable
R/W
0’h
JD1_1 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
115
Rev. 0.91
ALC5672-VB
Datasheet
Name
en_irq_jd1_2
Bits
6
Read/Write
R/W
en_jd1_2_sticky
5
R/W
inv_jd1_2
4
R/W
en_irq_jd2
3
R/W
en_jd2_sticky
2
R/W
inv_jd2
1
R/W
reserved
0
R
Reset State Description
0’h
IRQ Output Source Configure of JD1_2 Jack Detection
Status
0’b: bypass
1’b: Normal
0’h
Sticky Control for JD1_2 Jack Detect
0’b: Disable
1’b: Enable
0’h
JD1_2 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
0’h
IRQ Output Source Configure of JD2 Jack Detection Status
0’b: bypass
1’b: Normal
0’h
Sticky Control for JD2 Jack Detect
0’b: Disable
1’b: Enable
0’h
JD2 Jack Detection Status Polarity
0’b: Normal
1’b: Output Invert
0’h
Reserved
10.79. MX-BEh: IRQ Control 2
Default: 0000’h
Name
en_irq_micbias1_ovc
d
Bits
15
reserved
en_micbias1_ovcd_st
icky
14
13
reserved
inv_micbias1_ovcd
12
11
reserved
Sta_micbias1_ovcd
10
9
reserved
8:0
Table 94. MX-BEh: IRQ Control 2
Read/Write Reset State Description
R/W
0’h
IRQ Output Source Configure of MICBIAS1 Over Current
Status
0’b: bypass
1’b: Normal
R/W
0’h
Reserved
R/W
0’h
Sticky Control for MICBIAS1 Over Current
0’b: Disable
1’b: Enable
R/W
0’h
Reserved
R/W
0’h
MICBIAS1 over current status polarity
0’b: Normal
1’b: Output Invert
R/W
0’h
Reserved
R
0’h
MICBIAS1 over current status
Read: return status of each status pin
Write: Write ‘0’ to clear stick bit
R/W
0’h
Reserved
116
Rev. 0.91
ALC5672-VB
Datasheet
10.80. MX-BFh: IRQ Control 3
Default: 0000’h
Name
reserved
sta_jd2
Bits
15
14
sta_jd1_2
13
sta_jd1_1
12
reserved
sta_gpio6
11
10
sta_gpio5
9
sta_gpio1
8
sta_gpio2
7
sta_gpio3
6
sta_gpio4
5
sta_gpio_jd1
4
en_irq_inline
3
sta_inline
2
en_inline_sticky
1
inv_inline
0
Table 95. MX-BFh: IRQ Control 3
Read/Write Reset State Description
R
0’h
Reserved
R
0’h
Status of JD2 Jack detection .
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
R
0’h
Status of JD1_2 Jack detection .
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
R
0’h
Status of JD1_1 Jack detection .
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
R
0’h
Reserved
R
0’h
GPIO6 Pin Status
Read: return status of each GPIO pin
R
0’h
GPIO5 Pin Status
Read: return status of each GPIO pin
R
0’h
GPIO1 Pin Status
Read: return status of each GPIO pin
R
0’h
GPIO2 Pin Status
Read: return status of each GPIO pin
R
0’h
GPIO3 Pin Status
Read: return status of each GPIO pin
R
0’h
GPIO4 Pin Status
Read: return status of each GPIO pin
R
0’h
Status of GPIO Jack detection 1
Read: Return status of Jack Detect Select output
Write: Write ‘0’ to clear stick bit
R/W
0’h
IRQ Output Source Configure of InLine Command Status
0’b: bypass
1’b: Normal
R
0’h
Status of InLine Command Trigger
Read: Return status of InLine Command Trigger
Write: Write ‘0’ to clear stick bit
R/W
0’h
Sticky Control for InLine Command
0’b: Disable
1’b: Enable
R/W
0’h
InLine Command Status Polarity
0’b: Normal
1’b: Output Invert
10.81. MX-C0h: GPIO Control 1
Default: 0000’h
117
Rev. 0.91
ALC5672-VB
Datasheet
Name
sel_gpio1_type
Bits
15
sel_gpio2_type
14
Reserved
Sel_i2s2_pin
13:9
8
sel_gpio5_type
7
sel_gpio6_type
6
Reserved
5:0
Table 96. MX-C0h: GPIO Control 1
Read/Write Reset State Description
R/W
0’h
GPIO1 Pin Function Select
0’b: GPIO1
1’b: IRQ output
R/W
0’h
GPIO2 Pin Function Select
0’b: GPIO2
1’b: DMIC1_SCL
R/W
0’h
Reserved
R/W
0’h
I2S-2 Pin Function Selection
0’b: I2S function pins
1’b: GPIO function pins
R/W
0’h
GPIO5 Pin Function Select
0’b: GPIO5
1’b: DMIC3_SDA
R/W
0’h
GPIO6 Pin Function Select
0’b: GPIO6
1’b: DMIC1_SDA
R/W
0’h
Reserved
10.82. MX-C1h: GPIO Control 2
Default: 0000’h
Name
reserved
sel_gpio5
Bits
15
14
sel_gpio5_logic
13
inv_gpio5
12
sel_gpio4
11
sel_gpio4_logic
10
inv_gpio4
9
sel_gpio3
8
Table 97. MX-C1h: GPIO Control 2
Read/Write Reset State Description
R/W
0’h
Reserved
R/W
0’h
GPIO5 Pin Configuration
0’b: Input
1’b: Output
R/W
0’h
GPIO5 Output Pin Control
0’b: Drive Low
1’b: Drive High
R/W
0’h
GPIO5 Pin Polarity
0’b: Normal
1’b: Output Invert
R/W
0’h
GPIO4 Pin Configuration
0’b: Input
1’b: Output
R/W
0’h
GPIO4 Output Pin Control
0’b: Drive Low
1’b: Drive High
R/W
0’h
GPIO4 Pin Polarity
0’b: Normal
1’b: Output Invert
R/W
0’h
GPIO3 Pin Configuration
0’b: Input
1’b: Output
118
Rev. 0.91
ALC5672-VB
Datasheet
Name
sel_gpio3_logic
Bits
7
Read/Write
R/W
inv_gpio3
6
R/W
sel_gpio2
5
R/W
sel_gpio2_logic
4
R/W
inv_gpio2
3
R/W
sel_gpio1
2
R/W
sel_gpio1_logic
1
R/W
inv_gpio1
0
R/W
Reset State Description
0’h
GPIO3 Output Pin Control
0’b: Drive Low
1’b: Drive High
0’h
GPIO3 Pin Polarity
0’b: Normal
1’b: Output Invert
0’h
GPIO2 Pin Configuration
0’b: Input
1’b: Output
0’h
GPIO2 Output Pin Control
0’b: Drive Low
1’b: Drive High
0’h
GPIO2 Pin Polarity
0’b: Normal
1’b: Output Invert
0’h
GPIO1 Pin Configuration
0’b: Input
1’b: Output
0’h
GPIO1 Output Pin Control
0’b: Drive Low
1’b: Drive High
0’h
GPIO1 Pin Polarity
0’b: Normal
1’b: Output Invert
10.83. MX-C2h: GPIO Control 3
Default: 0000’h
Name
reserved
sel_gpio6
Bits
15:3
2
sel_gpio6_logic
1
inv_gpio6
0
Table 98. MX-C2h: GPIO Control 3
Read/Write Reset State Description
R/W
0’h
Reserved
R/W
0’h
GPIO6 Pin Configuration
0’b: Input
1’b: Output
R/W
0’h
GPIO6 Output Pin Control
0’b: Drive Low
1’b: Drive High
R/W
0’h
GPIO6 Pin Polarity
0’b: Normal
1’b: Output Invert
119
Rev. 0.91
ALC5672-VB
Datasheet
10.84. MX-CFh: SounzRealTM BassBack Control
Default: 0013’h
TM
Name
En_bb
Bits
15
Sel_bb_coef
14:12
Reserved
Bb_boost_gain
11:6
5:0
Table 99. MX-CFh: SounzReal BassBack Control
Read/Write Reset State Description
R/W
0’h
Enable BassBack Function
0’b: Disable
1’b: Enable
R/W
0’h
Select Control for BassBack Coefficient Type
000’b: Type A
001’b: Type B
010’b: Type C
011’b: Type D
1xx’b: Reserved
R
0’h
Reserved
R/W
13’h
Select Control BassBack Boost Gain
000001’b: 1.5dB
000010’b: 3dB
………
010011’b: 24dB
………
011111’b: 42dB, with 1.5dB/Step
10.85. MX-D0h: SounzRealTM TruTreble Control 1
Default: 0680’h
TM
Name
reserved
En_mp
Mp_eg
reserved
Eg
1
Table 100. MX-D0h: SounzReal TruTreble Control 1
Bits Read/Write Reset State Description
15:14
R/W
0’h
Reserved
13
R/W
0’h
Enable TruTreble Function
0’b: Disable
1’b: Enable
12:8
R/W
6’h
TruTreble Enhanced Gain Control
00000’b: -11.625dB
00001’b: -10.5dB
……….
00110’b: -3dB
...........
10100’b: 7.5dB
7:0
R/W
80’h
Reserved
Enhanced Gain
Eg
Enhanced Gain
-11.625dB
11
2.25 dB
120
Rev. 0.91
ALC5672-VB
Datasheet
2
-10.5 dB
12
3 dB
3
-9 dB
13
3.75 dB
4
-6.75 dB
14
4.5 dB
5
-4.5 dB
15
4.875 dB
6
-3 dB
16
5.625 dB
7
-1.875 dB
17
6 dB
8
-0.375 dB
18
6.375 dB
9
0.375 dB
19
7.125 dB
10
1.5 dB
20
7.5 dB
10.86. MX-D1h: SounzRealTM TruTreble Control 2
Default: 1C17’h
TM
Name
reserved
mp_hp_wt
mp_og
reserved
mp_hg
Table 101. MX-D1h: SounzReal l TruTreble Control 2
Bits Read/Write Reset State Description
15:14
R
0’h
Reserved
13
R/W
0’h
Select The Harmonic Weighting
0’b: a = 1/4(default)
1’b: a = 1/2
12:8
R/W
1C’h
Select The Origin Signal Gain
00000’b: -5.8125dB
00001’b: -5.625dB
…
10111’b: -0.5625 dB
...
11111’b: 12dB, with 0.1875dB/Step
7:6
R
0’h
Reserved
5:0
R/W
17’h
Select High Frequency Harmonic Gain
000000’b: -11.625dB
000001’b: -11.25dB
…
010111’b: -3dB
...
111111’b: 12dB, with 0.375dB/Step
(0.375 /step)
10.87. MX-D3h: Stereo1 ADC Wind Filter Control 1
Default: A220’h
Name
adj_hpf_2nd_en_stere
o1
Table 102. MX-D3h: Stereo1 ADC Wind Filter Control 1
Bits Read/Write Reset State Description
15
R/W
1’h
Stereo1 ADC Wind Filter Enable Control
0’b : Disable and bypass
1’b : Enable
121
Rev. 0.91
ALC5672-VB
Datasheet
Name
Bits
adj_hpf_coef_l_sel_st 14:12
ereo1
Read/Write
R/W
Reserved
adj_hpf_coef_r_sel_st
ereo1
11
10:8
R
R/W
reserved
7:0
R/W
Reset State Description
2’h
Stereo1 ADC Wind Filter Left Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
0’h
Reserved
2’h
Stereo1 ADC Wind Filter Right Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
20’h
Reserved
10.88. MX-D4h: Stereo1 ADC Wind Filter Control 2
Default: 0000’h
Name
reserved
Table 103. MX-D4h: Stereo1 ADC Wind Filter Control 2
Bits Read/Write Reset State Description
15:14
R
0’h
Reserved
122
Rev. 0.91
ALC5672-VB
Datasheet
Name
adj_hpf_coef_l_num_
stereo1
reserved
adj_hpf_coef_r_num_
stereo1
Bits
13:8
Read/Write
R/W
7:6
5:0
R
R/W
Reset State Description
0’h
Stereo1 ADC Wind Filter Right Channel Coefficient Fine
Selection (0~63)
0’h
Reserved
0’h
Stereo1 ADC Wind Filter Left Channel Coefficient Fine
Selection (0~63)
10.89. MX-D9h: Soft Volume & ZCD Control 1
Default: 0809’h
Name
en_softvol
Bits
15
reserved
en_o_svol
14
13
en_hpo_svol
12
en_zcd_digital
11
pow_zcd
10
reserved
sel_svol
9:4
3:0
Table 104. MX-D9h: Soft Volume & ZCD Control 1
Read/Write Reset State Description
R/W
0’h
Digital Soft Volume Delay Control
0’b: Disable
1’b: Enable
R/W
0’h
Reserved
R/W
0’h
OUTVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
R/W
0’h
HPOVOLL/R Soft Volume Delay Control
0’b: Disable
1’b: Enable
R/W
1’h
Digital Volume Zero Crossing Detection Control
0’b: Disable
1’b: Enable
R/W
0’h
Power On Zero Crossing
0’b: Power Down
1’b: Power On
R
0’h
Reserved
R/W
9’h
Soft Volume Change Delay Time
0000: 1 SVSYNC
0001: 2 SVSYNC
0010: 4 SVSYNC
0011: 8 SVSYNC
0100: 16 SVSYNC
0101: 32 SVSYNC
0110: 64 SVSYNC
0111: 128 SVSYNC
1000: 256 SVSYNC
1001: 512 SVSYNC
1010: 1024 SVSYNC
Others: Reserved
Note: SVSYNC=1/Fs, Step:-1.5dBFS
123
Rev. 0.91
ALC5672-VB
Datasheet
10.90. MX-DAh: Soft Volume & ZCD Control 2
Default: 0000’h
Name
reserved
en_zcd_outmixr
en_zcd_outmixl
en_zcd_hpmixr
en_zcd_hpmixl
reserved
en_zcd_recmixr
en_zcd_recmixl
Table 105. MX-DAh: Soft Volume & ZCD Control 2
Bits Read/Write Reset State Description
15:7
R/W
0’h
Reserved
6
R/W
0’h
OUTMIXR ZCD Control
0’b: Disable
1’b: Enable
5
R/W
0’h
OUTMIXL ZCD Control
0’b: Disable
1’b: Enable
4
R/W
0’h
HPMIXR ZCD Control
0’b: Disable
1’b: Enable
3
R/W
0’h
HPMIXL ZCD Control
0’b: Disable
1’b: Enable
2
R/W
0’h
Reserved
1
R/W
0’h
RECMIXR ZCD Control
0’b: Disable
1’b: Enable
0
R/W
0’h
RECMIXL ZCD Control
0’b: Disable
1’b: Enable
10.91. MX-DBh: Inline Command Control 1
Default: 0001’h
Name
sta_one_up_button
Bits
15
sta_double_up_button
14
sta_hold_up_button
13
sta_one_center_butto
n
sta_double_center_bu
tton
sta_hold_center_butto
n
sta_one_down_button
12
sta_double_down_but
ton
8
11
10
9
Table 106. MX-DBh: Inline Command Control 1
Read/Write Reset State Description
R
0’h
Status of One Click Command for Up Button
Write “1” to clear it
R
0’h
Status of Double Click Command for Up Button
Write “1” to clear it
R
0’h
Status of Hold Command for Up Button
Write “1” to clear it
R
0’h
Status of One Click Command for Center Button
Write “1” to clear it
R
0’h
Status of Double Click Command for Center Button
Write “1” to clear it
R
0’h
Status of Hold Command for Center Button
Write “1” to clear it
R
0’h
Status of One Click Command for Down Button
Write “1” to clear it
R
0’h
Status of Double Click Command for Down Button
Write “1” to clear it
124
Rev. 0.91
ALC5672-VB
Datasheet
Name
sta_hold_down_butto
n
En_inline
Bits
7
Read/Write
R
6
R/W
reserved
Sel_clk_mic
5
4:3
R
R/W
Mic_in_det_0_th
2:0
R/W
Reset State Description
0’h
Status of Hold Command for Down Button
Write “1” to clear it
0’h
Enable InLine Command
0’b: Disable
1’b: Enable
0’h
Reserved
0’h
Select InLine Command Debounce Clock
00’b: OSC/2^17
01’b: OSC/2^16
10’b: OSC/2^15
11’b: OSC/2^14
1’h
MIC Input Voltage Threshold Control (CMP0)
000’b: 0.09V
001’b: 0.12V
010’b: 0.15V
011’b: 0.18V
100’b: 0.17V
101’b: 0.23V
110’b: 0.29V
111’b: 0.34V
10.92. MX-DCh: Inline Command Control 2
Default: 0049’h
Name
en_inline_vol
Bits
15
sel_inline_ctl_if
14
Conti_hold_up
13
Conti_hold_center
12
Conti_hold_down
11
in_det_window
10:0
Table 107. MX-DCh: Inline Command Control 2
Read/Write Reset State Description
R/W
0’h
Enable Inline Command Direct to Control Digital Volume
0’b: Disable
1’b: Enable
R/W
0’h
Select The Inline Command Control Path
0’b: IF1 DAC Volume/Mute(Un-Mute)
1’b: IF2 DAC Volume/Mute(Un-Mute)
R/W
0’h
Select Hold Command Behavior for Up Button
0’b: One pulse trigger
1’b: Continue pulse trigger
R/W
0’h
Select Hold Command Behavior for Center Button
0’b: One pulse trigger
1’b: Continue pulse trigger
R/W
0’h
Select Hold Command Behavior for Down Button
0’b: One pulse trigger
1’b: Continue pulse trigger
Inline Command Click Window Control
R/W
49’h
MX-DB[4:3]=00’b => (1/OSC)*16384*n
MX-DB[4:3]=01’b => (1/OSC)*8192*n
MX-DB[4:3]=10’b => (1/OSC)*4096*n
MX-DB[4:3]=11’b => (1/OSC)*2048*n
(n=0~127)
125
Rev. 0.91
ALC5672-VB
Datasheet
10.93. MX-DDh: Inline Command Control 3
Default: 0009’h
Name
Reserved
Mic_in_det_1_th
Bits
15:6
5:3
Mic_in_det_2_th
2:0
Table 108. MX-DDh: Inline Command Control 3
Read/Write Reset State Description
R
0’h
Reserved
R/W
1’h
MIC Input Voltage Threshold Control (CMP1)
000’b: 0.36V
001’b: 0.39V
010’b: 0.42V
011’b: 0.45V
100’b: 0.68V
101’b: 0.74V
110’b: 0.80V
111’b: 0.86V
R/W
1’h
MIC Input Voltage Threshold Control (CMP2)
000’b: 0.69V
001’b: 0.71V
010’b: 0.74V
011’b: 0.77V
100’b: 1.31V
101’b: 1.37V
110’b: 1.43V
111’b: 1.48V
10.94. MX-E0h: Voice DSP Control 1
Default: 0000’h
Name
Aec_cmd
dsp_clk_sel
Bits
15:8
7:6
Aec_busy
5
Sel_dsp_cmd
4
Table 109. MX-E0h: Voice DSP Control 1
Read/Write Reset State Description
R/W
0’h
Voice DSP Command
R/W
0’h
Voice DSP Control Interface Clock Select
00’b: SYSCLK/3/16
01’b: SYSCLK/4/16
10’b: SYSCLK/6/16
11’b: SYSCLK/8/16
R
0’h
Voice DSP R/W Busy
0’b: Normal
1’b: Busy
R/W
0’h
Voice DSP R/W Command
0’b: Write
1’b: Read
126
Rev. 0.91
ALC5672-VB
Datasheet
Name
Sel_dsp_data_len
Bits
3:2
Read/Write
R/W
Sel_dsp_addr_len
1
R/W
Aec_cmd_start
0
R/W
Reset State Description
0’h
Voice DSP Control Interface Data Length
00’b: 0 byte
01’b: 1 byte
10’b: 2 byte
11’b: 3 byte
0’h
Voice DSP Control Interface Address Length
0’b: 8 bit
1’b: 16 bit
0’h
Write “1” to start Voice DSP Control Interface Command
10.95. MX-E1h: Voice DSP Control 2
Default: 0000’h
Name
Aec_addr
Bits
15:0
Table 110. MX-E1h: Voice DSP Control 2
Read/Write Reset State Description
R/W
0’h
Voice DSP Address
10.96. MX-E2h: Voice DSP Control 3
Default: 0000’h
Name
Aec_write_data
Bits
15:0
Table 111. MX-E2h: Voice DSP Control 3
Read/Write Reset State Description
R/W
0’h
Voice DSP Write Data
10.97. MX-E3h: Voice DSP Control 4
Default: 0000’h
Name
Reserved
Aec_write_data2
Bits
15:8
7:0
Table 112. MX-E3h: Voice DSP Control 4
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
Voice DSP Write Data
127
Rev. 0.91
ALC5672-VB
Datasheet
10.98. MX-E4h: Voice DSP Control 5
Default: 0000’h
Name
read_data_aec
Bits
15:0
Table 113. MX-E4h: Voice DSP Control 5
Read/Write Reset State Description
R
0’h
Voice DSP Read Data
10.99. MX-E5h: Voice DSP Control 6
Default: 0000’h
Name
Reserved
read_data_aec2
Bits
15:8
7:0
Table 114. MX-E5h: Voice DSP Control 6
Read/Write Reset State Description
R
0’h
Reserved
R
0’h
Voice DSP Read Data
10.100. MX-ECh: Mono ADC Wind Filter Control 1
Default: A200’h
Name
adj_hpf_2nd_en_mon
o
adj_hpf_coef_l_sel_
mono
Reserved
Table 115. MX-ECh: Mono ADC Wind Filter Control 1
Read/Write Reset State Description
R/W
1’h
Mono ADC Wind Filter Enable Control
0’b : Disable and bypass
1’b : Enable
14:12
R/W
2’h
Mono ADC Wind Filter Left Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
11
R
0’h
Reserved
Bits
15
128
Rev. 0.91
ALC5672-VB
Datasheet
Name
adj_hpf_coef_r_sel_
mono
Bits
10:8
Read/Write
R/W
reserved
7:0
R
Reset State Description
2’h
Mono ADC Wind Filter Right Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
0’h
Reserved
10.101. MX-EDh: Mono ADC Wind Filter Control 2
Default: 0000’h
Table 116. MX-EDh: Mono ADC Wind Filter Control 2
Name
Bits Read/Write Reset State Description
reserved
15:14
R
0’h
Reserved
adj_hpf_coef_l_num_ 13:8
R/W
0’h
Mono ADC Wind Filter Right Channel Coefficient Fine
mono
Selection (0~63)
Reserved
7:6
R
0’h
Reserved
adj_hpf_coef_r_num_ 5:0
R/W
0’h
Mono ADC Wind Filter Left Channel Coefficient Fine
mono
Selection (0~63)
10.102. MX-EEh: Stereo2 ADC Wind Filter Control 1
Default: A200’h
Name
adj_hpf_2nd_en_stere
o2
Table 117. MX-EEh: Stereo2 ADC Wind Filter Control 1
Bits Read/Write Reset State Description
15
R/W
1’h
Stereo2 ADC Wind Filter Enable Control
0’b : Disable and bypass
1’b : Enable
129
Rev. 0.91
ALC5672-VB
Datasheet
Name
Bits
adj_hpf_coef_l_sel_st 14:12
ereo2
Read/Write
R/W
Reserved
adj_hpf_coef_r_sel_st
ereo2
11
10:8
R
R/W
reserved
7:0
R
Reset State Description
2’h
Stereo2 ADC Wind Filter Left Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
0’h
Reserved
2’h
Stereo2 ADC Wind Filter Right Channel Coefficient Coarse
Selection
000’b :
fs=8k, fc = 20~2000Hz
fs=12k, fc = 30~3000Hz
fs=16k, fc = 40~4000Hz
001’b :
fs=24k, fc = 30~2458Hz
fs=32k, fc = 40~3278Hz
010’b :
fs=44.1k, fc = 28~1992Hz
fs=48k, fc = 30~2168Hz
011’b :
fs=88.2k, fc = 28~1869Hz
fs=96k, fc = 30~2034Hz
100’b :
fs=176.4k, fc = 27~1811Hz
fs=192k, fc = 30~1971Hz
Others: Reserved
0’h
Reserved
130
Rev. 0.91
ALC5672-VB
Datasheet
10.103. MX-EFh: Stereo2 ADC Wind Filter Control 2
Default: 0000’h
Table 118. MX-EFh: Stereo2 ADC Wind Filter Control 2
Name
Bits Read/Write Reset State Description
Reserved
15:14
R
0’h
Reserved
adj_hpf_coef_l_num_ 13:8
R/W
0’h
Stereo2 ADC Wind Filter Right Channel Coefficient Fine
stereo2
Selection (0~63)
Reserved
7:6
R
0’h
Reserved
adj_hpf_coef_r_num_ 5:0
R/W
0’h
Stereo2 ADC Wind Filter Left Channel Coefficient Fine
stereo2
Selection (0~63)
10.104. MX-F8h: Jack Detection Control
Default: 0000’h
Name
reserved
en_jd_combo_jack
Bits
15:8
7
polarity_jd_tri_cbj
6
Sel_jd_trigger_cbj
5:3
Sel_jd_trigger_hpo
2:0
Table 119. MX-F8h: Jack Detection Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
Enable Jack Detect to Trigger Combo Jack
0’b: Disable
1’b: Enable
R/W
0’h
Select Jack Detect Polarity to Trigger Combo Jack
0’b: Low trigger
1’b: High trigger
R/W
0’h
JD Trigger Source Selection for Combo Jack
000’b: From sta_gpio_jd1
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
100’b: Reserved
101’b: Reserved
110’b: From MX0B[12]
Others: Reserved
R/W
0’h
JD Trigger Source Selection for HPO
000’b: From sta_gpio_jd1
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
100’b: Reserved
101’b: Reserved
Others: Reserved
131
Rev. 0.91
ALC5672-VB
Datasheet
10.105. MX-F9h: Jack Detection Control
Default: 0000’h
Name
reserved
Sel_jd_trigger_spk
Bits
15:12
11:9
Reserved
Sel_jd_trigger_lout1
8:6
5:3
Reserved
2:0
Table 120. MX-F9h: Jack Detection Control
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
JD Trigger Source Selection for SPK_OUT
000’b: From sta_gpio_jd1
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
100’b: Reserved
101’b: Reserved
Others: Reserved
R
0’h
Reserved
R/W
0’h
JD Trigger Source Selection for LOUT1
000’b: From sta_gpio_jd1
001’b: From sta_jd1_1
010’b: From sta_jd1_2
011’b: From sta_jd2
100’b: Reserved
101’b: Reserved
Others: Reserved
R/W
0’h
Reserved
10.106. MX-FAh: General Control 1
Default: 8010’h
Name
Reserved
Rst_dsp
Bits
15:14
13
Sel_if1_adc1_data_in
1
12
Sel_if1_adc1_data_in
2
11
Sel_if1_adc2_data_in
1
10
Reserved
9:4
Table 121. MX-FAh: General Control 1
Read/Write Reset State Description
R/W
2’h
Reserved
R/W
0’h
Voice DSP Reset Control
0’b: Normal
1’b: Reset
R/W
0’h
Selection-1 for IF1 ADC1 Input Data
0’b: IF_ADC1
1’b: IF_ADC3
R/W
0’h
Selection-2 for IF1 ADC1 Input Data
0’b: IF_ADC1 or IF1_ADC3
1’b: TxDP_ADC
R/W
0’h
Selection for IF1 ADC2 Input Data
0’b: IF_ADC2
1’b: TxDP_ADC
R/W
1’h
Reserved
132
Rev. 0.91
ALC5672-VB
Datasheet
Name
En_detect_clk_sys
Bits
3
Read/Write
R/W
Reserved
digital_gate_ctrl
2:1
0
R
R/W
Reset State Description
0’h
Enable MCLK Detection and Auto Switch to RC Clock
When MCLK is Remove
0’b: Disable
1’b: Enable
0’h
Reserved
0’h
Enable MCLK Gating Control
0’b: Disable
1’b: Enable
10.107. MX-FBh: General Control 2
Default: 0033’h
Name
Reserved
Sel_adcdat1
Reserved
Sel_headset_mode
Bits
15
14
13:12
11
Sel_pow_capless
10
En_sel_in1_p
9
En_sel_in1_n
8
Reserved
Hp_depop_ctrl
7:5
4
Reserved
3:0
Table 122. MX-FBh: General Control 2
Read/Write Reset State Description
R/W
0’h
Reserved
R/W
0’h
Select ADCDAT1 Pin Configuration
0’b: Output
1’b: Input
R/W
0’h
Reserved
R/W
0’h
SLEEVE and RING2 Control for Headset Mode
0'b: For Normal Mode
1'b: For D3 Mode (Tie SLEEVE and RING2 to GND)
R/W
0’h
Headphone Capless Power Control
0’b: Controlled by combo jack function
1’b: Controlled by register (MX-8Eh)
R/W
0’h
IN1P Input Path Control
0’b: Disable
1’b: Enable
R/W
0’h
IN1N Input Path Control
0’b: Disable
1’b: Enable
R/W
1’h
Reserved
R/W
1’h
Headphone De-pop Mode Control
0’b: Disable
1’b: Enable
R/W
3’h
Reserved
133
Rev. 0.91
ALC5672-VB
Datasheet
10.108. MX-FCh: General Control 3
Default: 0080’h
Name
Sel_power_saving_ir
q_1
Bits
15:14
reserved
En_i2s2_mono_mode
13
12
En_i2s_tdm_modeb
11
En_power_saving_irq
10
Sel_power_saving_ir
q_2
9:8
Reserved
7:0
Table 123. MX-FCh: General Control 3
Read/Write Reset State Description
R/W
0’h
Select Option-1 JD Source for IRQ Power Saving Mode
00’b: JD1_1
01’b: JD1_2
10’b: JD2
11’b: JD3
R/W
0’h
Reserved
R/W
0’h
Enable I2S2 Mono Mode
0'b: Disable
1'b: Enable
R/W
0’h
Enable I2S TDM Mode-2
0'b: Disable (TDM Mode-1)
1'b: Enable (TDM Mode-2)
R/W
0’h
Enable IRQ Power Saving Mode
0’b: Disable
1’b: Enable
R/W
0’h
Select Option-2 JD Source for IRQ Power Saving Mode
00’b: JD1_1
01’b: JD1_2
10’b: JD2
11’b: JD3
R/W
0’h
Reserved
10.109. PR-3Dh: ADC/DAC RESET Control
Default: 2808’h
Name
Reserved
En_ckgen_adc
Bits
15:13
12
Reserved
Ckxen_dac
11
10
En_ckgen_dac
9
En_psv_dac
8
Reserved
7:0
Table 124. PR-3Dh: ADC/DAC RESET Control
Read/Write Reset State Description
R/W
1’h
Reserved
R/W
0’h
Enable ADC Clock Generator
0’b: Disable
1’b: Enable
R/W
1’h
Reserved
R/W
0’h
Enable Chopper Function of DAC
0’b: Disable
1’b: Enable
R/W
0’h
Enable DAC Clock Generator
0’b: Disable
1’b: Enable
R/W
0’h
Enable Power Saving Mode of DAC
0’b: Disable
1’b: Enable
R/W
8’h
Reserved
134
Rev. 0.91
ALC5672-VB
Datasheet
10.110. PR-A4h: DAC_L EQ (LPF:a1)
Default: 1C10’h
Name
lpf_a1
Bits
15:0
Table 125. PR-A4h: DAC_L EQ (LPF2:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.111. PR-A5h: DAC_L EQ (LPF:H0)
Default: 01F4’h
Name
lpf_h0
Bits
15:0
Table 126. PR-A5h: DAC_L EQ (LPF2:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.112. PR-A6h: DAC_R EQ (LPF:a1)
Default: 1C10’h
Name
lpf_a1
Bits
15:0
Table 127. PR-A6h: DAC_R EQ (LPF2:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.113. PR-A7h: DAC_R EQ (LPF:H0)
Default: 01F4’h
Name
lpf_h0
Bits
15:0
Table 128. PR-A7h: DAC_R EQ (LPF:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
135
Rev. 0.91
ALC5672-VB
Datasheet
10.114. PR-AEh: DAC_L EQ (BPF2:a1)
Default: C882’h
Name
Bpf2_a1
Bits
15:0
Table 129. PR-AEh: DAC_L EQ (BPF2:a1)
Read/Write Reset State Description
R/W
C882’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.115. PR-AFh: DAC_L EQ (BPF2:a2)
Default: 1C10’h
Name
Bpf2_a2
Bits
15:0
Table 130. PR-AFh: DAC_L EQ (BPF2:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.116. PR-B0h: DAC_L EQ (BPF2:H0)
Default: 01F4’h
Name
Bpf2_h0
Bits
15:0
Table 131. PR-B0h: DAC_L EQ (BPF2:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.117. PR-B1h: DAC_R EQ (BPF2:a1)
Default: C882’h
Name
Bpf2_a1
Bits
15:0
Table 132. PR-B1h: DAC_R EQ (BPF2:a1)
Read/Write Reset State Description
R/W
C882’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
136
Rev. 0.91
ALC5672-VB
Datasheet
10.118. PR-B2h: DAC_R EQ (BPF2:a2)
Default: 1C10’h
Name
Bpf2_a2
Bits
15:0
Table 133. PR-B2h: DAC_R EQ (BPF2:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.119. PR-B3h: DAC_R EQ (BPF2:H0)
Default: 01F4’h
Name
Bpf2_h0
Bits
15:0
Table 134. PR-B3h: DAC_R EQ (BPF2:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.120. PR-B4h: DAC_L EQ (BPF3:a1)
Default: E904’h
Name
Bpf3_a1
Bits
15:0
Table 135. PR-B4h: DAC_L EQ (BPF3:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.121. PR-B5h: DAC_L EQ (BPF3:a2)
Default: 1C10’h
Name
Bpf3_a2
Bits
15:0
Table 136. PR-B5h: DAC_L EQ (BPF3:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
137
Rev. 0.91
ALC5672-VB
Datasheet
10.122. PR-B6h: DAC_L EQ (BPF3:H0)
Default: 01F4’h
Name
Bpf3_h0
Bits
15:0
Table 137. PR-B6h: DAC_L EQ (BPF3:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.123. PR-B7h: DAC_R EQ (BPF3:a1)
Default: E904’h
Name
Bpf3_a1
Bits
15:0
Table 138. PR-B7h: DAC_R EQ (BPF3:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.124. PR-B8h: DAC_R EQ (BPF3:a2)
Default: 1C10’h
Name
Bpf3_a2
Bits
15:0
Table 139. PR-B8h: DAC_R EQ (BPF3:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.125. PR-B9h: DAC_R EQ (BPF3:H0)
Default: 01F4’h
Name
Bpf3_h0
Bits
15:0
Table 140. PR-B9h: DAC_R EQ (BPF3:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
138
Rev. 0.91
ALC5672-VB
Datasheet
10.126. PR-BAh: DAC_L EQ (BPF4:a1)
Default: E904’h
Name
Bpf4_a1
Bits
15:0
Table 141. PR-BAh: DAC_L EQ (BPF4:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.127. PR-BBh: DAC_L EQ (BPF4:a2)
Default: 1C10’h
Name
Bpf4_a2
Bits
15:0
Table 142. PR-BBh: DAC_L EQ (BPF4:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.128. PR-BCh: DAC_L EQ (BPF4:H0)
Default: 01F4’h
Name
Bpf4_h0
Bits
15:0
Table 143. PR-BCh: DAC_L EQ (BPF4:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.129. PR-BDh: DAC_R EQ (BPF4:a1)
Default: E904’h
Name
Bpf4_a1
Bits
15:0
Table 144. PR-BDh: DAC_R EQ (BPF4:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
139
Rev. 0.91
ALC5672-VB
Datasheet
10.130. PR-BEh: DAC_R EQ (BPF4:a2)
Default: 1C10’h
Name
Bpf4_a2
Bits
15:0
Table 145. PR-BEh: DAC_R EQ (BPF4:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.131. PR-BFh: DAC_R EQ (BPF4:H0)
Default: 01F4’h
Name
Bpf4_h0
Bits
15:0
Table 146. PR-BFh: DAC_R EQ (BPF4:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.132. PR-C0h: DAC_L EQ (HPF1:a1)
Default: 1C10’h
Name
Hpf1_a1
Bits
15:0
Table 147. PR-C0h: DAC_L EQ (HPF1:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.133. PR-C1h: DAC_L EQ (HPF1:H0)
Default: 01F4’h
Name
Hpf1_h0
Bits
15:0
Table 148. PR-C1h: DAC_L EQ (HPF1:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
140
Rev. 0.91
ALC5672-VB
Datasheet
10.134. PR-C2h: DAC_R EQ (HPF1:a1)
Default: 1C10’h
Name
Hpf1_a1
Bits
15:0
Table 149. PR-C2h: DAC_R EQ (HPF1:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.135. PR-C3h: DAC_R EQ (HPF1:H0)
Default: 01F4’h
Name
Hpf1_h0
Bits
15:0
Table 150. PR-C3h: DAC_R EQ (HPF1:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.136. PR-C4h: DAC_L EQ (HPF2:a1)
Default: 2000’h
Name
Hpf2_a1
Bits
15:0
Table 151. PR-C4h: DAC_L EQ (HPF2:a1)
Read/Write Reset State Description
R/W
2000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.137. PR-C5h: DAC_L EQ (HPF2:a2)
Default: 0000’h
Name
Hpf2_a2
Bits
15:0
Table 152. PR-C5h: DAC_L EQ (HPF2:a2)
Read/Write Reset State Description
R/W
0000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
141
Rev. 0.91
ALC5672-VB
Datasheet
10.138. PR-C6h: DAC_L EQ (HPF2:H0)
Default: 1FF1’h
Name
Hpf2_h0
Bits
15:0
Table 153. PR-C6h: DAC_L EQ (HPF2:H0)
Read/Write Reset State Description
R/W
1FF1’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.139. PR-C7h: DAC_R EQ (HPF2:a1)
Default: 2000’h
Name
Hpf2_a1
Bits
15:0
Table 154. PR-C7h: DAC_R EQ (HPF2:a1)
Read/Write Reset State Description
R/W
2000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.140. PR-C8h: DAC_R EQ (HPF2:a2)
Default: 0000’h
Name
Hpf2_a2
Bits
15:0
Table 155. PR-C8h: DAC_R EQ (HPF2:a2)
Read/Write Reset State Description
R/W
0000’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.141. PR-C9h: DAC_R EQ (HPF2:H0)
Default: 1FF1’h
Name
Hpf2_h0
Bits
15:0
Table 156. PR-C9h: DAC_R EQ (HPF2:H0)
Read/Write Reset State Description
R/W
1FF1’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
142
Rev. 0.91
ALC5672-VB
Datasheet
10.142. PR-CAh: DAC_L EQ Pre-Volume Control
Default: 0800’h
Name
Da_eq_pre_vol_l
Table 157. PR-CAh: DAC_L EQ Pre-Volume Control
Bits Read/Write Reset State Description
15:0
R/W
0800’h
DAC Left Channel EQ Pre-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
10.143. PR-CBh: DAC_R EQ Pre-Volume Control
Default: 0800’h
Name
Da_eq_pre_vol_l
Bits
15:0
Table 158. PR-CBh: DAC_R EQ Pre-Volume Control
Read/Write Reset State Description
R/W
0800’h
DAC Right Channel EQ Pre-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
10.144. PR-CCh: DAC_L EQ Post-Volume Control
Default: 0800’h
Name
Da_eq_post_vol_l
Table 159. PR-CCh: DAC_L EQ Post-Volume Control
Bits Read/Write Reset State Description
15:0
R/W
0800’h
DAC Left Channel EQ Post-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
143
Rev. 0.91
ALC5672-VB
Datasheet
10.145. PR-CDh: DAC_R EQ Post-Volume Control
Default: 0800’h
Name
Da_eq_post_vol_l
Table 160. PR-CDh: DAC_R EQ Post-Volume Control
Bits Read/Write Reset State Description
15:0
R/W
0800’h
DAC Right Channel EQ Post-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
10.146. PR-CEh: ADC EQ (LPF:a1)
Default: 1C10’h
Name
ad_eq_lpf_a1
Bits
15:0
Table 161. PR-CEh: ADC EQ (LPF:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.147. PR-CFh: ADC EQ (LPF:H0)
Default: 01F4’h
Name
ad_eq_lpf_h0
Bits
15:0
Table 162. PR-CFh: ADC EQ (LPF:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.148. PR-D0h: ADC EQ (BPF1:a1)
Default: E904’h
Name
ad_eq_Bpf1_a1
Bits
15:0
Table 163. PR-D0h: ADC EQ (BPF1:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
144
Rev. 0.91
ALC5672-VB
Datasheet
10.149. PR-D1h: ADC EQ (BPF1:a2)
Default: 1C10’h
Name
Ad_eq_Bpf1_a2
Bits
15:0
Table 164. PR-D1h: ADC EQ (BPF1:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.150. PR-D2h: ADC EQ (BPF1:H0)
Default: 01F4’h
Name
ad_eq_Bpf1_h0
Bits
15:0
Table 165. PR-D2h: ADC EQ (BPF1:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.151. PR-D3h: ADC EQ (BPF2:a1)
Default: E904’h
Name
ad_eq_Bpf2_a1
Bits
15:0
Table 166. PR-D3h: ADC EQ (BPF2:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.152. PR-D4h: ADC EQ (BPF2:a2)
Default: 1C10’h
Name
Ad_eq_Bpf2_a2
Bits
15:0
Table 167. PR-D4h: ADC EQ (BPF2:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
145
Rev. 0.91
ALC5672-VB
Datasheet
10.153. PR-D5h: ADC EQ (BPF2:H0)
Default: 01F4’h
Name
ad_eq_Bpf2_h0
Bits
15:0
Table 168. PR-D5h: ADC EQ (BPF2:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.154. PR-D6h: ADC EQ (BPF3:a1)
Default: E904’h
Name
ad_eq_Bpf3_a1
Bits
15:0
Table 169. PR-D6h: ADC EQ (BPF3:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.155. PR-D7h: ADC EQ (BPF3:a2)
Default: 1C10’h
Name
Ad_eq_Bpf3_a2
Bits
15:0
Table 170. PR-D7h: ADC EQ (BPF3:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.156. PR-D8h: ADC EQ (BPF3:H0)
Default: 01F4’h
Name
ad_eq_Bpf3_h0
Bits
15:0
Table 171. PR-D8h: ADC EQ (BPF3:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
146
Rev. 0.91
ALC5672-VB
Datasheet
10.157. PR-D9h: ADC EQ (BPF4:a1)
Default: E904’h
Name
ad_eq_Bpf4_a1
Bits
15:0
Table 172. PR-D9h: ADC EQ (BPF4:a1)
Read/Write Reset State Description
R/W
E904’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
10.158. PR-DAh: ADC EQ (BPF4:a2)
Default: 1C10’h
Name
Ad_eq_Bpf4_a2
Bits
15:0
Table 173. PR-DAh: ADC EQ (BPF4:a2)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a2 should be in -2 ~ 1.99)
10.159. PR-DBh: ADC EQ (BPF4:H0)
Default: 01F4’h
Name
ad_eq_Bpf4_h0
Bits
15:0
Table 174. PR-DBh: ADC EQ (BPF4:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.160. PR-DCh: ADC EQ (HPF1:a1)
Default: 1C10’h
Name
Ad_eq_hpf1_a1
Bits
15:0
Table 175. PR-DCh: ADC EQ (HPF1:a1)
Read/Write Reset State Description
R/W
1C10’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the a1 should be in -2 ~ 1.99)
147
Rev. 0.91
ALC5672-VB
Datasheet
10.161. PR-DDh: ADC EQ (HPF1:H0)
Default: 01F4’h
Name
ad_eq_hpf1_h0
Bits
15:0
Table 176. PR-DDh: ADC EQ (HPF1:H0)
Read/Write Reset State Description
R/W
01F4’h
2’s complement in 3.13 format. (The range is from –4~3.99,
the H0 should be in -4 ~ 3.99)
10.162. PR-E1h: ADC EQ Pre-Volume Control
Default: 0800’h
Name
ad_eq_pre_vol
Bits
15:0
Table 177. PR-E1h: ADC EQ Pre-Volume Control
Read/Write Reset State Description
R/W
0800’h
ADC Left Channel EQ Pre-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
10.163. PR-E2h: ADC EQ Post-Volume Control
Default: 0800’h
Name
Ad_eq_post_vol
Bits
15:0
Table 178. PR-E2h: ADC EQ Post-Volume Control
Read/Write Reset State Description
R/W
0800’h
ADC Left Channel EQ Post-Volume Control
2’s Complement in 5.11 Format. (Default is 0dB)
The range is from -16 ~ 15.99, pre-gain should be in 0 ~
15.99 [+24dB ~ -66dB]
10.164. PR-E5h: DAC_L Biquad EQ (BPF1:h0-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_h0_l_msb
12:0
Table 179. PR-E5h: DAC_L Biquad EQ (BPF1:h0-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
148
Rev. 0.91
ALC5672-VB
Datasheet
10.165. PR-E6h: DAC_L Biquad EQ (BPF1:h0-2)
Default: 0000’h
Name
Eq_biquad_h0_l_lsb
Table 180. PR-E6h: DAC_L Biquad EQ (BPF1:h0-2)
Bits Read/Write Reset State Description
15:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.166. PR-E7h: DAC_L Biquad EQ (BPF1:b1-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_b1_l_msb
12:0
Table 181. PR-E7h: DAC_L Biquad EQ (BPF1:b1-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.167. PR-E8h: DAC_L Biquad EQ (BPF1:b1-2)
Default: 0000’h
Name
Eq_biquad_b1_l_lsb
Bits
15:0
Table 182. PR-E8h: DAC_L Biquad EQ (BPF1:b1-2)
Read/Write Reset State Description
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.168. PR-E9h: DAC_L Biquad EQ (BPF1:b2-1)
Default: 0000’h
Name
Reserved
Table 183. PR-E9h: DAC_L Biquad EQ (BPF1:b2-1)
Bits Read/Write Reset State Description
15:13
R
0’h
Reserved
Eq_biquad_b2_l_msb
12:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
149
Rev. 0.91
ALC5672-VB
Datasheet
10.169. PR-EAh: DAC_L Biquad EQ (BPF1:b2-2)
Default: 0000’h
Name
Eq_biquad_b2_l_lsb
Table 184. PR-EAh: DAC_L Biquad EQ (BPF1:b2-2)
Bits Read/Write Reset State Description
15:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.170. PR-EBh: DAC_L Biquad EQ (BPF1:a1-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_a1_l_msb
12:0
Table 185. PR-EBh: DAC_L Biquad EQ (BPF1:a1-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.171. PR-ECh: DAC_L Biquad EQ (BPF1:a1-2)
Default: 0000’h
Name
Eq_biquad_a1_l_lsb
Bits
15:0
Table 186. PR-ECh: DAC_L Biquad EQ (BPF1:a1-2)
Read/Write Reset State Description
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.172. PR-EDh: DAC_L Biquad EQ (BPF1:a2-1)
Default: 0000’h
Name
Reserved
Table 187. PR-EDh: DAC_L Biquad EQ (BPF1:a2-1)
Bits Read/Write Reset State Description
15:13
R
0’h
Reserved
Eq_biquad_a2_l_msb
12:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
150
Rev. 0.91
ALC5672-VB
Datasheet
10.173. PR-EEh: DAC_L Biquad EQ (BPF1:a2-2)
Default: 0000’h
Name
Eq_biquad_a2_l_lsb
Table 188. PR-EEh: DAC_L Biquad EQ (BPF1:a2-2)
Bits Read/Write Reset State Description
15:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.174. PR-EFh: DAC_R Biquad EQ (BPF1:h0-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_h0_r_msb
12:0
Table 189. PR-EFh: DAC_R Biquad EQ (BPF1:h0-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.175. PR-F0h: DAC_R Biquad EQ (BPF1:h0-2)
Default: 0000’h
Name
Eq_biquad_h0_r_lsb
Bits
15:0
Table 190. PR-F0h: DAC_R Biquad EQ (BPF1:h0-2)
Read/Write Reset State Description
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.176. PR-F1h: DAC_R Biquad EQ (BPF1:b1-1)
Default: 0000’h
Name
Reserved
Table 191. PR-F1h: DAC_R Biquad EQ (BPF1:b1-1)
Bits Read/Write Reset State Description
15:13
R
0’h
Reserved
Eq_biquad_b1_r_msb
12:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
151
Rev. 0.91
ALC5672-VB
Datasheet
10.177. PR-F2h: DAC_R Biquad EQ (BPF1:b1-2)
Default: 0000’h
Name
Eq_biquad_b1_r_lsb
Table 192. PR-F2h: DAC_R Biquad EQ (BPF1:b1-2)
Bits Read/Write Reset State Description
15:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.178. PR-F3h: DAC_R Biquad EQ (BPF1:b2-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_b2_r_msb
12:0
Table 193. PR-F3h: DAC_R Biquad EQ (BPF1:b2-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.179. PR-F4h: DAC_R Biquad EQ (BPF1:b2-2)
Default: 0000’h
Name
Eq_biquad_b2_r_lsb
Bits
15:0
Table 194. PR-F4h: DAC_R Biquad EQ (BPF1:b2-2)
Read/Write Reset State Description
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.180. PR-F5h: DAC_R Biquad EQ (BPF1:a1-1)
Default: 0000’h
Name
Reserved
Table 195. PR-F5h: DAC_R Biquad EQ (BPF1:a1-1)
Bits Read/Write Reset State Description
15:13
R
0’h
Reserved
Eq_biquad_a1_r_msb
12:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
152
Rev. 0.91
ALC5672-VB
Datasheet
10.181. PR-F6h: DAC_R Biquad EQ (BPF1:a1-2)
Default: 0000’h
Name
Eq_biquad_a1_r_lsb
Table 196. PR-F6h: DAC_R Biquad EQ (BPF1:a1-2)
Bits Read/Write Reset State Description
15:0
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.182. PR-F7h: DAC_R Biquad EQ (BPF1:a2-1)
Default: 0000’h
Name
Reserved
Bits
15:13
Eq_biquad_a2_r_msb
12:0
Table 197. PR-F7h: DAC_R Biquad EQ (BPF1:a2-1)
Read/Write Reset State Description
R
0’h
Reserved
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.183. PR-F8h: DAC_R Biquad EQ (BPF1:a2-2)
Default: 0000’h
Name
Eq_biquad_a2_r_lsb
Bits
15:0
Table 198. PR-F8h: DAC_R Biquad EQ (BPF1:a2-2)
Read/Write Reset State Description
R/W
0’h
2’s complement in 4.25 format. (The range is from –8~7.99)
10.184. MX-FEh: Vendor ID
Default: 10EC’h
Name
Vendor_id
Bits
15:0
Table 199. MX-FEh: Vendor ID
Read/Write Reset State Description
R
10EC’h
Vendor ID
153
Rev. 0.91
ALC5672-VB
Datasheet
11. Electrical Characteristics
11.1. DC Characteristics
11.1.1. Absolute Maximum Ratings
Table 200. Absolute Maximum Ratings
Parameter
Symbol
Min
Typ
Power Supplies
Digital IO Buffer
DBVDD
-0.3
Digital Core
DCVDD
-0.3
Analog
AVDD
-0.3
Headphone
CPVDD
-0.3
Micbias
MICVDD
-0.3
Speaker
SPKVDD
-0.3
Operating Ambient Temperature
Ta
-25
Storage Temperature
Ts
-55
Note 1: SPKVDD=5V with 3.5% duty cycle Power bouncing up to SPKVDD=7V is acceptable.
Max
Units
3.63
1.4
1.98
1.98
3.63
71
+85
+125
V
V
V
V
V
V
o
C
o
C
11.1.2. Recommended Operating Conditions
Table 201. Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Units
Digital IO Buffer
DBVDD
1.71
1.8
3.6
V
Digital Core
DCVDD
1.05
1.2
1.3
V
Analog
AVDD
1.71
1.8
1.9
V
Analog
DACREF
1.71
1.8
1.9
V
Headphone
CPVDD
1.71
1.8
1.9
V
Micbias
MICVDD
3.0
3.3
3.6
V
Speaker
SPKVDD1
3.0
3.6/5.0
5.5
V
Note 1: A 10µF Capacitor must be connected from SPKVDD to SPKGND, and should be placed as close as possible to
the SPKVDD pin.
11.1.3. Static Characteristics
Table 202. Static Characteristics
Parameter
Symbol
Min
Typ
Input Voltage Range
VIN
-0.30
Low Level Input Voltage
VIL
High Level Input Voltage
VIH
0.65DBVDD
High Level Output Voltage
VOH
0.9DBVDD
Low Level Output Voltage
VOL
Output Buffer High Drive Current
15
Output Buffer Low Drive Current
14.7
Input Buffer Pull-Up Resistor
125
148
Input Buffer Pull-Down Resistor
193
225
Note: DBVDD=1.8V, DCVDD=1.2V, Tambient=40C.
154
Max
DBVDD+0.30
0.35DBVDD
0.1DBVDD
180
266
Units
V
V
V
V
V
mA
mA
K
K
Rev. 0.91
ALC5672-VB
Datasheet
11.2. Analog Performance Characteristics
Table 203. Analog Performance Characteristics
Parameter
Min
Typ
Full Scale Input Voltage
Line Inputs (Single-ended)
0.6
MIC Inputs (Single-ended )
0.6
MIC Inputs (Differential)
1.2
Full Scale Output Voltage
Line Outputs (Single-ended)
1.0
Line Outputs (Differential)
1.0
Headphone Amplifiers Outputs (For 10KOhm Load)
1.0
Headphone Amplifiers Outputs (For 16Ohm Load)
0.9
Headphone Amplifiers Outputs (For 32Ohm Load)
1.0
Speaker Amplifiers Outputs
2.9
(SPKVDD=5.0V with 4 Load, 1% THD+N)
S/N Ratio
Stereo DAC Direct to HP_L/R with 16/32/10KOhm
100
Stereo DAC Direct to SPK_OUT with 8Ohm/5V (Differential)
93
Line_In to Stereo ADC with 0dB (Single-end)
MIC_In to Stereo ADC with 0dB (Differential or Single-end)
MIC_In to Stereo ADC with 20dB and MICBIAS (Differential or
Single-end)
MIC_In to Stereo ADC with 40dB and MICBIAS (Differential or
Single-end)
MIC_In to Stereo ADC with 50dB and MICBIAS (Differential or
Single-end)
Total Harmonic Distortion + Noise
DAC Direct to HP_L/R with 16Ohm
Po = 20mW/CH (16Ohm) (with AES17 Filter)
Po = 20mW/CH (32Ohm) (with AES17 Filter)
93
93
85
Max
Units
-
Vrms
Vrms
Vrms
-
Vrms
Vrms
Vrms
Vrms
Vrms
Vrms
102
dBA
dBA
95
95
dBA
dBA
dBA
72
dBA
65
dBA
-81
-81
-83
-83
dB
dB
DAC Direct to HP_L/R with 10KOhm
-3dBFS
-85
dB
DAC Direct to SPK_OUT (Differential)
Po=1.2W (5V/8Ohm)
Po=2.1W (5V/4Ohm)
Po=920mW (4.2V/8Ohm)
Po=650mW (3.6V/8Ohm)
