CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
CA-IS372x High-Speed Dual-Channel Digital Isolators
1.
Key Features
•
•
•
•
•
•
•
•
Signal Rate: DC to 150Mbps
Wide Operating Supply Voltage: 2.5V to 5.5V
Wide Operating Temperature Range: -40°C to 125°C
No Start-Up Initialization Required
Default Output High and Low Options
High Electromagnetic Immunity
High CMTI: ±100kV/µs (Typical)
Low Power Consumption (Typical):
▪
1.5mA per Channel at 1Mbps with 5.0V Supply
▪
6.6mA per Channel at 100Mbps with 5.0V Supply
Precise Timing (Typical)
▪
8ns Propagation Delay
▪
1ns Pulse Width Distortion
▪
2ns Propagation Delay Skew
▪
5ns Minimum Pulse Width
Isolation Rating up to 5.0kVrms
Isolation Barrier Life: >40 Years
Schmitt Trigger Inputs
RoHS-Compliant Packages
▪
SOIC8
▪
SOIC8 Wide Body
•
•
•
•
•
2.
Applications
•
•
•
•
•
•
Industrial Automation Systems
Motor Control
Medical Electronics
Isolated Switch Mode Supplies
Solar Inverters
Isolated ADC, DAC
3.
Description
two channels in the same direction, the CA-IS3721 device
has one forward and one reverse-direction channels, and
the CA-IS3722 device has the channel configuration that is
opposite to CA-IS3721. All devices have fail-safe mode
option. If the input power or signal is lost, default output is
low for devices with suffix L and high for devices with suffix
H.
CA-IS372x devices has high insulation capability to handle
noise and surge on a data bus or other circuits from entering
the local ground and interfering with or damaging sensitive
circuitry. High CMTI ability promises the correct
transmission of digital signal. The CA-IS372x devices are
available in 8-pin SOIC and 8-pin wide body SOIC packages.
And the CA-IS372x devices are also available in 8-pin wide
body SOIC package. All products have 3.75kVrms isolation
rating, and products in wide-body packages support
insulation withstanding up to 5kVrms.
Device Information
PART
NUMBER
CA-IS3720,
CA-IS3721,
CA-IS3722
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
BODY SIZE(NOM)
SOIC8 (S)
4.90 mm × 3.90 mm
SOIC8-WB(G)
5.85 mm ×7.50 mm
Simplified Channel Structure
Channel A side
Schmitt Trigger
The CA-IS372x devices are high-performance dual - channel
digital isolators with precise timing characteristics and low
power consumption. The CA-IS372x devices provide high
electromagnetic immunity and low emissions, while
isolating CMOS digital I/Os. All device versions have Schmitt
trigger input for high noise immunity. Each isolation channel
consists of a transmitter and a receiver separated by silicon
dioxide (SiO2) insulation barrier. The CA-IS3720 device has
PACKAGE
Isolation
Barrrier
Channel B side
Mixer
VIN
Driver
VOUT
Driver
RX
GNDA
GNDB
Channel A side and B side are separated by isolation
capacitors. GNDA and GNDB are the isolated ground for
signals and supplies of A side and B side respectively.
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
4.
Ordering Guide
Table 4-1 Ordering Guide for Valid Ordering Part Number
Ordering Part Number
Number of Inputs
A Side
Number of Inputs
B Side
Default
Output
Isolation
Rating (kV)
Output
Enable
Package
CA-IS3720LS
2
0
Low
3.75
No
SOIC8
CA-IS3720LG
2
0
Low
5.0
No
SOIC8-WB
CA-IS3720HS
2
0
High
3.75
No
SOIC8
CA-IS3720HG
2
0
High
5.0
No
SOIC8-WB
CA-IS3721LS
1
1
Low
3.75
No
SOIC8
CA-IS3721LG
1
1
Low
5.0
No
SOIC8-WB
CA-IS3721HS
1
1
High
3.75
No
SOIC8
CA-IS3721HG
1
1
High
5.0
No
SOIC8-WB
CA-IS3722LS
1
1
Low
3.75
No
SOIC8
CA-IS3722LG
1
1
Low
5.0
No
SOIC8-WB
CA-IS3722HS
1
1
High
3.75
No
SOIC8
CA-IS3722HG
1
1
High
5.0
No
SOIC8-WB
2
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
Table of Contents
1.
2.
3.
4.
5.
6.
6.9.1.
6.9.2.
6.9.3.
Key Features .......................................................1
Applications ........................................................1
Description .........................................................1
Ordering Guide ...................................................2
PIN Descriptions and Functions ...........................4
Specifications......................................................5
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
Absolute Maximum Ratings ................................5
ESD Ratings..........................................................5
Recommended Operating Conditions .................5
Thermal Information ...........................................6
Power Rating .......................................................6
Insulation Specifications .....................................7
Safety-Related Certifications ...............................8
Electrical Characteristics .....................................9
6.8.1.
6.8.2.
6.8.3.
6.9.
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C..........9
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C.......9
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C.........9
6.10.
Timing Characteristics ....................................... 13
6.10.1.
6.10.2.
6.10.3.
7.
8.
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C ....... 10
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C .... 11
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C ...... 12
VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C... 13
VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C 13
VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C.. 13
Parameter Measurement Information ............... 14
Detailed Description ......................................... 16
8.1.
8.2.
8.3.
Theory of Operation ......................................... 16
Functional Block Diagram ................................. 16
Device Operation Modes .................................. 17
9. Application and Implementation ....................... 18
10. Package Information ......................................... 19
10.1.
10.2.
8-Pin SOIC Package ........................................... 19
8-Pin Wide Body SOIC Package ......................... 20
TAPE AND REEL INFORMATION ................................. 21
Supply Current Characteristics ..........................10
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
3
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
5.
PIN Descriptions and Functions
CA-IS3720 8-Pin SOIC Top View
1
VI1
2
TX
VI2
3
TX
GNDA
4
ISOLATION
BARRIER
VDDA
8
VDDB
RX
7
VO1
RX
6
VO2
5
GNDB
8
VDDB
RX
7
VO1
TX
6
VI2
5
GNDB
8
VDDB
TX
7
VI1
RX
6
VO2
5
GNDB
CA-IS3721 8-Pin SOIC Top View
1
VI1
2
TX
VO2
3
RX
GNDA
4
ISOLATION
BARRIER
VDDA
CA-IS3722 8-Pin SOIC Top View
1
VO1
2
RX
VI2
3
TX
GNDA
4
ISOLATION
BARRIER
VDDA
Figure 5-1 CA-IS372x in 8-Pin SOIC and 8-Pin Wide Body SOIC Package Top View
Table 5-1 CA-IS372x in 8-Pin SOIC and 8-Pin Wide Body SOIC Package Pin Description and Functions
Name
VDDA
VI1/VO1
VI2/VO2
GNDA
GNDB
VI2/VO2
VI1/VO1
VDDB
4
SOIC8 Pin#
1
2
3
4
5
6
7
8
Type
Supply
Digital I/O
Digital I/O
Ground
Ground
Digital I/O
Digital I/O
Supply
Description
Side A Power Supply
Side A Digital Input for CA-IS3720/21 or Output for CA-IS3722
Side A Digital Input for CA-IS3720/22 or Output for CA-IS3721.
Side A Ground
Side B Ground
Side B Digital Input for CA-IS3721 or Output for CA-IS3720/22.
Side B Digital Input for CA-IS3722 or Output for CA-IS3720/21.
Side B Power Supply
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6. Specifications
6.1.
Absolute Maximum Ratings1
MIN
-0.5
-0.5
-20
Voltage2
MAX
6.0
VDDA+0.53
20
150
150
UNIT
V
V
mA
°C
°C
VDDA, VDDB
Supply
Vin
Voltage at Ax, Bx, ENx
IO
Output Current
TJ
Junction Temperature
TSTG
Storage Temperature
-65
NOTE:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2. All voltage values except differential I/O bus voltages are with respect to the local ground terminal (GNDA or GNDB) and are peak voltage
values.
3. Maximum voltage must not exceed 6 V.
6.2.
ESD Ratings
VESD Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins1
VALUE
±4000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins2
±1000
UNIT
V
NOTE:
1. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
2. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3.
Recommended Operating Conditions
VDDA, VDDB
VDD（UVLO+）
Supply Voltage
VDD Undervoltage Threshold When Supply Voltage is Rising
MIN
2.375
1.95
TYP
3.3
2.24
MAX
5.5
2.375
VDD（UVLO-）
VDD Undervoltage Threshold When Supply Voltage is Falling
1.88
2.10
2.325
VHYS（UVLO）
VDD Undervoltage Threshold Hysteresis
70
140
250
IOH
High-level Output Current
IOL
Low-level Output Current
VIH
High-level Input Voltage
VIL
Low-level Input Voltage
DR
Data Rate
TA
Ambient Temperature
NOTE:
1. VDDO = Output-side VDD
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
VDDO1 = 5V
VDDO = 3.3V
VDDO = 2.5V
VDDO = 5V
VDDO = 3.3V
VDDO = 2.5V
-4
-2
-1
V
mV
mA
4
2
1
2.0
0
-40
UNIT
V
V
27
0.8
150
125
mA
V
V
Mbps
°C
5
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.4.
Thermal Information
CA-IS372x
S (SOIC)
G(SOIC)
8 Pins
8 Pins
109.0
92.3
54.4
45.3
52.0
50.5
13.2
14.0
THERMAL METRIC
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
Junction-to-case(top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
ψJB
Junction-to-board characterization parameter
RθJC(bottom)
Junction-to-case(bottom) thermal resistance
6.5.
49.3
n/a
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Power Rating
PARAMETER
CA-IS3720
PD
PDA
PDB
CA-IS3721
PD
PDA
PDB
CA-IS3722
PD
PDA
PDB
6
51.5
n/a
UNIT
TEST CONDITIONS
Maximum Power Dissipation
Maximum Power Dissipation on Side-A
Maximum Power Dissipation on Side-B
VDDA = VDDB = 5.5 V, CL = 15 pF,
Maximum Power Dissipation
Maximum Power Dissipation on Side-A
Maximum Power Dissipation on Side-B
VDDA = VDDB = 5.5 V, CL = 15 pF,
Maximum Power Dissipation
Maximum Power Dissipation on Side-A
Maximum Power Dissipation on Side-B
VDDA = VDDB = 5.5 V, CL = 15 pF,
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
TJ = 150°C, Input a 75-MHz 50% duty
cycle square wave
MIN
TYP
MAX
UNIT
120
20
100
mW
mW
mW
120
60
60
mW
mW
mW
120
60
60
mW
mW
mW
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.6. Insulation Specifications
PARAMETR
CLR
External clearance1
CPG
External creepage1
DTI
CTI
Distance through the insulation
Comparative tracking index
Material group
Overvoltage category per IEC 60664-1
DIN V VDE V 0884-11:2017-012
VIORM
Maximum repetitive peak isolation voltage
VIOWM
Maximum working isolation voltage
VIOTM
Maximum transient isolation voltage
VIOSM
Maximum surge isolation voltage3
qpd
Apparent charge4
CIO
Barrier capacitance, input to output5
RIO
Isolation resistance5
TEST CONDITIONS
Shortest terminal-to-terminal distance through air
Shortest terminal-to-terminal distance across the
package surface
Minimum internal gap (internal clearance)
DIN EN 60112 (VDE 0303-11); IEC 60112
According to IEC 60664-1
Rated mains voltage ≤ 300 VRMS
Rated mains voltage ≤ 400 VRMS
Rated mains voltage ≤ 600 VRMS
AC voltage (bipolar)
AC voltage; Time dependent dielectric breakdown
(TDDB) Test
DC voltage
VTEST = VIOTM,
t = 60 s (qualification);
VTEST = 1.2 × VIOTM,
t= 1 s (100% production)
Test method per IEC 60065, 1.2/50 μs waveform,
VTEST = 1.6 × VIOSM (qualification)
Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.2 × VIORM, tm = 10 s
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s;
Vpd(m) = 1.6 × VIORM, tm = 10 s
Method b1, At routine test (100% production) and
preconditioning (type test)
Vini = 1.2 × VIOTM, tini = 1 s;
Vpd(m) = 1.875 × VIORM, tm = 1 s
VIO = 0.4 × sin (2πft), f = 1 MHz
VIO = 500 V, TA = 25°C
VIO = 500 V, 100°C ≤ TA ≤ 125°C
VIO = 500 V at TS = 150°C
Pollution degree
VALUE
UNIT
G
8
S
4
8
4
mm
14
>600
I
I-IV
I-IV
I-III
14
>600
I
I-III
I-III
n/a
μm
V
1414
637
VPK
1000
450
VRMS
1414
637
VDC
7070
5300
VPK
6250
5000
VPK
≤5
≤5
≤5
≤5
≤5
≤5
~0.5
>1012
>1011
>109
2
~0.5
>1012
>1011
>109
2
pF
5000
3750
VRMS
mm
pC
Ω
UL 1577
VISO
Maximum withstanding isolation voltage
VTEST = VISO , t = 60 s (qualification),
VTEST = 1.2 × VISO , t = 1 s (100% production)
NOTE:
1.
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care
should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the
printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases.
Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
2.
This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by
means of suitable protective circuits.
3.
Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
4.
Apparent charge is electrical discharge caused by a partial discharge (pd).
5.
All pins on each side of the barrier tied together creating a two-terminal device.
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
7
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.7.
Safety-Related Certifications
VDE(Pending)
CSA(Pending)
Certified according to DIN
V VDE V 0884-11:2017-01
Certified according to IEC
60950-1, IEC 62368-1 and
IEC 60601-1
8
UL(Pending)
CQC(Pending)
Recognized under UL
1577 Component
Recognition Program
Certified according to
GB4943.1-2011
TUV(Pending)
Certified according to EN
61010-1:2010 (3rd Ed)
and EN 609501:2006/A2:2013
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.8. Electrical Characteristics
6.8.1. VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
TEST CONDITIONS
IOH = -4mA; See Figure 7-1
IOL = 4mA; See Figure 7-1
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
1
VI = VDDI or 0 V, VCM = 1200 V; See Figure 7-3
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 5 V
MIN
TYP
VDDO1-0.4 4.8
0.2
1.4
1.67
1.0
1.23
0.30
0.44
MAX
0.4
1.9
1.4
0.50
4
-4
75
50
100
2
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µS
pF
NOTE:
1.
2.
3.
VDDI = Input-side VDD, VDDO = Output-side VDD
The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
Measured from pin to Ground.
6.8.2. VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
TEST CONDITIONS
IOH = -4mA; See Figure 7-1
IOL = 4mA; See Figure 7-1
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
VI = VDDI1 or 0 V, VCM = 1200 V; See Figure 7-3
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 3.3 V
MIN
TYP
VDDO1-0.4 3.1
0.2
1.4
1.67
1.0
1.23
0.30
0.44
MAX
0.4
1.9
1.4
0.50
4
-4
75
50
100
2
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µs
pF
NOTE:
1. VDDI = Input-side VDD, VDDO = Output-side VDD
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
3. Measured from pin to Ground.
6.8.3. VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
VOH
VOL
VIT+(IN)
VIT-(IN)
VI(HYS)
IIH
IIL
ZO
CMTI
CI
PARAMETER
High-level Output Voltage
Low-level Output Voltage
Positive-going Input Threshold
Negative-going Input Threshold
Input Threshold Hysteresis
High-Level Input Leakage Current
Low-Level Input Leakage Current
Output Impedance2
Common-mode Transient Immunity
Input Capacitance3
TEST CONDITIONS
IOH = -4mA; See Figure 7-1
IOL = 4mA; See Figure 7-1
VIH = VDDA at Ax or Bx or ENx
VIL = 0 V at Ax or Bx
VI = VDDI1 or 0 V, VCM = 1200 V; See Figure 7-3
VI = VDD/ 2 + 0.4×sin(2πft), f = 1 MHz,
VDD = 2.5 V
MIN
TYP
VDDO1-0.4 2.3
0.2
1.4
1.67
1.0
1.23
0.30
0.44
-4
75
50
100
2
MAX
0.4
1.9
1.4
0.50
4
UNIT
V
V
V
V
V
µA
µA
Ω
kV/µS
pF
NOTE:
1. VDDI = Input-side VDD, VDDO = Output-side VDD
2. The nominal output impedance of an isolator driver channel is approximately 50 Ω ± 40%.
3. Measured from pin to Ground.
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
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CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.9.
Supply Current Characteristics
6.9.1. VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
PARAMETER
SUPPLY
CURRENT
TEST CONDITION
MIN
TYP
MAX
UNIT
CA-IS3720
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3720L);
VIN = VDDI1 (CA-IS3720H)
VIN = VDDI (CA-IS3720L);
VIN = 0V(CA-IS3720H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
0.8
1.6
2.3
1.6
1.6
1.7
1.6
2.7
1.6
12.2
1.2
2.3
3.5
2.4
2.3
2.6
2.3
4.0
2.3
18.2
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.2
2.2
7.0
7.0
2.0
2.0
3.1
3.1
2.6
2.6
3.3
3.3
10.5
10.5
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.2
2.2
7.0
7.0
2.0
2.0
3.1
3.1
2.6
2.6
3.3
3.3
10.5
10.5
mA
CA-IS3721
Supply Curr2.0ent – DC Signal
Supply Curre3.1nt – AC Signal
VIN = 0V (CA-IS3721L);
VIN = VDDI (CA-IS3721H)
VIN = VDDI (CA-IS3721L);
VIN = 0V(CA-IS3721H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
CA-IS3722
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3722L);
VIN = VDDI (CA-IS3722H)
VIN = VDDI (CA-IS3722L);
VIN = 0V(CA-IS3722H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
Note:
1. VDDI = Input-side VDD
10
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CA-IS3720, CA-IS3721, CA-IS3722
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6.9.2. VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
PARAMETER
SUPPLY
CURRENT
TEST CONDITION
MIN
TYP
MAX
UNIT
CA-IS3720
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3720L);
VIN = VDDI1 (CA-IS3720H)
VIN = VDDI (CA-IS3720L);
VIN = 0V(CA-IS3720H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
0.8
1.6
2.3
1.6
1.6
1.7
1.6
2.4
1.6
9.2
1.2
2.3
3.5
2.4
2.3
2.6
2.3
3.6
2.3
13.7
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.1
2.1
5.5
5.5
2.0
2.0
3.1
3.1
2.6
2.6
3.2
3.2
8.2
8.2
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.1
2.1
5.5
5.5
2.0
2.0
3.1
3.1
2.6
2.6
3.2
3.2
8.2
8.2
mA
CA-IS3721
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3721L);
VIN = VDDI (CA-IS3721H)
VIN = VDDI (CA-IS3721L);
VIN = 0V(CA-IS3721H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
CA-IS3722
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3722L);
VIN = VDDI (CA-IS3722H)
VIN = VDDI (CA-IS3722L);
VIN = 0V(CA-IS3722H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
Note:
1. VDDI = Input-side VDD
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6.9.3. VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
PARAMETER
SUPPLY
CURRENT
TEST CONDITION
MIN
TYP
MAX
UNIT
CA-IS3720
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3720L);
VIN = VDDI1 (CA-IS3720H)
VIN = VDDI (CA-IS3720L);
VIN = 0V(CA-IS3720H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
0.8
1.6
2.3
1.6
1.6
1.7
1.6
2.2
1.6
7.2
1.2
2.3
3.5
2.4
2.3
2.6
2.3
3.3
2.3
10.7
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.0
2.0
4.5
4.5
2.0
2.0
3.1
3.1
2.6
2.6
3.0
3.0
6.7
6.7
mA
1Mbps
(500kHz)
10Mbps
(5MHz)
100Mbps
(50MHz)
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
IDDA
IDDB
1.3
1.3
2.1
2.1
1.8
1.8
2.0
2.0
4.5
4.5
2.0
2.0
3.1
3.1
2.6
2.6
3.0
3.0
6.7
6.7
mA
CA-IS3721
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3721L);
VIN = VDDI (CA-IS3721H)
VIN = VDDI (CA-IS3721L);
VIN = 0V(CA-IS3721H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
CA-IS3722
Supply Current – DC Signal
Supply Current – AC Signal
VIN = 0V (CA-IS3722L);
VIN = VDDI (CA-IS3722H)
VIN = VDDI (CA-IS3722L);
VIN = 0V(CA-IS3722H)
All Channels Switching with 50% Duty
Cycle Square Wave Clock Input with 5V
Amplitude; CL = 15 pF for Each Channel
Note:
1. VDDI = Input-side VDD
12
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CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
6.10. Timing Characteristics
6.10.1. VDDA = VDDB = 5 V ± 10%, TA = -40 to 125°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
DR
Data Rate
0
150
Mbps
PWmin
Minimum Pulse Width
5.0
ns
tPLH, tPHL Propagation Delay Time
5.0 8.0 13.0
ns
See Figure 7-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2 4.5
ns
tsk(o)
Channel-to-channel Output Skew Time1
Same-direction
0.4 2.5
ns
tsk(pp)
Part-to-part Skew Time2
2.0 4.5
ns
tr
Output Signal Rise Time
See Figure 7-1
2.5 4.0
ns
tf
Output Signal Fall Time
See Figure 7-1
2.5 4.0
ns
tDO
Default Output Delay Time from Input Power Loss
See Figure 7-2
8
12
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
6.10.2. VDDA = VDDB = 3.3 V ± 10%, TA = -40 to 125°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
DR
Data Rate
0
150
Mbps
PWmin
Minimum Pulse Width
5.0
ns
tPLH, tPHL Propagation Delay Time
5.0 8.0 13.0
ns
See Figure 7-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2 4.5
ns
1
tsk(o)
Channel-to-channel Output Skew Time
Same-direction
0.4 2.5
ns
tsk(pp)
Part-to-part Skew Time2
2.0 4.5
ns
tr
Output Signal Rise Time
See Figure 7-1
2.5 4.0
ns
tf
Output Signal Fall Time
See Figure 7-1
2.5 4.0
ns
tDO
Default Output Delay Time from Input Power Loss
See Figure 7-2
8
12
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
6.10.3. VDDA = VDDB = 2.5 V ± 5%, TA = -40 to 125°C
PARAMETER
TEST CONDITIONS
MIN TYP MAX
UNIT
DR
Data Rate
0
150
Mbps
PWmin
Minimum Pulse Width
5.0
ns
tPLH, tPHL Propagation Delay Time
5.0 8.0 13.0
ns
See Figure 7-1
PWD
Pulse Width Distortion |tPLH - tPHL|
0.2 5.0
ns
tsk(o)
Channel-to-channel Output Skew Time1
Same-direction
0.4 2.5
ns
tsk(pp)
Part-to-part Skew Time2
2.0 5.0
ns
tr
Output Signal Rise Time
See Figure 7-1
2.5 4.0
ns
tf
Output Signal Fall Time
See Figure 7-1
2.5 4.0
ns
tDO
Default Output Delay Time from Input Power Loss
See Figure 7-2
8
12
ns
tSU
Start-up Time
15 40
µs
NOTE:
1. tsk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction
while driving identical loads.
2. tsk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction
while operating at identical supply voltages, temperature, input signals and loads.
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Parameter Measurement Information
Isolation Barrier
7.
IN
VIN1
OUT
50%
VIN
VOUT
tPHL
tPLH
CL2
50Ω
50%
90%
VOUT
50%
50%
10%
tf
tr
NOTE:
1. A square wave generator generate the VIN input signal with the following constraints: waveform frequency ≤ 100kHz, 50%
duty cycle, tr≤3ns, tf≤3ns. Since the waveform generator has an output impedance of Zout = 50Ω, the 50Ω resistor in the
figure is used for matching. There is no need in the actual application.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance. Since the load capacitance influence
the output rising time, it’s a key factor in the timing characteristic measurement.
Figure 7-1 Timing Characteristics Test Circuit and Voltage Waveforms
VDDI1
VDDO
VDDI
VDDO
IN = 0 V for CA-IS372xH
IN = VDDI for CA-IS372xL
IN
Isolation Barrier
2.15V
OUT
0V
VOUT
tDO
Default High for CA-IS371x/2xH
CL2
VOH
VOUT
50%
Default Low for CA-IS371x/2xL
VOL
NOTE:
1. Power Supply Ramp Rate = 10 mV/ns. VDDI should ramp over 2.15V but no higher than 5.5V.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance. Since the load capacitance influence
the output rising time, it’s a key factor in the timing characteristic measurement.
Figure 7-2 Default Output Delay Time Test Circuit and Voltage Waveforms
14
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CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
IN
CBP4
VDDO
Isolation Barrier
VDDI
OUT
VOUT3
CBP4
CL2
GNDA
High
Voltage
Surge
Generator1
GNDB
NOTE:
1. The High Voltage Surge Generator generates repetitive high voltage surges with > 1kV amplitude and 100kV/μs slew rate.
2. CL is the load capacitance about 15pF together with the instrumentation capacitance.
3. Pass-fail criteria: The output must remain stable whenever the high voltage surges come.
4. CBP is the 0.1 ~ 1uF bypass capacitance.
Figure 7-3 Common-Mode Transient Immunity Test Circuit
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CA-IS3720, CA-IS3721, CA-IS3722
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8.
8.1.
Detailed Description
Theory of Operation
The CA-IS37xx family of devices use a simple ON-OFF keying (OOK) modulation scheme to transmit signal across the SiO2
isolation capacitors that provide a robust insulation between two different voltage domain and act as a high frequency signal
path between the input and the output. The transmitter (TX) modulates the input signal onto the carrier frequency, that is, TX
delivers high frequency signal across the isolation barrier in one input state and delivers no signal across the barrier in the other
input state. Then the receiver rebuilds the input signal according to the detected in-band energy. This simple architecture offers
a robust isolated data path and requires no special considerations or initialization at start-up. The capacitor-based signal path is
fully differential to maximize noise immunity, which is also known as common-mode transient immunity. Advanced circuitry
techniques are applied for better EMI introduced by the carrier signal and IO switching. The capacitively-coupled architecture
provides much higher electromagnetic immunity compared to the inductively-coupled one. And OOK modulation scheme
eliminates the missing-pulse error that occurs in the pulse modulation method. A simplified functional block diagram and
conceptual operation waveforms of a single channel is shown in Figure 8-1 and Figure 8-2.
8.2.
Functional Block Diagram
Isolation
Barrier
Transmitter (TX)
Receiver (RX)
Schmitt
Trigger
Driver
VIN
Modulator
Demodulator
VOUT
RF Carrier
Generator
Figure 8-1 Functional Block Diagram of a Single Channel
VIN
Signal through
isolation barrier
VOUT
Figure 8-2 Conceptual Operation Waveforms of a Single Channel
16
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上海川土微电子有限公司
8.3. Device Operation Modes
Table 8-1 provides the operation modes for the CA-IS372x devices.
Table 8-1 Operation Mode Table1
VDDI
VDDO
PU
PU
PD
PU
INPUT(Ax/Bx)2
H
L
OUTPUT (Ax/Bx)
H
L
Open
Default
X
Default
OPERATION
Normal operation mode:
A channel’s output follows the input state
Default output fail-safe mode:
If a channel’s input is left open, its output goes to the default value (Low for CA-IS372xL
and High for CA-IS372xH).
Default output fail-safe mode:
If the input side VDD is unpowered, the outputs go in to the default output fail-safe mode
(Low for CA-IS372xL and High for CA-IS372xH)
If the output side VDD is unpowered, the outputs’ states are undetermined.3
X
PD
X
Undetermined
NOTE:
1. VDDI = Input-side VDD; VDDO = Output-side VDD; PU = Powered up (VCC ≥ 2.375 V); PD = Powered down (VCC ≤ 2.25 V); X = Irrelevant; H =
High level; L = Low level.
2. A strongly driven input signal can weakly power the floating VDD through an internal protection diode and cause undetermined output.
3. The outputs are in undetermined state when 2.25V < VDDI, VDDO < 2.375 V.
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CA-IS3720, CA-IS3721, CA-IS3722
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9.
Application and Implementation
Unlike optocouplers, which need external components to improve performance, provide bias, or limit current, the CA-IS372x
family device CMOS digital isolator needs only two external VDD bypass capacitors (0.1μF to 1 μF) to operate. Its TTL level
compatible input terminals draw only micro amps of leakage current, allowing them to be driven without external buffering
circuits. The output terminals have a characteristic impedance of 50 Ω (rail-to-rail swing) and are available in both forward and
reverse channel configurations. The circuit of Figure 9-1 is typical for most applications of CA-IS37xx series products and is as
easy to use as a standard logic gate.
CA-IS37xx Series Products
VDD1
VDDA
VDD2
VDDB
0.1uF
0.1uF
IN1
A1
TX
INm-1
Am-1
TX
OUTm
Am
RX
OUTn
An
RX
ISOLATION BARRIER
GNDA
GNDB
OUT1
RX
B1
RX
Bm-1
TX
Bm
INm
TX
Bn
INn
OUTm-1
Figure 9-1 CA-IS37xx Series Digital Isolator Application Schematic
18
Copyright © 2019, Chipanalog Incorporated
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CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
10. Package Information
10.1. 8-Pin SOIC Package
The figure below illustrates the package details and the recommended land pattern details for the CA-IS372x digital isolator in
a 8-pin narrow-body SOIC package. The values for the dimensions are shown in millimeters.
5.00
4.80
8
0.60
1.27
5
2.00
4.00
3.80
5.40
6.20
5.80
PIN I ID
1
4
TOP VIEW
RECOMMENDED LAND PATTERN
0.70 1.75
0.50 1.25
0.50
0.25
1.80
1.35
0.51
0.306
0.25
0.10
1.27BSC
8°
0°
0.80
0.30
1.04REF
FRONT VIEW
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LEFT-SIDE VIEW
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CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
10.2. 8-Pin Wide Body SOIC Package
The figure below illustrates the package details and the recommended land pattern details for the CA-IS372x digital isolator in
a 8-pin wide body SOIC package. The values for the dimensions are shown in millimeters.
5.95
5.75
8
0.60
1.27
5
2.00
7.60
7.40
11.75
11.25
10.90
PIN I ID
1
4
TOP VIEW
RECOMMENDED LAND PATTERN
1.07
2.386
0.97
2.186
2.80
2.35
0.51
0.31
1.27BSC
FRONT VIEW
20
0.46
0.36
1.0
0.50
8°
0°
2.0REF
LEFT-SIDE VIEW
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
CA-IS3720, CA-IS3721, CA-IS3722
上海川土微电子有限公司
TAPE AND REEL INFORMATION
TAPE DIMENSIONS
REEL DIMENSIONS
A0
B0
K0
W
P1
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
*All dimensions are nominal
Device
Package
Type
Package
Drawing
Pins
SPQ
CA-IS3720LSR
CA-IS3720LGR
CA-IS3720HSR
CA-IS3720HGR
CA-IS3721LSR
CA-IS3721LGR
CA-IS3721HSR
CA-IS3721HGR
CA-IS3722LSR
CA-IS3722LGR
CA-IS3722HSR
CA-IS3722HGR
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
S
G
S
G
S
G
S
G
S
G
S
G
8
8
8
8
8
8
8
8
8
8
8
8
2500
1000
2500
1000
2500
1000
2500
1000
2500
1000
2500
1000
Copyright © 2019, Chipanalog Incorporated
上海川土微电子有限公司
Reel
Diameter
(mm)
330
330
330
330
330
330
330
330
330
330
330
330
Reel
Width
W1 (mm)
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
12.4
16.4
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
6.5
12.05
6.5
12.05
6.5
12.05
6.5
12.05
6.5
12.05
6.5
12.05
5.4
6.15
5.4
6.15
5.4
6.15
5.4
6.15
5.4
6.15
5.4
6.15
2.1
3.3
2.1
3.3
2.1
3.3
2.1
3.3
2.1
3.3
2.1
3.3
8.0
16.0
8.0
16.0
8.0
16.0
8.0
16.0
8.0
16.0
8.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
12.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
21
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上海川土微电子有限公司
IMPORTANT NOTICE
The above information is for reference only and is used to assist Chipanalog customers in design and development. Chipanalog
reserves the right to change the above information due to technological innovation without prior notice.
Chipanalog products are all factory tested. The customers shall be responsible for self-assessment and determine whether it is
applicable for their specific application. Chipanalog's authorization to use the resources is limited to the development of related
applications that the Chipanalog products involved in. In addition, the resources shall not be copied or displayed. And Chipanalog
shall not be liable for any claim, cost, and loss arising from the use of the resources.
Trademark Information
Chipanalog Inc. ®, Chipanalog® are trademarks or registered trademarks of Chipanalog.
http://www.chipanalog.com
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