FM25Q04
4M-BIT SERIAL FLASH MEMORY
Datasheet
Sep. 2017
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
1
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FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
2
1. Description
The FM25Q04 is a 4M-bit (512K-byte) Serial Flash
memory,
with
advanced
write
protection
mechanisms. The FM25Q04 supports the standard
Serial Peripheral Interface (SPI), Dual/Quad I/O as
well as 2-clock instruction cycle Quad Peripheral
Interface (QPI). They are ideal for code shadowing to
RAM, executing code directly from Dual/Quad SPI
(XIP) and storing voice, text and data.
The FM25Q04 can be programmed 1 to 256 bytes
at a time, using the Page Program instruction. It is
designed to allow either single Sector/Block at a
time or full chip erase operation. The FM25Q04
can be configured to protect part of the memory as
the software protected mode. The device can
sustain a minimum of 100K program/erase cycles on
each sector or block.
2. Features
4Mbit of Flash memory
– 128 uniform sectors with 4K-byte each
– 8 uniform blocks with 64K-byte each
– 16 uniform blocks with 32K-byte each
– 256 bytes per programmable page
Wide Operation Range
– 2.3V~3.6Vsingle voltage supply
– Industrial temperature range
Serial Interface
– Standard SPI: CLK, CS#, DI, DO, WP#
– Dual SPI: CLK, CS#, DQ0, DQ1, WP#
– Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
– QPI: CLK, CS#, DQ0, DQ1, DQ2, DQ3
– Continuous READ mode support
– Allow true XIP (execute in place) operation
High Performance
– Max FAST_READ clock frequency: 104MHz
– Dual I/O Data transfer up to 208Mbits/s
– Quad I/O I/O Data transfer up to 416Mbits/s
– Typical page program time: 1.5ms
– Typical sector erase time: 80ms
– Typical block erase time: 120/150ms
– Typical chip erase time: 1.2s
Low Power Consumption
– Typical standby current: 1μA
Security
– Software and hardware write protection
– Lockable 2X512-Byte OTP security sectors
– 64-Bit Unique ID for each device(1)
– Discoverable Parameters (SFDP) Register
FM25Q044M-BITSERIAL FLASH MEMORY
High Reliability
– Endurance: 100,000 program/erase cycles
– Data retention: 20 years
Green Package
– 8-pin SOP (150mil)
– 8-pin SOP (208mil)
– 8-pin TSSOP8
– 8-pin TDFN(2×3mm)
– All Packages are RoHS Compliant and Halogenfree
Note 1.This feature is available upon special order.
Please contact Shanghai Fudan Microelectronics Group
Co., Ltd for details.
3. Packaging Type
SOP 8 (150mil)
CS#
DO(DQ1)
1
2
8
7
VCC
HOLD#(DQ3)
WP#(DQ2)
VSS
3
4
6
5
CLK
DI(DQ0)
CS#
DO(DQ1)
WP#(DQ2)
VSS
1
2
3
4
TDFN8 (2x3mm)
CS#
DO(DQ1)
WP#(DQ2)
VSS
VCC
HOLD#(DQ3)
CLK
DI(DQ0)
8
2
7
3
6
4
5
VCC
HOLD#(DQ3)
CLK
DI(DQ0)
TSSOP8
SOP 8 (208mil)
8
7
6
5
1
CS#
DO(DQ1)
WP#(DQ2)
VSS
1
2
3
4
8
7
6
5
VCC
HOLD#(DQ3)
CLK
DI(DQ0)
4. Pin Configurations
PIN PIN
NO. NAME
1
CS#
DO
2
(DQ1)
WP#
3
(DQ2)
4
VSS
DI
5
(DQ0)
6
CLK
HOLD#
7
(DQ3)
8
VCC
I/O
FUNCTION
I Chip Select Input
Data Output (Data Input Output
I/O (1)
1)
Write Protect Input (Data Input
I/O
Output 2)(2)
Ground
Data Input (Data Input Output
I/O (1)
0)
I Serial Clock Input
Hold Input (Data Input Output
I/O (2)
3)
Power Supply
Note:
1 DQ0 and DQ1 are used for Dual SPI instructions.
2 DQ0 – DQ3 are used for Quad SPI and QPI instructions.
Ver. 1.4
Datasheet
3
5.
Block Diagram
X
Y
Decoder Decoder
Address
Generator
HV Generator
Memory
Array
HOLD(DQ3)
Y-Gating
Serial Output logic
WP
CS
DI
DO
Serial Input Logic
CLK
SRAM
Sense
Amplifier
WP(DQ2)
DO(DQ1)
DI(DQ0)
HOLD
Clock
Generator
State Machine
Figure 1 FM25Q04 Serial Flash Memory Block Diagram
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
4
6.
Pin Descriptions
Serial Clock (CLK): The SPI Serial Clock Input (CLK) pin provides the timing for serial input and
output operations.
Serial Data Input, Output and I/Os (DI, DO and DQ0, DQ1, DQ2, DQ3): The FM25Q04 supports
standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI instructions use the
unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the
rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO
(output) to read data or status from the device on the falling edge of CLK.
Dual/Quad SPI and QPI instructions use the bidirectional DQ pins to serially write instructions,
addresses or data to the device on the rising edge of CLK and read data or status from the
device on the falling edge of CLK. Quad SPI and QPI instructions require the non-volatile Quad
Enable bit (QE) in Status Register-2 to be set. When QE=1, the WP# pin becomes DQ2 and
HOLD# pin becomes DQ3.
Chip Select (CS#): The SPI Chip Select (CS#) pin enables and disables device operation.
When CS# is high, the device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2,
DQ3) pins are at high impedance. When deselected, the devices power consumption will be at
standby levels unless an internal erase, program or write status register cycle is in progress.
When CS# is brought low, the device will be selected, power consumption will increase to active
levels and instructions can be written to and data read from the device. After power-up, CS#
must transition from high to low before a new instruction will be accepted. The CS# input must
track the VCC supply level at power-up (see “9 Write Protection” and Figure 72). If needed a pullup resister on CS# can be used to accomplish this.
HOLD (HOLD#): The HOLD# pin allows the device to be paused while it is actively selected.
When HOLD# is brought low, while CS# is low, the DO pin will be at high impedance and signals
on the DI and CLK pins will be ignored (don’t care). When HOLD# is brought high, device
operation can resume. The HOLD# function can be useful when multiple devices are sharing the
same SPI signals. The HOLD# pin is active low. When the QE bit of Status Register-2 is set for
Quad I/O, the HOLD# pin function is not available since this pin is used for DQ3.
Write Protect (WP#): The Write Protect (WP#) pin can be used to prevent the Status Registers
from being written. Used in conjunction with the Status Register’s Block Protect (CMP, TB, BP2,
BP1 and BP0) bits and Status Register Protect (SRP) bits, a portion as small as a 4KB sector or
the entire memory array can be hardware protected. The WP# pin is active low. However, when
the QE bit of Status Register-2 is set for Quad I/O, the WP# pin function is not available since
this pin is used for DQ2.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
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7.
Memory Organization
The FM25Q04 array is organized into 2,048 programmable pages of 256-bytes each. Up to 256
bytes can be programmed (bits are programmed from 1 to 0) at a time. Pages can be erased in
groups of 16 (4KB sector erase), groups of128 (32KB block erase), groups of 256 (64KB block
erase) or the entire chip (chip erase).TheFM25Q04 has 128 erasable sectors, 16 erasable 32-k
byte blocks and 8 erasable 64-k byte blocks respectively. The small 4KB sectors allow for
greater flexibility in applications that require data and parameter storage.
Table 1
Block
(64KB)
7
Block
(32KB)
15
|
14
6
13
|
12
5
11
|
10
4
9
|
8
3
7
|
6
2
5
|
4
1
3
|
2
0
1
|
0
FM25Q044M-BITSERIAL FLASH MEMORY
Memory Organization
Sector
(4KB)
127
…
112
111
…
96
95
…
80
79
…
64
63
…
48
47
…
32
31
…
16
15
…
2
1
0
Ver. 1.4
Address Range
07F000h
…
070000h
06F000h
…
060000h
05F000h
…
050000h
04F000h
…
040000h
03F000h
…
030000h
02F000h
…
020000h
01F000h
…
010000h
00F000h
…
002000h
001000h
000000h
07FFFFh
…
070FFFh
06FFFFh
…
060FFFh
05FFFFh
…
050FFFh
04FFFFh
…
040FFFh
03FFFFh
…
030FFFh
02FFFFh
…
020FFFh
01FFFFh
…
010FFFh
00FFFFh
…
002FFFh
001FFFh
000FFFh
Datasheet
6
8.
Device Operations
Power On
Reset (66h + 99h)
Reset (66h + 99h)
Device
Initialization
Standard SPI
Dual SPI
Quad SPI
operations
Enable QPI (38h)
Disable QPI (FFh)
QPI
operations
Figure 2 FM25Q04 Serial Flash Memory Operation Diagram
8.1.
Standard SPI
The FM25Q04 is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write instructions, addresses or data to the device
on the rising edge of CLK. The DO output pin is used to read data or status from the device on
the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between
Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in
standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is
normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high
on the falling and rising edges of CS#.
CS#
CLK
MODE3
MODE3
MODE0
MODE0
DI
DO
DONT CARE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
HIGH IMPEDANCE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB
Figure 3 The difference between Mode 0 and Mode 3
8.2.
Dual SPI
The FM25Q04 supports Dual SPI operation when using instructions such as “Fast Read Dual
Output (3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to
or from the device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI
Read instructions are ideal for quickly downloading code to RAM upon power-up (codeshadowing) or for executing non-speed- critical code directly from the SPI bus (XIP). When using
Dual SPI instructions, the DI and DO pins become bidirectional I/O pins: DQ0 and DQ1.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
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8.3.
Quad SPI
The FM25Q04 supports Quad SPI operation when using instructions such as “Fast Read Quad
Output (6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read
Quad I/O (E3h)”. These instructions allow data to be transferred to or from the device four to six
times the rate of ordinary Serial Flash. The Quad Read instructions offer a significant improvement in
continuous and random access transfer rates allowing fast code-shadowing to RAM or execution
directly from the SPI bus (XIP). When using Quad SPI instructions the DI and DO pins become
bidirectional DQ0 and DQ1 and the WP # and HOLD# pins become DQ2 and DQ3 respectively. Quad
SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set.
8.4.
QPI
The FM25Q04 supports Quad Peripheral Interface (QPI) operations only when the device is
switched from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction.
The typical SPI protocol requires that the byte-long instruction code being shifted into the device only
via DI pin in eight serial clocks. The QPI mode utilizes all four DQ pins to input the instruction code,
thus only two serial clocks are required. This can significantly reduce the SPI instruction overhead
and improve system performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI
mode are exclusive. Only one mode can be active at any given time. “Enable QPI (38h)” and
“Disable QPI (FFh)” instructions are used to switch between these two modes. Upon power-up or
after a software reset using “Reset (99h)” instruction, the default state of the device is
Standard/Dual/Quad SPI mode. To enable QPI mode, the non-volatile Quad Enable bit (QE) in
Status Register-2 is required to be set. When using QPI instructions, the DI and DO pins become
bidirectional DQ0 and DQ1, and the WP# and HOLD# pins become DQ2 and DQ3 respectively. See
Figure 2 for the device operation modes.
8.5.
Hold
For Standard SPI and Dual SPI operations, the HOLD# signal allows the FM25Q04 operation to
be paused while it is actively selected (when CS# is low). The HOLD# function may be useful in
cases where the SPI data and clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a priority interrupt requires use of the
SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the
buffer so programming can resume where it left off once the bus is available again. The HOLD#
function is only available for standard SPI and Dual SPI operation, not during Quad SPI or QPI.
To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition
will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is
not already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD#
condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If
the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK.
During a HOLD# condition, the Serial Data Output (DO) is high impedance, and Serial Data
Input (DI) and Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept
active (low) for the full duration of the HOLD# operation to avoid resetting the internal logic state
of the device.
Active
Hold
Active
Hold
Active
Figure 4 HoldCondition Waveform
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
8
9.
Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise
and other adverse system conditions that may compromise data integrity. To address this
concern, the FM25Q04 provides several means to protect the data from inadvertent writes.
Write Protect Features
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software and Hardware (WP# pin) write protection using Status Register
Write Protection using Power-down instruction
Lock Down write protection for Status Register until the next power-up
One Time Program (OTP) write protection for array and Security Sectors using Status
Register.
Upon power-up or at power-down, the FM25Q04 will maintain a reset condition while VCC is
below the threshold value of VWI, (See “12.3Power-up Timing” and Figure 72). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC
voltage exceeds VWI, all program and erase related instructions are further disabled for a time
delay of tPUW . This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip
Erase and the Write Status Register instructions. Note that the chip select pin (CS#) must track
the VCC supply level at power-up until the VCC-min level and tVSL time delay is reached. If
needed a pull-up resister on CS# can be used to accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status
Register Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before
a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction will
be accepted. After completing a program, erase or write instruction the Write Enable Latch (WEL)
is automatically cleared to a write-disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and
setting the Status Register Protect (SRP0, SRP1) and Block Protect (CMP, TB, BP2, BP1 and
BP0) bits. These settings allow a portion as small as a 4KB sector or the entire memory array to
be configured as read only. Used in conjunction with the Write Protect (WP#) pin, changes to the
Status Register can be enabled or disabled under hardware control. See Status Register section
for further information. Additionally, the Power-down instruction offers an extra level of write
protection as all instructions are ignored except for the Release Power-down instruction.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
9
10.
Status Register
The Read Status Register instructions can be used to provide status on the availability of the
Flash memory array, if the device is write enabled or disabled, the state of write protection, Quad
SPI setting, Security Sector lock status. The Write Status Register instruction can be used to
configure the device write protection features, Quad SPI setting and Security Sector OTP lock.
Write access to the Status Register is controlled by the state of the non-volatile Status Register
Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual SPI
operations, the WP# pin.
Factory default for all Status Register bits are 0.
S7
S6
SRP0 RFU
S5
S4
S3
S2
S1
S0
TB
BP2
BP1
BP0
WEL
WIP
STATUS REGISTER PROTECT 0
(non-volatile)
Reserved
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
Figure 5 Status Register-1
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
10
S15
S14
S13
S12
RFU
ERR WPS CMP
S11
S10
S9
S8
LB1
LB0
QE
SRP1
Reserved
Error Status
(volatile, Read only)
Write Protect Selection
(non-volatile)
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BIT
(non-Volatile)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(non-volatile)
Figure 6 Status Register-2
S23
S22
S21
S20
S19
RFU
RFU
RFU
RFU RFU
S18
S17
S16
RFU DRV1 DRV0
Reserved
Output Driver Strength
(Volatile/Non-Volatile Writable)
Figure 7 Status Register-3
10.1.
WIP Bit
WIP is a read only bit in the status register (S0) that is set to a 1 state when the device is
executing a Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write
Status Register or Erase/Program Security Sectorinstruction. During this time the device will
ignore further instructions except for the Read Status Register instruction (see tW , tPP, tSE,tBE, and
tCE in “12.6AC Electrical Characteristics”). When the program, erase or write status register(or
security sector)instruction has completed, the WIP bit will be cleared to a 0 state indicating the
device is ready for further instructions.
10.2.
Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after
executing a Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write
disabled. A write disable state occurs upon power-up or after any of the following instructions:
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
11
Write Disable, Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase,
Write Status Register, Erase Security Sector and Program Security Sector.
10.3.
Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4,
S3, and S2) that provide Write Protection control and status. Block Protect bits can be set using
the Write Status Register Instruction (see tW in “12.6AC Electrical Characteristics”). All, none or a
portion of the memory array can be protected from Program and Erase instructions (see Table
3Status Register Memory Protection). The factory default setting for the Block Protection Bits is
0, none of the array protected.
10.4.
Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect
from the Top (TB=0) or the Bottom (TB=1) of the array as shown in Table 3Status Register
Memory Protection table. The factory default setting is TB=0. The TB bit can be set with the
Write Status Register Instruction depending on the state of the SRP0, SRP1 and WEL bits.
10.5.
Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It
is used in conjunction with TB, BP2, BP1 and BP0 bits to provide more flexibility for the array
protection. Once CMP is set to 1, previous array protection set by TB, BP2, BP1 and BP0 will be
reversed. For instance, when CMP=0, a top 4KB sector can be protected while the rest of the
array is not; when CMP=1, the top 4KB sector will become unprotected while the rest of the
array become read-only. Please refer to Table 3Status Register Memory Protection table for
details. The default setting is CMP=0.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
12
10.6.
Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status
register (S8 and S7). The SRP bits control the method of write protection: software protection,
hardware protection, power supply lock-down or one time programmable (OTP) protection.
Table 2
Status
Register
SRP1 SRP0 WP#
0
0
X
0
1
0
0
1
1
1
0
X
1
1
X
Status Register Protect bits
Description
WP# pin has no control. The Status register can be
written to after a Write Enable instruction, WEL=1.
(Factory Default)
Hardware
When WP# pin is low the Status Register locked and can
Protected
not be written to.
Hardware
When WP# pin is high the Status register is unlocked and
Unprotected can be written to after a Write Enable instruction, WEL=1.
Power Supply Status Register is protected and can not be written to
Lock-Down again until the next power-down, power-up cycle.(1)
One Time Status Register is permanently protected and can not be
Program
written to.
Software
Protection
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0)
state.
10.7.
Error Bit (ERR)
The Error bit is a status flag, which shows the status of last Program/Erase operation. It will be
set to "1", if the Program/Erase operation fails. It will be set to “0”, after reset or WREN instruction.
10.8.
Security Sector Lock Bits (LB1, LB0)
The Security Register Lock Bit (LB1-0) are non-volatile One Time Program (OTP) bits in Status
Register (S12,S11) that provide the write protect control and status to the Security Registers.
The default state of LB1-0 is 0, Security Registers are unlocked. LB1-0 can be set to 1
individually using the Write Status Register instruction. LB1-0 are One Time Programmable
(OTP), once it’s set to 1, the corresponding 512-Bytes Security Register will become read-only
permanently.
10.9.
Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows
Quad SPI and QPI operation. When the QE bit is set to a 0 state (factory default), the WP# pin
and HOLD# are enabled. When the QE bit is set to a 1, the Quad DQ2 and DQ3 pins are enabled,
and WP# and HOLD# functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in
QPI mode, QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot
change QE bit from a “1” to a “0”.
WARNING: If the WP# or HOLD# pins are tied directly to the power supply or ground
during standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
13
10.10. Write Protect Selection (WPS)
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0, the
device will use the combination of CMP, TB, BP[2:0] to protect a specific area of the memory
array. When WPS=1, the device will utilize the Individual Sector Locks to protect any individual
sector. The default value for all Individual Sector Lock bits is 1 upon device power on or after
reset.
10.11. Reserved Bits (RFU)
There are a few reserved Status Register bits that may be read out as a “0” or “1”.It is
recommended to ignore the values of those bits. During a “Write Status Register” instruction, the
Reserved Bits can be written as “0”, but there will not be any effects.
10.12. Output driver strength (DRV1, DRV0)
The DRV1 & DRV0 bits are used to determine the output driver strength.
DRV1, DRV0
Driver Strength
0,0
0,1
1,0
1,1
FM25Q044M-BITSERIAL FLASH MEMORY
100%
75%
50%
25%
Ver. 1.4
Datasheet
14
10.13. Status Register Memory Protection (WPS=0, CMP=0)
Table 3
Status Register Memory Protection (CMP=0)
STATUS
REGISTER
FM25Q04 (4M-BIT) MEMORY PROTECTION
TB BP2 BP1 BP0
X
0
0
0
1
1
1
X
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
X
0
1
0
1
1
0
1
X
PROTECTED
BLOCK(S)
NONE
7
6 and 7
4 thru 7
0
0 and 1
0 thru 3
0 thru 7
PROTECTED
ADDRESSES
NONE
070000h – 07FFFFh
060000h – 07FFFFh
040000h – 07FFFFh
000000h – 00FFFFh
000000h – 01FFFFh
000000h – 03FFFFh
000000h – 07FFFFh
PROTECTED
DENSITY
NONE
64KB
128KB
256KB
64KB
128KB
256KB
512KB
PROTECTED
PORTION
NONE
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/8
Lower 1/4
Lower 1/2
ALL
10.14. Status Register Memory Protection (WPS=0, CMP=1)
Table 4
Status Register Memory Protection (CMP=1)
STATUS
REGISTER
FM25Q04 (4M-BIT) MEMORY PROTECTION
TB BP2 BP1 BP0
X
0
0
0
1
1
1
X
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
X
0
1
0
1
1
0
1
X
PROTECTED
BLOCK(S)
0 thru 7
0 thru 6
0 thru 5
0 thru 3
1 thru 7
2 thru 7
4 thru 7
NONE
PROTECTED
ADDRESSES
000000h – 07FFFFh
000000h – 06FFFFh
000000h – 05FFFFh
000000h – 03FFFFh
010000h – 07FFFFh
020000h – 07FFFFh
040000h – 07FFFFh
NONE
PROTECTED
DENSITY
512KB
448KB
384KB
256KB
448KB
384KB
256KB
NONE
PROTECTED
PORTION
All
Lower7/8
Lower3/4
Lower1/2
Upper 1/8
Upper 1/4
Upper 1/2
NONE
10.15. Status Register Memory Protection (WPS=1)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
15
Individual Sector Locks:
128 Sectors(Top/Bottom)
Sector 127(4KB)
Sector 126(4KB)
Individual Sector Lock:
36h + Address
.....
}
Individual Sector Unlock:
39h + Address
Read Sector Lock:
3Dh + Address
Global Sector Lock:
7Eh
Sector 1(4KB)
Sector 0(4KB)
Global Sector Unlock:
98h
Figure 8 Individual Sector Locks
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
16
11.
Instructions
The Standard/Dual/Quad SPI instruction set of the FM25Q04 consists of 39 basic instructions
that are fully controlled through the SPI bus (see Table 6~Table 8Instruction Set). Instructions
are initiated with the falling edge of Chip Select (CS#). The first byte of data clocked into the DI
input provides the instruction code. Data on the DI input is sampled on the rising edge of clock
with most significant bit (MSB) first.
The QPI instruction set of the FM25Q04 consists of 25 basic instructions that are fully controlled
through the SPI bus (see Table 9 Instruction Set). Instructions are initiated with the falling edge
of Chip Select (CS#). The first byte of data clocked through DQ[3:0] pins provides the instruction
code. Data on all four DQ pins are sampled on the rising edge of clock with most significant bit
(MSB) first. All QPI instructions, addresses, data and dummy bytes are using all four DQ pins to
transfer every byte of data with every two serial clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address
bytes, data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are
completed with the rising edge of edge CS#. Clock relative timing diagrams for each instruction
are included in Figure 9 through Figure 76. All read instructions can be completed after any
clocked bit. However, all instructions that Write, Program or Erase must complete on a byte
boundary (CS# driven high after a full 8-bits have been clocked) otherwise the instruction will be
ignored. This feature further protects the device from inadvertent writes. Additionally, while the
memory is being programmed or erased, or when the Status Register is being written, all
instructions except for Read Status Register will be ignored until the program or erase cycle has
completed.
11.1.
Manufacturer and Device Identification
Table 5
OP Code
ABh
90h,92h,94h
9Fh
FM25Q044M-BITSERIAL FLASH MEMORY
Manufacturer and Device Identification
MF7-MF0
ID15-ID0
ID7-ID0
12h
12h
A1h
A1h
4013h
Ver. 1.4
Datasheet
17
11.2.
Standard SPI Instructions Set
Table 6
Standard SPI Instructions Set (1)
INSTRUCTION NAME
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
CLOCK NUMBER
Write Enable
Volatile SR Write Enable
Write Disable
Read Status Register-1
Write Status Register-1
(0-7)
06h
50h
04h
05h
01h
(8-15)
(16-23)
(24-31)
(32-39)
(40-47)
(S7-S0)(2)
S7-S0
Read Status Register-2
35h
(S15-S8)(2)
Write Status Register-2
31h
S15-S8
Read Status Register-3
15h (S23-S16)(2)
Write Status Register-3
11h
S23-S16
Page Program
02h
A23-A16
Sector Erase (4KB)
20h
A23-A16
Block Erase (32KB)
52h
A23-A16
Block Erase (64KB)
D8h
A23-A16
Chip Erase
C7h/60h
Power-down
B9h
Read Data
03h
A23-A16
Fast Read
0Bh
A23-A16
Release Powerdown / ID(4) ABh
dummy
(4)
Manufacturer/Device ID
90h
dummy
JEDEC ID(4)
9Fh
Read SFDP Register
Read Unique ID
5Ah
(5)
(6)
Erase Security Sectors
Program Security Sectors(6)
Read Security Sectors(6)
Individual Sector Lock
Individual Sector Unlock
Read Sector Unlock
Global Sector Lock
Global Sector Unlock
Enable QPI
Enable Reset
Reset
01h can be used to program Status Register1&2
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A15-A8
A7-A0
(D7-D0)
A15-A8
A7-A0
dummy
dummy
dummy (ID7-ID0)(2)
dummy
00h
(MF7-MF0)
(ID15(MF7ID8)
(ID7-ID0)
MF0)Manufa
Memory Capacity
cturer
Type
00h
00h
A7-A0
dummy
4Bh
dummy
dummy
dummy
44h
42h
48h
36h
39h
3Dh
7Eh
98h
38h
66h
99h
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
FM25Q044M-BITSERIAL FLASH MEMORY
D7-D0
Ver. 1.4
dummy
D7-D0
dummy
D7-D0(3)
(D7-D0)
(ID7-ID0)
(D7-D0)
(UID63UID0)
D7-D0(3)
(D7-D0)
Datasheet
18
11.3.
Dual SPI Instructions Set
Table 7
INSTRUCTION
NAME
CLOCK NUMBER
Fast Read Dual
Output
11.4.
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(0-7)
(8-15)
(16-23)
(24-31)
(32-39)
(40-47)
3Bh
A23-A16
A15-A8
A7-A0
dummy
(D7-D0, …)(8)
Fast Read Dual I/O
BBh
A23-A8(7)
A7-A0, M7M0 (7)
(D7D0, …)(8)
Manufacturer/Device
ID by
Dual I/O(4)
92h
A23-A8(7)
A7-A0, M7M0(7)
(MF7-MF0,
ID7-ID0)
Quad SPI Instructions Set
Table 8
INSTRUCTION
NAME
CLOCK NUMBER
Quad SPI Instructions Set
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(0-7)
(8-15)
(16-23)
(24-31)
(40-47)
Quad Page Program
32h
A23-A16
A15-A8
A7-A0
(32-39)
D7D0, …(10)
Fast Read Quad
Output
6Bh
A23-A16
A15-A8
A7-A0
Fast Read Quad I/O
EBh
A23-A0,
M7-M0(9)
A23-A0,
M7-M0(9)
A23-A0,
M7-M0(9)
xxxxxx,
W6-W4(9)
(xxxx, D7D0)(11)
(xx, D7D0)(12)
(D7D0, …)(10)
(D7D0, …)(10)
(D7D0, …)(10)
Word Read Quad
I/O(13)
Octal Word Read
Quad I/O(14)
11.5.
Dual SPI Instructions Set
E7h
E3h
Set Burst with Wrap
77h
Manufacture/Device
ID by
Quad I/O(4)
94h
A23-A0,
M7-M0(9)
D7-D0, …(3)
dummy
(D7-D0, …)(10)
xxxx, (MF7(MF7-MF0,
MF0, ID7ID7-ID0, …)
ID0)
QPI Instructions Set
Table 9
INSTRUCTION NAME BYTE 1
CLOCK NUMBER
Write Enable
Volatile SR Write
Enable
Write Disable
Read Status Register-1
Write Status Register-1
Read Status Register-2
Write Status Register-2
Read Status Register-3
(0,1)
06h
QPI Instructions Set (15)
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
(2,3)
(4,5)
(6,7)
(8,9)
(10,11)
50h
04h
05h
01h
35h
31h
15h
FM25Q044M-BITSERIAL FLASH MEMORY
(S7-S0)(2)
S7-S0
01h can be used to program Status Register-1&2
(2)
(S15-S8)
S15-S8
(S23-
Ver. 1.4
Datasheet
19
INSTRUCTION NAME BYTE 1
Write Status Register-3
Page Program
Sector Erase (4KB)
Block Erase (32KB)
Block Erase (64KB)
Chip Erase
Power-down
Set Read Parameters
Fast Read
Burst Read with
Wrap(17)
Fast Read Quad I/O
Release Powerdown /
ID(4)
Manufacturer/Device
ID(4)
JEDEC ID
(4)
11h
02h
20h
52h
D8h
C7h/60
h
B9h
C0h
0Bh
BYTE 2
S16)(2)
S23-S16
A23-A16
A23-A16
A23-A16
A23-A16
P7-P0
A23-A16
BYTE 3
BYTE 4
BYTE 5
BYTE 6
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0(10)
D7-D0(3)
A7-A0
dummy(16)
(D7-D0)
(16)
A15-A8
0Ch
A23-A16
A15-A8
A7-A0
dummy
(D7-D0)
EBh
A23-A16
A15-A8
A7-A0
M7-M0(16)
(D7-D0)
ABh
dummy
dummy
dummy
(ID7-ID0)(2)
90h
dummy
dummy
00h
(MF7-MF0)
9Fh
(MF7-MF0)
Manufacture
r
(ID15ID8)
Memory
Type
(ID7ID0)
Capacity
(ID7-ID0)
Disable QPI
FFh
Enable Reset
66h
Reset
99h
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )”
indicate data output from the device on either 1, 2 or 4 DQ pins.
2. The Status Register contents and Device ID will repeat continuously until CS# terminates the
instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and
Program Security Sectors, up to 256 bytes of data input. If more than 256 bytes of data are
sent to the device, the addressing will wrap to the beginning of the page and overwrite
previously sent data.
4. See Table 5Manufacturer and Device Identification table for device ID information.
5. This feature is available upon special order. Please contact Shanghai Fudan Microelectronics Group
Co., Ltd for details.
6. Security Sector Address:
Security Sector 1: A23-A12 = 000h; A11-A8=00~01h; A7-A0 = byte address
Security Sector 2: A23-A12 = 001h; A11-A8=00~01h; A7-A0 = byte address
7. Dual SPI address input format:
DQ0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
DQ1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
8. Dual SPI data output format:
DQ0 = (D6, D4, D2, D0)
DQ1 = (D7, D5, D3, D1)
9. Quad SPI address input format:
Set Burst with Wrap input format:
DQ0 = A20, A16, A12, A8, A4, A0, M4, M0
DQ0 = x, x, x, x, x, x, W4, x
DQ1 = A21, A17, A13, A9, A5, A1, M5, M1
DQ1 = x, x, x, x, x, x, W5, x
DQ2 = A22, A18, A14, A10, A6, A2, M6, M2
DQ2 = x, x, x, x, x, x, W6, x
DQ3 = A23, A19, A15, A11, A7, A3, M7, M3
DQ3 = x, x, x, x, x, x, x, x
10. Quad SPI data input/output format:
DQ0 = (D4, D0, …)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
20
11.
12.
13.
14.
15.
DQ1 = (D5, D1, …..)
DQ2 = (D6, D2, …..)
DQ3 = (D7, D3, …..)
Fast Read Quad I/O data output format:
DQ0 = (x, x, x, x, D4, D0, D4, D0)
DQ1 = (x, x, x, x, D5, D1, D5, D1)
DQ2 = (x, x, x, x, D6, D2, D6, D2)
DQ3 = (x, x, x, x, D7, D3, D7, D3)
Word Read Quad I/O data output format:
DQ0 = (x, x, D4, D0, D4, D0, D4, D0)
DQ1 = (x, x, D5, D1, D5, D1, D5, D1)
DQ2 = (x, x, D6, D2, D6, D2, D6, D2)
DQ3 = (x, x, D7, D3, D7, D3, D7, D3)
For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0)
For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0)
QPI Command Address, Data input/output format:
CLK#
0
1
2
3
4
5
6
7
8
9
10
11
DQ0
C4
C0
A20 A16 A12
A8
A4
A0
D4
D0
D4
D0
DQ1
C5
C1
A21 A17 A13
A9
A5
A1
D5
D1
D5
D1
DQ2
C6
C2
A22 A18 A14 A10
A6
A2
D6
D2
D6
D2
DQ3
C7
C3
A23 A19 A15 A11
A7
A3
D7
D3
D7
D3
16. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst
Read with Wrap is controlled by read parameter P7 ~ P4.
17. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 ~
P0.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
21
11.6.
Write Enable (WREN) (06h)
The Write Enable (WREN) instruction (Figure 9) sets the Write Enable Latch (WEL) bit in the
Status Register to a 1. The WEL bit must be set prior to every Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase, Write Status Register and Erase/Program
Security Sectors instruction. The Write Enable (WREN)instruction is entered by driving CS# low,
shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then
driving CS# high.
CS#
CS#
Mode 3
CLK
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 0
Mode 3
0
1
Mode 0
Mode 3
Mode 0
Instruction
(06h)
Mode 0
DQ0
Instruction (06h)
DI
(DQ0)
DQ1
DQ2
High Impedance
D0
(DQ1)
DQ3
Figure 9 Write Enable Instruction for SPI Mode (left) or QPI Mode (right)
11.7.
Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 10.1 can also be written to as volatile
bits. This gives more flexibility to change the system configuration and memory protection
schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the
endurance of the Status Register non-volatile bits. To write the volatile values into the Status
Register bits, the Write Enable for Volatile Status Register (50h) instruction must be issued prior
to a Write Status Register (01h/31h/11h) instruction. Write Enable for Volatile Status Register
instruction (Figure 10) will not set the Write Enable Latch (WEL) bit, it is only valid for the Write
Status Register instruction to change the volatile Status Register bit values.
CS#
CS#
Mode 3
CLK
Mode 3
CLK
0
1
2
3
4
5
Mode 0
6
7
Mode 3
Mode 0
0
1
Mode 0
Mode 3
Mode 0
Instruction(
50h)
DQ0
Instruction (50h)
DI
(DQ0)
DQ1
DQ2
D0
(DQ1)
High Impedance
DQ3
Figure 10 Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI
Mode (right)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
22
11.8.
Write Disable(WRDI) (04h)
The Write Disable (WRDI) instruction (Figure 11) resets the Write Enable Latch (WEL) bit in the
Status Register to a 0. The Write Disable(WRDI) instruction is entered by driving CS# low,
shifting the instruction code “04h” into the DI pin and then driving CS# high. Note that the WEL
bit is automatically reset after Power-up and upon completion of the Write Status Register,
Erase/Program Security Sectors, Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase and Reset instructions.
CS#
CS#
Mode 3
CLK
Mode 3
CLK
0
1
2
3
4
5
6
7
Mode 3
1
Mode 0
Mode 3
Mode 0
0
Mode 0
Instruction
(04h)
Mode 0
DQ0
Instruction (04h)
DI
(DQ0)
DQ1
DQ2
High Impedance
D0
(DQ1)
DQ3
Figure 11 Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
11.9.
Read Status Register-1(RDSR1) (05h) , Status Register-2
(RDSR2) (35h)& Status Register-3 (RDSR3) (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction
is entered by driving CS# low and shifting the instruction code “05h” for Status Register-1, “35h”
for Status Register-2 or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The
status register bits are then shifted out on the DO pin at the falling edge of CLK with most
significant bit (MSB) first as shown in Figure 12. The Status Register bits are shown in Figure
5 ,Figure 6 and Figure 7.
The Read Status Register instruction may be used at any time, even while a Program, Erase or
Write Status Register cycle is in progress. This allows the WIP status bit to be checked to
determine when the cycle is complete and if the device can accept another instruction. The
Status Register can be read continuously, as shown in Figure 13. The instruction is completed
by driving CS# high.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
0
Mode 0
Instruction (05h/35h/15h)
DI
(DQ0)
Status Register 1/2/3 out
D0
(DQ1)
Status Register 1/2/3 out
High Impedance
7
«=MSB
6
5
4
«
3
2
1
0
7
6
5
4
3
2
7
«
Figure 12 Read Status Register Instruction (SPI Mode)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
23
CS#
Mode 3
CLK
0
1
2
4
3
5
Mode 0
Instruction
05h/35h/15h
DQ0
4
0
4
0
4
DQ1
5
1
5
1
5
DQ2
6
2
6
2
6
DQ3
7
3
7
3
7
SR1/2/3 out SR1/2/3 out
Figure 13 Read Status Register Instruction (QPI Mode)
11.10. Write Status Register-1(WRSR)(01h), Status Register-2 (31h)
& Status Register-3 (11h)
The Write Status Register (WRSR)instruction allows the Status Register to be written. Only nonvolatile Status Register bits SRP0, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) , WPS,
CMP, LB1, LB0 QE, SRP1 (bits 5 thru 0 of Status Register-2) , DRV0, DRV1(bits 2 thru 1 of
Status Register-3) can be written to. All other Status Register bit locations are read-only and will
not be affected by the Write Status Register (WRSR)instruction. LB1-0are non-volatile OTP bits,
once it is set to 1, it cannot be cleared to 0. The Status Register bits are shown in shown in
Figure 5 ,Figure 6 and Figure 7 and described in 10Status Register.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must
previously have been executed for the device to accept the Write Status Register (WRSR)
instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered
by driving CS# low, sending the instruction code “01h”, and then writing the status register data
byte as illustrated in Figure 14 and Figure 15.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction
must have been executed prior to the Write Status Register (WRSR)instruction (Status Register
bit WEL remains 0). However, SRP1 and LB1-0, cannot be changed from “1” to “0” because of
the OTP protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction,
the volatile Status Register bit values will be lost, and the non-volatile Status Register bit values
will be restored.
To complete the Write Status Register (WRSR)instruction, the CS# pin must be driven high after
the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register
(WRSR)instruction will not be executed. If CS# is driven high after the eighth clock the CMP, QE
and SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after CS# is driven
high, the self-timed Write Status Register cycle will commence for a time duration of tW (See
“12.6AC Electrical Characteristics”). While the Write Status Register cycle is in progress, the
Read Status Register instruction may still be accessed to check the status of the WIP bit. The
WIP bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and
ready to accept other instructions again. After the Write Status Register cycle has finished, the
FM25Q044M-BITSERIAL FLASH MEMORY
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24
Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after CS# is driven high,
the Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See
“12.6AC Electrical Characteristics”). WIP bit will remain 0 during the Status Register bit refresh
period.
The Write Status Register (WRSR) instruction can be used in both SPI mode and QPI mode.
However, the QE bit cannot be written to when the device is in the QPI mode, because QE=1 is
required for the device to enter and operate in the QPI mode.
CS#
0
Mode 3
CLK
1
2
3
4
5
6
8
7
10
11
12
13
14
15
Mode 0
Mode 3
Mode 0
Instruction
(01h/31h/11h)
Status Register 1/2/3 in
DI
(DQ0)
D0
(DQ1)
9
7
6
5
4
3
2
1
0
«
High Impedance
«=MSB
Figure 14 Write Status Register Instruction (SPI Mode)
CS#
Mode 3
CLK
0
1
2
3
Mode 3
Mode 0
Mode 0
Instruction
01h/31h/11h
SR 1/2/3
in
DQ0
4
0
4
0
DQ1
5
1
5
1
DQ2
6
2
6
2
DQ3
7
3
7
3
Figure 15 Write Status Register Instruction (QPI Mode)
The FM25Q02 is also backward compatible to FMSH’s previous generations of serial flash
memories, in which the Status Register-1&2 can be written using a single “Write Register-1(01h)”
command. To complete the Write Status Register1&2, the CS# pin must be driven high after the
sixteenth bit of data that is clocked in as shown in Figure 16&Figure 17 . If CS# is driven high
after the eighth clock, the Write Status Register (WRSR)instruction will only program the Status
Register-1, the Status Register-2 will not be affected.
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25
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 3
Mode 0
Instruction (01h)
Status Register 1 in
DI
(DQ0)
D0
(DQ1)
10
Mode 0
7
6
5
4
3
2
Status Register 2 in
1
0
«
15
14
13
12
11
10
9
8
«
High Impedance
«=MSB
Figure 16 Write Status Register-1/2 Instruction (backward compatible, SPI Mode)
CS#
Mode 3
CLK
0
1
2
3
4
5
Mode 3
Mode 0
Mode 0
Instruction
01h
SR1 in
SR2 in
DQ0
4
0
12
8
DQ1
5
1
13
9
DQ2
6
2
14
10
DQ3
7
3
15
11
Figure 17 Write Status Register-1/2 Instruction (backward compatible, QPI Mode)
11.11. Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the
memory. The instruction is initiated by driving the CS# pin low and then shifting the instruction
code “03h” followed by a 24-bit address A23-A0 into the DI pin. The code and address bits are
latched on the rising edge of the CLK pin. After the address is received, the data byte of the
addressed memory location will be shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first. The address is automatically incremented to the next higher
address after each byte of data is shifted out allowing for a continuous stream of data. This
means that the entire memory can be accessed with a single instruction as long as the clock
continues. The instruction is completed by driving CS# high.
The Read Data instruction sequence is shown in Figure 18. If a Read Data instruction is issued
while an Erase, Program or Write cycle is in process (WIP =1) the instruction is ignored and will
not have any effect on the current cycle. The Read Data instruction allows clock rates from D.C.
to a maximum of fR (see“12.6AC Electrical Characteristics”).
The Read Data (03h) instruction is only supported in Standard SPI mode.
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26
CS#
0 1
Mode3
CLK Mode0
2
4
3
5 6
8 9 10
7
28 29 30 31 32 33 34 35 36 37 38 39
24-Bit Addess
Instruction (03h)
DI
(DQ0)
23 22 21
▲
DO
(DQ1)
2
3
1
0
Data Out1
HIGH IMPEDANCE
5
6
7
▲
4
3
Data Out2
2
1
0
7
▲ = MSB
Figure 18 Read Data Instruction (SPI Mode only)
11.12. Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the
highest possible frequency of FR (see “12.6AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 19. The dummy
clocks allow the devices internal circuits additional time for setting up the initial address. During
the dummy clocks the data value on the DI pin is a “don’t care”.
CS#
Mode
3
CLK
0
1
Mode
0
2
3
4
5
6
8
7
9
10
Instruction (0Bh)
28
29
30
31
3
2
1
0
45
46
47
48
49
50
0
7
6
5
24-Bit Address
DI
(DQ0)
23
22
21
42
43
«
High Impedance
D0
(DQ1)
«=MSB
CS#
31
32
33
34
35
36
37
38
39
40
41
44
51
52
53
54
55
2
1
0
CLK
Dummy Clocks
DI
(DQ0)
0
Data Out 2
Data Out 1
D0
(DQ1)
High Impedance
7
6
5
4
3
2
1
4
3
7
«
«
Figure 19 Fast Read Instruction (SPI Mode)
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the
number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to
accommodate wide range applications with different needs for either maximum Fast Read
frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting,
the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of
dummy clocks upon power up or after a Reset instruction is 2.
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27
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Mode 0
Instruction
IOs switch from
Input to Output
A23-16
A15-8
A7-0
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
0Bh
Dummy«
Byte1
Byte2
* "Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Figure 20 Fast Read Instruction (QPI Mode)
11.13. Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh)
instruction except that data is output on two pins; DQ0 and DQ1. This allows data to be
transferred from the FM25Q04 at twice the rate of standard SPI devices. The Fast Read Dual
Output instruction is ideal for quickly downloading code from Flash to RAM upon power-up or for
applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the
highest possible frequency of FR (see “12.6AC Electrical Characteristics”). This is accomplished
by adding eight “dummy” clocks after the 24-bit address as shown in Figure 21. The dummy
clocks allow the device's internal circuits additional time for setting up the initial address. The
input data during the dummy clocks is “don’t care”. However, the DQ0 pin should be highimpedance prior to the falling edge of the first data out clock.
FM25Q044M-BITSERIAL FLASH MEMORY
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28
CS#
0
Mode 3
CLK
1
2
3
4
5
6
8
7
9
10
29
30
31
2
1
0
Mode 0
Instruction (3Bh)
24-Bit Address
DI
(DQ0)
D0
(DQ1)
28
23
22
21
3
«
High Impedance
«=MSB
CS#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
CLK
IO0 switches from
Input to Output
Dummy Clocks
DI
(DQ0)
0
6
4
2
0
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
7
5
3
1
6
4
2
0
6
7
5
3
1
7
«
High Impedance
D0
(DQ1)
7
«
«
Data Out 1
Figure 21
«
Data Out 2
«
Data Out 3
Data Out 4
Fast Read Dual Output Instruction (SPI Mode only)
11.14. Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh)
instruction except that data is output on four pins, DQ0, DQ1, DQ2, and DQ3. A Quad enable of
Status Register-2 must be executed before the device will accept the Fast Read Quad Output
Instruction (Status Register bit QE must equal 1). The Fast Read Quad Output Instruction allows
data to be transferred from the FM25Q04 at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see
“12.6AC Electrical Characteristics”). This is accomplished by adding eight “dummy” clocks after
the 24-bit address as shown in Figure 22. The dummy clocks allow the device's internal circuits
additional time for setting up the initial address. The input data during the dummy clocks is “don’t
care”. However, the DQ pins should be high-impedance prior to the falling edge of the first data
out clock.
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29
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28
29
30
31
2
1
0
Mode 0
Instruction (6Bh)
24-Bit Address
DQ0
23
22
21
3
«
High Impedance
DQ1
High Impedance
DQ2
High Impedance
DQ3
«=MSB
CS#
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
CLK
IO0 switches from
Input to Output
Dummy Clocks
DQ0
DQ1
DQ2
DQ3
0
High Impedance
High Impedance
High Impedance
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Byte4
Figure 22 Fast Read Quad Output Instruction (SPI Mode only)
11.15. Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining
two I/O pins, DQ0 and DQ1. It is similar to the Fast Read Dual Output (3Bh) instruction but with
the capability to input the Address bits A23-A0 two bits per clock. This reduced instruction
overhead may allow for code execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 23.
The upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction
through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the
(M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction
(after CS# is raised and then lowered) does not require the BBh instruction code, as shown in
Figure 24. This reduces the instruction sequence by eight clocks and allows the Read address to
FM25Q044M-BITSERIAL FLASH MEMORY
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Datasheet
30
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFFFh on
DQ0 for the next
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (BBh)
A23-16
DI
(DQ0)
D0
(DQ1)
A15-8
A7-0
22
20
18
16
14
12
10
8
6
4
2
0
23
21
19
17
15
13
11
9
7
5
3
1
6
4
2
0
7
5
3
1
«
«
«=MSB
M7-0
CS#
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
CLK
IOs switch from
Input to Output
DI
(DQ0)
0
D0
(DQ1)
1
6
4
2
0
7
5
3
1
«
6
4
2
0
7
5
3
1
«
Byte 1
6
4
2
0
7
5
3
1
«
Byte 2
6
4
2
0
6
7
5
3
1
7
«
Byte 3
Byte 4
Figure 23 Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI
Mode only)
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31
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
Mode 0
A23-16
A15-8
A7-0
M7-0
DI
(DQ0)
22
20
18
16
14
12
10
8
6
4
2
0
D0
(DQ1)
23
21
19
17
15
13
11
9
7
5
3
1
6
4
2
0
7
5
3
1
30
31
«
«
«=MSB
CS#
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
CLK
IOs switch from
Input to Output
DI
(DQ0)
0
6
4
2
0
6
4
2
0
6
4
2
0
6
4
2
0
6
D0
(DQ1)
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
«
«
Byte 1
«
Byte 2
«
Byte 3
Byte 4
Figure 24 Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode
only)
11.16. Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction
except that address and data bits are input and output through four pins DQ0, DQ1, DQ2 and DQ3
and four Dummy clocks are required in SPI mode prior to the data output. The Quad I/O
dramatically reduces instruction overhead allowing faster random access for code execution (XIP)
directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to enable
the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 25.
The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction
through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the
(M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction
(after CS# is raised and then lowered) does not require the EBh instruction code, as shown in
Figure 26. This reduces the instruction sequence by eight clocks and allows the Read address to
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.
FM25Q044M-BITSERIAL FLASH MEMORY
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32
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Mode 0
Instruction (EBh)
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy Dummy
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
Dq3
23
19
15
11
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Figure 25 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI
Mode)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 0
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy Dummy
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Figure 26 Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page
by issuing a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h)
command can either enable or disable the “Wrap Around” feature for the following EBh
commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8,
16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address
specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section,
the output will wrap around to the beginning boundary automatically until CS# is pulled high to
terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the
wrap around section within a page. See “11.19Set Burst with Wrap (77h)” for detail descriptions.
FM25Q044M-BITSERIAL FLASH MEMORY
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33
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 27. When
QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters
(C0h)” instruction to accommodate a wide range application with different needs for either
maximum Fast Read frequency or minimum data access latency. Depending on the Read
Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or
8. The default number of dummy clocks upon power up or after a Reset instruction is 2. In QPI
mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the
default setting, the data output will follow the Continuous Read Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O
instruction. Please refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To
perform a read operation with fixed data length wrap around in QPI mode, a dedicated “Burst
Read with Wrap” (0Ch) instruction must be used. Please refer to “11.38Burst Read with Wrap
(0Ch)” for details.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mode 0
Instruction
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0«
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
EBh
Byte1
Byte2
Byte3
* "Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Figure 27 Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI
Mode)
11.17. Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required
prior to the data output. The Quad I/O dramatically reduces instruction overhead allowing faster
random access for code execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of
Status Register-2 must be set to enable the Word Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits A23-A0, as shown in Figure 28.
FM25Q044M-BITSERIAL FLASH MEMORY
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34
The upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction
through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the
(M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance prior to the falling
edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction
(after CS# is raised and then lowered) does not require the E7h instruction code, as shown in
Figure 29. This reduces the instruction sequence by eight clocks and allows the Read address to
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1,0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Mode 0
Instruction (E7h)
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Figure 28 Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI
Mode only)
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Mode 0
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
Dummy
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Figure 29 Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode
only)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page
by issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
35
command can either enable or disable the “Wrap Around” feature for the following E7h
commands. When “Wrap Around” is enabled, the data being accessed can be limited to either a 8,
16, 32 or 64-byte section of a 256-byte page. The output data starts at the initial address
specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section,
the output will wrap around to the beginning boundary automatically until CS# is pulled high to
terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address
and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing
multiple read commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used
to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the
wrap around section within a page. See “11.19Set Burst with Wrap (77h)”for detail descriptions.
11.18. Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh)
instruction except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the
dummy clocks are not required, which further reduces the instruction overhead allowing even
faster random access for code execution (XIP). The Quad Enable bit (QE) of Status Register-2
must be set to enable the Octal Word Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through
setting the “Continuous Read Mode” bits M7-M0 after the input Address bits A23-A0, as shown in
Figure 30. The upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad
I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower
nibble bits of the (M3-0) are don’t care (“x”). However, the DQ pins should be high-impedance
prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction
(after CS# is raised and then lowered) does not require the E3h instruction code, as shown in
Figure 31. This reduces the instruction sequence by eight clocks and allows the Read address to
be immediately entered after CS# is asserted low. If the “Continuous Read Mode” bits M5-4 do
not equal to (1, 0), the next instruction (after CS# is raised and then lowered) requires the first
byte instruction code, thus returning to normal operation. It is recommended to input FFh on DQ0
for the next instruction (8 clocks), to ensure M4 = 1 and return the device to normal operation.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Mode 0
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
3
7
Instruction (E3h)
Byte1
Byte2
Byte3
Byte4
Figure 30 Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10,
SPI Mode only)
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
36
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
Mode 0
IOs switch from
Input to Output
A23-16
A15-8
A7-0
M7-0
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
0
4
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
3
7
Byte1
Byte2
Byte3
Byte4
Figure 31 Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI
Mode only)
11.19. Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast
Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64byte section within a 256-byte page. Certain applications can benefit from this feature and
improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the
CS# pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap
Bits”, W7-0. The instruction sequence is shown in Figure 32. Wrap bit W7 and the lower nibble
W3-0 are not used.
W6, W5
00
01
10
11
W4 = 0
Wrap Around
Wrap Length
Yes
Yes
Yes
Yes
8-byte
16-byte
32-byte
64-byte
W4 =1 (default)
Wrap Around
Wrap Length
No
No
No
No
N/A
N/A
N/A
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and
“Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte
section within any page. To exit the “Wrap Around” function and return to normal read operation,
another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4
upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the
controller issues a Set Burst with Wrap instruction to reset W4 = 1 prior to any normal Read
instructions since FM25Q04 does not have a hardware Reset Pin.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read
operation with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
37
valid in QPI mode and can also be re-configured by “Set Read Parameters (C0h)” instruction.
Refer to “11.37Set Read Parameters (C0h)” and “11.38Burst Read with Wrap (0Ch)” for details.
CS#
Mode 3
CLK
0
1
2
3
4
5
6
8
7
9
10
11
12
13
14
15
Mode 3
Mode 0
Mode 0
don’t
care
Instruction (77h)
don’t
care
DQ0
X
X
X
X
DQ1
X
X
X
X
DQ2
X
X
X
DQ3
X
X
X
don’t
care
X
Wrap
Bit
X
W4
X
X
X
W5
X
X
X
X
W6
X
X
X
X
X
X
Figure 32 Set Burst with Wrap Instruction (SPI Mode only)
11.20. Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be
programmed at previously erased (FFh) memory locations. A Write Enable instruction must be
executed before the device will accept the Page Program Instruction (Status Register bit WEL= 1).
The instruction is initiated by driving the CS# pin low then shifting the instruction code “02h”
followed by a 24-bit address A23-A0 and at least one data byte, into the DI pin. The CS# pin must
be held low for the entire length of the instruction while data is being sent to the device. The Page
Program instruction sequence is shown in Figure 33 and Figure 34.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant
address bits) should be set to 0. If the last address byte is not zero, and the number of clocks
exceeds the remaining page length, the addressing will wrap to the beginning of the page. In
some cases, less than 256 bytes (a partial page) can be programmed without having any effect
on other bytes within the same page. One condition to perform a partial page program is that the
number of clocks can not exceed the remaining page length. If more than 256 bytes are sent to
the device the addressing will wrap to the beginning of the page and overwrite previously sent
data.
As with the write and erase instructions, the CS# pin must be driven high after the eighth bit of the
last byte has been latched. If this is not done the Page Program instruction will not be executed.
After CS# is driven high, the self-timed Page Program instruction will commence for a time
duration of tPP (See “12.6AC Electrical Characteristics”). While the Page Program cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of
the WIP bit. The WIP bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Page Program cycle
has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Page
Program instruction will not be executed if the addressed page is protected by the Block Protect
(CMP, TB, BP2, BP1, and BP0) bits.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
38
CS#
0
Mode 3
CLK
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
2
1
0
Mode 0
Instruction (02h)
Data Byte 1
24-Bit Address
DI
(DQ0)
23
22
21
3
2
1
7
0
6
5
4
3
«
«
«=MSB
46
47
48
49
50
51
52
53
54
55
2079
45
2078
44
2077
43
2076
42
2075
41
2074
40
2073
39
2072
CS#
CLK
Mode 0
Data Byte 2
DI
(DQ0)
Mode 3
0
7
6
5
4
3
Data Byte 3
2
1
0
7
«
6
5
4
3
Data Byte 256
2
1
0
7
6
5
4
3
2
1
0
«
«
Figure 33 Page Program Instruction (SPI Mode)
2
3
4
5
6
7
8
9
10
11
12
13
519
1
518
0
517
Mode 3
CLK
516
CS#
Mode 0
Mode 3
Mode 0
Instruction
A23-16
02h
A15-8
A7-0
Byte1
Byte2
Byte3
Byte 255
Byte 256
DQ0
20
16
12
8
4
0
4
0
4
0
4
0
4
0
4
0
DQ1
21
17
13
9
5
1
5
1
5
1
5
1
5
1
5
1
DQ2
22
18
14
10
6
2
6
2
6
2
6
2
6
2
6
2
DQ3
23
19
15
11
7
3
7
3
7
3
7
3
7
3
7
3
Figure 34 Page Program Instruction (QPI Mode)
11.21. Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at
previously erased (FFh) memory locations using four pins: DQ0, DQ1, DQ2, and DQ3. The Quad
Page Program can improve performance for PROM Programmer and applications that have slow
clock speeds = 1 / FR or 1/fR ;
2. This parameter is characterized and is not 100% tested.
Table13
MAX
AC Characteristics (VCC = 2.3V to 2.7V)
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.3V to 2.7V, (unless
otherwise noted).
SYMBOL
FR
fR
tCLQV
tPP
tSE
tBE1
tBE2
tCE
PARAMETER
Serial Clock Frequency for:
FAST_READ, PP, SE, BE, DP, RES, WREN,
WRDI, WRSR
Serial Clock Frequency for READ, RDSR, RDID
Output Valid from CLK
Page Programming Time
Sector Erase Time
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
MIN
SPEC
TYP
10
100
800
1000
3
MAX
UNIT
80
MHz
33
9
35
1200
3000
5000
30
MHz
ns
ms
ms
ms
ms
s
Datasheet
69
CS#
tCH
CLK
I/O
OUTPUT
tCLQX
tCLQV
tCLQX
tCLQV
tCL
tSHQZ
LSB OUT
tQLQH
tQHQL
Figure 74 Serial Output Timing
tSHSL
CS#
tCHSL
tCHSH
tSLCH
tSHCH
CLK
tDVCH
I/O
INPUT
I/O
OUTPUT
tCHDX
tCLCH
MSB IN
tCHCL
LSB IN
(High Impedance)
Figure 75 Serial Input Timing
CS#
tHLCH
tCHHL
tHHCH
CLK
tCHHH
tHLQZ
tHHQX
I/O
OUTPUT
I/O
INPUT
HOLD#
Figure 76 Hold Timing
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
70
13.
Ordering Information
FM 25Q 04 -XXX -C -H
Company Prefix
FM = Fudan Microelectronics Group Co.,ltd
Product Family
25Q = 2.3~3.6V Serial Flash with 4KB Uniform-Sector,
Dual/Quad SPI & QPI
Product Density
04= 4M-bit
Package Type (1)
SO = 8-pin SOP（150mil）
SOB = 8-pin SOP（208mil）
TS = 8-pin TSSOP8
DN = 8-pin TDFN (2mm x 3mm)
(2)
Product Carrier
U = Tube
T = Tape and Reel
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Note:
1. For SO, TS, DN package, MSL1 package are available, for detail please contact local sales
office.
2. For Thinner package please contact local sales office.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
71
14.
Part Marking Scheme
14.1.
SOP8 (150mil)
FM25Q04
YYWWALHM
Moisture Sensitivity Level
1 = MSL1
Blank=MSL3
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Lot Number（just with 0~9、A~Z）
Assembly’s Code
Work week during which the product was molded (eg..week 12)
The last two digits of the year In which the product was sealed / molded.
14.2.
SOP8 (208mil)
FM25Q04
YYWWALHM
Moisture Sensitivity Level
1 = MSL1
Blank=MSL3
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Lot Number（just with 0~9、A~Z）
Assembly’s Code
Work week during which the product was molded (eg..week 12)
The last two digits of the year In which the product was sealed / molded.
14.3.
TSSOP8
FM25Q04
YYWWALHM
MSL Code
Blank = MSL3
1 = MSL1
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Lot Number（just with 0~9、A~Z）
Assembly’s Code
Work week during which the product was molded (eg..week 12)
The last two digits of the year In which the product was sealed / molded.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
72
14.4.
TDFN8(2x3mm)
5
Q 2
Y M
A
L
H
Product Density Code
The month (hexadecimal digit) in which the product was molded.
The last one digit of the year In which the product was sealed / molded.
HSF ID Code
M
G = RoHS Compliant, Halogen-free, Antimony-free
Moisture Sensitivity Level
1 = MSL1
Blank=MSL3
Lot Number（just with 0~9、A~Z）
Assembly’s Code
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
73
15.
Packaging Information
SOP 8 (150mil)
Symbol
MIN
A
1.350
A1
0.050
b
0.330
c
0.150
D
4.700
E1
3.700
E
5.800
e
1.270(BSC)
L
0.400
θ
0°
NOTE:
1. Dimensions are in Millimeters.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
MAX
1.750
0.250
0.510
0.260
5.150
4.100
6.200
1.270
8°
Datasheet
74
SOP 8 (208mil)
Symbol
MIN
A
––
A1
0.050
b
0.350
c
0.100
D
5.130
E1
5.180
E
7.700
e
L
0.500
θ
0°
NOTE:
1. Dimensions are in Millimeters.
FM25Q044M-BITSERIAL FLASH MEMORY
MAX
2.100
0.250
0.500
0.250
5.330
5.380
8.100
1.270(BSC)
Ver. 1.4
0.850
8°
Datasheet
75
TSSOP8
Symbol
MIN
D
2.900
E1
4.300
b
0.190
c
0.090
E
6.200
A
A1
0.050
e
0.650 (BSC)
L
0.450
θ
0°
NOTE:
1. Dimensions are in Millimeters.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
MAX
3.100
4.500
0.300
0.200
6.600
1.200
0.150
0.750
8°
Datasheet
76
TDFN8(2x3mm)
Symbol
MIN
A
0.700
A1
0.000
D
1.900
E
2.900
D2
1.400
E2
1.400
k
0.150(MIN)
b
0.200
e
0.500(TYP)
L
0.200
NOTE:
1. Dimensions are in Millimeters.
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
MAX
0.800
0.050
2.100
3.100
1.600
1.700
0.300
0.500
Datasheet
77
16.
Revision History
Publication
Pages
Revise Description
date
preliminary Sep. 2015
79 Initial Document Release.
0.1
Oct. 2015
79 Updated the Supply Voltage.
1.0
Jul. 2016
79 Updated the AC characteristics.
1.1
Oct.2016
79 Updated the DC/AC Electrical Characteristics
1.2
Jan. 2017
79 Updated the DC/AC Electrical Characteristics
1.3
May.2017
79 Corrected some typo
1.4
Aug. 2017
79 Corrected some typo
Version
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
78
Sales and Service
Shanghai Fudan Microelectronics Group Co., Ltd.
Address: Bldg No. 4, 127 Guotai Rd,
Shanghai City China.
Postcode: 200433
Tel: (86-021) 6565 5050
Fax: (86-021) 6565 9115
Shanghai Fudan Microelectronics (HK) Co., Ltd.
Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road,
Tsimshatsui East, Kowloon, Hong Kong
Tel: (852) 2116 3288 2116 3338
Fax: (852) 2116 0882
Beijing Office
Address: Room 423, Bldg B,Gehua Building,
1 QingLongHutong, Dongzhimen Alley north Street,
Dongcheng District, Beijing City, China.
Postcode: 100007
Tel: (86-010) 8418 6608
Fax: (86-010) 8418 6211
Shenzhen Office
Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel,
Huaqiang Rd (North),
Shenzhen City, China.
Postcode: 518028
Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611
Fax: (86-0755) 8335 9011
Shanghai Fudan Microelectronics (HK) Ltd Taiwan
Representative Office
Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist.,
Taipei City 114, Taiwan
Tel : (886-2) 7721 1890 (886-2) 7721 1889
Fax: (886-2) 7722 3888
Shanghai Fudan Microelectronics (HK) Ltd Singapore
Representative Office
Address : 237, Alexandra Road, #07-01 The Alexcier, Singapore
159929
Tel : (65) 6472 3688
Fax: (65) 6472 3669
Shanghai Fudan Microelectronics Group Co., Ltd NA Office
Address: 2490 W. Ray Road Suite#2
Chandler, AZ 85224 USA
Tel : (480) 857-6500 ext 18
Web Site: http://www.fmsh.com/
FM25Q044M-BITSERIAL FLASH MEMORY
Ver. 1.4
Datasheet
79
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