ZD25Q64BSIGT

ZD25Q64B 64M Ver.B SPI NOR FLASH 1 ZD25Q64B Table of Contents 1. 1. FEATURES ................................................................................................................. ......................5 2. GENERAL DESCRIPTION .................................................................................................................5 3. PIN / PAD CONFIGURATION .............................................................................................................6 3.1 3.2 8-Pad WSON 6X5-MM, 8X6-MM................................................................................... 6 3.3 16-Pin SOP 300-MIL ...................................................................................................... 7 3.4 4. 5. 8-pin VSOP 208-MIL, SOP 208-MIL, TSSOP 173-MIL .................................................. 6 24BallTFBGA.....................................................................................................................7 PIN / PAD DESCRIPTION ..................................................................................................................8 4.1 VSOP 208-MIL, SOP 200-MIL, WSON 6X5-MM, WSON 8X6-MM, 24-Ball TFBGA .......8 4.2 SOP 300-MIL......................................................................................................................8 4.3 Package Type.................................................................................................................... ........8 SIGNAL DESCRIPTION......................................................................................................................9 5.1 Chip Select (/CS ............................................................................... ................................9 5.2 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3 ...................................9 5.3 Write Protect (/WP ............................................................................ ................................9 5.4 HOLD (/HOLD...................................................................................................................9 5.5 Serial Clock (CLK..............................................................................................................9 6. BLOCK DIAGRAM ............................................................................................................................ 10 7. FUNCTIONAL DESCRIPTION .........................................................................................................11 8. 7.1 Standard SPI Instructions .............................................................................................. 11 7.2 Dual SPI Instructions ..................................................................................................... 11 7.3 Quad SPI Instructions .................................................................................................... 11 7.4 QPI Function.................................................................................................................12 7.5 Hold Function ................................................................................. ..............................12 WRITE PROTECTION ...................................................................................................................... 12 8.1 9. Write protect Features ................................................................................................... 13 STATUS REGISTER ........................................................................................................................ 14 9.1 BUSY...........................................................................................................................15 9.2 Write Enable Latch (WEL .............................................................................................. 15 9.3 Block Protect Bits (BP2, BP1, BP0 ................................................................................ 15 9.4 Top/Bottom Block protect (TB ........................................................................................ 15 9.5 Sector/Block Protect (SEC ............................................................................................. 15 9.6 Status Register protect (SRP1, SRP0 ........................................................................... 16 9.7 Quad Enable (QE… ...................................................................................................... 16 9.8 Complement Protect (CMP ............................................................................................ 16 9.9 Erase/Program Suspend Status (SUS ..........................................................................16 9.10 Status Register Memory Protection (CMP = 0 .............................................................. 17 9.11 Status Register Memory Protection (CMP = 1 ...............................................................18 10. INSTRUCTIONS ............................................................................................................................... 19 10.1 Manufacturer and Device Identification .........................................................................19 10.2 Instruction Set Table 1(SPI Instruction ...........................................................................20 10.3 Instruction Set Table 2 (Dual SPI Instruction ..................................................................21 10.4 Instruction Set Table 3 (Quad SPI Instruction ................................................................21 10.5 Instruction Set Table 4 (QPI Instruction .........................................................................22 2 ZD25Q64B 10.6 Write Enable (06h ..........................................................................................................24 10.7 Write Enable for Volatile Status Register (50h .............................................................. 24 10.8 Write Disable (04h ........................................................................................................ 25 10.9 Read Status Register-1 (05h and Read Status Register-2 (35h ....................................26 10.10 Write Status Register (01h ............................................................................................. 27 10.11 Write Status Register-2 (31h ......................................................................................... 28 10.12 Read Data (03h..............................................................................................................29 10.13 Fast Read (0Bh...............................................................................................................29 10.14 Fast Read Dual Output (3Bh ......................................................................................... 31 10.15 Fast Read Quad Output (6Bh ........................................................................................ 32 10.16 Fast Read Dual I/O (BBh .............................................................................................. 32 10.17 Fast Read Quad I/O (EBh .............................................................................................. 35 10.18 Page Program (02h........................................................................................................ 38 10.19 Quad Page Program (33h .............................................................................................. 40 10.20 Sector Erase (20h ........................................................................................................ 42 10.21 32KB Block Erase (52h ................................................................................................. 43 10.22 64KB Block Erase (D8h ................................................................................................ 44 10.23 Chip Erase (C7h / 60h ................................................................................................... 45 10.24 Erase / Program Suspend (75h ..................................................................................... 46 10.25 Erase / Program Resume (7Ah ...................................................................................... 48 10.26 Deep Power-down (B9h ................................................................................................ 49 10.27 Release Deep Power-down / Device ID (ABh..............................................................50 10.28 Read Manufacturer/ Device ID (90h .............................................................................. 52 10.29 Read Manufacturer / Device ID Dual I/O (92h .............................................................. 53 10.30 Read Manufacturer / Device ID Quad I/O (94h ............................................................. 54 10.31 JEDEC ID (9Fh ............................................................................................................. 55 10.32 Enable QPI (38h .......................................................................................................... 56 10.33 Disable QPI (FFh ........................................................................................................ 56 10.34 Word Read Quad I/O (E7h ............................................................................................ 57 10.35 Set Burst with Wrap (77h .............................................................................................. 59 10.36 Burst Read with Wrap (0Ch ........................................................................................... 60 10.37 Set Read Parameters (C0h ........................................................................................... 62 10.38 Enable Reset (66h and Reset (99h ................................................................................ 63 10.39 Read Serial Flash Discovery Parameter (5Ah ...............................................................64 10.40 Enter Secured OTP (B1h .............................................................................................. 68 10.41 Exit Secured OTP (C1h ................................................................................................. 68 10.42 Read Security Register (2Bh ......................................................................................... 69 10.43 Write Security Register (2Fh ......................................................................................... 70 11. 4K-bit Secured OTP ......................................................................................................................... 71 12. ELECTRICAL CHARACTERISTICS .................................................................................................72 12.1 Absolute Maximum Ratings ........................................................................................... 72 12.2 Operating Ranges..........................................................................................................72 12.3 Endurance and Data Retention ..................................................................................... 72 12.4 Power-up Timing and Write Inhibit Threshold… ............................................................73 12.5 DC Electrical Characteristics ......................................................................................... 74 3 ZD25Q64B 12.6 AC Measurement Conditions .........................................................................................76 12.7 AC Electrical Characteristics ..........................................................................................77 12.8 AC Electrical Characteristics (Cont’d .............................................................................78 12.9 Input Timing ...................................................................................................................79 12.10 Output Timing ................................................................................................................79 12.11 Hold Timing ....................................................................................................................79 13. PACKAGE SPECIFICATION ............................................................................................................80 13.1 8-Pin VSOP 208-mil ......................................................................................................80 13.2 8-Pin SOP 208-mil ........................................................................................................81 13.3 8-contact 6x5 WSON ....................................................................................................82 13.4 8-contact 6x5 WSON(Cont’d ..........................................................................................83 13.5 24-Ball TFBGA ..............................................................................................................84 14. ORDERING INFORMATION ............................................................................................................85 4 ZD25Q64B 1. FEATURES ■ SPI Flash Memory −64M-bit / 8M–byte Serial Flash −256-bytes per programmable page ■ Low Power Consumption −Single 2.7 to 3.6V supply −5mA active current −4K-bit secured OTP −80MHz Fast Read Data >108MHz 0Bh >133MHz (SR7SR0 (2 (SR15SR8(2 (SR7SR0 (SR15SR8 (SR15SR8 A23-A16 A15-A8 A7-A0 dummy dummy (D7-D0 A23-A16 A15-A8 A7-A0 dummy dummy dummy (D7D0 A23-A16 A15-A8 A7-A0 dummy dummy dummy dummy (D7-D0 Page Program 02h A23-A16 A15-A8 A7-A0 Sector Erase(4KB 20h A23-A16 A15-A8 A7-A0 Block Erase(32KB 52h A23-A16 A15-A8 A7-A0 Block Erase(64KB D8h A23-A16 A15-A8 A7-A0 Chip Erase 60h/ C7h Erase/Program Suspend 75h Erase/Program Resume 7Ah Deep Power-down B9h Release Deep power down ABh Dummy dummy dummy (ID7ID0(2 Read Manufacturer/ Device ID(4 90h 00h 00h 00h or 01h (MID7MID0 Read JEDEC ID(4 9Fh (MID7MID0 Manufact urer (D7-D0 Memory Type (D7-D0 Capacity Type Enter Security B1h Exit Security C1h Read Security Register 2Bh Write Security Register 2Fh A23-A16 A15-A8 A7-A0 (M7-M0 dummy (D7-D0 A23-A16 A15-A8 A7-A0 (M7-M0 dummy dummy (D7D0 A23-A16 A15-A8 A7-A0 (M7-M0 dummy dummy dummy >80MHz Fast Read Quad I/O >108MHz EBh >133MHz Reset Enable (D7D0 (3 (DID7DID0 (SC7SC0 (10 (D7D0 66h 22 ZD25Q64B Reset 99h Disable QPI FFh >80MHz Burst Read with Wrap >108MHz 0Ch >133MHz A23-A16 A15-A8 A7-A0 dummy dummy (D7-D0 A23-A16 A15-A8 A7-A0 dummy dummy dummy (D7D0 A23-A16 A15-A8 A7-A0 dummy dummy dummy dummy A15-A8 A7-A0 Set Read Parameter C0h P7-P0 Quad Page Program 33h A23-A16 Notes: 1. 2. 3. 4. 5. 6. (D7D0 (D7-D0 Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “(” indicate data being read from the device on the IO pin. SR = status register, The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction. At least one byte of data input is required for Page Program, Quad Page Program and Program Security Register, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data. See Manufacturer and Device Identification table for Device ID information. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3, M1 Dual Output data IO0 = (D6, D4, D2, D0 IO1 = (D7, D5, D3, D1 7. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 8. Quad Input/ Output Data IO0 = (D4, D0… IO1 = (D5, D1… IO2 = (D6, D2… IO3 = (D7, D3… 9. Fast Read Quad I/O Data Output IO0 = (x, x, x, x, D4, D0… IO1 = (x, x, x, x, D5, D1… IO2 = (x, x, x, x, D6, D2… IO3 = (x, x, x, x, D7, D3… Set Burst with Wrap Input IO0 = x, x, x, x, x, x, W4, x IO1 = x, x, x, x, x, x, W5, x IO2 = x, x, x, x, x, x, W6, x IO3 = x, x, x, x, x, x, x x 10. SC = security register 23 ZD25Q64B 9.6 Write Enable (06h Write Enable instruction is for setting the Write Enable Latch (WEL bit in the Status Register. The WEL bit must be set prior to every Program, Erase and Write Status Register instruction. To enter the Write Enable instruction, /CS goes low prior to the instruction “06h” into Data Input (DI pin on the rising edge of CLK, and then driving /CS high. 9.7 Write Enable for Volatile Status Register (50h This gives more flexibility to change the system configuration and memory protection schemes quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status Register (50h instruction must be issued prior to a Write Status Register (01h instruction. Write Enable for Volatile Status Register instruction (Figure 7 will not set the Write Enable Latch (WEL bit. Once Write Enable for Volatile Status Register is set, a Write Enable instruction should not have been issued prior to setting Write Status Register instruction (01h or 31h. 24 ZD25Q64B 9.8 Write Disable (04h The Write Disable instruction is to reset the Write Enable Latch (WEL bit in the Status Register. To enter the Write Disable instruction, /CS goes low prior to the instruction “04h” into Data Input (DI pin on the rising edge of CLK, and then driving /CS high. WEL bit is automatically reset writedisable status of “0” after Power-up and upon completion of the every Program, Erase and Write Status Register instructions. 25 ZD25Q64B 9.9 Read Status Register-1 (05h and Read Status Register-2 (35h The Read Status Register instructions are to read the Status Register. The Read Status Register can be read at any time (even in program/erase/write Status Register and Write Security Register condition. It is recommended to check the BUSY bit before sending a new instruction when a Program, Erase, Write Status Register or Write Status Register operation is in progress. The instruction is entered by driving /CS low and sending the instruction code “05h” for Status Register-1 or “35h” for Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB first as shown in (figure 9. The Status Register can be read continuously. The instruction is completed by driving /CS high.   26 ZD25Q64B 9.10 Write Status Register (01h The Write Status Register instruction is to write only non-volatile Status Register-1 bits (SRP0, SEC, TB, BP2, BP1 and BP0 and Status Register-2 bits (CMP, QE and SRP1. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status Register bit WEL must equal 1. Once write is enabled, the instruction is entered by driving /CS low, sending the instruction code, and then writing the status register data byte as illustrated in figure 10. The /CS pin must be driven high after the eighth or sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be executed. If /CS is driven high after the eighth clock, the CMP, QE and SRP1 bits will be cleared to 0. After /CS is driven high, the selftimed Write Status Register cycle will commence for a time duration of tw (See AC Characteristics. While the Write Status Register cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a 0 when the cycle is finished and ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in Status Register will be cleared to 0. 27 ZD25Q64B 9.11 Write Status Register-2 (31h The Write Status Register-2 instruction is to write only non-volatile Status Register-2 bits (CMP, QE and SRP1. A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status Register bit WEL must equal 1. Once write is enabled, the instruction is entered by driving /CS low, sending the instruction code, and then writing the status register data byte as illustrated in figure 11. Using Write Status Register-2 (31h instruction, software can individually access each one-byte status registers via different instructions. 28 ZD25Q64B 9.12 Read Data (03h The Read Data instruction is to read data out from the device. The instruction is initiated by driving the /CS pin low and then sending the instruction code “03h” with following a 24-bit address (A23A0 into the DI pin. After the address is received, the data byte of the addressed memory location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB first. The address is automatically incremented to the next higher address after byte of data is shifted out allowing for a continuous stream of data. This means that the entire memory can be accessed with a single instruction as long as the clock continues. The instruction is completed by driving /CS high. The Read Data instruction sequence is shown in (figure 12. If a Read Data instruction is issued while an Erase, Program or Write Status Register cycle is in process (BUSY=1 the instruction is ignored and will not have any effects on the current cycle. The Read Data instruction allows clock rates from D.C to a maximum of fR (see AC Electrical Characteristics.   9.13 Fast Read (0Bh The Fast Read instruction is high speed reading mode that it can operate at the highest possible frequency of FR. The address is latched on the rising edge of the CLK. After the 24-bit address, this is accomplished by adding “dummy” clocks as shown in (figure 13. The dummy clocks means the internal circuits require time to set up the initial address. During the dummy clocks, the data value on the DO pin is a “don’t care”. Data of each bit shifts out on the falling edge of CLK. 29 ZD25Q64B  Fast Read in QPI Mode When QPI mode is enabled, the number of dummy clock is configured by the “Set Read Parameters (C0h” instruction to accommodate wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bit P[4] and P[5] setting, the number of dummy clocks can be configured as either 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 4. (Please refer to figure 13b, 13c, 13d.   30 ZD25Q64B 9.14 Fast Read Dual Output (3Bh By using two pins (IO0 and IO1, instead of just IO0, The Fast Read Dual Output instruction allows data to be transferred from the ZD25Q64B at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to RAM upon powerup or for application that cache code-segments to RAM for execution. The Fast Read Dual Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics. After the 24-bit address, this is accomplished by adding eight “dummy” clocks as shown in (figure 14. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the dummy clocks, the data value on the DO pin is a “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock. 31 ZD25Q64B 9.15 Fast Read Quad Output (6Bh By using four pins (IO0, IO1, IO2, and IO3, The Fast Read Quad Output instruction allows data to be transferred from the ZD25Q64B at four times the rate of standard SPI devices. A Quad enable of Status Register-2 must be executed before the device will accept the Fast Read Quad Output instruction (Status Register bit QE must equal 1. The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC Electrical Characteristics. This is accomplished by adding eight “dummy” clocks after the 24- bit address as shown in (figure 15. The dummy clocks allow the internal circuits additional time for setting up the initial address. During the dummy clocks, the data value on the DO pin is a “don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock  32 ZD25Q64B 9.16 Fast Read Dual I/O (BBh The Fast Read Dual I/O instruction reduces cycle overhead through double access using two IO pins: IO0 and IO1. Continuous read mode The Fast Read Dual I/O instruction can further reduce cycle overhead through setting the Mode bits (M7-0 after the input Address bits (A23-0. The upper nibble of the Mode (M7-4 controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0 are don’t care (“X”, However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0 equal “Ax” hex, then the next Fast Dual I/O instruction (after /CS is raised and then lowered does not require the instruction (BBh code, as shown in (figure 16b. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after /CS is asserted low. If Mode bits (M7-0 are any value other “Ax” hex, the next instruction (after /CS is raised and then lowered requires the first byte instruction code, thus returning to normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0 before issuing normal instructions. 33 ZD25Q64B 34 ZD25Q64B 9.17 Fast Read Quad I/O (EBh The Fast Read Quad I/O instruction reduces cycle overhead through quad access using four IO pins: IO0, IO1, IO2, and IO3. The Quad Enable bit (QE of Status Register-2 must be set to enable the Fast read Quad I/O Instruction. Continuous read mode The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the Mode bits (M7-0 with following the input Address bits (A23-0, as shown in (figure 17a. The upper nibble of the Mode (M7-4 controls the length of the next Fast Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the Mode (M3-0 are don’t care (“X”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the Mode bits (M7-0 equal “Ax” hex, then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered does not require the EBh instruction code, as shown in (figure 17b. This reduces the instruction sequence by eight clocks and allows the address to be immediately entered after /CS is asserted low. If the Mode bits (M7-0 are any value other than “Ax” hex, the next instruction (after /CS is raised and then lowered requires the first byte instruction code, thus retuning normal operation. A Mode Bit Reset can be used to reset Mode Bits (M7-0 before issuing normal instructions.  35 ZD25Q64B Wrap Around in SPI mode The Fast Read Quad I/O instruction can also be used to access specific portion within a page by issuing a “Set Burst with Wrap” (77h instruction prior Fast Read Quad I/O (EBh instruction. The “Set Burst with Wrap” (77h instruction can either enable or disable the “Wrap Around” feature for the following Fast Read Quad I/O instruction. When “Wrap Around” is enabled, the data being accessed can be limited to an 8/16/32/64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte of data without issuing multiple read instructions. (Please refer to 10.35 Set Burst with Wrap. Fast Read Quad I/O in QPI mode When QPI mode in enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h” instruction to accommodate a wide range applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P [4] and P [5] setting, the number of dummy clocks can be configured as either 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset (99h instruction is 4. “Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. In QPI mode, the “Continuous Read Mode” bits M7-0 are also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read Mode bits immediately. “Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read operation with fixed data length wrap around in QPI mode, a “Burst Read with Wrap” (0Ch instruction must be used. (Please refer to 10.36 Burst Read with Wrap.   36 ZD25Q64B 37 ZD25Q64B 9.18 Page Program (02h The Page Program instruction is for programming the memory to be “0”. A Write Enable instruction must be issued before the device accept the Page Program Instruction (Status Register bit WEL= 1. After the Write Enable (WREN instruction has been decoded, the device sets the Write Enable Latch (WEL. The instruction is entered by driving the /CS pin low and then sending the instruction code “02h” with following a 24-bits address (A23-A0 and at least one data byte, into the DI pin. The /CS pin must be driven low for the entire time of the instruction while data is being sent to the device. (Please refer to figure 18. If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven high, the self-timed Page Program instruction will commence for a time duration of tPP (See AC Characteristics. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in the Status Register is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0 bits. 38 ZD25Q64B  39 ZD25Q64B 9.19 Quad Page Program (33h The Quad Page Program instruction is to program the memory as being “0” at previously erased memory areas. The Quad Page Program takes four pins: IO0, IO1, IO2 and IO3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 5MHz. System using faster clock speed will not get more benefit for the Quad Page Program as the required internal page program time is far more than the time data clock-in. To use Quad Page Program, the Quad Enable bit must be set, A Write Enable instruction must be executed before the device will accept the Quad Page Program instruction (Status Register-1, WEL=1. The instruction is initiated by driving the /CS pin low then sending the instruction code “33h” with following a 24-bit address (A23-A0 and at least one data, into the IO pins. The /CS pin must be held low for the entire length of the instruction while data is being sent to the device. All other functions of Quad Page Program are perfectly same as standard Page Program. (Please refer to figure 19.   40 ZD25Q64B  41 ZD25Q64B 9.20 Sector Erase (20h The Sector Erase instruction is to erase the data of the selected sector as being “1”. The instruction is used for 4K-byte sector. Prior to the Sector Erase Instruction, the Write Enable instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0. (Please refer to figure 20. The /CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Sector Erase instruction will not be executed. After /CS goes high, the self-timed Sector Erase instruction will commence for a time duration of tSE (See AC Characteristics. While the Sector Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in the Status Register is cleared to 0. The sector Erase instruction will not be executed if the addressed page is protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0 bits. 42 ZD25Q64B 9.21 32KB Block Erase (52h The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction is used for 32K-byte Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0. (Please refer to figure 21. The /CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE1 (See AC Characteristics. While the Block Erase cycle is in progress, the Read Status Register instruction may still be read the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in the Status Register is cleared to 0. The Block erase instruction will not be executed if the addressed page is protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0 bits. 43 ZD25Q64B 9.22 64KB Block Erase (D8h The Block Erase instruction is to erase the data of the selected block as being “1”. The instruction is used for 64K-byte Block erase operation. Prior to the Block Erase Instruction, a Write Enable instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0. (Please refer to figure 22. The /CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction will commence for a time duration of tBE2 (See AC Characteristics. While the Block Erase cycle is in progress, the Read Status Register instruction may still be read the status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in the Status Register is cleared to 0. The Block erase instruction will not be executed if the addressed page is protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0 bits. 44 ZD25Q64B 9.23 Chip Erase (C7h / 60h The Chip Erase instruction clears all bits in the device to be FFh (all 1s. Prior to the Chip Erase Instruction, a Write Enable instruction must be issued. The instruction is initiated by driving the /CS pin low and shifting the instruction code “C7h” or “60h”. (Please refer to figure 23. The /CS pin must go high after the eighth bit of the last byte has been latched in, otherwise, the Chip Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will commence for a duration of tCE (See AC Characteristics. While the Chip Erase cycle is in progress, the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL bit in the Status Register is cleared to 0. The Chip erase instruction will not be executed if any page is protected by the Protect (CMP, SEC, TB, BP2, BP1 and BP0 bits. 45 ZD25Q64B 9.24 Erase / Program Suspend (75h The Erase/Program Suspend instruction allows the system to interrupt a Sector Erase, Block Erase operation or a Page Program, Quad Page Program operation. Erase Suspend is valid only during the Sector or Block erase operation. The Write Status Register1(01h, Write Status Register-2 (31h instruction and Erase instructions (20h, 52h, D8h, C7h, 60h are not allowed during Erase Suspend. During the Chip Erase operation, the Erase Suspend instruction is ignored. Program Suspend is valid only during the Page Program, Quad Page Program operation. The Write Status Register-1(01h, Write Status Register-2 (31h instruction and Program instructions (02h and 33h are not allowed during Program Suspend. The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics is required to suspend the erase or program operation. After Erase/Program Suspend, the SUS bit in the Status Register will be set from 0 to 1 immediately and The BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS”. For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”. Unexpected power off during the Erase/Program suspend state will reset the device and release the suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block that was being suspended may become corrupted. It is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. (Please refer to figure 24. 46 ZD25Q64B 47 ZD25Q64B 9.25 Erase / Program Resume (7Ah The Erase/Program Resume instruction “7Ah” is to re-work the Sector or Block Erase operation or the Page Program operation upon an Erase/Program Suspend. The Resume instruction “7Ah” will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals to 0. After issued, the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will be ignored by the device. Resume instruction cannot be accepted if the previous Erase/Program Suspend operation was interrupted by unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be issued within a minimum of time of “tSUS” following a previous Resume instruction. (Please refer to figure 25. 48 ZD25Q64B 9.26 Deep Power-down (B9h Executing the Deep Power-down instruction is the best way to put the device in the lowest power consumption. The Deep Power-down instruction reduces the standby current (from ICC1 to ICC2, as specified in AC characteristics. The instruction is entered by driving the /CS pin low with following the instruction code “B9h”. (Please refer to figure 26. The /CS pin must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in; otherwise, the Deep Power-down instruction is not executed. After /CS goes high, it requires a delay of tDP and the Deep Power-down mode is entered. While in the Release Deep Power-down / Device ID instruction, which restores the device to normal operation, will be recognized. All other instructions are ignored including the Read Status Register instruction, which is always available during normal operation. Deep Power-down Mode automatically stops at Power-Down, and the device always Power-up in the Standby Mode. 49 ZD25Q64B 9.27 Release Deep Power-down / Device ID (ABh The Release Deep Power-down / Device ID instruction is a multi-purpose instruction. It can be used to release the device from the Deep Power-down state or obtain the device identification (ID. The instruction is issued by driving the /CS pin low, sending the instruction code “ABh” and driving /CS high as shown in figure 27a & 27b. Release from Deep Power-down require the time duration of tRES1 (See AC Characteristics for re-work a normal operation and accepting other instructions. The /CS pin must keep high during the tRES1 time duration. To obtain the Device ID in SPI mode, instruction is initiated by driving the /CS pin low and sending the instruction code “ABh” with following 3-dummy bytes. The Device ID bits are then shifted on the falling edge of CLK with most significant bit (MSB first as shown in figure 27c & 27d. After /CS is driven high it must keep high for a time duration of tRES2 (See AC Characteristics. The Device ID can be read continuously. The instruction is completed by driving /CS high. If the Release from Deep Power-down /Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals 1 the instruction is ignored and will not have any effects on the current cycle. 50 ZD25Q64B 51 ZD25Q64B 9.28 Read Manufacturer/ Device ID (90h The Read Manufacturer/ Device ID instruction provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/ Device ID instruction is very similar to the Release from Power-down / Device ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit address (A23-A0 of 000000h. After which, the Manufacturer ID(BAh and the Device ID(16h are shifted out on the falling edge of CLK with most significant bit (MSB first as shown in figure 28a & 28b. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. 52 ZD25Q64B 9.29 Read Manufacturer / Device ID Dual I/O (92h The Read Manufacturer/ Device ID Dual I/O instruction provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Dual I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24-bit address (A23-A0 of 000000h. After which, the Manufacturer ID(BAh and the Device ID(16h are shifted out on the falling edge of CLK with most significant bit (MSB first as shown in figure 29. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. 53 ZD25Q64B 9.30 Read Manufacturer / Device ID Quad I/O (94h The Read Manufacturer/ Device ID Quad I/O instruction provides both the JEDEC assigned manufacturer ID and the specific device ID. The Read Manufacturer/ Device ID instruction is very similar to the Fast Read Quad I/O instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a 24-bit address (A23-A0 of 000000h. After which, the Manufacturer ID(BAh and the Device ID(16h are shifted out on the falling edge of CLK with most significant bit (MSB first as shown in figure 30. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The Manufacturer and Device ID can be read continuously, alternating from one to the other. The instruction is completed by driving /CS high. 54 ZD25Q64B 9.31 JEDEC ID (9Fh For compatibility reasons, the ZD25Q64B provides several instructions to electronically determine the identity of the device. The Read JEDEC ID instruction is congruous with the JEDEC standard for SPI compatible serial flash memories that was adopted in 2003. The instruction is entered by driving the /CS pin low with following the instruction code “9Fh”. JEDEC assigned Manufacturer ID byte and two Device ID bytes, Memory Type (ID-15-ID8 and Capacity (ID7-ID0 are then shifted out on the falling edge of CLK with most significant bit (MSB first shown in figure 31. For memory type and capacity values refer to Manufacturer and Device Identification table. The JEDEC ID can be read continuously. The instruction is terminated by driving/CS high. 55 ZD25Q64B 9.32 Enable QPI (38h The ZD25Q64B support both Standard/Dual/Quad Serial Peripheral interface (SPI and Quad Peripheral Interface (QPI. However, SPI mode and QPI mode cannot be used at the same time. Enable QPI instruction is the only way to switch the device from SPI mode to QPI mode. In order to switch the device to QPI mode, the Quad Enable (QE bit in Status Register 2 must be set to 1 first, and an Enable QPI instruction must be issued. If the Quad Enable (QE bit is 0, the Enable QPI instruction will be ignored and the device will remain in SPI mode. After power-up, the default state of the device is SPI mode. See the instruction Set Table 1-3 for all the commands supported in SPI mode and the instruction Set Table 4 for all the instructions supported in QPI mode. When the device is switched from SPI mode to QPI mode, the existing Write Enable and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. 9.33 Disable QPI (FFh By issuing Disable QPI (FFh instruction, the device is reset SPI mode. When the device is switched from QPI mode to SPI mode, the existing Write Enable Latch (WEL and Program/Erase Suspend status, and the Wrap Length setting will remain unchanged. 56 ZD25Q64B 9.34 Word Read Quad I/O (E7h The Quad I/O dramatically reduces instruction overhead allowing faster random access for code execution (XIP directly from the Quad SPI. The Quad Enable bit (QE of Status Register-2 must be set to enable the Word Read Quad I/O instruction. The lowest Address bit (A0 must equal 0 and only two dummy clocks are required prior to the data output. Continuous Read Mode The Word Read Quad I/O instruction can further reduce instruction overhead through setting the “Continuous Read Mode” bits (M7-0 after the input Address bits (A23-0, as shown in Figure 34a. The upper nibble of the (M7-4 controls the length of the next Word Read Quad I/O instruction through the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M[3:0] are don’t care (“X”. However, the IO pins should be high-impedance prior to the falling edge of the first data out clock. If the “Continuous Read Mode” bits M[7-4]= Ah, then the next Fast Read Quad I/O instruction (after /CS is raised and then lowered does not require the E7h instruction code, as shown in Figure 34b. This reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS is asserted low. If the “Continuous Read Mode” bits M[7:4] do not equal to Ah(1,0,1,0 the next instruction (after /CS is raised and then lowered requires the first byte instruction code, thus returning to normal operation.  57 ZD25Q64B Wrap Around in SPI mode The Word Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap” (77h instruction prior to E7h. The “Set Burst with Wrap” (77h instruction can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap Around” is enabled, the output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64-byte of data without issuing read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable or disable the “Wrap Around” operation while W6-5 is used to specify the length of the wrap around section within a page. See 10.35 for detail descriptions. 58 ZD25Q64B 9.35 Set Burst with Wrap (77h The Set Burst with Wrap (77h instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain applications can benefit from this feature and improve the overall system code execution performance. Before the device will accept the Set Burst with Wrap instruction, a Quad enable of Status Register-2 must be executed (Status Register bit QE must equal 1. The Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The instruction sequence is shown in Set Burst with Wrap Instruction Sequence. Wrap bit W7 and W3-0 are not used. W6, W5 W4 = 0 W4 = 1(Default Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 Yes 16-byte No N/A 1 0 Yes 32-byte No N/A 1 1 Yes 64-byte No N/A Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and Word Read Quad I/O instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap instruction or Reset (99h instruction to reset W4 = 1 prior to any normal Read instructions since ZD25Q64B does not have a hardware Reset Pin. 59 ZD25Q64B 9.36 Burst Read with Wrap (0Ch The “Burst Read with Wrap (0Ch” instruction provides an alternative way to perform the read operation with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh” instruction in QPI mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the “Wrap Length” once the ending boundary is reached. The “Wrap Length” and the number of dummy of clocks can be configured by the “Set Read Parameters (C0h” instruction.   60 ZD25Q64B   61 ZD25Q64B 9.37 Set Read Parameters (C0h In QPI mode, to accommodate a wide range of applications with different needs for either maximum read frequency or minimum data access latency, “Set Read Parameters (C0h” instruction can be used to configure the number of dummy clocks for “Fast Read (0Bh”, “Fast Read Quad I/O (EBh” & “Burst Read with Wrap (0Ch” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read with Wrap (0Ch” instruction. In Standard SPI mode, the “Set Read Parameters (C0h” instruction is not accepted. The dummy clocks for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the instruction. Table 10.2 - 10.5 for details. The “Wrap Length” is set by W6-5 bit in the “Set Burst with Wrap (77h” instruction. This setting will remain unchanged when the device is switched from Standard SPI mode to QPI mode. The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of dummy clocks is 4. P5, P4 Dummy Clocks Maximum Read Freq. P1, P0 Wrap Length 0 0 4 80MHz 00 8-byte 0 1 4 80MHz 01 16-byte 1 0 6 108MHz 10 32-byte 1 1 8 133MHz 11 64-byte 62 ZD25Q64B 9.38 Enable Reset (66h and Reset (99h Because of the small package and the limitation on the number of pins, the ZD25Q64B provide a software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going internal operations will be terminated and the device will return to its default power-on state and lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL status, Program/Erase Suspend status, Continuous Read Mode bit setting, Read parameter setting and Wrap bit setting. “Enable Reset (66h” and “Reset (99h” instructions can be issued in either SPI mode or QPI mode. To avoid accidental reset, both instructions must be issued in sequence. Any other instructions other than “Reset (99h” after the “Enable (66h” instruction will disable the “Reset Enable” state. A new sequence of “Enable Reset (66h” and “Reset (99h” is needed to reset the device. Once the Reset instruction is accepted by the device will take approximately tRST= 30us to reset. During this period, no instruction will be accepted. Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when Reset instruction sequence is accepted by device. It is recommended to check the BUSY bit and the SUS bit in Status Register before issuing the Reset instruction sequence. 63 ZD25Q64B 9.39 Read Serial Flash Discovery Parameter (5Ah The Read Serial Flash Discovery Parameter (SFDP instruction allows reading the Serial Flash Discovery Parameter area (SFDP. This SFDP area is composed of 2048 read-only bytes containing operating characteristics and vendor specific information. The SFDP area is factory programmed. If the SFDP area is blank, the device is shipped with all the SFDP bytes at FFh. If only a portion of the SFDP area is written to, the portion not used is shipped with bytes in erased state (FFh. The instruction sequence for the read SFDP has the same structure as that of a Fast Read instruction. First, the device is selected by driving Chip Select (/CS Low. Next, the 8-bit instruction code (5Ah and the 24-bit address are shifted in, followed by 8 dummy clock cycles. The bytes of SFDP content are shifted out on the Serial Data Output (DO starting from the specified address. Each bit is shifted out during the falling edge of Serial Clock (CLK. The instruction sequence is shown here. The Read SFDP instruction is terminated by driving Chip Select (/CS High at any time during data output. 64 ZD25Q64B Read Serial Flash Discovery Parameter (SFDP BYTE ADDRESS DATA DESCRIPTION COMMENT 00h 53h SFDP Signature 01h 46h SFDP Signature SFDP Signature 02h 44h SFDP Signature =50444653h 03h 50h SFDP Signature 04h 01h SFDP Minor Revisions 05h 01h SFDP Major Revisions 06h 00h Number of Parameter Header(NPH 07h FFh Reserved 08h BAh PID(0(3 : Manufacture JEDEC ID 09h 00h PID(0 : Serial Flash Basics Minor Revisions Serial Flash Basics 0Ah 01h PID(0 : Serial Flash Basics Major Revisions Revision 1.0 0Bh 04h PID(0 : Serial Flash Basics Length 4 Dwords (2 0Ch 80h PID(0 : Address of Parameter ID(0 Table (A7-A0 0Dh 00h PID(0 : Address of Parameter ID(0 Table (A15-A8 0Eh 00h PID(0 : Address of Parameter ID(0 Table (A23-A16 0Fh FFh Reserved ... (1 FFh Reserved 80h E5h Bit[7:5] = 111 Reserved Bit[4:3] = 00 Non-volatile Status Register Bit[2] = 1 Page Programmable Bit[1:0] = 01 Support 4KB Erase SFDP revision 1.1 1 Parameter Header BAh PID(0 Table Address = 000080h 65 ZD25Q64B Read Serial Flash Discovery Parameter (SFDP (cont’d BYTE ADDRESS 81h 82h DATA 20h F1h DESCRIPTION COMMENT Opcode for 4K-Byte Erase Bit[7] = 1 Reserved Bit[6] = 1 Supports Single Input Quad Output Bit[5] = 1 Supports Quad Input Quad Output Bit[4] = 1 Supports Dual Input Dual Output Bit[3] = 0 Dual Transfer Rate not Supported Bit[2:1] = 00 3-Byte/24-Bit Addressing Bit[0] = 1 Supports Single Input Dual Output 83h FFh Reserved 84h FFh Flash Size in Bits 85h FFh Flash Size in Bits 64 Mega Bits = 86h FFh Flash Size in Bits 03FFFFFFh 87h 03h Flash Size in Bits 88h 44h 89h EBh 8Ah 08h 8Bh 6Bh 8Ch 08h 8Dh 3Bh 8Eh 80h 8Fh BBh 90h Bit[7:5] = 010 8 Mode Bits are needed Fast Read Bit[4:0] = 00100 16 Dummy Bits are needed Quad I/O Opcode for Quad Input Quad Output Fast Read Setting Bit[7:5] = 000 No Mode Bits are needed Fast Read Bit[4:0] = 01000 8 Dummy Bits are needed Quad Output Opcode for Single Input Quad Output Fast Read Setting Bit[7:5] = 000 No Mode Bits are needed Fast Read Bit[4:0] = 01000 8 Dummy Bits are needed Dual Output Opcode for Single Input Dual Output Fast Read Bit[7:5] = 100 8 Mode Bits are needed Bit[4:0] = 00000 No Dummy Bits are needed Opcode for Dual Input Dual Output Fast Read Bit[7:5]= 111 Reserved Bit[4]=1 Supports Quad input opcode & address and quad output data Fast Read FEh Bit[3:1]=111 Reserved Bit[0]=0 Not support Dual Input opcode & address Setting Fast Read Dual I/O Setting Fast Read in QPI mode 66 ZD25Q64B and dual output data Fast Read 91h FFh Reserved 92h FFh Reserved 93h FFh Reserved 94h FFh Reserved 95h FFh Reserved Fast Read Bit[7:5]=000 No Mode Bits are needed Bit[4:0]=00000 No Dummy Bits are needed 96h 00h 97h FFh Reserved. Opcode Not to be supported. 98h FFh Reserved 99h FFh Reserved Dual I/O in QPI Setting Fast Read Bit[7:5]=010 8 Mode Bits are needed Bit[4:0]=00100 8 Dummy Bits are needed(≤80Mhz 9Ah 44h 9Bh EBh Opcode for Quad Input Quad Output Fast Read in QPI mode 9Ch 0Ch Sector type 1 size= 4Kbytes 9Dh 20h Opcode for Erase of Sector Type 1 9Eh 0Fh Sector type 2 size= 32Kbytes 9Fh 52h Opcode for Erase of Sector Type 2 A0h 10h Sector type 3 size= 64Kbytes A1h D8h Opcode for Erase of Sector Type 3 A2h 00h Sector type 4 size not to exist A3h FFh Reserved. Opcode Not to be supported. ...(1 FFh Reserved E8h-EFh xxh Reserved F0h-FFh xxh Reserved Quad I/O in QPI Setting Erase for Sector Type 1/2 Erase for Sector Type 3/4 Notes: 1. Data stored in Byte Address 10h to 7Fh & A4 to 90h to FFh are reserved, the value is FFh. 2. 1 Dword = 4 Bytes. 3. PID(x = Parameter Identification Table(x 67 ZD25Q64B 10. 40 Enter Secured OTP (B1h The Enter Secured OTP instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is independent from main array, which may be used to store unique serial number for system identifier. After entering the Secured OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP data cannot be updated again once it is lock-down Please note that Write Status Register-1, Write Status Register-2 and Write Security Register instructions are not acceptable during the access of secure OTP region. Once security OTP is lock down, only commands related with read are valid. The Enter Secured OTP instruction sequence is shown in figure 40. 10.41 Exit Secured OTP (C1h The Exit Secured OTP instruction is for exiting the additional 4K-bit secured OTP mode. (Please refer to figure 41. 68 ZD25Q64B 10.42 Read Security Register (2Bh The Read Security Register can be read the value of Security Register bits at any time (even in program/erase/write status register-1 and write status register-2 condition and continuously. Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex-factory or not. When it is “0”, it indicates non-factory lock, “1” indicates factory-lock. Lock-down Secured OTP (LDSO bit. By writing Write Security Register instruction, the LDSO bit may be set to “1” for customer lock-down purpose. However, once the bit it set to “1” (Lock-down, the LDSO bit and the 4K-bit Secured OTP area cannot be updated any more. While it is in 4K-bit Secured OTP mode, array access is not allowed to write. Security Register Definition Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 x x x x x x reserved reserved reserved reserved reserved reserved Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit Volatile bit Bit1 LDSO (indicate if lockdown 0 = not lock-down 1 = lockdown(can not program/e rase OTP NonVolatile bit Bit0 Secured OTP indicator bit 0 = non factory lock 1 = factory lock NonVolatile bit 69 ZD25Q64B 10.43 Write Security Register (2Fh The Write Security Register instruction is for changing the values of Security Register bits. Unlike Write Status Register, the Write Enable instruction is not required before writing Write Security Register instruction. The Write Security Register instruction may change the value of bit1 (LDSO bit for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to “1”, the Secured OTP area cannot be updated any more. The /CS must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. 70 ZD25Q64B 11. 4K-bit Secured OTP It’s for unique identifier to provide 4K-bit one-time-program area for setting device unique serial number which may be set by factory or system customer. Please refer to table of “4K-bit secured OTP definition”. - Security register bit 0 indicates whether the chip is locked by factory or not. - To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with ENSO command and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing EXSO command - Customer may lock-down bit1 as “1”. Please refer to “table of security register definition” for security register bit definition and table of “4K-bit secured OTP definition” for address range definition. - Note. Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured OTP mode, array access is not allowed to write. 4K-bit secured OTP definition Address range Size 000000 ~ 00000F 128-bit 000010 ~ 0001FF 3968-bit Standard Factory Lock ESN (Electrical Serial Number Customer Lock Determined by customer N/A 71 ZD25Q64B 12. ELECTRICAL CHARACTERISTICS 12.1 Absolute Maximum Ratings (1 PARAMETERS SYMBOL Supply Voltage VCC Voltage Applied to Any Pin VIO Transient Voltage on any Pin VIOT CONDITIONS RANGE UNIT -0.6 to VCC+0.4 V Relative to Ground -0.6 to VCC +0.4 V