80-000286

Critical Link, LLC www.CriticalLink.com www.MityDSP.com MityDSP L138/1808/1810/6748 Debug Adapter 27-NOV-2012 FEATURES  MityDSP-L138 Family Debug Adapter  DSP/ARM and FPGA debug interfaces  Compatible Critical Link System on Modules o o o o o o o MityDSP-L138 MityDSP-L138F MityARM-1808 MityARM-1808F MityARM-1810 MityARM-1810F MityDSP-6748F Top Bottom DESCRIPTION The L138/1808/1810/6748 Debug Adapter board for the MityDSP-L138 Family of System on Modules from Critical Link allows for access to the DSP, ARM and FPGA (module dependent) debug interfaces. Each compatible System on Module includes a 31pin Hirose connector which this adapter board connects to. 1 Copyright © 2012, Critical Link LLC Specifications Subject to Change Critical Link, LLC www.CriticalLink.com www.MityDSP.com MityDSP L138/1808/1810/6748 Debug Adapter 27-NOV-2012 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS If Military/Aerospace specified cards are required, please contact the Critical Link Sales Office or unit Distributors for availability and specifications. Ambient Temperature Range Commercial Storage Temperature Range o Humidity o -40 C to 80 C 0oC to 70oC 0 to 95% Non-condensing DEBUG INTERFACE A Hirose 31 pin connector (DF9-31P-1V(32)) is provided on each compatible module to allow for the connection of this adapter board for both FPGA and OMAP-L138 processor debug. Below is the pin-out for the Hirose connector and the debug connectors on the adapter board. This adapter is available through your Critical Link representative; please see the ordering information, Table 4, below. Debug Interface Connector Description (J1) Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 I/O - GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Table 1 OMAP-L138 Hirose Connector Signal Pin I/O Signal 2 O OMAP EMU1 4 O OMAP EMU0 6 I OMAP TCK 8 O OMAP RTCK 10 O OMAP TDO 12 OMAP VCC / 3.3V 14 I OMAP TDI 16 I OMAP TRST 18 I OMAP TMS 20 GND 22 O NC / FPGA VREF / VCCAUX 24 I NC / FPGA TMS 26 I NC / FPGA TCK 28 O NC / FPGA TDO 30 I NC / FPGA TDI 2 Copyright © 2012, Critical Link LLC Specifications Subject to Change Critical Link, LLC www.CriticalLink.com www.MityDSP.com MityDSP L138/1808/1810/6748 Debug Adapter 27-NOV-2012 Processor JTAG Interface Description (J2) Connection for the processor, L138/1808/1810/6748, JTAG and emulator interfaces of a compatible System on Module from Critical Link. Pin 1 3 5 7 9 11 13 I/O I I O O I O Table 2 OMAP-L138 JTAG Connector Pad Signal Pin I/O Signal OMAP TMS 2 I OMAP TRST OMAP TDI 4 GND OMAP VCC / 3.3V 6 KEY OMAP TDO 8 GND OMAP RTCK 10 GND OMAP TCK 12 GND OMAP EMU0 14 O OMAP EMU1 FPGA JTAG Interface Description (J3) Connection for Xilinx FPGA JTAG interface of a compatible System on Module from Critical Link. Pin 1 3 5 7 9 11 13 I/O - GND GND GND GND GND GND GND Table 3 FPGA JTAG Connector Pad Signal Pin I/O Signal 2 O FPGA VREF / VCCAUX 4 I FPGA TMS 6 I FPGA TCK 8 O FPGA TDO 10 I FPGA TDI 12 No Connect 14 No Connect ORDERING INFORMATION The following table lists the standard debug adapter ordering information. For shipping status, availability, and lead time please contact your Critical Link representative. Table 4: Standard Debug Adapter Part Number Part Number Description 80-000286 L138/1808/1810/6748 JTAG Debug Adapter 3 Copyright © 2012, Critical Link LLC Specifications Subject to Change Critical Link, LLC www.CriticalLink.com www.MityDSP.com MityDSP L138/1808/1810/6748 Debug Adapter 27-NOV-2012 MECHANICAL INTERFACE The mechanical outline of the Debug Adapter is illustrated in Figure 1, as shown below. Figure 1 L138/1808/1810/6748 Debug Adapter Mechanical Outline REVISION HISTORY Date 27-NOV-2012 Change Description Initial revision 4 Copyright © 2012, Critical Link LLC Specifications Subject to Change