2Pai Semi
Enhanced ESD, 3.0 kV rms/5.0 kV rms
150Kbps Triple-Channel Digital Isolators
π130U/π131U
Data Sheet
FEATURES
Ultra-low power consumption (150Kbps): 0.62mA/Channel
High data rate: 150kbps
High common-mode transient immunity: 150 kV/µs typical
High robustness to radiated and conducted noise
Isolation voltages:
π13xx3x: AC 3000Vrms
π13xx6x: AC 5000Vrms
High ESD rating:
ESDA/JEDEC JS-001-2017
Human body model (HBM) ±8kV, all pins
Safety and regulatory approvals (Pending)：
UL certificate number: E494497
3000Vrms/5000Vrms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate number: 40047929
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 707V peak/1200V peak
CQC certification per GB4943.1-2011
3 V to 5.5 V level translation
Wide temperature range: -40°C to 125°C
16-lead, RoHS-compliant, SOIC_N, SOIC_W and SSOP package
APPLICATIONS
General-purpose multichannel isolation
Industrial field bus isolation
Isolation Industrial automation systems
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
GENERAL DESCRIPTION
The π1xxxxx is a 2PaiSemi digital isolators product family that
includes over hundreds of digital isolator products. By using
maturated standard semiconductor CMOS technology and 2PaiSEMI
iDivider technology, these isolation components provide
outstanding performance characteristics and reliability superior to
alternatives such as optocoupler devices and other integrated
isolators.
Intelligent voltage divider technology (iDivider technology) is a new
generation digital isolator technology invented by 2PaiSEMI. It uses
the principle of capacitor voltage divider to transmit voltage signal
directly cross the isolator capacitor without signal modulation and
demodulation.
The π1xxxxx isolator data channels are independent and are
available in a variety of configurations with a withstand voltage
rating of 1.5 kV rms to 5.0 kV rms and the data rate from DC up to
600Mbps (see the Ordering Guide). The devices operate with the
supply voltage on either side ranging from 3.0 V to 5.5 V, providing
compatibility with lower voltage systems as well as enabling voltage
translation functionality across the isolation barrier. The fail-safe
state is available in which the outputs transition to a preset state
when the input power supply is not applied.
FUNCTIONAL BLOCK DIAGRAMS
π130X3X
π130X6X
VDD1
1
16
VDD2
GND1
2
15
GND2
VOA
VIA
3
14
VOA
VOB
VIB
4
13
VOB
12
VOC
VIC
5
12
VOC
6
11
NC
NC 6
11
NC
NC 7
10
EN2
9
GND2
VDD1
1
GND1
2
15
GND2
VIA
3
14
VIB
4
13
VIC
5
NC
16
VDD2
NC
7
10
NC
GND1
8
9
GND2
π131X3X
GND1
8
VDD1
1
16
VDD 2
GND1
2
15
GND 2
π131X6X
VDD1
1
16
VDD2
GND1
2
15
GND2
VIA
3
14
VOA
VIA
3
14
VOA
VIB
4
13
VOB
VIB
4
13
VOB
VOC
5
12
V IC
VOC
5
12
V IC
NC
6
11
NC
NC
6
11
NC
NC
7
10
NC
EN1 7
10
EN2
GND
8
9
8
9
GND 2
1
GND2
GND1
Figure 1.π130xxx/π131xxx functional Block Diagram
VDD1
VDD2
CIN
COUT
0.1uF
0.1uF
1
2
3
4
5
6
7
8
VIN_A
VIN_B
VIN_C
GND1
VDD1
GND1
VIA
VIB
VIC
NC
NC
GND1
VDD2
GND2
VOA
VOB
VOC
NC
NC
GND2
16
15
14
13
12
11
10
9
VOUT_A
VOUT_B
VOUT_C
GND2
Figure 2.π130x3x Typical Application Circuit
Rev.1.6
Information furnished by 2Pai semi is believed to be accurate and reliable. However, no
responsibility is assumed by 2Pai semi for its use, nor for any infringements of patents or
other rights of third parties that may result from its use. Specifications subject to change
without notice. No license is granted by implication or otherwise under any patent or patent
rights of 2Pai semi.
Trademarks and registered trademarks are the property of their respective owners.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China
021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
π130U/π131U
Data Sheet
PIN CONFIGURATIONS AND FUNCTIONS
Table 1.π130Uxx Pin Function Descriptions
Pin No.
Name
Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
3
VIA
Logic Input A.
4
VIB
Logic Input B.
5
VIC
Logic Input C.
6
NC
No connect.
7
NC
No connect.
8
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
NC/EN2
DD1
DD2
1
11
NC
No connect for π130U3X.
Output enable for π130U6X. Output pins on side 2 are
enabled when EN2 is high or open and in high-impedance
state when EN2 is low.
No connect.
12
VOC
Logic Output C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
15
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
16
VDD2
Supply Voltage for Isolator Side 2.
2
IA
OA
IB
OB
IC
OC
/EN2
1
2
Figure 3.π130Uxx Pin Configuration
Table 2.π131Uxx Pin Function Descriptions
Pin No. Name Description
1
VDD1
Supply Voltage for Isolator Side 1.
2
GND1
Ground 1. This pin is the ground reference for Isolator Side 1.
3
VIA
Logic Input A.
IA
OA
4
VIB
Logic Input B.
IB
OB
5
VOC
Logic Output C.
6
NC
No connect.
7
NC
DD1
2
OC
8
GND1
No connect for π131U3X.
Output enable for π131U6X. Output pins on side 1 are enabled
when EN1 is high or open and in high-impedance state when
EN1 is low.
Ground 1. This pin is the ground reference for Isolator Side 1.
9
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
10
NC
11
NC
No connect for π131U3X.
Output enable for π131U6X. Output pins on side 2 are enabled
when EN2 is high or open and in high-impedance state when
EN2 is low.
No connect.
12
VIC
Logic Input C.
13
VOB
Logic Output B.
14
VOA
Logic Output A.
15
GND2
Ground 2. This pin is the ground reference for Isolator Side 2.
16
VDD2
Supply Voltage for Isolator Side 2.
Rev. 1.6 | Page 2 of 17
DD2
1
IC
/EN2
/EN1
1
2
Figure 4.π131Uxx Pin Configuration
π130U/π131U
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.Absolute Maximum Ratings4
TA = 25°C, unless otherwise noted.
Parameter
Rating
Supply Voltages (VDD1-GND1, VDD2-GND2)
−0.5 V to +7.0 V
Input Voltages (VIA, VIB)1
−0.5 V to VDDx + 0.5 V
Output Voltages (VOA, VOB)1
−0.5 V to VDDx + 0.5 V
Average Output Current per
Pin2
Side 1 Output Current (IO1)
−10 mA to +10 mA
Average Output Current per
Pin2
Side 2 Output Current (IO2)
−10 mA to +10 mA
Common-Mode Transients Immunity 3
−200 kV/µs to +200 kV/µs
Storage Temperature (TST) Range
−65°C to +150°C
Ambient Operating Temperature (TA) Range
−40°C to +125°C
Notes:
1 VDDx is the side voltage power supply VDD, where x = 1 or 2.
2 See Figure 5 for the maximum rated current values for various temperatures.
3 See Figure 15 for Common-mode transient immunity (CMTI) measurement.
4 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating
conditions for extended periods may affect product reliability.
RECOMMENDED OPERATING CONDITIONS
Table 4.Recommended Operating Conditions
Parameter
Symbol
Supply Voltage
High Level Input Signal Voltage
Low Level Input Signal Voltage
High Level Output Current
Low Level Output Current
Maximum Data Rate
Junction Temperature
Ambient Operating Temperature
VDDx 1
VIH
VIL
IOH
IOL
TJ
TA
Min
Typ
3
0.7*VDDx1
0
-6
Max
Unit
5.5
VDDx1
0.3*VDDx1
V
V
V
mA
mA
Kbps
°C
°C
6
150
150
125
0
-40
-40
Notes:
1V
DDx is the side voltage power supply VDD, where x = 1 or 2.
Truth Tables
Table 5.π130U3x/π131U3x Truth Table
VIx Input1
VDDI State1
VDDO State1
Low
High
Open
Don’t Care4
Don’t Care4
Powered2
Powered2
Powered2
Unpowered3
Powered2
Powered2
Powered2
Powered2
Powered2
Unpowered3
Default Low
Default High
VOx Output1
VOx Output1
Low
High
Low
Low
High Impedance
Low
High
High
High
High Impedance
Test Conditions /Comments
Normal operation
Normal operation
Default output
Default output5
Notes:
1 VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel.
2 Powered means VDDx≥ 2.9 V
3 Unpowered means VDDx < 2.3V
4 Input signal (VIx) must be in a low state to avoid powering the given VDDI1 through its ESD protection circuitry.
5 If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input
status logic signal after around 3us.
Rev. 1.6 | Page 3 of 17
π130U/π131U
Data Sheet
Table 6.π130U6x/π131U6x Truth Table
VIx Input1
EN1/2 State
VDDI State1
VDDO State1
Low
High
Don’t Care4
Open
Don’t Care4
Don’t Care4
Don’t Care4
High or NC
High or NC
L
High or NC
High or NC
L
Don’t Care4
Powered2
Powered2
Powered2
Powered2
Unpowered3
Unpowered3
Powered2
Powered2
Powered2
Powered2
Powered2
Powered2
Powered2
Unpowered3
Default Low
VOx Output1
Low
High
High Impedance
Low
Low
High Impedance
High Impedance
Default High
VOx Output1
Low
High
High Impedance
High
High
High Impedance
High Impedance
Test Conditions /Comments
Normal operation
Normal operation
Disabled
Default output5
Default output5
Notes:
1VIx/VOx are the input/output signals of a given channel (A or B). VDDI/VDDO are the supply voltages on the input/output signal sides of this given channel.
2Powered means VDDx≥ 2.9 V
3Unpowered means V
DDx < 2.3V
4Input signal (V ) must be in a low state to avoid powering the given V
1
Ix
DDI through its ESD protection circuitry.
5If the VDDI goes into unpowered status, the channel outputs the default logic signal after around 1us. If the VDDI goes into powered status, the channel outputs the input
status logic signal after around 3us.
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Table 7.Switching Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
Unit
Minimum Pulse Width
Maximum Data Rate
Propagation Delay Time1,4
Pulse Width Distortion4
Part to Part Propagation Delay
Skew4
Channel to Channel Propagation
Delay Skew4
Output Signal Rise/Fall Time4
Common-Mode Transient
Immunity3
ESD（HBM - Human body
model）
PW
6.5
us
Kbps
3.0
4.5
us
3.2
4.8
us
0
0.02
0.2
us
0
0.02
0.2
us
0.3
us
0.3
us
0
0.2
us
0
0.2
us
150
tpHL, tpLH
PWD
tPSK
tCSK
tr/tf
CMTI
ESD
100
1.5
ns
150
kV/µs
±8
kV
Notes:
1 tpLH = low-to-high propagation delay time, tpHL = high-to-low propagation delay time. See Figure 13.
2 VDDx is the side voltage power supply VDD, where x = 1 or 2.
3 See Figure 15 for Common-mode transient immunity (CMTI) measurement.
4 Output Signal Terminated 50Ω
Table 8.DC Specifications
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, unless otherwise noted.
Rev. 1.6 | Page 4 of 17
Test Conditions/Comments
Within pulse width distortion (PWD) limit
Within PWD limit
The different time between 50% input signal to
50% output signal 50% @ 5VDC supply
@ 3.3VDC supply
The max different time between tpHL and tpLH@
5VDC supply. And The value is | tpHL - tpLH |
@ 3.3VDC supply
The max different propagation delay time
between any two devices at the same
temperature, load and voltage @ 5VDC supply
@ 3.3VDC supply
The max amount propagation delay time
differs between any two output channels in
the single device @ 5VDC supply.
@ 3.3VDC supply
10% to 90% signal terminated 50Ω，See Figure
12.
VIN = VDDx2 or 0V, VCM = 1000 V
All pins
π130U/π131U
Data Sheet
Symbol
Rising Input Signal Voltage Threshold
Falling Input Signal Voltage Threshold
High Level Output Voltage
Low Level Output Voltage
VIT+
VITVOH 1
Min
Typ
0.3* VDDX1
VDDx − 0.1
VDDx − 0.2
VOL
Input Current per Signal Channel
VDDx1 Undervoltage Rising Threshold
VDDx1 Undervoltage Falling Threshold
VDDx1 Hysteresis
IIN
VDDxUV+
VDDxUV−
VDDxUVH
Max
1
−10
2.5
2.4
0.6*VDDx
0.4* VDDX1
VDDx
VDDx − 0.1
0
0.1
0.5
2.8
2.65
0.15
0.7*VDDx
Unit
1
Test Conditions/Comments
V
V
V
V
V
V
µA
V
V
V
0.1
0.2
10
2.95
2.75
−20 µA output current
−2 mA output current
20 µA output current
2 mA output current
0 V ≤ Signal voltage ≤ VDDX1
Notes:
1V
DDx is the side voltage power supply VDD, where x = 1 or 2.
Table 9.Quiescent Supply Current
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
Parameter
Symbol
Min
Typ
Max
π130Uxx Quiescent Supply Current
@ 5VDC Supply
π130Uxx Quiescent Supply Current
@ 3.3VDC Supply
π131Uxx Quiescent Supply Current
@ 5VDC Supply
π131Uxx Quiescent Supply Current
@ 3.3VDC Supply
Unit
Test Conditions
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.28
1.12
0.11
1.21
0.35
1.40
0.14
1.51
0.45
1.83
0.18
1.96
mA
mA
mA
mA
0V Input signal
0V Input signal
5V Input signal
5V Input signal
IDD1 (Q)
0.21
0.27
0.35
mA
0V Input signal
IDD2 (Q)
1.10
1.38
1.79
mA
0V Input signal
IDD1 (Q)
0.10
0.13
0.17
mA
3.3V Input signal
IDD2 (Q)
1.19
1.49
1.94
mA
3.3V Input signal
IDD1 (Q)
IDD2 (Q)
IDD1 (Q)
IDD2 (Q)
0.56
0.85
0.49
0.85
0.70
1.06
0.61
1.07
0.90
1.38
0.79
1.39
mA
mA
mA
mA
0V Input signal
0V Input signal
5V Input signal
5V Input signal
IDD1 (Q)
0.51
0.63
0.82
mA
0V Input signal
IDD2 (Q)
0.81
1.01
1.32
mA
0V Input signal
IDD1 (Q)
0.48
0.61
0.79
mA
3.3V Input signal
IDD2 (Q)
0.84
1.05
1.37
mA
3.3V Input signal
Table 10.Total Supply Current vs. Data Throughput (CL = 0 pF)
VDD1 - VGND1 = VDD2 - VGND2 = 3.3VDC±10% or 5VDC±10%, TA=25°C, CL = 0 pF, unless otherwise noted.
2 Kbps
50Kbps
Parameter
Symbol
Min
Typ
Max
Min
Typ
Max
π130Uxx Supply Current@ 5VDC
@ 3.3VDC
π131Uxx Supply Current@ 5VDC
@ 3.3VDC
150Kbps
Min
Typ
Max
Unit
IDD1
0.24
0.36
0.24
0.36
0.25
0.38
mA
IDD2
1.45
2.18
1.47
2.21
1.49
2.24
mA
IDD1
0.18
0.27
0.18
0.27
0.18
0.27
mA
IDD2
1.41
2.12
1.42
2.13
1.43
2.15
mA
IDD1
0.60
0.90
0.61
0.92
0.62
0.93
mA
IDD2
1.05
1.58
1.07
1.61
1.09
1.64
mA
IDD1
0.55
0.83
0.56
0.84
0.57
0.86
mA
IDD2
1.03
1.55
1.05
1.58
1.07
1.61
mA
Rev. 1.6 | Page 5 of 17
π130U/π131U
Data Sheet
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 11.Insulation Specifications
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Internal Gap (Internal
Clearance)
Tracking Resistance (Comparative
Tracking Index)
Symbol
Value
Unit
Test Conditions/Comments
π13xU3x
π13xU6x
3000
5000
L (CLR)
4
8
mm min
L (CRP)
4
8
mm min
11
21
µm min
Insulation distance through insulation
>600
>600
V
DIN EN 60112 (VDE 0303-11):2010-05
I
I
CTI
Material Group
V rms
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
IEC 60112:2003 + A1:2009
PACKAGE CHARACTERISTICS
Table 12.Package Characteristics
Parameter
Resistance (Input to Output)1
Capacitance (Input to
Output)1
Symbol
Typical Value
Unit
π13xU3x
π13xU6x
RI-O
10 11
10 11
Ω
Test Conditions/Comments
CI-O
1.5
1.5
pF
@1MHz
Input Capacitance2
CI
3
3
pF
@1MHz
IC Junction to Ambient Thermal
Resistance
θJA
100
45
°C/W
Thermocouple located at center of
package underside
Notes:
1The device is considered a 2-terminal device; SOIC-16 Pin 1 - Pin 8(WSOIC-16 Pin 1-Pin8 and SSOP16 Pin 1-Pin8) are shorted together as the one terminal, and SOIC-16 Pin
9- Pin 16(WSOIC-16 Pin 9-Pin16 and SSOP16 Pin 9-Pin16) are shorted together as the other terminal.
2Testing from the input signal pin to ground.
REGULATORY INFORMATION
See Table 13 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross
isolation waveforms and insulation levels.
Table 13.Regulatory
Regulatory
π13xU3x
π13xU6x
UL
Recognized under UL 1577
Component Recognition Program1
Single Protection, 3000 V rms Isolation Voltage
File (E494497)
Recognized under UL 1577
Component Recognition Program1
Single Protection, 5000 V rms Isolation Voltage
File (pending)
CSA
Approved under CSA Component Acceptance Notice 5A
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 500 V rms (707 V peak)
Reinforced insulation at 250 V rms
(353 V peak)
File (pending)
Approved under CSA Component Acceptance Notice 5A
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Basic insulation at 845 V rms (1200 V peak)
Reinforced insulation at 422 V rms
(600 V peak)
File (pending)
VDE
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation, VIORM = 707 V peak, VIOSM = 4615 V peak
File (40047929)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-122
Basic insulation, VIORM = 1200 V peak, VIOSM = 7000V peak
File (pending)
CQC
Certified under
CQC11-471543-2012
Certified under
CQC11-471543-2012
Rev. 1.6 | Page 6 of 17
π130U/π131U
Data Sheet
Regulatory
π13xU3x
π13xU6x
GB4943.1-2011
Basic insulation at 500 V rms (707 V peak) working voltage
Reinforced insulation at
250 V rms (353 V peak)
File (pending)
GB4943.1-2011
Basic insulation at 845 V rms (1200 V peak) working voltage
Reinforced insulation at
422 V rms (600 V peak)
File (pending)
Notes:
1 In accordance with UL 1577, each π130U3X/π131U3X is proof tested by applying an insulation test voltage ≥ 3600 V rms for 1 sec; each π130U6X/π131U6X is proof tested by
applying an isulation test voltage ≥ 7200 V rms for 1 sec
2 In accordance with DIN V VDE V 0884-10, each π130U3X/π131U3X is proof tested by applying an insulation test voltage ≥ 1326 V peak for 1 sec (partial discharge
detection limit = 5 pC); each π130U6X/π131U6X is proof tested by ≥ 2250 V peak for 1 sec. The * marking branded on the component designates DIN V VDE V 0884-10
approval.
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the
maintenance of the safety data. The * marking on packages denotes DIN V VDE V 0884-10 approval.
Table 14.VDE Insulation Characteristics
Description
Test Conditions/Comments
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method B1
VIORM × 1.875 = Vpd (m), 100% production
test, tini = tm = 1 sec, partial discharge <
5 pC
Symbol
Characteristic
Unit
π13xU3x
π13xU6x
VIORM
I to IV
I to III
I to III
40/105/21
2
707
I to IV
I to III
I to III
40/105/21
2
1200
V peak
Vpd (m)
1326
2250
V peak
Vpd (m)
1061
1800
V peak
849
1440
V peak
VIOTM
4200
7071
V peak
VIOSM
4615
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Surge Isolation Voltage Basic
Surge Isolation Voltage Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10
sec, partial discharge < 5 pC
Basic insulation, 1.2 µs rise time, 50 µs,
50% fall time
Reinforced insulation, 1.2 µs rise time,
50 µs, 50% fall time
Maximum value allowed in the event of
a failure (see Figure 5)
VIOSM
TS
PS
RS
VIO = 800 V
Rev. 1.6 | Page 7 of 17
V peak
V peak
150
1.67
>109
150
2.78
>109
°C
W
Ω
π130U/π131U
Data Sheet
3
3.2
2.9
Propagation Delay Time(uS)
Power Supply Undervoltage Threshold
Figure 5.Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per VDE (left: π13xU3x; right: π13xU6x)
2.8
2.7
2.6
2.5
2.4
VDDxUV+(V）
VDDxUV−(V）
2.3
3
2.8
2.6
tpLH(uS)@3.3V
2.4
tpHL(uS)@5V
tpLH(uS)@5V
2.2
2.2
0
50
100
0
150
50
100
150
Free-Air Temperature ( °C)
Free-Air Temperature ( °C)
Figure 6.UVLO vs. Free-Air Temperature
Figure 7.Propagation Delay Time vs. Free-Air Temperature
1.2
1.4
1.0
0.8
0.6
0.4
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 3.3V Input
IDD2@ 3.3V Input
0.2
0.0
0
50
100
Free-Air Temperature ( °C)
150
Figure 8.π130Uxx Quiescent Supply Current with 3.3V Supply vs. Free-Air
Temperature
π130Uxx Quiescent Supply Current (mA)
π130Uxx Quiescent Supply Current (mA)
tpHL(uS)@3.3V
1.2
1.0
0.8
0.6
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
0.4
0.2
0.0
0
50
100
Free-Air Temperature ( °C)
150
Figure 9.π130Uxx Quiescent Supply Current with 5V Supply vs. Free-Air
Temperature
Rev. 1.6 | Page 8 of 17
π130U/π131U
0.9
1.0
0.8
0.9
π131Uxx Quiescent Supply Current (mA)
π131Uxx Quiescent Supply Current (mA)
Data Sheet
0.7
0.6
0.5
0.4
0.3
IDD1@ 0V Input
0.2
IDD1@ 3.3V Input
IDD2@ 0V Input
IDD2@ 3.3V Input
0.1
0.0
0
50
100
Free-Air Temperature ( °C)
150
Figure 10.π131Uxx Quiescent Supply Current with 3.3V Supply vs. Free-Air
Temperature
Figure 12.Transition time waveform measurement
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
IDD1@ 0V Input
IDD2@ 0V Input
IDD1@ 5V Input
IDD2@ 5V Input
0.0
0
50
100
Free-Air Temperature ( °C)
150
Figure 11.π131Uxx Quiescent Supply Current with 5V Supply vs. Free-Air
Temperature
Figure 13. Propagation delay time waveform measurement
Rev. 1.6 | Page 9 of 17
π130U/π131U
Data Sheet
APPLICATIONS INFORMATION
OVERVIEW
The π1xxxxx are 2PaiSemi digital isolators product family based on
2PaiSEMI unique iDivider technology. Intelligent voltage Divider
technology (iDivider technology) is a new generation digital isolator
technology invented by 2PaiSEMI. It uses the principle of capacitor
voltage divider to transmit signal directly cross the isolator capacitor
without signal modulation and demodulation. Compare to the
traditional Opto-couple technology, icoupler technology, OOK
technology, iDivider is a more essential and concise isolation signal
transmit technology which leads to greatly simplification on circuit
design and therefore significantly improves device performance,
such as lower power consumption, faster speed, enhanced antiinterference ability, lower noise.
By using maturated standard semiconductor CMOS technology and
the innovative iDivider design, these isolation components provide
outstanding performance characteristics and reliability superior to
alternatives such as optocoupler devices and other integrated
isolators. The π1xxxxx isolator data channels are independent and
are available in a variety of configurations with a withstand voltage
rating of 1.5 kV rms to 5.0 kV rms and the data rate from DC up to
600Mbps (see the Ordering Guide).
The π130Uxx/π131Uxx are the outstanding 150Kbps Triple-channel
digital isolators with the enhanced ESD capability. the devices
transmit data across an isolation barrier by layers of silicon dioxide
isolation.
The devices operate with the supply voltage on either side ranging
from 3.0 V to 5.5 V, offering voltage translation of 3.3 V, and 5 V logic.
The π130Uxx/π131Uxx have very low propagation delay and high
speed. The input/output design techniques allow logic and supply
voltages over a wide range from 3.0 V to 5.5 V, offering voltage
translation of 3.3 V and 5 V logic. The architecture is designed for
high common-mode transient immunity and high immunity to
electrical noise and magnetic interference.
See the Ordering Guide for the model numbers that have the failsafe output state of low or high.
Avoid reducing the isolation capability, Keep the space underneath
the isolator device free from metal such as planes, pads, traces and
vias.
To minimize the impedance of the signal return loop, keep the solid
ground plane directly underneath the high-speed signal path, the
closer the better. The return path will couple between the nearest
ground plane to the signal path. Keep suitable trace width for
controlled impedance transmission lines interconnect.
To reduce the rise time degradation, keep the length of input/output
signal traces as short as possible, and route low inductance loop for
the signal path and It’s return path.
VDD1
VDD2
GND1
GND2
VIA/VOA
VIB
VIC/VOC
VOA/VIA
VOB
VOC/VIC
NC
NC
GND1
NC
NC
GND2
Figure 14.Recommended Printed Circuit Board Layout
CMTI MEASUREMENT
To measure the Common-Mode Transient Immunity (CMTI) of
π1xxxxx isolator under specified common-mode pulse magnitude
(VCM) and specified slew rate of the common-mode pulse (dVCM/dt)
and other specified test or ambient conditions, The common-mode
pulse generator (G1) will be capable of providing fast rising and
falling pulses of specified magnitude and duration of the commonmode pulse (VCM) and the maximum common-mode slew rates
(dVCM/dt) can be applied to π1xxxxx isolator coupler under
measurement. The common-mode pulse is applied between one
side ground GND1 and the other side ground GND2 of π1xxxxx
isolator and shall be capable of providing positive transients as well
as negative transients.
PCB LAYOUT
The low-ESR ceramic bypass capacitors must be connected between
VDD1 and GND1 and between VDD2 and GND2. The bypass capacitors
are placed on the PCB as close to the isolator device as possible. The
recommended bypass capacitor value is between 0.1 μF and 10 μF.
The user may also include resistors (50–300 Ω) in series with the
inputs and outputs if the system is excessively noisy, or in order to
enhance the anti ESD ability of the system.
Figure 15.Common-mode transient immunity (CMTI) measurement
Rev.1.6 | Page 10 of 17
π130U/π131U
Data Sheet
OUTLINE DIMENSIONS
Figure 16. 16-Lead Narrow Body SOIC [NB SOIC-16] Outline Package
Figure 17.16-Lead Wide Body Outline Package [16-Lead SOIC_W]
Rev.1.6 | Page 11 of 17
π130U/π131U
Data Sheet
Figure 18.16-Lead SSOP Outline Package [SSOP16]
Land Patterns
16-Lead Narrow Body SOIC [NB SOIC-16]
The figure below illustrates the recommended land pattern details for the π1xxxxx in a 16-pin narrow-body SOIC. The table below lists the
values for the dimensions shown in the illustration.
Figure 19.16-Lead Narrow Body SOIC [NB SOIC-16] Land Pattern
Table 15.16-Lead Narrow Body SOIC [NB SOIC-16] Land Pattern Dimensions
Dimension
Feature
C1
Pad column spacing
E
Pad row pitch
X1
Pad width
Y1
Pad length
Parameter
5.40
1.27
0.60
1.55
Note：
1.This land pattern design is based on IPC -7351
2.All feature sizes shown are at maximum material condition and a card fabrication tolerance of 0.05 mm is assumed.
Rev.1.6 | Page 12 of 17
Unit
mm
mm
mm
mm
π130U/π131U
Data Sheet
16-Lead SOIC_W
The figure below illustrates the recommended land pattern details for the π1xxxxx in a 16-pin wide-body SOIC package. The table lists the
values for the dimensions shown in the illustration.
Figure 20.16-Lead Wide Body SOIC [WB SOIC-16] Land Pattern
Table 16. 16-Lead Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
C1
Pad column spacing
E
Pad row pitch
X1
Pad width
Y1
Pad length
Parameter
9.40
1.27
0.60
1.90
Unit
mm
mm
mm
mm
Note：
1.This land pattern design is based on IPC -7351
2.All feature sizes shown are at maximum material condition and a card fabrication tolerance of 0.05 mm is assumed.
16-Lead SSOP
The figure below illustrates the recommended land pattern details for the π1xxxxx in a 16-Lead SSOP package. The table lists the values for the
dimensions shown in the illustration.
Figure 21. 16-Lead SSOP Land Pattern
Table 17. 16-Lead SSOP Land Pattern Dimensions
Dimension
Feature
C1
Pad column spacing
E
Pad row pitch
X1
Pad width
Y1
Pad length
Parameter
5.40
0.635
0.40
1.55
Note：
1.This land pattern design is based on IPC -7351
2.All feature sizes shown are at maximum material condition and a card fabrication tolerance of 0.05 mm is assumed.
Rev.1.6 | Page 13 of 17
Unit
mm
mm
mm
mm
π130U/π131U
Data Sheet
Top Marking
Line 1
Line 2
Line 3
πXXXXXX=Product name
YY = Work Year
WW = Work Week
ZZ=Manufacturing code from assembly house
XXXX, no special meaning
REEL INFORMATION
16-Lead Narrow Body SOIC [NB SOIC-16]
Note：The Pin 1 of the chip is in the quadrant Q1
16-Lead Wide Body SOIC [WB SOIC-16]
Rev.1.6 | Page 14 of 17
π130U/π131U
Data Sheet
Note：The Pin 1of the chip is in the quadrant Q1
16-Lead SSOP
ORDERING GUIDE
No. of
Withstand
Fail-Safe
No. of Inputs,
Package
Inputs, VDD1
Voltage Rating
Output
MSL Peak Temp 2
VDD2 Side
Description
Side
(kV rms)
State
π130U31
−40 to 125°C
3
0
3
High
NB SOIC-16
Level-3-260C-168 HR
π130U30
−40 to 125°C
3
0
3
Low
NB SOIC-16
Level-3-260C-168 HR
π131U31
−40 to 125°C
2
1
3
High
NB SOIC-16
Level-3-260C-168 HR
π131U30
−40 to 125°C
2
1
3
Low
NB SOIC-16
Level-3-260C-168 HR
π130U61
−40 to 125°C
3
0
5
High
WB SOIC-16
Level-3-260C-168 HR
π130U60
−40 to 125°C
3
0
5
Low
WB SOIC-16
Level-3-260C-168 HR
π131U61
−40 to 125°C
2
1
5
High
WB SOIC-16
Level-3-260C-168 HR
π131U60
−40 to 125°C
2
1
5
Low
WB SOIC-16
Level-3-260C-168 HR
π130U31S
−40 to 125°C
3
0
3
High
16-Lead SSOP
Level-3-260C-168 HR
π130U30S
−40 to 125°C
3
0
3
Low
16-Lead SSOP
Level-3-260C-168 HR
π131U31S
−40 to 125°C
2
1
3
High
16-Lead SSOP
Level-3-260C-168 HR
π131U30S
−40 to 125°C
2
1
3
Low
16-Lead SSOP
Level-3-260C-168 HR
1.
Pai1xxxxx is equals to π1xxxxx in the customer BOM.
2. MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Model
Name 1
Temperature
Range
Rev.1.6 | Page 15 of 17
Quantity
per reel
2500
2500
2500
2500
1500
1500
1500
1500
4000
4000
4000
4000
π130U/π131U
Data Sheet
PART NUMBER NAMED RULE
π(1)(2)(0)(A)(3)(0)(S)
SeriesNumber:
1,2,3...
Total Channel Am ount:
N=N Channels N=2,3,4,5,6...
Reverse Channel Amount:
N=N Channels N=0,1,2,3...
Data Rate:A=600Mbps
E=200Mbps
M=10Mbps
U=150Kbps
Isolation Voltag es:
N=3 3KVrms AC
N=4 4KVrms AC
N=6 5 or 6KVrms AC
Fail-Safe Output Stat e:
0=Logic Low
1=Logic High
Optional:
S=SSOP Package
Q=AEC-Q100 Qualified
Notes:
Pai1xxxxx is equals to π1xxxxx in the customer BOM
IMPORTANT NOTICE AND DISCLAIMER
2Pai semi intends to provide customers with the latest, accurate, and in-depth documentation. However, no responsibility is assumed by 2Pai
semi for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Characterization data,
available modules, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for
illustrative purposes only. 2Pai semi reserves the right to make changes without further notice and limitation to product information,
specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. 2Pai semi
shall have no liability for the consequences of use of the information supplied herein.
Trademarks and registered trademarks are the property of their respective owners. This document does not imply, or express copyright
licenses granted hereunder to design or fabricate any integrated circuits.
Room 308-309, No.22, Boxia Road, Pudong New District, Shanghai, 201203, China 021-50850681
2Pai Semiconductor Co., Limited. All rights reserved.
http://www.rpsemi.com/
Rev.1.6 | Page 16 of 17
π130U/π131U
Data Sheet
REVISION HISTORY
Revision
Updated
Date
Page
1
Victory
2018/
09/20
All
2
Victory
2018/
11/28
P1,P11
3
Devin
2019/
09/08
P1,P7,P11,P13,P
14,P15
Page1,11,14
Page 5
Page 6
Page7
4
Mr. Han
2020/
03/20
Page8
Page 11
Page 12
Page 14
Page 15
Page 16
Change Record
Initial version
Changed CIN，COUT in Figure2 from 0.1uF to 1uF.
Changed the recommended bypass capacitor value from between 0.1 μF and 1 μF to
between 0.1 μF and 10 μF.
P1: Changed the address from ‘Room 19307, Building 8, No.498, GuoShouJing Road’ to
‘Room 308-309, No.22, Boxia Road’; Changed ‘(W)SOIC package’ to ‘SOIC_N, SOIC_W
and SSOP package’; Add iDivider technology description in General Description.
Changed CIN，COUT in Figure2 from 1uF to 0.1uF.
P7: Add ‘and SSOP16 Pin 1-Pin8’ and ‘and SSOP16 Pin 9-Pin16’ in note 1.
P11: Add iDivider technology description in overview.
P13: Add Figure19. 16-Lead SSOP Outline Package drawing
P14: Add 16-Lead SSOP Reel drawing; Updated 16-Lead SOIC_W reel drawing.
P15: Add character ‘S’ and ‘Q’ in part number named rule; Changed the SOIC_W
quantity from ‘1000 per reel’ to ‘1500 per reel’; Add ‘π130U31S、π130U30S、
π131U31S、π131U30S’ in ordering guide
Changed the Isolation voltages ofπ12xx6x from 6kV to 5kV.
Changed minimum” VDDx Undervoltage Rising Threshold” from 2.45V to 2.5V
Changed typical” VDDx Undervoltage Rising Threshold” from 2.65V to 2.8V
Changed maximum” VDDx Undervoltage Rising Threshold” from 2.9V to 2.95V
Changed minimum” VDDx Undervoltage Falling Threshold” from 2.3V to 2.4V
Changed typical” VDDx Undervoltage Falling Threshold” from 2.5V to 2.65V
Change CTI from “>400” to “>600”, changed “Material Group” from “II” to” I”
Changed” Capacitance (Input to Output)” from 0.6pF to 1.5pF
Old version: Single Protection,6000V rms Isolation Voltage
New version: Single Protection, 5000V rms Isolation Voltage
Old version: To enhance the robustness of a design, the user may also include resistors
(50–300 Ω) in series with the inputs and outputs if the system is excessively noisy.
New version: The user may also include resistors (50–300 Ω) in series with the inputs
and outputs if the system is excessively noisy, or in order to enhance the anti ESD
ability of the system.
Added “Land Patterns”
Added “Top Marking”
Updated “REEL INFORMATION”
Added “MSL peak temp” in tab ORDERING GUIDE
Added “IMPORTANT NOTICE AND DISCLAIMER”
Rev.1.6 | Page 17 of 17
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