Critical Link, LLC
www.CriticalLink.com
MitySOM-5CSX Development Kit
6 August 2014
FEATURES
MitySOM-5CSX Development Board
MitySOM-5CSX SoM Module
Additional Hardware Included:
UART to USB Cable
Ethernet Cable
AC to DC 24V 2.7A Adapter
Software and Documentation:
Integrated +2.5V/+3.3V/+5V/+12V
Power Supplies
ATX Power Supply Compatible
Digital Interfaces:
10/100/1000 MBit Ethernet Interface
Debug UART to USB
USB OTG Interface
Dual Electrically Isolated CAN Bus
Interfaces
SD/MMC Card Socket
APPLICATIONS
Expansion
Linux Kernel
uBoot
Development Environment - Virtual
Machine
Development Board Schematics
Development Board Gerber Files
Development Board BOM
Full HSMC Interface
Partial HSMC Interface
PCI-e x4
MitySOM-5CSX Evaluation
Test and Measurement
Factory Automation
Industrial Automation
Embedded Instrumentation
Test and Measurement
Rapid Prototyping
DESCRIPTION
The MitySOM-5CSX Development Kit provides all the hardware and software support
for system designers and developers to evaluate the Critical Link MitySOM-5CSX
System on Module. The MitySOM-5CSX Development Kit comes complete with the
MitySOM-5CSX module that meets your project’s needs.
The MitySOM-5CSX Development Kit includes on-board Debug UART to USB
converter, 10/100/1000 GBit Ethernet, Universal Serial Bus (USB 2.0) USB-On-The-Go
(OTG) communication interfaces. Full and Partial HSMC connectors are compatible with
a wide range of existing add-on cards, dual electrically isolated CAN and PCI-e x4
expansion ports provide a comprehensive set of interface options.
Multi Media Card (MMC) interface supporting Secure Digital (SD) cards. Configuration
dip-switches, debug switches, RTC battery and a SOM current input monitoring circuit
round out the Development Kit. All powered from a single 24VDC input (adapter
included) or a standard ATX PC power supply with onboard +2.5V/+3.3V/+5V/12V
power supplies.
1
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Critical Link, LLC
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MitySOM-5CSX Development Kit
6 August 2014
A block diagram of the MitySOM-5CSX Development Kit is illustrated in Figure 1 on
the following page. Control of the on-board interface hardware and connected Expansion
IO cards require proper configuration of the MitySOM-5CSX Module. While not
required, it is strongly recommended that the MitySOM software development kit and
supplied API be used to manage these interfaces.
MitySOM-5CSX Development Kit
MitySOM-5CSX
HID / Thumb drive
USB OTG
PC Serial
Port
UART to USB
Bridge
SD Card
SD
Connector
Ethernet 10/100/1000
RJ-45 &
Magnetics
Full HSMC Interface
(89 IO Pins Connected)
Micrel KSZ9031
Ethernet PHY
160-Pin HSMC
Full HSMC JTAG Debug
Interface
10-pin Header
Partial HSMC Interface
(20 IO Pins Connected)
160-Pin HSMC
PC/Modules
PCIe 4X Header
Altera
Cyclone V SX/SE SoC
Dual Arm Cortex-A8
Up to 925MHz
SATA Header
Status/Debug
Indicators
LED’s
Reset and Debug
Buttons
Configuration Switches
Dip Switches
CAN 1
10-pin Header
ISO 1050
CAN 2
10-pin Header
ISO 1050
Battery
(RTC)
+1.8V From MityArm
Module
+5V MityArm Module
+18V to 24V
or
ATX Power Supply
Input
Power
Management
+3.3V Peripherals
+5V ISO 2 (CAN 2)
+1.2V Ethernet
+12V PCIe
Figure 1: MitySOM-5CSX Development Kit Block Diagram
Additional details about the Cyclone V SX/SE SoC, available peripherals, their features
and FPGA IO details are provided in the data sheet at the Altera website
(http://www.altera.com/devices/processor/soc-fpga/cyclone-v-soc/cyclone-v-soc.html).
2
Copyright © 2007-2013, Critical Link LLC
Critical Link, LLC
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MitySOM-5CSX Development Kit
6 August 2014
Feature Descriptions
Debug UART to USB Interface Description .................................................................... 4
USB 2.0 Interface Description ......................................................................................... 4
MultiMedia Card (SD) Interface Description ................................................................... 4
Gigabit Ethernet Interface Description ............................................................................. 4
SATA Interface Description ............................................................................................ 4
RTC Battery (VBat) ........................................................................................................ 4
Full HSMC Interface Description .................................................................................... 5
Full HSMC JTAG Debug Interface Description............................................................... 5
Partial HSMC Interface Description ................................................................................ 5
PCI-e x4 Interface Description ........................................................................................ 5
Dual CAN Interface Description...................................................................................... 5
Debug/User Switch Descriptions ..................................................................................... 5
Boot Configuration Dip-Switch Description .................................................................... 6
Electrical Interface Descriptions
Input Power – J601 and J600 ........................................................................................... 8
Main Power Switch – S600 ............................................................................................. 8
MultiMedia Card (SD) Interface – J403 ........................................................................... 8
Debug/Boot UART - USB Interface – J400 ..................................................................... 8
USB 2.0 Interface (OTG) – J401 ..................................................................................... 8
Dual CAN Interface – J404 & J405 ................................................................................. 9
SATA Interface – J402 .................................................................................................... 9
PCIe Interface – J200 .................................................................................................... 10
Full HSMC Interface- J300............................................................................................ 11
Full HSMC JTAG Debug Interface – J302 .................................................................... 14
Partial HSMC Interface – J301 ...................................................................................... 15
10/100/1000 Ethernet Interface – J500........................................................................... 17
Boot Configuration header – J106 ................................................................................. 17
3
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MitySOM-5CSX Development Kit
6 August 2014
Debug UART to USB Interface Description
The on-board UART to USB Bridge, FTDI FT230X, provides a serial interface at data
rates up to 115,200 baud. The USB serial interface, J400 - Console, is routed to the
primary MitySOM serial bootloading port, UART0. It allows for general module debug,
remote code download and FLASH upgrades on an attached MitySOM from this
connector when interfaced with a PC.
When connected to a Windows XP, Vista, 7 or 8 PC no drivers are required as Windows
Update is used to obtain the drivers.
USB 2.0 Interface Description
The on-board USB OTG interface utilizes a mini B type connector J401 and interfaces
with the USB phy on the MitySOM-5CSX module. This phy is connected to the USB0
controller within the Cyclone V SoC HPS. Linux drivers are available. This interface
allows for a connection to either a PC or a USB device through the use of a USB-OTG to
USB A type adapter, not included.
MultiMedia Card (SD) Interface Description
The on-board MultiMedia Card (MMC) slot uses a Secure Digital connector J403 which
supports standard (3.3V) cards. U-Boot configuration information and Linux drivers are
available.
Gigabit Ethernet Interface Description
The on-board Ethernet interface features a Micrel KSZ9031 Ethernet PHY capable of
running at 10/100/1000Mbit including link auto-negotiation and RGMII/MDIO
capability. An industry standard RJ-45 connector is provided for external connection.
This Ethernet interface may be used to perform remote code download via U-Boot and
FLASH upgrades on an attached MitySOM-5CSX module in addition to standard
network interfacing.
SATA Interface Description
The on-board SATA connector allows for connection to the MitySOM-5CSX module
gigabit transceivers. To take advantage of the SATA interface an IP core needs to be
used. There are a number of companies that offer such cores and you can contact your
Critical Link representative for a recommendation.
RTC Battery (VBat)
The MitySOM-5CSX Development Board includes a 3V battery to power the RTC on the
module. This battery is identifier B600 and is a Panasonic BR1225-1VC. Note that if the
battery gets discharged, below 1.2V, a new battery may be required for proper module
function. If the battery voltage is between 1.2V and 1.8V a slower JTAG clock frequency
may be needed for JTAG debugging. Please contact a Critical Link representative for
details.
4
Copyright © 2007-2013, Critical Link LLC
Critical Link, LLC
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MitySOM-5CSX Development Kit
6 August 2014
Full HSMC Interface Description
The Full High Speed Mezzanine Card (HSMC) interface allows for the use of add-on
cards that are designed for the Altera Cyclone V on the MitySOM-5CSX module. A
number of “off the shelf” boards/kits are available from Critical Link and other third
parties that are compatible with this interface.
Full HSMC JTAG Debug Interface Description
The 10-pin JTAG header J302 is available onboard for debugging of a device that is
connected to the Full HSMC connector, J300.
Partial HSMC Interface Description
The Full High Speed Mezzanine Card (HSMC) interface allows for the use of add-on
cards that are designed for the Altera Cyclone V on the MitySOM-5CSX module. This
interface offers access to a single Gigabit transceiver interface as well.
PCI-e x4 Interface Description
The on-board 4-channel PCI-e interface provides both root port and endpoint mode
support for PCI-e x1, x2 and x4 devices when a MitySOM-5CSX is used. In addition an
on-board 100MHz clock is provided as well as +12V and +3.3V external power supplies.
Dual CAN Interface Description
The on-board CAN provides a set of CAN V2.0B compliant interfaces. These interfaces
are managed by the MitySOM-5CSX module directly.
The galvanic isolation is provided by a dedicated TI ISO1050 transceiver for each
interface. The ISO1050 is powered by an isolated power supply with 1000V* isolation
from the primary supply.
Jumpers JP400 (CAN 1) and JP401 (CAN 0) can provide dedicated bus termination of
120Ohm. To enable termination, place shorting jumper across JP504.
The electrical interfaces are provided via J404 (CAN1) and J405 (CAN0), 10-pin
shrouded headers.
Linux Driver and API examples are available to support CAN functionality.
Debug/User Switch Descriptions
A total of 5 switches are present on the 5CSX Development Kit.
S400, S401 and S402 are tied to HPS GPIO pins on the module edge connector; pins 252,
264 and 266 respectively. These switches can be utilized for any user defined functions.
S403 is for the HPS Warm Reset which just causes the MitySOM Cyclone V SoC to
perform a soft reset.
S404 is for the Cold Reset which causes the MitySOM input power supply to be toggled.
5
Copyright © 2007-2013, Critical Link LLC
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MitySOM-5CSX Development Kit
6 August 2014
Boot Configuration Dip-Switch Description
The 5CSX Development Kit features a series of 10 clock and boot configuration dipswitches. These dip switches determine the order of peripherals for a valid boot image as
well as the clock source selection.
MSEL (5 Switches), CLKSEL (2 Switches) and BOOTSEL (3 Switches) are configured
via S100.
By default the MitySOM-5CSX Development Kits is required to boot initially from the
MMC/SD card.
6
Copyright © 2007-2013, Critical Link LLC
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MitySOM-5CSX Development Kit
6 August 2014
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
If Military/Aerospace specified cards are
required, please contact the Critical Link
Sales Office or unit Distributors for
availability and specifications.
Ambient Temperature
Range
Humidity
Maximum Supply Voltage
Storage Temperature Range
-40 to 85C
0 to 95%
Non-condensing
25.2 V
-40 to 85C
ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Conditions
Typical
Maximum Power Supply Output
IMax
24V Supply (AC Adapter) all components
1
IMax
12.0V Supply for external components
1
IMax
5.0V Supply for external components
1
IMax
3.3V Supply for external components
Power Dissipation
VS
Supply Voltage
2
IS
Supply Current
24±5%
250
Limit
Units
(Limits)
2.7
2.0
2.0
3.0
A
A
A
A
V
mA
Notes:
1. The maximum current supplied to external components should be limited to the specified maximum for
all externally connected power supplies
2. PCI-e/HSMC cards not attached, 100% ARM utilization, RS-232 and Ethernet are enabled and active.
7
Copyright © 2007-2013, Critical Link LLC
Critical Link, LLC
www.CriticalLink.com
MitySOM-5CSX Development Kit
6 August 2014
ELECTRICAL INTERFACE DESCRIPTIONS
Input Power – J601 and J600
The MitySOM-5CSX Development Kit power interface, J601, requires a single +24Volt
power supply. A recommended input supply rating of at least 2A is recommended and a
2.7A supply is included with each Development Kit.
Table 1: Input Power Interface Pin Description
Signal J601 Position
+24V
1
GND
2
Additionally the MitySOM-5CSX Development Kit provides a standard ATX PC power
supply connector, J600, which can be utilized; power supply not included. Any supply
capable of 100W or more is recommended. When this type of input supply is used J601
should NOT be connected.
Note that when an ATX power supply is used there is no control logic on the
Development Kit so when connected the Development Kit will be powered unless an
external switch is used or the supply is unplugged from AC power.
Main Power Switch – S600
An input power switch is present on the Development Kit, S600, which controls the
power input, on or off, from J601. It has no effect on the ATX power supply input, J600.
MultiMedia Card (SD) Interface – J403
The MitySOM-5CSXx Development Kit provides a MMC interface that uses a standard
Secure Digital (SD) card slot for the physical interface. Through the use of SD card
adapters MicroSD and MiniSD cards can be used in this slot. By default the slot is
supplied with 3.3V for use with standard SD cards and the R140 resistor can be depopulated while R139 is populated to provide a 1.8V supply for SDHC cards.
Debug/Boot UART - USB Interface – J400
Table 2: J400 Mini USB Connector Pin Assignments
Pin
1
2
3
4
5
Signal
VBUS
DD+
GND
SHIELD
Type
Power
I/O
I/O
GND
GND
Standard
USB 2.0
USB 2.0
-
Notes
USB data minus line
USB data plus line
USB 2.0 Interface (OTG) – J401
Table 3: J401 Pin Assignments
Pin
1
2
3
4
5
Signal
USB1_VBUS
USB1_D_N
USB1_D_P
USB1_ID
GND
Type
POWER
I/O
I/O
I/O
POWER
Standard
USB 2.0
USB 2.0
-
8
Notes
USB data minus line
USB data plus line
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MitySOM-5CSX Development Kit
6 August 2014
Dual CAN Interface – J404 & J405
Table 4: J404 CAN1 & J405 CAN0 Connector1 Pin Assignments
Pin
1
2
3
4
5
6
7
8
9
10
Signal
RESERVED
CANL
GND_ISOCANx2
RESERVED
RESERVED
RESERVED
CANH
RESERVED
+5V_CANx2
RESERVED
Type
I/O
Power
I/O
Power
-
Standard
-
Notes
CAN Bus Signal L
CAN Bus Isolated Ground
-
CAN Bus Signal H
-
Isolated +5V Output, 20mA Max
Note 1: Please see Figure 2 for physical pin-out of connector
Note 2: The ‘x’ at the end of the signal names is either a 1 or a 0 depending on which
CAN interface you are using.
5
4
3
2
1
10
9
8
7
6
Figure 2: J404 and J405 Pin-out (Top View)
SATA Interface – J402
Table 5 describes the pin-out of the SATA connector on the MitySOM-5CSX
development board. A SATA core is needed in the FPGA fabric to utilize this interface.
Table 5: J402 Pin Assignments
Pin
1
2
3
4
5
6
7
Signal
GND
SATA_RX_C_P
SATA_RX_C_N
GND
SATA_TX_C_N
SATA_TX_C_P
GND
SoM Pin
232
234
241
239
-
Type
POWER
I
I
POWER
O
O
POWER
Standard
-
9
Notes
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MitySOM-5CSX Development Kit
6 August 2014
PCIe Interface – J200
Table 6 describes the pin-out of the PCI-e x4 capable interface on the MitySOM-5CSX
development board. The I/O “type” is in reference to the signal direction from the
SoM/development board.
Table 6: J200 Pin Assignments
Pin
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
Signal
GND
+12V_EXT
+12V_EXT
GND
JTAG2
JTAG3
JTAG4
JTAG5
+3.3V_EXT
+3.3V_EXT
PCIE1_PERST_SJN
GND
PCIE_CLK0_R_P
PCIE_CLK0_R_N
GND
PCIE1_RX_0_P
PCIE1_RX_0_N
GND
RESERVED
GND
PCIE1_RX_1_P
PCIE1_RX_1_N
GND
GND
PCIE1_RX_2_P
PCIE1_RX_2_N
GND
GND
PCIE1_RX_3_P
PCIE1_RX_3_N
GND
RESERVED
+12V_EXT
+12V_EXT
+12V_EXT
GND
PCIE1_SMCLK
PCIE1_SMDAT
GND
+3.3V_EXT
JTAG1
+3.3V_EXT
PCIE1_WAKEN
RESERVED
GND
PCIE_TX_0_P
PCIE_TX_0_N
GND
PCIE1_X1_PRSNT2N
SoM Pin
21
204
202
208
210
214
216
226
228
69
71
83
209
211
101
Type
POWER
POWER
POWER
POWER
NC
NC
NC
POWER
POWER
I
POWER
O
O
POWER
I
I
POWER
POWER
I
I
POWER
POWER
I
I
POWER
POWER
I
I
POWER
POWER
POWER
POWER
POWER
I
I/O
POWER
POWER
NC
POWER
O
POWER
O
O
POWER
I
10
Standard
1A Max
1A Max
1A Max
1A Max
1A Max
1A Max
-
Notes
Note 2
Note 2
TCK – 2.2k ohm resistor to ground
TDI – No connect
TDO – No connect
TMS – No connect
Note 1
Note 1
100MHz clock, U200, to PCI-e device
100MHz clock, U200, to PCI-e device
Note 1
TRSTn – No connect
Note 1
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B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
MitySOM-5CSX Development Kit
6 August 2014
GND
PCIE_TX_1_P
PCIE_TX_1_N
GND
GND
PCIE_TX_2_P
PCIE_TX_2_N
GND
GND
PCIE_TX_3_P
PCIE_TX_3_N
GND
RESERVED
PCIE1_X4_PRSNT2N
GND
215
217
221
223
233
235
162
-
POWER
O
O
POWER
POWER
O
O
POWER
POWER
O
O
POWER
I
POWER
-
Notes:
1. The maximum total current supplied to external components from the +3.3V supply should be limited to
less than 3.0A. The maximum current allowed per connector pin is 1A.
2. The maximum total current supplied to external components from the +12V supply should be limited to
less than 2.0A. The maximum current allowed per connector pin is 1A.
Full HSMC Interface- J300
Table 7 describes the pin-out of the Full HSMC interface on the MitySOM-5CSX
development board. The I/O “type” is in reference to the signal direction from the
SoM/development board.
Table 7: J300 Connector Pin Assignments
Pin
1 - 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Schematic Signal
RESERVED
HSMC1_SMSDA
HSMC1_SMSCL
HSMC1_JTAG_TCK
HSMC1_JTAG_TMS
HSMC1_JTAG_TDO
HSMC1_JTAG_TDI
HSMC1_CLKOUT0
HSMC1_CLKIN0
HSMC1_D0
HSMC1_D1
HSMC1_D2
HSMC1_D3
+3.3V
+12V
HSMC1_TX0_P
HSMC1_RX0_P
HSMC1_TX0_N
HSMC1_RX0_N
+3.3V
+12V
HSMC1_TX1_P
HSMC1_RX1_P
HSMC1_TX1_N
HSMC1_RX1_N
SoM Pin
54
56
160
99
74
90
76
106
68
87
70
89
78
91
80
93
Type
I/O
O
O
I
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
11
Notes
Bank 4A
Bank 4A
J302 – Pin 1
J302 – Pin 5
J302 – Pin 3
J302 – Pin 9
Bank 3B
Bank 3B
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
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57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
+3.3V
+12V
HSMC1_TX2_P
HSMC1_RX2_P
HSMC1_TX2_N
HSMC1_RX2_N
+3.3V
+12V
HSMC1_TX3_P
HSMC1_RX3_P
HSMC1_TX3_N
HSMC1_RX3_N
+3.3V
+12V
HSMC1_TX4_P
HSMC1_RX4_P
HSMC1_TX4_N
HSMC1_RX4_N
+3.3V
+12V
HSMC1_TX5_P
HSMC1_RX5_P
HSMC1_TX5_N
HSMC1_RX5_N
+3.3V
+12V
HSMC1_TX6_P
HSMC1_RX6_P
HSMC1_TX6_N
HSMC1_RX6_N
+3.3V
+12V
HSMC1_TX7_P
HSMC1_RX7_P
HSMC1_TX7_N
HSMC1_RX7_N
+3.3V
+12V
HSMC1_CLKOUT1_P
HSMC1_CLKIN1_P
HSMC1_CLKOUT1_N
HSMC1_CLKIN1_N
+3.3V
+12V
HSMC1_TX8_P
HSMC1_RX8_P
HSMC1_TX8_N
HSMC1_RX8_N
+3.3V
+12V
HSMC1_TX9_P
HSMC1_RX9_P
HSMC1_TX9_N
HSMC1_RX9_N
+3.3V
+12V
HSMC1_TX10_P
HSMC1_RX10_P
HSMC1_TX10_N
MitySOM-5CSX Development Kit
6 August 2014
82
95
84
97
86
105
88
107
94
109
96
111
98
113
100
115
102
121
104
123
110
133
112
135
114
177
116
179
118
137
120
139
122
141
124
143
138
145
140
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
O
I
O
I
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
12
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 8A
Bank 4A
Bank 8A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
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116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161 - 172
HSMC1_RX10_N
+3.3V
+12V
HSMC1_TX11_P
HSMC1_RX11_P
HSMC1_TX11_N
HSMC1_RX11_N
+3.3V
+12V
HSMC1_TX12_P
HSMC1_RX12_P
HSMC1_TX12_N
HSMC1_RX12_N
+3.3V
+12V
HSMC1_TX13_P
HSMC1_RX13_P
HSMC1_TX13_N
HSMC1_RX13_N
+3.3V
+12V
HSMC1_TX14_P
HSMC1_RX14_P
HSMC1_TX14_N
HSMC1_RX14_N
+3.3V
+12V
HSMC1_TX15_P
HSMC1_RX15_P
HSMC1_TX15_N
HSMC1_RX15_N
+3.3V
+12V
HSMC1_TX16_P
HSMC1_RX16_P
HSMC1_TX16_N
HSMC1_RX16_N
+3.3V
+12V
HSMC1_CLKOUT2_P
HSMC1_CLKIN2_P
HSMC1_CLKOUT2_N
HSMC1_CLKIN2_N
+3.3V
HSMC1_PRSNTN
GND
MitySOM-5CSX Development Kit
6 August 2014
147
142
149
144
151
146
155
148
157
150
159
152
161
154
163
156
165
164
167
166
169
168
171
170
173
178
172
180
174
85
-
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
O
I
O
I
Power
O
Power
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
2.5V
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 3B
Bank 3B
Bank 3B
Bank 3B
Note 1
Note 2
Bank 8A
Bank 8A
Bank 8A
Bank 8A
Note 1
Bank 4A
Notes:
1. The maximum total current supplied to external components from the +3.3V supply should be limited to
less than 3.0A. The maximum current allowed per connector pin is 1A.
2. The maximum total current supplied to external components from the +12V supply should be limited to
less than 2.0A. The maximum current allowed per connector pin is 1A.
Please see the following Altera documentation concerning the HSMC specification
(http://www.altera.com/literature/ds/hsmc_spec.pdf).
13
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MitySOM-5CSX Development Kit
6 August 2014
Full HSMC JTAG Debug Interface – J302
Table 8 describes the pin-out of the Full HSMC JTAG interface on the MitySOM-5CSX
development board. This allows for debug of JTAG supported HSMC cards/devices.
Table 8: J101 JTAG Pin Assignments
Pin
1
2
3
4
5
6–8
9
10
Schematic Signal
HSMC1_JTAG_TCK
GND
HSMC1_JTAG_TDO
+3.3V_EXT
HSMC1_JTAG_TMS
RESERVED
HSMC1_JTAG_TDI
GND
SoM Pin
-
Type
Power
Power
Power
Standard
Notes
J300 – Pin 35
1A Max
J300 – Pin 37
Note 1
J300 – Pin 36
J300 – Pin 38
14
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MitySOM-5CSX Development Kit
6 August 2014
Partial HSMC Interface – J301
Table 9 describes the pin-out of the partial HSMC interface on the MitySOM-5CSX
development board. The I/O “type” is in reference to the signal direction from the
SoM/development board.
Table 9: J506 Connector Pin Assignments
Pin
1 - 28
29
30
31
32
33
34
35 – 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
Schematic Signal
RESERVED
HSMC2_GTX0_P
HSMC2_GRX0_P
HSMC2_GTX0_N
HSMC2_GRX0_N
HSMC2_SMSDA
HSMC2_SMSCL
RESERVED
HSMC2_D1_P
HSMC2_D2_P
HSMC2_D1_N
HSMC2_D2_N
+3.3V
+12V
HSMC2_TX0_P
HSMC2_RX0_P
HSMC2_TX0_N
HSMC2_RX0_N
+3.3V
+12V
HSMC2_TX1_P
HSMC2_RX1_P
HSMC2_TX1_N
HSMC2_RX1_N
+3.3V
+12V
HSMC2_TX2_P
HSMC2_RX2_P
HSMC2_TX2_N
HSMC2_RX2_N
+3.3V
+12V
HSMC2_TX3_P
HSMC2_RX3_P
HSMC2_TX3_N
HSMC2_RX3_N
+3.3V
+12V
HSMC2_TX4_P
HSMC2_RX4_P
HSMC2_TX4_N
HSMC2_RX4_N
+3.3V
+12V
HSMC2_TX5_P
HSMC2_RX5_P
HSMC2_TX5_N
HSMC2_RX5_N
+3.3V
+12V
J303 Pin
17
16
19
13
18
14
21
11
20
12
23
9
21
10
25
7
24
8
-
SoM Pin
245
238
247
240
58
56
65
61
67
63
64
77
66
79
62/196
73
198
71
192
203
194
205
188
199
190
201
184
195
186
197
42
191
44
193
-
Type
O
I
O
I
I/O
O
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
15
Standard
Notes
Transceiver
Transceiver
Transceiver
Transceiver
Bank 4A
Bank 4A
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Bank 4A
Bank 4A
Bank 4A
Bank 4A
Note 1
Note 2
Note 3
Bank 4A
Note 3
Bank 4A
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
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83
84
85
86
87
88
89
90
91
92
93
94
95 - 98
99
100
101 - 104
105
106
107 - 110
111
112
113 - 116
117
118
119 - 122
123
124
125 - 128
129
130
131 - 134
135
136
137 - 140
141
142
143 - 146
147
148
149 - 152
153
154
155
156
157
158
159
160
161 - 172
HSMC2_TX6_P
HSMC2_RX6_P
HSMC2_TX6_N
HSMC2_RX6_N
+3.3V
+12V
HSMC2_TX7_P
HSMC2_RX7_P
HSMC2_TX7_N
HSMC2_RX7_N
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
RESERVED
+3.3V
+12V
HSMC2_CLK_P
RESERVED
HSMC2_CLK_N
RESERVED
+3.3V
HSMC2_PRSNTN
GND
MitySOM-5CSX Development Kit
6 August 2014
27
5
26
6
29
3
28
4
-
53
187
55
189
47
183
49
185
60
-
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
I/O
I/O
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
O
O
Power
I
Power
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
2.5V
2.5V
2.5V
2.5V
1A Max
1A Max
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
Note 3
Note 3
Note 3
Note 3
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
1A Max
1A Max
Note 1
Note 2
100MHz clock, U102, to HSMC device
100MHz clock, U102, to HSMC device
1A Max
Note 1
Bank 4A
Notes:
1. The maximum total current supplied to external components from the +3.3V supply should be limited to
less than 3.0A. The maximum current allowed per connector pin is 1A.
2. The maximum total current supplied to external components from the +12V supply should be limited to
less than 2.0A. The maximum current allowed per connector pin is 1A.
3. These pins are only connected when using a module with expanded IO capabilities.
Please see the following Altera documentation concerning the HSMC specification
(http://www.altera.com/literature/ds/hsmc_spec.pdf).
16
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MitySOM-5CSX Development Kit
6 August 2014
10/100/1000 Ethernet Interface – J500
The MitySOM-5CSX Development Kit provides a RJ-45 connection for a Gigabit
10/100/1000 Ethernet connection. This connection follows standard TIA/EIA-568B pinout as shown in Table 10 below. The Ethernet PHY, Micrel KSZ9031, will auto negotiate
to the speed of the device it is connected to.
Table 10: J500 Ethernet RJ45 Pin Assignments
Pin
1
2
3
4
5
6
7
8
Signal
TXRXA_P
TXRXA_N
TXRXB_P
TXRXB_N
TXRXC_P
TXRXC_N
TXRXD_P
TXRXD_N
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Standard
Notes
Boot Configuration header – J106
The boot mode, as determined by the 10 CONFIG switches, is selected on the rising edge
of the PWRONRSTn Reset Input Pin of the Cyclone V processor which is controlled by
the PMIC of the MitySOM-5CSX module. Each boot configuration pin on the
development kit is connected to a weak pull up, ‘1’, unless a switch is closed which pulls
that configuration pin down to ground, ‘0’.
The MitySOM-5CSX Development Kits default boot configuration mode is shown in
Figure 3 below. As seen this equates to a boot configuration setting of S1 to S10,
0000011101. Please reference the Cyclone V Technical Reference Manual for
complete details on how the vast array of boot mode options.
Figure 3: Default Development Kit Boot Jumper Mode
17
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MitySOM-5CSX Development Kit
6 August 2014
Included Components
The following table lists the components that are included with a MitySOM-5CSX
Development Kit. See Table 12 for specific development kit ordering information.
Table 11: Included Items
Description
Interface Port
MitySOM-5CSX Development Kit Board
n/a
MitySOM-5CSX Module
J100
Mini USB Cable for Debug Console
J400
24V 2.7A AC to DC Supply
J601
Ethernet cable – 7 foot
J500
USB Drive with Development Environment
n/a
Development Kit Schematic Files
n/a
Development Kit Gerber Drawings
n/a
Development Kit Bill Of Materials
n/a
Development Kit Quick Start Guide
n/a
Qty. Included
Qty. 1
Qty. 1
Qty. 1
Qty. 1
Qty. 1
Qty. 1
MitySOM-5CSX Development Kit Board with MitySOM-5CSX Module
18
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MitySOM-5CSX Development Kit
6 August 2014
ORDERING INFORMATION
Development Kits
The following table lists the standard MitySOM-5CSX Development Kit configurations.
For shipping status, availability, and lead time of these or other configurations please
contact your Critical Link representative.
Table 12: Standard Model Numbers
Development Kit Model
Module Included
Module Junction Temp
80-000640
5CSX-H6-42A-RC
0oC to 90o C
80-000639
5CSX-H6-42A-RI
-40oC to 105o C
MECHANICAL INTERFACE DESCRIPTION
Main Board Interface / Mounting
Figure 4: MitySOM-5CSX Development Kit Outline, Mounting Hole Locations,
(Top View, inches)
19
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MitySOM-5CSX Development Kit
6 August 2014
REVISION HISTORY
Date
12-JAN-2014
31-APR-2014
6-AUG-2014
Change Description
Initial revision.
Updates and changes from review and initial release.
Updates and changes to encompass more detailed pinout.
20
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