Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
FEATURES
TI AM1810 ARM9 Application Processor
-
375 MHz ARM926EJ-S MPU
16 KB L1 Program Cache
16 KB L1 Data Cache
8 KB Internal RAM
64 KB boot ROM
JTAG Emulation/Debug
On-Board Xilinx Spartan-6 FPGA
- Up To XC6SLX45
Up To 2,088 KBits Block RAM
Up To 6,822 Slices (6 Input LUTs)
- 1050 Mbps data rate
- JTAG Interface/Debug
APPLICATIONS
Embedded Instrumentation
Industrial Automation
Industrial Instrumentation
Medical Instrumentation
Embedded Control Processing
Network Enabled Data Acquisition
Test and Measurement
Software Defined Radio
Bar Code Scanners
Power Protection Systems
Portable Data Terminals
Up To 256 MB mDDR2 CPU RAM
Up To 512 MB Parallel NAND FLASH
8 MB SPI based NOR FLASH
Integrated Power Management
Standard SO-DIMM-200 Interface
- 96 FPGA User I/O Pins
- 10/100 EMAC MII / MDIO
- 2 UARTS
- 2 McBSPs
- 2 USB Ports
- Video Output
- Camera/Video Input
- MMC/SD
- SATA
- ePWM, eCAP
- EMIFA
- Single 3.3V Power Supply
BENEFITS
Rapid Development / Deployment
Multiple Connectivity and Interface Options
Rich User Interfaces
High System Integration
High Level OS Support
High Level OS Support
- Linux
- QNX
- Windows Embedded CE Ready
- ThreadX Real Time OS
PROFIBUS Interface
- Certified by PI International
- Real-Time Linux Drivers
- Up to 6Mbaud operation
DESCRIPTION
The MitySOM-1810F is a highly configurable, very small form-factor processor card that
features a Texas Instruments AM1810 375MHz ARM Applications Processor tightly
integrated with the Xilinx Spartan-6 Field Programmable Gate Array (FPGA),
PROFIBUS, FLASH (NAND and NOR) and mDDR2 RAM memory subsystems.
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
The design of the MitySOM-1810F allows end users the capability to develop
programs/logic images for both the ARM processor and the FGPA. The MitySOM1810F provides a complete and flexible digital processing infrastructure necessary for the
most demanding embedded applications development.
The AM1810 includes an ARM926EJ-S micro-processor unit (MPU) capable of running
the rich software applications programming interfaces (APIs) expected by modern system
designers. The ARM architecture supports several operating systems, including RealTime Linux, QNX and Windows XP embedded. Linux drivers are available for all
interfaces, including the PROFIBUS interface.
8MB NOR Flash
(SPI interface)
For uBoot
bootloader
Up To 256MB
mDDR Memory
16-bit wide
1.2V
Up To 512MB
NAND Flash
16-bit wide
For root FFS
1.8V
2.5V
Power
Management
3.3V
EMIFA (16-bit)
System
Clocks
JTAG/Emulator
JTAG
Header
JTAG
MMCSD 1
LCD
uPP
Xilinx
Spartan-6
FPGA
Up To XC6SLX45
CSG324 pkg.
Programmable I/O
I/O Bank Power
Boot Config
Resets & RTC
SATA
USB 0,1
Timers
eCAP
eHRPWM
I2C 0,1
McASP
SPI 0,1
McBSP 0,1
MMCSD 0
UART 0,1,2
EMAC MII/MDIO
Boot
Config
FPGA I/O
Banks can be
1.8V, 2.5V, or
3.3V
I/O Bank Power
VPIF I/O
GND
(Many pins are multiplexed between peripherals)
UHPI
3.3 V
EMAC RMII
Programmable I/O
Texas Instruments
AM1810
375-MHz ARM926EJ-S ™ RISC MPU
SO-DIMM-200 (DDR2 Connector)
Figure 1 MitySOM-1810F Block Diagram
Figure 1 provides a top level block diagram of the MitySOM-1810F processor card. As
shown in the figure, the primary interface to the MitySOM-1810F is through a standard
SO-DIMM-200 card edge interface. The interface provides power, synchronous serial
connectivity, and up to 96 pins of configurable FPGA I/O for application defined
interfacing. Details of the SO-DIMM-200 connector interface are included in the SODIMM-200 Interface Description, below.
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
PROFIBUS Interface
Texas Instruments Inc. (TI) has integrated PROFIBUS functionality into its AM1810
Sitara ARM microprocessor (MPU). The solution utilizes one of the onboard UARTS
and connects directly to the RS-485 transceiver and therefore eliminates the need of an
external PROFIBUS ASIC or FPGA. Customers using the MitySOM-1810 in their
industrial application can save cost and reduce design complexity as well as PCB space.
Furthermore, the industrial application benefits from the low-power architecture of the
Sitara ARM MPU and the MitySOM-1810 platform from TI and Critical Link.
The AM1810 Sitara ARM MPU PROFIBUS Slave solution has been certified by
PROFIBUS International (PI).
The PROFIBUS real-time frame handler (Fieldbus Data Link or FDL) is encapsulated in
the Programmable Real-Time Unit Subsystem (PRUSS), which is part of the AM1810
Sitara ARM MPU on-chip peripherals. The PRUSS uses one Universal Asynchronous
Receiver/Transmitter (UART) and a timer to generate PROFIBUS-compliant frames. The
industrial application and the PROFIBUS DP-Protocol (Layer 7) are operated on the
ARM. The solution can be completed with an RS-485 transceiver suitable for harsh
environments, such as TI’s ISO1176T or ISO1176 placed on the base board to the
MitySOM-1810F.
The PROFIBUS subsystem uses the PRUs that implement real-time frame handling;
PROFIBUS message transmission, frame validation and communication with the ARM
processor. The PROFIBUS subsystem interfaces with one of the UARTs in the AM1810
Sitara ARM MPU, which is designated for PROFIBUS communication at up to 6Mbaud
data rate. The PRU uses interrupts to interact with the ARM where the PROFIBUS stack
(Layer 7, DP Protocol) and the industrial application is run. All process data handling like
cyclic, acyclic and service access point (SAP) between the PROFIBUS stack on ARM
and the PRU is through the internal memory.
Additional details about the AM1810 Sitara ARM MPU, available peripherals and their
features are provided in the data sheet at the TI website (www.ti.com/am1810).
FPGA Bank I/O
The MitySOM-1810F provides 96 lines of FPGA I/O directly to the SO-DIMM-200 card
edge interface. The 96 lines of FPGA I/O are distributed across 2 banks of the FPGA.
These I/O lines and their associated logic are completely configurable within the FPGA
at the end user’s discretion.
With the Xilinx Spartan-6 series FPGA, up to the XC6SLX45, each of the user controlled
banks may be configured to operate on a different electrical interface standard based on
input voltage provided at the card edge connector. The banks support 3.3V, 2.5V, and
1.8V standard CMOS switching level technology. In addition, the I/O lines from the
FPGA have been routed as differential pairs and support higher speed LVDS standards as
well as SSTL 2.5 switching standards. Various forms of termination (pull-up/pull-down,
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
digitally controlled impedance matching) are available within the FPGA switch fabric.
Refer to the Xilinx Spartan 6 user’s guide for more information.
AM1810 mDDR2 Memory Interface
The AM1810 includes a dedicated DDR2 SDRAM memory interface. The MitySOM1810F includes up to 256 MB of mDDR2 RAM integrated with the AM1810 processor.
The bus interface is capable of burst transfer rates of 532 MB / second.
AM1810 SPI NOR FLASH Interface
The MitySOM-1810F includes 8 MB of SPI NOR FLASH. This FLASH memory is
intended to store a factory provided bootloader, and typically a compressed image of a
Linux kernel for the ARM core processor.
EMIFA / NAND FLASH Interface
The Asynchronous External Memory Interface (EMIFA) interface available on the
AM1810 is available on the SO-DIMM-200 connector. The EMIFA interface includes 3
chip select spaces. The EMIF interface supports multiple data width transfers and bus
wait state configurations based on chip select space. 8, and 16 bit data word sizes may be
used.
Up to 512 MB of on-board NAND FLASH memory is connected to the AM1810 using
the EMIFA bus. The FLASH memory is 8 bits wide and is connected to the third chip
select line of the EMIFA (CE1). The FLASH memory is typically used to store the
following types of data:
-
ARM Linux / Windows Embedded CE / QNX embedded root file-system
FPGA application images
runtime ARM software
runtime application data (non-volatile storage)
AM1810 Camera and Video Interfaces
The AM1810 includes an optional video port I/O interface commonly used to drive LCD
screens as well as a camera input interface. These interfaces have been routed directly to
the SO-DIMM-200 connector.
Debug Interface
Both the JTAG interface signals for the FPGA and the JTAG signals for the AM1810
processor have been brought out to a Hirose header that is intended for use with an
available Critical Link breakout adapter. This header can be removed for production
units; please contact your Critical Link representative for details.
This adapter is not included with individual modules but is included with each Critical
Link Development Kit that is ordered. If an adapter, Critical Link (CL) part number 80000286, is needed please contact your Critical Link representative.
4
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
Software and Application Development Support
Users of the MitySOM-1810F are encouraged to develop applications using the
MitySOM-1810F software development kit provided by Critical Link LLC. The
development kit includes an implementation of an OpenEmbedded board support
package providing an Angstrom based Linux distribution and compatible gcc compiler
tool-chain with debugger.
To support rapid FPGA and applications development, netlist components - compatible
with the Xilinx ISE FPGA synthesis tool – for commonly used FPGA designs and a
corresponding set of Linux loadable kernel modules are included. The libraries provide
the necessary functions needed to configure the MitySOM-1810F, program standalone
embedded applications, and interface with the various hardware components both on the
processor board as well as a custom application carrier card. The libraries include several
interface “cores” – FPGA and ARM software modules designed to interface with various
high performance data converter modules (ADCs, DACs, LCD and touchscreen
interfaces, etc) – as well as bootloading and FLASH programming utilities.
Growth Options
The MitySOM-1810F has been designed to support several upgrade options. These
options include various speed grades, memory configurations, and operating temperature
specifications including commercial and industrial temperature ranges. The available
options are listed in the section below containing ordering information. For additional
ordering information and details regarding these options, or to inquire about a particular
configuration not listed below, please contact a Critical Link sales representative.
5
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
If Military/Aerospace specified cards are
required, please contact the Critical Link Sales
Office or unit Distributors for availability and
specifications.
Ambient Temperature
Range Commercial
Ambient Temperature
Range Industrial
Humidity
Maximum Supply Voltage, Vcc
Storage Temperature Range
Shock, Z-Axis
Shock, X/Y-Axis
3.5 V
MIL-STD-810F
-65oC to 80oC
±10 g
±10 g
0oC to 70oC
-40oC to 85oC
0 to 95%
Non-condensing
Contact Critical
Link for Details
SO-DIMM-200 Interface Description
The primary interface connector for the MitySOM-1810F is the SO-DIMM card edge
interface.
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
I/O
I
O
O
I
I
I
I/O
I/O
O
I/O
I/O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Table 1 SO-DIMM Pin-Out
Signal
Pin
I/O
+3.3 V in
2
+3.3 V in
4
+3.3 V in
6
GND
8
GND
10
RESET_IN#
12
SATA_TX_P
14
I/O
SATA_TX_N
16
I/O
SATA_RX_P
18
I/O
SATA_RX_N
20
I/O
USB0_ID
22
I/O
USB1_D_N
24
I/O
USB1_D_P
26
I/O
USB0_VBUS
28
I/O
USB0_D_N
30
I/O
USB0_D_P
32
I/O
USB0_DRVVBUS
34
I/O
3V RTC Battery
36
I/O
+3.3 V in
38
+3.3 V in
40
GND
42
SPI1_MISO
44
I/O
SPI1_MOSI
46
I/O
SPI1_ENA
48
I/O
SPI1_CLK
50
I/O
SPI1_SCS1
52
I/O
Reserved
54
I/O
I2C0_SCL
56
I/O
I2C0_SDA
58
I/O
6
Signal
+3.3 V in
+3.3 V in
+3.3 V in
GND
GND
EXT_BOOT#
GP0_7
GP0_10
GP0_11
GP0_15
GP0_6
GP0_14
GP0_12
GP0_5
GP0_13
GP0_1
GP0_4
GP0_3
+3.3 V in
+3.3 V in
GND
GP0_2
GP0_0
GP0_8
GP0_9
MMCSD0_DAT7
MMCSD0_DAT6
MMCSD0_DAT5
MMCSD0_DAT4
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Pin
59
I/O
I/O
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
Signal
UART2_TXD
/
I2C1_SDA
UART2_RXD / I2C1_SCL
GND
UART1_TXD
UART1_RXD
MDIO_CLK
MDIO_DAT
MII_RXCLK
MII_RXDV
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
GND
MII_CRS
MII_RXER
B1 _47_P.U17
B1_ 47_N.U18
B1 _45_P.T17
B1_ 45_N.T18
B1_43_P.P17
B1_43_N.P18
B1_41_P.N17
B1_41_N.N18
GND
B1_39_P.M16
B1_39_N.M18
B1_37_P.L17
B1_37_N.L18
B1_35_P.K17
B1_35_N.K18
B1_33_P.J16
B1_33_N.J18
B1_31_P.H17
B1_31_N.H18
GND
B1_29_P.G16
B1_29_N.G18
B1_27_P.F17
B1_27_N.F18
B1_25_P.E16
B1_25_N.E18
B1_23_P.D17
B1_23_N.D18
B1_21_P.C17
B1_21_N.C18
GND
B0_19_P.B16
B0_19_N.A16
B0_17_P.C15
7
Pin
60
I/O
I/O
Signal
MMCSD0_DAT3
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O*
I/O*
I/O*
MMCSD0_DAT2
GND
MMCSD0_DAT1
MMCSD0_DAT0
MMCSD0_CMD
MMCSD0_CLK
MII_TXCLK
MII_TXD3
MII_TXD2
MII_TXD1
MII_TXD0
MII_TXEN
GND
MII_COL
FPGA_SUSPEND
B1 _48_P.M14
B1_ 48_N.N14
B1 _46_P.N15
B1_ 46_N.N16
B1 _44_P.L12
B1_ 44_N.L13
B1 _42_P.K12
B1_ 42_N.K13
GND
B1 _40_P.L15
B1_ 40_N.L16
B1 _38_P.K15
B1_ 38_N.K16
B1 _36_P.J13
B1_ 36_N.K14
B1 _34_P.H15
B1_ 34_N.H16
B1 _32_P.H13
B1_ 32_N.H14
GND
B1 _30_P.F15
B1_ 30_N.F16
B1 _28_P.H12
B1_ 28_N.G13
B1 _26_P.F14
B1_ 26_N.G14
B0 _24_P.F13
B0_ 24_N.E13
B0 _22_P.D14
B0_ 22_N.C14
GND
B0 _20_P.F12*
B0_ 20_N.E12*
B0 _18_P.D12*
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Pin
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
Signal
B0_17_N.A15
B0_15_P.B14
B0_15_N.A14
B0_13_P.C13
B0_13_N.A13
B0_11_P.B12
B0_11_N.A12
GND
B0_9_P.B11
B0_9_N.A11
B0_7_P.C10
B0_7_N.A10
B0_5_P.B9
B0_5_N.A9
B0_3_P.B8
B0_3_N.A8
B0_1_P.C7
B0_1_N.A7
GND
VCCO_1
VCCO_1
Pin
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
I/O
I/O*
I/O*
I/O*
I/O
I/O
I/O*
I/O*
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
Signal
B0_ 18_N.C12*
B0 _16_P.F11*
B0_ 16_N.E11*
B0 _14_P.D11
B0_ 14_N.C11
B0 _12_P.E7*
B0_ 12_N.E8*
GND
B0 _10_P.D9
B0_ 10_N.C9
B0 _8_P.D8
B0_ 8_N.C8
B0 _6_P.D6
B0_ 6_N.C6
B0 _4_P.B6
B0_ 4_N.A6
B0 _2_P.C5
B0_ 2_N.A5
GND
VCCO_0
VCCO_0
* The Xilinx 6SLX45 FPGA does not bond I/O Buffers to balls E7, E8, F11,
E11, D12, C12, E12, and F12 of the package used for this module. For
MitySOM-1810F configurations using this FPGA option, these edge
connector signals should be treated as no-connects and will not function as
FPGA I/O lines.
The signal group description for the above pins is included in Table 2
Table 2 Signal Group Description
Signal / Group
3.3 V in
EXT_BOOT#
I/O
N/A
I
RESET_IN#
I
SPI_XXXX
I/O
MII_XXXX
I/O
Description
3.3 volt input power referenced to GND.
Bootstrap configuration pin. Pull low to configure
booting from external UART1.
Manual Reset. When pulled to GND for a
minimum of 1 usec, resets the DSP processor.
The pins with an SPI_ prefix are direct
connections to the AM1810 pins supporting the
SPI1 interface. The SPI1_CLK, SPI1_ENA,
SPI1_MISO, SPI1_MOSI pins must remain
configured for the SPI function in order to support
interfacing to the on-board SPI boot ROM. For
details please refer to the AM1810 processor
specifications.
The pins with an MII_ prefix are direct
connections to the AM1810 pins supporting the
8
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Signal / Group
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
I/O
MDIO_XX
I/O
GP0_X
IO
SATA_TX_P/N
O
SATA_RX P/N
I
GND
BX_Y_P.ZZ,
BX_Y_N.ZZ
VCCO_X
USB0_XXXX,
USB1_XXXX
N/A
IO
I
I/O
Description
media independent interface (MII) function. The
MII pins provide multiplex capability and may
alternately be used as UART, GPIO, and SPI
control pins. For details please refer to the
AM1810 processor specification.
The MDIO_CLK and MDIO_DAT signals are
direct connects to the corresponding MDIO
signals on the AM1810 processor. These pins
may be configured for GPIO.
General Purpose / multiplexed pins. These pins are
direct connects to the corresponding GP0[X] pins
on the AM1810 processor. The include support
for the McASP, general purpose I/O, UART flow
control, and McBSP 1. For details please refer to
the AM1810 processor specifications.
These pins are direct connects to the AM1810
SATA_TX differential Serial ATA controller pins.
These pins are direct connects to the AM1810
SATA_RX differential Serial ATA controller pins.
System Digital Ground.
FPGA I/O pins. These pins are routed directly to
FPGA pins ZZ. The “X” indicates which FPGA
bank the pin is allocated. The bank is either 0 or
1. The FPGA fabric supports routing pins in
differential pairs, the Y_P and Y_N portion of the
name indicates the pair number and polarity. The
pins have been routed in pairs with phase matched
line lengths.
FPGA Bank interface power input. These pins
must be tied to the desired voltage used for the
FPGA Bank 0 or 1 interface pins. Please refer to
the VCCO input pin specifications for the Xilinx
Spartan 6 family of devices for further
information. Typical values are 3.3V and 2.5
volts.
The USBN_ prefixed pins are direct connects to
the corresponding pins on the AM1810 processor.
For details please refer to the AM1810 processor
specifications.
9
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MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
DEBUG INTERFACE
Below is the pin-out for the Hirose 31 pin header (DF9-31P-1V(32)) that interfaces with
an available adapter board, CL part number 80-000286, to debug the AM1810 and
FPGA.
Debug Interface Connector Description (J2)
Pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
I/O
-
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Table 3 OMAP-L138 Hirose Connector
Signal
Pin
I/O
Signal
2
O
OMAP EMU1
4
O
OMAP EMU0
6
I
OMAP TCK
8
O
OMAP RTCK
10
O
OMAP TDO
12
OMAP VCC / 3.3V
14
I
OMAP TDI
16
I
OMAP TRST
18
I
OMAP TMS
20
GND
22
O
FPGA VREF / VCCAUX
24
I
FPGA TMS
26
I
FPGA TCK
28
O
FPGA TDO
30
I
FPGA TDI
ELECTRICAL CHARACTERISTICS
Symbol
V33
I33
I33-max
FCPU
FEMIF
Table 4: Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Units
Voltage supply, 3.3 volt input.
3.2
3.3
3.4
Volts
Quiescent Current draw, 3.3 volt input
TBS
TBS
mA
Max current draw, positive 3.3 volt input.
TBS
TBS
mA
CPU internal clock Frequency (PLL output)
25
375
375
MHz
EMIF bus frequency
Must be ½ CPU
100
MHz
1. Power utilization of the MitySOM-1810F is heavily dependant on end-user application. Major
factors include: ARM CPU PLL configuration, DSP Utilization FPGA utilization, and external
DDR2 RAM utilization.
10
Copyright © 2012, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
ORDERING INFORMATION
The following table lists the standard module configurations. For shipping status,
availability, and lead time of these or other configurations please contact your Critical
Link representative.
Model
1810-DG-225-RC
1810-DG-225-RI
Table 5: Standard Model Numbers
NOR
ARM Speed
FPGA
NAND Flash
Flash
375 MHz
6SLX16
8MB
256MB
375 MHz
6SLX16
8MB
256MB
RAM
128MB
128MB
Operating
Temp
0oC to 70o C
-40oC to 85o C
MECHANICAL INTERFACE
A mechanical outline of the MitySOM-1810F is illustrated in Figure 2, below.
Figure 2 MitySOM-1810F Mechanical Outline
11
Copyright © 2012, Critical Link LLC
Specifications Subject to Change
Critical Link, LLC
www.criticallink.com
MitySOM
MitySOM-1810F Processor Card
5-MAR-2014
REVISION HISTORY
Date
23-FEB-2012
11-DEC-2012
5-MAR-2014
Change Description
Preliminary Draft, Updates and Release
Update Debug Header information, added MIL-STD-810F and
Up To notation for RAM and NAND
Update MitySOM product name.
12
Copyright © 2012, Critical Link LLC
Specifications Subject to Change
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