ALC662 Series
(ALC662-GR, ALC662-VC0-GR, ALC662-VC1-GR)
5.1 CHANNEL HIGH DEFINITION AUDIO CODEC
DATASHEET
Rev. 1.3
03 July 2009
Track ID: JATR-1076-21
Realtek Semiconductor Corp.
No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
ALC662 Series
Datasheet
COPYRIGHT
©2009 Realtek Semiconductor Corp. All rights reserved. No part of this document may be reproduced,
transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any
means without the written permission of Realtek Semiconductor Corp.
DISCLAIMER
Realtek provides this document “as is”, without warranty of any kind. Realtek may make improvements
and/or changes in this document or in the product described in this document at any time. This document
could include technical inaccuracies or typographical errors.
TRADEMARKS
Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document
are trademarks/registered trademarks of their respective owners.
USING THIS DOCUMENT
This document is intended for the hardware and software engineer’s general information on the Realtek
ALC662 codec IC.
Though every effort has been made to ensure that this document is current and accurate, more
information may have become available subsequent to the production of this guide.
REVISION HISTORY
Revision
1.0
1.1
Release Date
2007/01/15
2008/03/15
1.2
2008/12/02
1.3
2009/07/03
Summary
First release for ALC662.
Added ALC662-VC (ALC662 C version) data.
Update passband ripple information in Table 82, page 64.
Correct General Description and Software Features sections. The ALC662 supports
Dolby Digital Live (Dolby Home Theater is not supported).
ALC662-VC part number corrected to ALC662-VC0-GR.
Added ALC662-VC1-GR part number information.
Revised Table 85, page 66.
5.1 Channel High Definition Audio Codec
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ALC662 Series
Datasheet
Table of Contents
1.
GENERAL DESCRIPTION ..............................................................................................................................................1
2.
FEATURES .........................................................................................................................................................................2
2.1.
2.2.
2.3.
HARDWARE FEATURES ................................................................................................................................................2
SOFTWARE FEATURES ..................................................................................................................................................3
ALC662-VC SERIES UPGRADED FEATURES FOR FUTURE WLP ..................................................................................4
3.
SYSTEM APPLICATIONS...............................................................................................................................................4
4.
BLOCK DIAGRAM ...........................................................................................................................................................5
5.
PIN ASSIGNMENTS .........................................................................................................................................................6
5.1.
6.
PIN DESCRIPTIONS.........................................................................................................................................................7
6.1.
6.2.
6.3.
6.4.
6.5.
7.
PACKAGE AND VERSION IDENTIFICATION ....................................................................................................................6
DIGITAL I/O PINS .........................................................................................................................................................7
ANALOG I/O PINS ........................................................................................................................................................7
FILTER/REFERENCE......................................................................................................................................................8
POWER/GROUND ..........................................................................................................................................................8
NC (NOT CONNECTED) PINS ........................................................................................................................................8
HIGH DEFINITION AUDIO LINK PROTOCOL .........................................................................................................9
7.1.
LINK SIGNALS ..............................................................................................................................................................9
7.1.1. Signal Definitions .................................................................................................................................................10
7.1.2. Signaling Topology...............................................................................................................................................11
7.2.
FRAME COMPOSITION ................................................................................................................................................12
7.2.1. Outbound Frame – Single SDO............................................................................................................................12
7.2.2. Outbound Frame – Multiple SDOs.......................................................................................................................13
7.2.3. Inbound Frame – Single SDI ................................................................................................................................14
7.2.4. Inbound Frame – Multiple SDIs...........................................................................................................................15
7.2.5. Variable Sample Rates .........................................................................................................................................15
7.3.
RESET AND INITIALIZATION .......................................................................................................................................18
7.3.1. Link Reset .............................................................................................................................................................18
7.3.2. Codec Reset ..........................................................................................................................................................19
7.3.3. Codec Initialization Sequence ..............................................................................................................................20
7.4.
VERB AND RESPONSE FORMAT ..................................................................................................................................20
7.4.1. Command Verb Format........................................................................................................................................20
7.4.2. Response Format..................................................................................................................................................23
7.5.
POWER MANAGEMENT ...............................................................................................................................................23
7.5.1. System Power State Definitions............................................................................................................................23
7.5.2. Power Controls in NID 01h..................................................................................................................................24
7.5.3. Powered Down Conditions...................................................................................................................................24
8.
SUPPORTED VERBS AND PARAMETERS................................................................................................................25
8.1.
VERB – GET PARAMETERS (VERB ID=F00H).............................................................................................................25
8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................25
8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................25
8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h) .....................................................26
8.1.4. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h) ..........................................................26
8.1.5. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) ...............................................26
8.1.6. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h) ..................................................27
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8.1.7. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) ................................................28
8.1.8. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) .................................................29
8.1.9. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch) ..................................................................29
8.1.10.
Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) ..........................30
8.1.11.
Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h) ........................30
8.1.12.
Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) .......................................................31
8.1.13.
Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) .................................................31
8.1.14.
Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)..................................................31
8.1.15.
Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)..........................................................32
8.1.16.
Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)..............................................32
8.2.
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ................................................................................33
8.3.
VERB – SET CONNECTION SELECT (VERB ID=701H) .................................................................................................33
8.4.
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H) .........................................................................................34
8.5.
VERB – GET PROCESSING STATE (VERB ID=F03H) ...................................................................................................37
8.6.
VERB – SET PROCESSING STATE (VERB ID=703H) ....................................................................................................38
8.7.
VERB – GET COEFFICIENT INDEX (VERB ID=DH)......................................................................................................38
8.8.
VERB – SET COEFFICIENT INDEX (VERB ID=5H) .......................................................................................................38
8.9.
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH) ............................................................................................39
8.10.
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H)..............................................................................................39
8.11.
VERB – GET AMPLIFIER GAIN (VERB ID=BH) ...........................................................................................................40
8.12.
VERB – SET AMPLIFIER GAIN (VERB ID=3H) ............................................................................................................43
8.13.
VERB – GET CONVERTER FORMAT (VERB ID=AH)....................................................................................................44
8.14.
GET CONVERTER FORMAT SUPPORT ..........................................................................................................................44
8.15.
VERB – SET CONVERTER FORMAT (VERB ID=2H) .....................................................................................................45
8.16.
VERB – GET POWER STATE (VERB ID=F05H)............................................................................................................46
8.17.
VERB – SET POWER STATE (VERB ID=705H).............................................................................................................46
8.18.
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H) ...............................................................................47
8.19.
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ................................................................................47
8.20.
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H) ..............................................................................................48
8.21.
VERB – SET PIN WIDGET CONTROL (VERB ID=707H) ...............................................................................................49
8.22.
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H) ...........................................................................50
8.23.
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ............................................................................50
8.24.
VERB – GET PIN SENSE (VERB ID=F09H)..................................................................................................................51
8.25.
VERB – EXECUTE PIN SENSE (VERB ID=709H)..........................................................................................................51
8.26.
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH).........................................................52
8.27.
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3) 52
8.28.
VERB – GET BEEP GENERATOR (VERB ID=F0AH) ...................................................................................................53
8.29.
VERB – SET BEEP GENERATOR (VERB ID=70AH) ....................................................................................................53
8.30.
VERB – GET GPIO DATA (VERB ID= F15H) ..............................................................................................................54
8.31.
VERB – SET GPIO DATA (VERB ID= 715H)...............................................................................................................54
8.32.
VERB – GET GPIO ENABLE MASK (VERB ID=F16H).................................................................................................55
8.33.
VERB – SET GPIO ENABLE MASK (VERB ID=716H) .................................................................................................55
8.34.
VERB – GET GPIO DIRECTION (VERB ID=F17H).......................................................................................................56
8.35.
VERB – SET GPIO DIRECTION (VERB ID=717H) .......................................................................................................56
8.36.
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H).........................................................57
8.37.
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H)..........................................................57
8.38.
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH)..........................................58
8.39.
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH)............................................59
8.40.
VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/D22H/F23H) ..................................................................60
8.41.
VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0])..........................................................................................................................................................................60
8.42.
VERB – GET EAPD CONTROL (VERB ID=F0CH) .......................................................................................................61
8.43.
VERB – SET EAPD CONTROL (VERB ID=70CH)........................................................................................................61
8.44.
VERB – FUNCTION RESET (VERB ID=7FFH) ..............................................................................................................62
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9.
ELECTRICAL CHARACTERISTICS ..........................................................................................................................63
9.1.
DC CHARACTERISTICS ...............................................................................................................................................63
9.1.1. Absolute Maximum Ratings ..................................................................................................................................63
9.1.2. Threshold Voltage ................................................................................................................................................63
9.1.3. Digital Filter Characteristics ...............................................................................................................................64
9.1.4. SPDIF Output Characteristics .............................................................................................................................64
9.2.
AC CHARACTERISTICS ...............................................................................................................................................65
9.2.1. Link Reset and Initialization Timing ....................................................................................................................65
9.2.2. Link Timing Parameters at the Codec ..................................................................................................................66
9.2.3. SPDIF Output Timing...........................................................................................................................................67
9.2.4. Test Mode .............................................................................................................................................................67
9.3.
ANALOG PERFORMANCE ............................................................................................................................................68
10.
10.1.
10.2.
10.3.
10.4.
11.
11.1.
12.
APPLICATION CIRCUITS .......................................................................................................................................69
FILTER CONNECTION .................................................................................................................................................69
ONBOARD FRONT PANEL HEADER CONNECTION AND FRONT PANEL I/O ..................................................................70
ANALOG INPUT/OUTPUT CONNECTION ......................................................................................................................71
OPTIONAL SPDIF OUTPUT .........................................................................................................................................71
MECHANICAL DIMENSIONS.................................................................................................................................72
MECHANICAL DIMENSIONS NOTES ............................................................................................................................73
ORDERING INFORMATION ...................................................................................................................................74
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Datasheet
List of Tables
TABLE 1.
TABLE 2.
TABLE 3.
TABLE 4.
TABLE 5.
TABLE 6.
TABLE 7.
TABLE 8.
TABLE 9.
TABLE 10.
TABLE 11.
TABLE 12.
TABLE 13.
TABLE 14.
TABLE 15.
TABLE 16.
TABLE 17.
TABLE 18.
TABLE 19.
TABLE 20.
TABLE 21.
TABLE 22.
TABLE 23.
TABLE 24.
TABLE 25.
TABLE 26.
TABLE 27.
TABLE 28.
TABLE 29.
TABLE 30.
TABLE 31.
TABLE 32.
TABLE 33.
TABLE 34.
TABLE 35.
TABLE 36.
TABLE 37.
TABLE 38.
TABLE 39.
TABLE 40.
TABLE 41.
TABLE 42.
TABLE 43.
TABLE 44.
TABLE 45.
TABLE 46.
TABLE 47.
TABLE 48.
TABLE 49.
TABLE 50.
TABLE 51.
TABLE 52.
DIGITAL I/O PINS .........................................................................................................................................................7
ANALOG I/O PINS ........................................................................................................................................................7
FILTER/REFERENCE .....................................................................................................................................................8
POWER/GROUND..........................................................................................................................................................8
NOT CONNECTED PINS .................................................................................................................................................8
LINK RESET# ...........................................................................................................................................................10
HDA SIGNAL DEFINITIONS ........................................................................................................................................10
DEFINED SAMPLE RATE AND TRANSMISSION RATE ...................................................................................................16
48KHZ VARIABLE RATE OF DELIVERY TIMING .........................................................................................................16
44.1KHZ VARIABLE RATE OF DELIVERY TIMING ......................................................................................................17
40-BIT COMMANDS IN 4-BIT VERB FORMAT .............................................................................................................20
40-BIT COMMANDS IN 12-BIT VERB FORMAT ...........................................................................................................20
SUPPORTED COMMANDS ...........................................................................................................................................21
SUPPORTED PARAMETERS .........................................................................................................................................22
SOLICITED RESPONSE FORMAT .................................................................................................................................23
UNSOLICITED RESPONSE FORMAT .............................................................................................................................23
SYSTEM POWER STATE DEFINITIONS ........................................................................................................................23
POWER CONTROLS IN NID 01H .................................................................................................................................24
POWERED DOWN CONDITIONS ..................................................................................................................................24
VERB – GET PARAMETERS (VERB ID=F00H) ............................................................................................................25
PARAMETER – VENDOR ID (VERB ID=F00H, PARAMETER ID=00H).........................................................................25
PARAMETER – REVISION ID (VERB ID=F00H, PARAMETER ID=02H) .......................................................................25
PARAMETER – SUBORDINATE NODE COUNT (VERB ID=F00H, PARAMETER ID=04H) ..............................................26
PARAMETER – FUNCTION GROUP TYPE (VERB ID=F00H, PARAMETER ID=05H)......................................................26
PARAMETER – AUDIO FUNCTION CAPABILITIES (VERB ID=F00H, PARAMETER ID=08H).........................................26
PARAMETER – AUDIO WIDGET CAPABILITIES (VERB ID=F00H, PARAMETER ID=09H) ............................................27
PARAMETER – SUPPORTED PCM SIZE, RATES (VERB ID=F00H, PARAMETER ID=0AH)...........................................28
PARAMETER – SUPPORTED STREAM FORMATS (VERB ID=F00H, PARAMETER ID=0BH) ..........................................29
PARAMETER – PIN CAPABILITIES (VERB ID=F00H, PARAMETER ID=0CH)...............................................................29
PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, INPUT AMPLIFIER PARAMETER ID=0DH) ......................30
PARAMETER – AMPLIFIER CAPABILITIES (VERB ID=F00H, OUTPUT AMPLIFIER PARAMETER ID=12H)....................30
PARAMETER – CONNECT LIST LENGTH (VERB ID=F00H, PARAMETER ID=0EH)......................................................31
PARAMETER – SUPPORTED POWER STATES (VERB ID=F00H, PARAMETER ID=0FH)................................................31
PARAMETER – PROCESSING CAPABILITIES (VERB ID=F00H, PARAMETER ID=10H) .................................................31
PARAMETER – GPIO CAPABILITIES (VERB ID=F00H, PARAMETER ID=11H)............................................................32
PARAMETER – VOLUME KNOB CAPABILITIES (VERB ID=F00H, PARAMETER ID=13H) ............................................32
VERB – GET CONNECTION SELECT CONTROL (VERB ID=F01H) ...............................................................................33
VERB – SET CONNECTION SELECT (VERB ID=701H).................................................................................................33
VERB – GET CONNECTION LIST ENTRY (VERB ID=F02H).........................................................................................34
VERB – GET PROCESSING STATE (VERB ID=F03H)...................................................................................................37
VERB – SET PROCESSING STATE (VERB ID=703H)....................................................................................................38
VERB – GET COEFFICIENT INDEX (VERB ID=DH) .....................................................................................................38
VERB – SET COEFFICIENT INDEX (VERB ID=5H).......................................................................................................38
VERB – GET PROCESSING COEFFICIENT (VERB ID=CH)............................................................................................39
VERB – SET PROCESSING COEFFICIENT (VERB ID=4H) .............................................................................................39
VERB – GET AMPLIFIER GAIN (VERB ID=BH)...........................................................................................................40
VERB – SET AMPLIFIER GAIN (VERB ID=3H)............................................................................................................43
VERB – GET CONVERTER FORMAT (VERB ID=AH) ...................................................................................................44
GET CONVERTER FORMAT SUPPORT .........................................................................................................................44
VERB – SET CONVERTER FORMAT (VERB ID=2H).....................................................................................................45
VERB – GET POWER STATE (VERB ID=F05H) ...........................................................................................................46
VERB – SET POWER STATE (VERB ID=705H)............................................................................................................46
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TABLE 53.
TABLE 54.
TABLE 55.
TABLE 56.
TABLE 57.
TABLE 58.
TABLE 59.
TABLE 60.
TABLE 61.
TABLE 62.
TABLE 63.
TABLE 64.
TABLE 65.
TABLE 66.
TABLE 67.
TABLE 68.
TABLE 69.
TABLE 70.
TABLE 71.
TABLE 72.
TABLE 73.
TABLE 74.
TABLE 75.
TABLE 76.
TABLE 77.
TABLE 78.
TABLE 79.
TABLE 80.
TABLE 81.
TABLE 82.
TABLE 83.
TABLE 84.
TABLE 85.
TABLE 86.
TABLE 87.
TABLE 88.
VERB – GET CONVERTER STREAM, CHANNEL (VERB ID=F06H)...............................................................................47
VERB – SET CONVERTER STREAM, CHANNEL (VERB ID=706H) ...............................................................................47
VERB – GET PIN WIDGET CONTROL (VERB ID=F07H)..............................................................................................48
VERB – SET PIN WIDGET CONTROL (VERB ID=707H)...............................................................................................49
VERB – GET UNSOLICITED RESPONSE CONTROL (VERB ID=F08H)...........................................................................50
VERB – SET UNSOLICITED RESPONSE CONTROL (VERB ID=708H) ...........................................................................50
VERB – GET PIN SENSE (VERB ID=F09H) .................................................................................................................51
VERB – EXECUTE PIN SENSE (VERB ID=709H) .........................................................................................................51
VERB – GET CONFIGURATION DEFAULT (VERB ID=F1CH/F1DH/F1EH/F1FH) ........................................................52
VERB – SET CONFIGURATION DEFAULT BYTES 0, 1, 2, 3 (VERB ID=71CH/71DH/71EH/71FH FOR BYTES 0, 1, 2, 3)
..................................................................................................................................................................................52
VERB – GET BEEP GENERATOR (VERB ID= F0AH)..................................................................................................53
VERB – SET BEEP GENERATOR (VERB ID= 70AH)...................................................................................................53
VERB – GET GPIO DATA (VERB ID= F15H) .............................................................................................................54
VERB – SET GPIO DATA (VERB ID= 715H) ..............................................................................................................54
VERB – GET GPIO ENABLE MASK (VERB ID= F16H) ...............................................................................................55
VERB – SET GPIO ENABLE MASK (VERB ID=716H).................................................................................................55
VERB – GET GPIO DIRECTION (VERB ID=F17H) ......................................................................................................56
VERB – SET GPIO DIRECTION (VERB ID=717H).......................................................................................................56
VERB – GET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=F19H) ........................................................57
VERB – SET GPIO UNSOLICITED RESPONSE ENABLE MASK (VERB ID=719H) .........................................................57
VERB – GET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID= F0DH, F0EH) .........................................58
VERB – SET DIGITAL CONVERTER CONTROL 1 & CONTROL 2 (VERB ID=70DH, 70EH) ...........................................59
VERB – GET SUBSYSTEM ID [31:0] (VERB ID=F20H/F21H/F22H/F23H) ..................................................................60
VERB – SET SUBSYSTEM ID [31:0] (VERB ID=723H FOR [31:24], 722H FOR [23:16], 721H FOR [15:8], 720H FOR
[7:0]) .........................................................................................................................................................................60
VERB – GET EAPD CONTROL (VERB ID=F0CH) ......................................................................................................61
VERB – SET EAPD CONTROL (VERB ID=70CH) .......................................................................................................61
VERB – FUNCTION RESET (VERB ID=7FFH) .............................................................................................................62
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................63
THRESHOLD VOLTAGE ..............................................................................................................................................63
DIGITAL FILTER CHARACTERISTICS ..........................................................................................................................64
SPDIF OUTPUT CHARACTERISTICS ...........................................................................................................................64
LINK RESET AND INITIALIZATION TIMING .................................................................................................................65
LINK TIMING PARAMETERS AT THE CODEC ...............................................................................................................66
SPDIF OUTPUT TIMING.............................................................................................................................................67
ANALOG PERFORMANCE ...........................................................................................................................................68
ORDERING INFORMATION ..........................................................................................................................................74
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Datasheet
List of Figures
FIGURE 1.
FIGURE 2.
FIGURE 3.
FIGURE 4.
FIGURE 5.
FIGURE 6.
FIGURE 7.
FIGURE 8.
FIGURE 9.
FIGURE 10.
FIGURE 11.
FIGURE 12.
FIGURE 13.
FIGURE 14.
FIGURE 15.
FIGURE 16.
FIGURE 17.
FIGURE 18.
FIGURE 19.
FIGURE 20.
BLOCK DIAGRAM .......................................................................................................................................................5
PIN ASSIGNMENTS ......................................................................................................................................................6
HDA LINK PROTOCOL ................................................................................................................................................9
BIT TIMING ...............................................................................................................................................................10
SIGNALING TOPOLOGY .............................................................................................................................................11
SDO OUTBOUND FRAME ..........................................................................................................................................12
SDO STREAM TAG IS INDICATED IN SYNC..............................................................................................................12
STRIPED STREAM ON MULTIPLE SDOS .....................................................................................................................13
SDI INBOUND STREAM .............................................................................................................................................14
SDI STREAM TAG AND DATA ..................................................................................................................................14
CODEC TRANSMITS DATA OVER MULTIPLE SDIS ....................................................................................................15
LINK RESET TIMING .................................................................................................................................................19
CODEC INITIALIZATION SEQUENCE ..........................................................................................................................20
LINK RESET AND INITIALIZATION TIMING ................................................................................................................65
LINK SIGNAL TIMING ...............................................................................................................................................66
OUTPUT TIMING .......................................................................................................................................................67
FILTER CONNECTION ................................................................................................................................................69
ONBOARD FRONT PANEL HEADER CONNECTION AND FRONT PANEL I/O ................................................................70
ANALOG INPUT/OUTPUT CONNECTION ....................................................................................................................71
OPTIONAL SPDIF OUTPUT .......................................................................................................................................71
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Datasheet
1.
General Description
ALC662 products are 5.1 Channel High Definition Audio Codecs designed for Windows Vista premium
desktop and mobile PCs. The ALC662, ALC662-VC0, and ALC662-VC1 (ALC662 version C series)
meet audio performance and function requirements for the latest Microsoft WLP3.10 (Windows Logo
Program).
The ALC662-VC series (ALC662-VC0 and ALC662-VC1) are upgraded versions of the ALC662 that
pass stricter WLP performance requirements (See section 2.3 ALC662-VC Series Upgraded Features for
Future WLP, page 4).
The ALC662 series feature three stereo DACs, two stereo ADCs, and legacy analog input to analog
output mixing, to provide fully integrated audio solutions for multimedia PCs and ultra mobile devices.
All analog IO (except CD-IN and PCBEEP) are input and output capable, and three headphone amplifiers
are also integrated to drive earphones on front (port-E and port-F) and rear panel (port-D).
The ALC662 series support 16/20/24-bit SPDIF output function and a sampling rate of up to 96kHz.
They offer easy connection of PCs to high quality consumer electronic products such as digital decoders
and speakers.
The ALC662 series support host audio from Intel chipsets, and also from any other HDA compatible
audio controller. With EAX/Direct Sound 3D/I3DL2 compatibility, software utilities like Karaoke mode,
environment emulation, multi-band software equalizer, 3D positional audio, and optional Dolby® Digital
Live and DTS® CONNECT™ programs, the ALC662 series provide an excellent home entertainment
package and game experience for PC users.
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Datasheet
2.
Features
2.1.
Hardware Features
Meets premium audio requirements for Microsoft WLP 3.10 (ALC662 and ALC662-VC series)
Meets stricter performance requirements for future WLP (ALC662-VC series)
Six-channel DAC supports 16/20/24-bit PCM format for 5.1 channel audio solution
Two stereo ADCs support 16/20-bit PCM format
All DACs support independent 44.1k/48k/96kHz sample rate
All ADCs support independent 44.1k/48k/96kHz sample rate
Supports 44.1k/48k/96kHz SPDIF output
All analog jack ports are stereo input and output re-tasking
Analog differential CD input
Supports analog PCBEEP input
Integrates digital BEEP generator
Up to four channels of microphone array input are supported for AEC/BF application
Supports legacy analog input to analog output mixer
Three built-in headphone amplifiers for port-D (rear panel), port-E and port-F (front panel)
Software selectable 2.5V and 3.2V reference output for microphone bias
Software selectable boost gain (+10/+20/+30dB) for analog microphone input
Two jack detection pins: each supports detection of up to 4 jacks
Jack detection function is supported when device is in power down mode (D3)
Supports two GPIO pins (General Purpose Input Output)
Supports EAPD (External Amplifier Power Down) control for external amplifier
Supports 1.5V~3.3V scalable I/O for HD Audio link
Supports anti-pop mode when analog power AVDD is on and digital power is off
48-pin LQFP ‘Green’ package
The ALC662-VC series is fully pin compatible with the ALC662, and both are pin-to-pin compatible
with the ALC88x series and ALC262 series audio codecs
5.1 Channel High Definition Audio Codec
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Datasheet
2.2.
Software Features
Meets Microsoft WLP 3.10 and future WLP audio requirements
WaveRT based audio function driver and logo ready for Windows Vista
EAX™ 1.0 & 2.0 compatible
Direct Sound 3D™ compatible
I3DL2 compatible (Windows XP only)
3D Positional Audio
Emulation of 26 sound environments to enhance gaming experience
Multi-band software equalizer and software tools are provided
Voice Cancellation and Key Shifting effects
Dynamic range control (expander, compressor, and limiter) with adjustable parameters
Intuitive Configuration Panel (Realtek Audio Manager) for enhanced audio experience
Provides 10-foot GUI for Windows Media Center
Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF)
technology for voice application
Smart multiple streaming operation
Dolby® Digital Live (optional software feature)
DTS® CONNECT™ (optional software feature)
SRS® TruSurround HD (optional software feature)
5.1 Channel High Definition Audio Codec
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Datasheet
2.3.
ALC662-VC Series Upgraded Features for Future WLP
DAC and ADC keep good THD+N when tested with –1dB test signal (-3dB in WLP3.10)
DAC and ADC have less than ±0.02dB frequency response ripple (=100 usec
>= 4 BCLK
Initialization Sequence
BCLK
Normal Frame
SYNC is absent
SYNC
Driven Low
Pulled Low
SDOs
Driven Low
Pulled Low
SDIs
Driven Low
Pulled Low
Normal Frame
SYNC
2
8
Wake Event
9
RST#
Pulled Low
1
3
4
5
6
7
Figure 12. Link Reset Timing
7.3.2.
Codec Reset
A ‘Codec Reset’ is initiated via the Codec RESET command verb. It results in the target codec being
reset to the default state. After the target codec completes its reset operation, an initialization sequence is
requested.
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Datasheet
7.3.3.
Codec Initialization Sequence
n The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the
controller
o The codec stops driving the SDI during this turnaround period
pqrs The controller drives SDI to assign a CAD to the codec
t The controller releases the SDI after the CAD has been assigned
u Normal operating state
Figure 13. Codec Initialization Sequence
7.4.
Verb and Response Format
7.4.1.
Command Verb Format
There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with
12-bit identifiers (12-bit verbs) and 8-bits of data. Table 11 shows the 4-bit verb structure of a command
stream sent from the controller to operate the codec. Table 12 is the 12-bit verb structure that gets and
controls parameters in the codec.
Bit [39:32]
Reserved
Table 11. 40-Bit Commands in 4-Bit Verb Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Codec Address
Node ID
Verb ID
Bit [15:0]
Payload
Bit [39:32]
Reserved
Table 12. 40-Bit Commands in 12-Bit Verb Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Codec Address
Node ID
Verb ID
Bit [7:0]
Payload
5.1 Channel High Definition Audio Codec
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Datasheet
5.1 Channel High Definition Audio Codec
21
Power Widget*1
Volume Knob
Beep Generator
Vendor Defined Widget
Sum Widget
Pin Widget
Audio In Converter
Audio Out Converter
F00
Y
Y
Y
Y
Y
Y
F01 701
Y
Y
F02
Y
Y
Y
F03 703
D-- 5-C-- 4-B-- 3-Y
Y
Y
A-- 2-Y
Y
F0D 70D Y
Y
F0D 70E
Y
Y
F05 705
Y
F06 706
Y
Y
F04 704
F07 707
Y
F08 708
Y
F09 709
Y
F0C 70C F10- 710- F1A 71A
Beep Generator Control
F0A 70A Volume Knob Control
F0F 70F
Subsystem ID, Byte 0
F20 720
Y
Subsystem ID, Byte 1
F20 721
Y
Subsystem ID, Byte 2
F20 722
Y
Subsystem ID, Byte 3
F20 723
Y
Config Default, Byte 0
F1C 71C Y
Config Default, Byte 1
F1C 71D Y
Config Default, Byte 2
F1C 71E
Y
Config Default, Byte 3
F1C 71F
Y
RESET
7FF
Y
*1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.
Selector Widget
Get parameter
Connection Select
Get Connection List Entry
Processing State
Coefficient Index
Processing Coefficient
Amplifier Gain/Mute
Stream Format
Digital Converter 1
Digital Converter 2
Power State
Channel / Stream ID
SDI Select
Pin Widget Control
Unsolicited Enable
Pin Sense
EAPD / BTL Enable
All GPIO Control
Vendor Defined Group*1
HDMI Function Group*1
Modem Function Group*1
Audio Function Group
Root Node
Set Verb
Supported Verb
Get Verb
Table 13. Supported Commands
Y
Y
Y
-
-
Y
Y
-
Y
-
Y
Y
Y
-
-
-
-
Y
-
-
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Rev. 1.3
ALC662 Series
Datasheet
5.1 Channel High Definition Audio Codec
22
Power Widget*1
Volume Knob
Beep Generator
Vendor Defined Widget
Vendor ID
00
Y
Revision ID
02
Y
Subordinate Node Count
04
Y
Y
Function Group Type
05
Y
08
Y
Audio Function Group
Capabilities
Audio Widget Capabilities
09
Y
Y
Y
Y
Sample Size, Rate
0A
Y
Y
Y
Stream Formats
0B
Y
Y
Y
Pin Capabilities
0C
Y
Input Amp Capabilities
0D
Y
Y
Output Amp Capabilities
12
Y
Y
Connection List Length
0E
Y
Y
Y
Supported Power States
0F
Y
Y
Y
Y
Y
Processing Capabilities
10
GPI/O Count
11
Volume Knob Capabilities
13
*1: The ALC662 does not support Modem/HDMI/Vendor groups and Power State widgets.
Selector Widget
Sum Widget
Pin Widget
Audio In Converter
Audio Out Converter
Vendor Defined Group*1
HDMI Function Group*1
Modem Function Group*1
Audio Function Group
Root Node
Supported Parameter
Parameter ID
Table 14. Supported Parameters
-
-
-
-
-
Y
Y
Y
Y
-
-
Y
-
Y
-
Y
Y
Y
-
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ALC662 Series
Datasheet
7.4.2.
Response Format
There are two types of response from the codec to the controller. Solicited Responses are returned by the
codec in response to a current command verb. The codec will send Solicited Response data in the next
frame, without regard to the Set (Write) or Get (Read) command. The 32-bit response is interpreted by
software, opaque to the controller.
Unsolicited Responses are sent by the codec independently of software requests. Jack Detection or GPI
status information can be actively delivered to the controller and interpreted by software. The ‘Tag’ in
Bit[31:28] is used to identify unsolicited events. This tag is undefined in the HDA specifications.
Bit [35]
Valid
Bit [35]
Valid
7.5.
Table 15. Solicited Response Format
Bit [34]
Bit [33:32]
Unsol=0
Reserved
Bit [31:0]
Response
Table 16. Unsolicited Response Format
Bit [34]
Bit [33:32]
Bit [31:28]
Unsol=1
Reserved
Tag
Bit [27:0]
Response
Power Management
The ALC662 does not support Wake-Up events when in low-power mode. All power management state
changes in widgets are driven by software. Table 17 shows the System Power State Definitions. Table 18
indicates those nodes that support power management. To simplify power control, software can configure
whole codec power states through the audio function (NID=01h). Output converters (DACs) and input
converters (ADCs) have no individual power control to supply fine-grained power control.
7.5.1.
System Power State Definitions
Power States
D0
D1
D2
D3 (Hot)
D3 (Cold)
Table 17. System Power State Definitions
Definitions
All power on. Individual DACs and ADCs can be powered up or down as required.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, analog
reference stays up.
All amplifiers and converters (DACs and ADCs) are powered down. State maintained, but
analog reference is off (D1 + analog reference off).
Power still supplied. The codec stops the internal clock. State is maintained.
All power removed. State lost.
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Datasheet
7.5.2.
Power Controls in NID 01h
Table 18. Power Controls in NID 01h
Description
D0
D1
D2
LINK Response
Normal
Normal
Normal
Front DAC (Node 02h)
Normal
PD
PD
Surr DAC (Node 03h)
Normal
PD
PD
Cen/LFE DAC (Node 04h)
Normal
PD
PD
ADC (Node 08h)
Normal
PD
PD
ADC (Node 09h)
Normal
PD
PD
All Headphone Drivers
Normal
Normal
PD
All Mixers
Normal
Normal
PD
All Reference
Normal
Normal
PD
Note: PD=Powered Down.
Item
Audio Function
(NID=01h)
7.5.3.
D3
PD
PD
PD
PD
PD
PD
PD
PD
PD
Link Reset
PD
PD
PD
PD
PD
PD
Normal
Normal
Normal
Powered Down Conditions
Condition
LINK Response powered down
Front DAC powered down
Surr DAC powered down
CEN/LFE DAC powered down
ADC 08h powered down
ADC 09h powered down
Headphone Driver powered down
Mixers powered down
References powered down
Table 19. Powered Down Conditions
Description
Internal clock is stopped. SDATA-IN and SPDIF-OUT are floated with pulled
low 47K resistors internally. SPDIF-IN is also floated. Detection of ‘Link
Reset Entry’ and ‘Link Reset Exit’ sequences are supported. All states are
maintained if DVDD is supplied
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
Analog block and digital filter are powered down. Data on SDATA-IN is quiet
All headphone drivers are powered down
All internal mixer widgets are powered down. The DC reference and
VREFOUTx at individual pin complexes are still alive
All internal references, DC reference, and VREFOUTx at individual pin
complexes are off
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Datasheet
8.
Supported Verbs and Parameters
This section describes the Verbs and Parameters supported by various widgets in the ALC662. If a verb is
not supported by the addressed widget, it will respond with 32 bits of ‘0’.
8.1.
Verb – Get Parameters (Verb ID=F00h)
The ‘Get Parameters’ verb is used to get system information and the function capabilities of the HDA
codec. All the parameters are read-only. There are a total of 15 ID parameters defined for each widget.
Some parameters are supported only in a specific widget. Refer to section 7.4.1 Command Verb Format,
page 20, to get detailed information about supported parameters.
Table 20. Verb – Get Parameters (Verb ID=F00h)
Get Parameter Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=00h
Verb ID=F00h
Parameter ID[7:0]
32-bit Response
Note: If the parameter ID is not supported, the returned response is 32 bits of ‘0’.
8.1.1.
Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Table 21. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)
Codec Response Format
Bit
Description
31:16
Vendor ID=10ECh (Realtek’s PCI vendor ID).
15:0
Device ID=0662h.
Note: The Root Node (NID=00h) supports this parameter.
8.1.2.
Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Table 22. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)
Codec Response Format
Bit
Description
31:24
Reserved. Read as 0’s.
23:20
MajRev=1h. The major version number (in decimal) of the HDA Specification.
19:16
MinRev=0h. The minor version number (in decimal) of the HDA Specification.
15:8
Revision ID. The vendor’s revision number.
Note: 01h indicates ALC662 silicon.
7:0
Stepping ID. The vendor’s stepping number within the given Revision ID.
Note: The Root Node (NID=00h) supports this parameter.
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Datasheet
8.1.3.
Parameter – Subordinate Node Count
(Verb ID=F00h, Parameter ID=04h)
For the root node, the Subordinate Node Count provides information about audio function group nodes
associated with the root node.
For function group nodes, it provides the total number of widgets associated with this function node.
Table 23. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ID=04h)
Codec Response Format
Bit
Description
31:24
Reserved. Read as 0’s.
23:16
Starting Node Number. The starting node number in the sequential widgets.
15:8
Reserved. Read as 0’s.
7:0
Total Number of Nodes. For a root node, this is the total number of function groups in the root node.
For a function group, this is the total number of widget nodes in the function group.
8.1.4.
Parameter – Function Group Type
(Verb ID=F00h, Parameter ID=05h)
Table 24. Parameter – Function Group Type (Verb ID=F00h, Parameter ID=05h)
Codec Response Format
Bit
Description
31:9
Reserved. Read as 0’s.
8
UnSol Capable.
0: Unsolicited response is not supported by this function group
1: Unsolicited response is supported by this function group
7:0
Function Group Type.
00h: Reserved
01h: Audio Function
02h: Modem Function
03h~7Fh: Reserved
80h~FFh: Vendor Defined Function
8.1.5.
Parameter – Audio Function Capabilities
(Verb ID=F00h, Parameter ID=08h)
Table 25. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h)
Codec Response Format
Bit
Description
31:17
Reserved. Read as 0’s.
16
Beep Generator.
A ‘1’ indicates the presence of an integrated Beep generator within the Audio Function Group.
15:12
Reserved. Read as 0’s.
11:8
Input Delay. Number of samples delay from analog input to HDA link.
7:4
Reserved. Read as 0’s.
3:0
Output Delay. Number of samples delay from HDA link to analog output.
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Datasheet
8.1.6.
Parameter – Audio Widget Capabilities
(Verb ID=F00h, Parameter ID=09h)
Table 26. Parameter – Audio Widget Capabilities (Verb ID=F00h, Parameter ID=09h)
Codec Response Format
Bit
Description
31:24
Reserved. Read as 0’s.
23:20
Widget Type.
0h: Audio Output
1h: Audio Input
2h: Mixer
3h: Selector
4h: Pin Complex
5h: Power Widget
6h: Volume Knob Widget
7h~Eh: Reserved
Fh: Vendor defined audio widget
19:16
Delay. Samples delayed between the HDA link and widgets.
15:12
Reserved. Read as 0’s.
11:
L-R Swap.
0: Left channel and right channel swapping is not supported
1: Left channel and right channel swapping is supported
10
Power Control.
0: Power control is not supported on this widget
1: Power control is supported on this widget
9
Digital.
0: An analog input or output converter
1: A widget translating digital data between the HDA link and digital I/O (SPDIF, I2S, etc.)
8
ConnList. Connection List.
0: Connected to HDA link. No Connection List Entry will be queried
1: Connection List Entry must be queried
7
UnsolCap. Unsolicited Capable.
0: Unsolicited response is not supported
1: Unsolicited response is supported
6
ProcWidget. Processing Widget.
0: No processing control
1: Processing control is supported
5
Reserved. Read as 0.
4
Format Override.
Note: The ALC662 supports 16/20/24-bit with 44.1kHz, 48kHz, and 96kHz sample rate. The format
(parameter ID=0Ah) must be queried
3
AmpParOvr (AMP Param Override).
Override amplifier parameters (Gain Control) in individual output Pin Complexes, ADCs, and Mixer
widgets.
2
OutAmpPre (Out AMP Present).
There are amplifiers (Mute Control) in individual output Pin Complexes.
1
InAmpPre (In AMP Present).
There are amplifiers (Gain Control) in individual ADCs and Mixer widgets.
0
Stereo.
0: Mono Widget
1: Stereo Widget
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Datasheet
8.1.7.
Parameter – Supported PCM Size, Rates
(Verb ID=F00h, Parameter ID=0Ah)
Parameters in audio functions provide default information about formats. Individual converters have their
own parameters to provide supported formats if their ‘Format Override’ bit is set.
Table 27. Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah)
Codec Response Format
Bit
Description
31:21
Reserved. Read as 0’s.
20
B32. 32-bit audio format support.
0: Not supported
1: Supported
19
B24. 24-bit audio format support.
0: Not supported
1: Supported (The ALC662 DAC supports this format)
18
B20. 20-bit audio format support.
0: Not supported
1: Supported (The ALC662 DAC supports this format)
17
B16. 16-bit audio format support.
0: Not supported
1: Supported (The ALC662 DAC supports this format)
16
B8. 8-bit audio format support.
0: Not supported
1: Supported
15:12
Reserved. Read as 0’s.
11
R12. 384kHz (=8*48kHz) rate support.
0: Not supported
1: Supported
10
R11. 192kHz (=4*48kHz) rate support.
0: Not supported
1: Supported
9
R10. 176.4Hz (=4*44.1kHz) rate support.
0: Not supported
1: Supported
8
R9. 96kHz (=2*48kHz) rate support.
0: Not supported
1: Supported (The ALC662 DAC and ADC support this sample rate)
7
R8. 88.2kHz (=2*44.1kHz) rate support.
0: Not supported
1: Supported
6
R7. 48kHz rate support.
0: Not supported
1: Supported (The ALC662 DAC and ADC support this sample rate)
5
R6. 44.1kHz rate support.
0: Not supported
1: Supported (The ALC662 DAC and ADC support this sample rate)
4
R5. 32kHz (=2/3*48kHz) rate support.
0: Not supported
1: Supported
3
R4. 22.05kHz (=1/2*44.1kHz) rate support.
0: Not supported
1: Supported
2
R3. 16kHz (=1/3*48kHz) rate support.
0: Not supported
1: Supported
1
R2. 11.025kHz (=1/4*44.1kHz) rate support.
0: Not supported
1: Supported
0
R1. 8kHz (=1/6*48kHz) rate support.
0: Not supported
1: Supported
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Datasheet
8.1.8.
Parameter – Supported Stream Formats
(Verb ID=F00h, Parameter ID=0Bh)
Parameters in this node only provide default information for audio function groups. Individual converters
have their own parameters to provide supported formats if the ‘Format Override’ bit is set.
Table 28. Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh)
Codec Response Format
Bit
Description
31:3
Reserved. Read as 0’s.
2
AC3.
0: Not supported
1: Supported
1
Float32.
0: Not supported
1: Supported
0
PCM.
0: Not supported
1: Supported (The ALC662 DAC and ADC support this format)
Note: Input converters and output converters support this parameter.
8.1.9.
Parameter – Pin Capabilities
(Verb ID=F00h, Parameter ID=0Ch)
The Pin Capabilities parameter returns a bit field describing the capabilities of the Pin Complex widget.
Table 29. Parameter – Pin Capabilities (Verb ID=F00h, Parameter ID=0Ch)
Codec Response Format
Bit
Description
31:16
Reserved. Read as 0’s.
15:8
VREF Control Capability.
‘1’ in corresponding bit field indicates signal levels of associated Vrefout are specified as a percentage of
AVDD.
7:6
5
4
3
2
1
0
Reserved
100%
80%
Reserved
Ground
50%
Hi-Z
7
6
5
4
3
2
1
0
Reserved.
Balanced I/O Pin. ‘1’ indicates this pin complex has balanced pins.
Input Capable. ‘1’ indicates this pin complex supports input.
Output Capable. ‘1’ indicates this pin complex supports output.
Headphone Drive Capable. ‘1’ indicates this pin complex has an amplifier to drive a headphone.
Presence Detect Capable. ‘1’ indicates this pin complex can detect whether there is a device plugged in.
Trigger Required. ‘1’ indicates whether a software trigger is required for an impedance measurement.
Impedance Sense Capable.
‘1’ indicates this pin complex can perform analog sensing on the attached device to determine its type.
Note: Only Pin Complex widgets support this parameter.
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Datasheet
8.1.10.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 30. Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh)
Codec Response Format
Bit
Description
31
(Input) Mute Capable.
30:23
Reserved. Read as 0.
22:16
Step Size.
Indicates the size of each step in the gain range.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
7
Reserved. Read as 0.
6:0
Offset.
Indicates which step is 0dB.
8.1.11.
Parameter – Amplifier Capabilities
(Verb ID=F00h, Output Amplifier Parameter ID=12h)
Parameters in this node provide audio function group default information. Individual converters have
their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set.
Table 31. Parameter – Amplifier Capabilities (Verb ID=F00h, Output Amplifier Parameter ID=12h)
Codec Response Format
Bit
Description
31
(Output) Mute Capable.
30:23
Reserved. Read as 0.
22:16
Step Size.
Indicates the size of each step in the gain range. Each individual step may be 0~32dB, specified in 0.25dB
steps. ‘0’ indicates 0.25dB steps. ‘127’ indicates 32dB steps.
15
Reserved. Read as 0.
14:8
Number of Steps.
Indicates the number of steps in the gain range. ‘0’ means the gain is fixed.
7
Reserved. Read as 0.
6:0
Offset. Indicates which step is 0dB.
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Datasheet
8.1.12.
Parameter – Connect List Length
(Verb ID=F00h, Parameter ID=0Eh)
Parameters in this node provide audio function widget connection information.
Table 32. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh)
Codec Response Format
Bit
Description
31:8
Reserved. Read as 0.
7
Short Form.
0: Short Form
1: Long Form
6:0
Connect List Length.
Indicates the number of inputs connected to a widget. If the Connect List Length is 1, there is only one
input, and there is no Connection Select Control (not a MUX widget).
8.1.13.
Parameter – Supported Power States
(Verb ID=F00h, Parameter ID=0Fh)
Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh)
Codec Response Format
Bit
Description
31:4
Reserved. Read as 0’s.
3
D3Sup.
1: Power state D3 is supported
2
D2Sup.
1: Power state D2 is supported
1
D1Sup.
1: Power state D1 is supported
0
D0Sup.
1: Power state D0 is supported
8.1.14.
Parameter – Processing Capabilities
(Verb ID=F00h, Parameter ID=10h)
Table 34. Parameter – Processing Capabilities (Verb ID=F00h, Parameter ID=10h)
Codec Response Format
Bit
Description
31:16
Reserved. Read as 0’s.
15:8
NumCoeff. Number of Coefficient.
7:1
Reserved. Read as 0’s.
0
Benign.
0: Processing unit is not linear and time invariant
1: Processing unit is linear and time invariant
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.1.15.
Parameter – GPIO Capabilities
(Verb ID=F00h, Parameter ID=11h)
Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h)
Codec Response Format
Bit
Description
31
GPIWake=0. The ALC662 does not support GPIO wake-up function.
30
GPIUnsol=1. The ALC662 supports GPIO unsolicited response.
29:24
Reserved. Read as 0’s.
23:16
NumGPIs=00h. No GPI pin is supported.
15:8
NumGPOs=00h. No GPO pin is supported.
7:0
NumGPIOs=02h. Two GPIO pins are supported.
8.1.16.
Parameter – Volume Knob Capabilities
(Verb ID=F00h, Parameter ID=13h)
Table 36. Parameter – Volume Knob Capabilities (Verb ID=F00h, Parameter ID=13h)
Codec Response Format for NID=21h (Volume Control Knob)
Bit
Description
31:8
Reserved. Read as 0’s.
7
Delta.
0: Software cannot modify the Volume Control Knob volume
1: Software can write a base volume to the Volume Control Knob
6:0
NumSteps.
The number of steps in the range of the Volume Control Knob
Note: The ALC662 does not support volume knob and will respond with 0s to this parameter.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.2.
Verb – Get Connection Select Control (Verb ID=F01h)
Table 37. Verb – Get Connection Select Control (Verb ID=F01h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F01h
0’s
Bit[7:0] are Connection Index
Codec Response for NID = 19h (MIC2, PORT-F)
Bit
Description
31:8
0’s.
7:0
Connection Index Currently Set (Default value is 00h).
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Eh
Other: Reserved
Codec Response for NID = 1Bh (LINE2, PORT-E)
Bit
Description
31:8
0’s
7:0
Connection Index Currently Set (Default value is 00h).
00h: Sum Widget NID=0Ch
01h: Sum Widget NID=0Eh
Other: Reserved
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.3.
Verb – Set Connection Select (Verb ID=701h)
Table 38. Verb – Set Connection Select (Verb ID=701h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=701h
Select Index [7:0]
0’s for all nodes
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.4.
Verb – Get Connection List Entry (Verb ID=F02h)
Table 39. Verb – Get Connection List Entry (Verb ID=F02h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F02h Offset Index - N[7:0]
32-bit Response
Codec Response for NID=08h (ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 23h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=09h (ADC)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 22h (Sum Widget) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=0Bh (Mixer)
Bit
Description
31:24
Connection List Entry (N+3).
Returns 1Bh (Pin Complex – LINE2) for N=0~3.
Returns 15h (Pin Complex – SURR) for N=4~7.
23:16
Connection List Entry (N+2).
Returns 1Ah (Pin Complex – LINE1) for N=0~3.
Returns 14h (Pin Complex – FRONT) for N=4~7.
15:8
Connection List Entry (N+1).
Returns 19h (Pin Complex – MIC2) for N=0~3.
Returns 1Dh (Pin Complex – PCBEEP) for N=4~7.
7:0
Connection List Entry (N).
Returns 18h (Pin Complex – MIC1) for N=0~3.
Returns 16h (Pin Complex – CEN/LFE) for N=8~11.
Returns 00h for N>7.
Returns 00h for N>7.
Returns 00h for N>7.
Returns 1Ch (Pin Complex – CD) for N=4~7.
Returns 00h for N>11.
Codec Response for NID=0Ch (Front Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h
23:16
Connection List Entry (N+2).
Returns 00h.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
Codec Response for NID=0Ch (Front Sum)
Bit
Description
15:8
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
7:0
Connection List Entry (N).
Returns 02h (Front DAC) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=0Dh (Surround Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
7:0
Connection List Entry (N).
Returns 03h (Surround DAC) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=0Eh (Cen/Lfe Sum)
Bit
Description
31:24
Connection List Entry (N).
Returns 00h.
23:16
Connection List Entry (N+2).
Returns 00h.
15:8
Connection List Entry (N+1).
Returns 0Bh (Mixer) for N=0~3.
7:0
Connection List Entry (N).
Returns 04h (Cen/Lfe DAC) for N=0~3.
Returns 00h for N>3.
Returns 00h for N>3.
Codec Response for NID=14h (FRONT, Port-D)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h for n>3.
7:0
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=15h (SURR, Port-D)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h for n>3.
7:0
Connection List Entry (N).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Returns 00h for N>3.
5.1 Channel High Definition Audio Codec
35
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
Codec Response for NID=16h (CEN/LFE, Port-G)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h for n>3.
7:0
Connection List Entry (N).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=18h (MIC1, Port-B)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h for n>3.
7:0
Connection List Entry (N).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=19h (MIC2, Port-F)
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h for n>3.
15:8
Connection List Entry (N+1).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
7:0
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=1Ah (LINE1, Port-C)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h for n>3.
7:0
Connection List Entry (N).
Returns 0Dh (Sum Widget NID=0Dh) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=1Bh (LINE2, Port-E)
Bit
Description
31:16
Connection List Entry (N+3), (N+2).
Returns 0000h for n>3.
15:8
Connection List Entry (N+1).
Returns 0Eh (Sum Widget NID=0Eh) for N=0~3.
7:0
Connection List Entry (N).
Returns 0Ch (Sum Widget NID=0Ch) for N=0~3.
5.1 Channel High Definition Audio Codec
36
Returns 00h for N>3.
Returns 00h for N>3.
Returns 00h for N>3.
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
Codec Response for NID=1Eh (Pin Widget: SPDIF-OUT)
Bit
Description
31:8
Connection List Entry (N+3), (N+2), (N+1).
Returns 000000h.
7:0
Connection List Entry (N).
Returns 06h (SPDIF-OUT Converter) for N=0~3.
Returns 00h for N>3.
Codec Response for NID=22h/23h (Sum Widget)
Bit
Description
31:23
Connection List Entry (N+3).
Returns 1Bh (Pin Widget LINE2, port-E) for N=0~3.
Returns 15h (Pin Widget SURR, port-A) for N=4~7.
Returns 00h for n>7.
23:16
Connection List Entry (N+2).
Returns 1Ah (Pin Widget LINE1, port-C) for N=0~3.
Returns 14h (Pin Widget FRONT, port-D) for N=4~7.
Returns 00h for N>7.
15:8
Connection List Entry (N+1).
Returns 19h (Pin Widget MIC2, port-F) for N=0~3.
Returns 1Dh (Pin Widget PCBEEP) for N=4~7.
Returns 0Bh (Mixer) for N=8~11.
Returns 00h for N>11.
7:0
Connection List Entry (N).
Returns 18h (Pin Widget MIC1, port-B) for N=0~3.
Returns 1Ch (Pin Widget CD) for N=4~7.
Returns 16h (Pin Widget CEN/LFE, port-G) for N=8~11.
Returns 00h for N>11.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.5.
Verb – Get Processing State (Verb ID=F03h)
Table 40. Verb – Get Processing State (Verb ID=F03h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F03h
0’s
32-bit response
Codec Response for All NID
Bit
Description
31:0
Not Supported (returns 00000000h).
5.1 Channel High Definition Audio Codec
37
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.6.
Verb – Set Processing State (Verb ID=703h)
Table 41. Verb – Set Processing State (Verb ID=703h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=703h Processing State [7:0]
0’s for all nodes
Codec Response for all NID
Bit
Description
31:0
0’s.
8.7.
Verb – Get Coefficient Index (Verb ID=Dh)
Table 42. Verb – Get Coefficient Index (Verb ID=Dh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=20h
Verb ID=Dh
0’s
Bit [15:0] are Coefficient Index
Codec Response for NID=20h (Realtek Defined Registers)
Bit
Description
31:16
Reserved. Read as 0’s.
15:0
Coefficient Index.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.8.
Verb – Set Coefficient Index (Verb ID=5h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=20h
Table 43. Verb – Set Coefficient Index (Verb ID=5h)
Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=5h
Coefficient Index [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
38
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.9.
Verb – Get Processing Coefficient (Verb ID=Ch)
Table 44. Verb – Get Processing Coefficient (Verb ID=Ch)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=20h
Verb ID=Ch
0’s
Processing Coefficient [15:0]
Codec Response for NID=20h (Realtek Defined Registers)
Bit
Description
31:16
Reserved. Read as 0’s.
15:0
Processing Coefficient.
Codec Response for Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.10. Verb – Set Processing Coefficient (Verb ID=4h)
Table 45. Verb – Set Processing Coefficient (Verb ID=4h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
CAd=X
Node ID=20h
Verb ID=4h
Coefficient [15:0]
0’s for all nodes
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
39
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.11. Verb – Get Amplifier Gain (Verb ID=Bh)
This verb is used to get gain/attenuation settings from each widget.
Table 46. Verb – Get Amplifier Gain (Verb ID=Bh)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Bit [19:16]
Verb ID=Bh
Payload Bit [15:0]
‘Get’ payload [15:0]
Codec Response Format
Response [31:0]
Bit[7:0] are responsible for ‘Get’
‘Get’ Payload in Command Bit[15:0]
Bit
Description
15
Get Input/Output.
0: Input amplifier gain is requested
1: Output amplifier gain is requested
14
Reserved. Read as 0.
13
Get Left/Right.
0: Right amplifier gain is requested
1: Left amplifier gain is requested
12:4
Reserved. Read as 0’s.
3:0
Index[3:0] for Input Source.
Select amplifier for this converter. If a widget has no multiple input sources, the index will be ignored.
Codec Response for 02h (FRONT DAC), 03h (SURR DAC), 04h (CEN/LFE DAC)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Gain [6:0].
7-bit step value (0~64) specifying the volume from –64B~0dB in 1dB steps.
Codec Response for 08h (ADC)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –13.5B~+33dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).
5.1 Channel High Definition Audio Codec
40
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
Codec Response for 09h (ADC)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –13.5B~+33dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).
Codec Response for NID=0Bh (MIXER Sum Widget)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute (Default for all Index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0].
7-bit step value (0~31) specifying the volume from –34.5dB~+12dB in 1.5dB steps.
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0’s (No Output Amplifier Mute).
Codec Response for NID=0Ch~0Eh (Sum Widget: Front, Surr, Cen/Lfe)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=14h, 15h, 16h and 1Ah (Pin Widget: FRONT/SURR/CEN/LINE1)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0: Unmute
1: Mute (Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
5.1 Channel High Definition Audio Codec
41
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
Codec Response for NID=18h, 19h and 1Bh (Pin Widget: MIC1/MIC2/LINE2)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Mute).
Bit-15 is 1 in ‘Get Amplifier Gain’: Output Amplifier Mute.
0: Unmute
1: Mute (Default=1)
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Gain [6:0] specifying the boost from
0dB/10dB/20dB/30dB in 10dB steps (Default=0, 0dB).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=22h (Sum Widget)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute (Default=1 for all index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response for NID=23h (Sum Widget)
Bit
Description
31:8
0’s.
7
Bit-15 is 0 in ‘Get Amplifier Gain’: Input Amplifier Mute.
0: Unmute
1: Mute (Default=1 for all index)
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Mute).
6:0
Bit-15 is 0 in ‘Get Amplifier Gain’: Read as 0 (No Input Amplifier Gain).
Bit-15 is 1 in ‘Get Amplifier Gain’: Read as 0 (No Output Amplifier Gain).
Codec Response to Other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
5.1 Channel High Definition Audio Codec
42
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.12. Verb – Set Amplifier Gain (Verb ID=3h)
This verb is used to set amplifier gain/attenuation in each widget.
Table 47. Verb – Set Amplifier Gain (Verb ID=3h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Bit [19:8]
Verb ID=3h
Payload Bit [7:0]
‘Set’ payload [7:0]
Codec Response Format
Response [31:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
15
Set Output Amp.
1: Indicates output amplifier gain will be set
14
Set Input Amp.
1: Indicates input amplifier gain will be set
13
Set Left Amp.
1: Indicates left amplifier gain will be set
12
Set Right Amp.
1: Indicates right amplifier gain will be set
11:8
Index Offset (for input amplifiers on Sum widgets and Selector Widgets).
5-bit index offset in connection list is used to select the input gain that will be set on a Sum or a Selector
widget. The index is ignored if the node is not a Sum or a Selector widget, or the ‘Set Input Amp’ bit is not
set.
7
Mute.
0: Unmute
1: Mute (-∞gain)
6:0
Gain[6:0].
A 7-bit step value specifying the amplifier gain.
5.1 Channel High Definition Audio Codec
43
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.13. Verb – Get Converter Format (Verb ID=Ah)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Table 48. Verb – Get Converter Format (Verb ID=Ah)
Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=Ah
0’s
Bit[15:0] are converter format
Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC, and SPDIF-OUT).
Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h)
Bit
Description
31:16
Reserved. Read as 0.
15
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1
001b: *2
010b: *3
011b: *4
100b~111b: Reserved
10:8
Sample Base Rate Divisor (DIV).
000b: /1
001b: /2
010b: /3
011b: /4
100b: /5
101b: /6
110b: /7
111b: /8
Not supported. Always read as 000b.
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits
010b: 20 bits
011b: 24 bits
100b: 32 bits
101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel
1: 2 channels
2: 3 channels
………
15: 16 channels
8.14. Get Converter Format Support
NID=02h (Front DAC)
NID=03h (Surr DAC)
NID=04h (Cen/Lfe DAC)
NID=06h (SPDIF-OUT)
NID=08h (ADC)
NID=09h (ADC)
Table 49.
BASE
0
1
0
1
0
1
0
1
0
1
0
1
Get Converter Format Support
MULT
DIV
BITS
000b, 001b
000b
001, 010b, 011b
000b
000b
001, 010b, 011b
000b, 001b
000b
001, 010b, 011b
000b
000b
001, 010b, 011b
000b, 001b
000b
001, 010b, 011b
000b
000b
001, 010b, 011b
000b, 001b
000b
001, 010b, 011b
000b
000b
001, 010b, 011b
000b, 001b
000b
001b, 010b,
000b
000b
001b, 010b,
000b, 001b
000b
001b, 010b,
000b
000b
001b, 010b,
Sample Rate
48K, 96K
44.1K
48K, 96K
44.1K
48K, 96K
44.1K
48K, 96K
44.1K
48K, 96K
44.1K
48K, 96K
44.1K
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.15. Verb – Set Converter Format (Verb ID=2h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Table 50. Verb – Set Converter Format (Verb ID=2h)
Codec Response Format
Bit [19:16]
Payload Bit [15:0]
Response [31:0]
Verb ID=2h
Set format [15:0]
0’s for all nodes
‘Set’ Payload in Command Bit[15:0]
Bit
Description
31:16
Reserved. Read as 0.
15
Stream Type (TYPE).
0: PCM
1: Non-PCM
14
Sample Base Rate (BASE).
0: 48kHz
1: 44.1kHz
13:11
Sample Base Rate Multiple (MULT).
000b: *1
001b: *2
10:8
Sample Base Rate Divisor (DIV).
000b: /1
001b: /2
101b: /6
110b: /7
7
Reserved. Read as 0.
6:4
Bits per Sample (BITS).
000b: 8 bits
001b: 16 bits
101b~111b: Reserved
3:0
Number of Channels.
0: 1 channel
1: 2 channels
5.1 Channel High Definition Audio Codec
010b: *3
011b: *4
100b~111b: Reserved
010b: /3
111b: /8
011b: /4
100b: /5
010b: 20 bits
011b: 24 bits
100b: 32 bits
2: 3 channels
…..…
15: 16 channels
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.16. Verb – Get Power State (Verb ID=F05h)
Table 51. Verb – Get Power State (Verb ID=F05h)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Bit [19:8]
Verb ID= F05h
Codec Response Format
Response [31:0]
Power State [7:0]
Payload Bit [7:0]
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:6
Reserved. Read as 0’s.
5:4
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node. For Audio Function Group nodes
(NID=01h), PS-Act is always equal to PS-Set.
3:2
Reserved. Read as 0’s.
1:0
PS-Set. Set Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Set controls the current power setting of the referenced node.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.17. Verb – Set Power State (Verb ID=705h)
Table 52. Verb – Set Power State (Verb ID=705h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Bit [19:8]
Verb ID=705h
Payload Bit [7:0]
Power State [7:0]
Codec Response Format
Response [31:0]
0’s for all nodes
‘Power State’ in Command Bit[7:0]
Bit
Description
7:6
Reserved. Read as 0’s.
5:4
PS-Act. Actual Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
PS-Act indicates the actual power state of the referenced node.
3:2
Reserved. Read as 0’s.
1:0
PS-Set. Set Power State [1:0].
00: Power state is D0
01: Power state is D1
10: Power state is D2
11: Power state is D3
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.18. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Table 53. Verb – Get Converter Stream, Channel (Verb ID=F06h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F06h
0’s
Stream & Channel [7:0]
Codec Response for NID=02h~04h, 06h (Output Converters: FRONT, SURR, CEN/LFE DAC and SPDIF-OUT)
Codec Response for NID=08h and 09h (Input Converters: ADC 08h and ADC 09h)
Bit
Description
31:8
Reserved. Read as 0’s.
7:4
Stream[3:0].
The link stream used by the converter. 0000b is unused, 0001b is stream 1, etc.
3:0
Channel[3:0].
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.19. Verb – Set Converter Stream, Channel (Verb ID=706h)
Table 54. Verb – Set Converter Stream, Channel (Verb ID=706h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=706h Stream & Channel [7:0]
0’s for all nodes
‘Stream and Channel’ in Command Bit[7:0]
Bit
Description
31:8
Reserved. Read as 0’s.
7:4
Set Stream[3:0].
The link stream used by the converter. 0000b is stream 0, 0001b is stream 1, etc.
1:0
Set Channel[3:0].
The lowest channel used by the converter. A stereo converter will use the set channel n as well as n+1 for its
left and right channel.
5.1 Channel High Definition Audio Codec
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ALC662 Series
Datasheet
8.20. Verb – Get Pin Widget Control (Verb ID=F07h)
Table 55. Verb – Get Pin Widget Control (Verb ID=F07h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=F07h
0’s
Pin Control [7:0]
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh.
(Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)
Bit
Description
31:8
Reserved. Read as 0’s.
7
H-Phn Enable.
0: Disabled
1: Enabled
Note: Only NID=14h (FRONT), 19h (MIC2), and 1Bh (LINE2) support headphone amplifier.
6
Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).
0: Disabled
1: Enabled
Note: NID=1Ch (CD-IN) and 1Dh (PCBEEP) do not support output and are always read 0.
5
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
0: Disabled
1: Enabled
Note: NID=1Eh (SPDIF-OUT) does not support output and is always read 0.
4:3
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled, default for all)
001b: 50% of AVDD (The ALC662 supports 2.5V reference output when AVDD is 5V)
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD (The ALC662 supports 3.2V reference output when AVDD is 5V)
101b: 100% of AVDD
110b~111b: Reserved
Note: Only NID=18h, 19h, and 1Bh support reference output, other nodes will ignore this verb and respond
with 0.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.21. Verb – Set Pin Widget Control (Verb ID=707h)
Table 56. Verb – Set Pin Widget Control (Verb ID=707h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=707h
Pin Control [7:0]
0’s for all nodes
‘Pin Control’ in command [7:0]: (NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh)
(Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)
Bit
Description
31:8
Reserved. Read as 0’s.
7
H-Phn Enable.
0: Disabled
1: Enabled
Note: Only NID=14h (FRONT), 19h (MIC2), and 1Bh (LINE2) support headphone amplifier.
6
Out Enable (Output Buffet Enable, EN_OBUF for an I/O unit).
0: Disabled
1: Enabled
Note: NID=1Ch (CD-IN) and 1Dh(PCBEEP) do not support output and always read 0.
5
In Enable (Input Buffer Enable, EN_IBUF for an I/O unit).
0: Disabled
1: Enabled
Note: NID=1Eh (SPDIF-OUT) does not support output and always read 0.
4:3
Reserved.
2:0
VrefEn (Vrefout Enable Control).
000b: Hi-Z (Disabled, default for all)
001b: 50% of AVDD
010b: Ground 0V
011b: Reserved
100b: 80% of AVDD
101b: 100% of AVDD
110b~111b: Reserved
Note: Only NID=18h, 19h, and 1Bh support reference output. Other nodes will ignore this verb and
respond with 0.
5.1 Channel High Definition Audio Codec
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Rev. 1.3
ALC662 Series
Datasheet
8.22. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Determines whether a widget is enabled to send an unsolicited response. An HDA codec can use an
unsolicited response to inform software of a real time event.
Table 57. Verb – Get Unsolicited Response Control (Verb ID=F08h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID= F08h
0’s
32-bit Response
Codec Response for NID=01h (GPIO), 14h~16h, 18h~1Bh (Port jack detection)
Bit
Description
31:8
Reserved. Read as 0’s.
7
Unsolicited Response is Enabled.
0: Disabled
1: Enabled
6:4
Reserved. Read as 0’s.
3:0
Assigned Tag for Unsolicited Response.
The tag[3:0] is assigned by software to determine which widget generates unsolicited responses.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.23. Verb – Set Unsolicited Response Control (Verb ID=708h)
Enables a widget to generate an unsolicited response.
Table 58. Verb – Set Unsolicited Response Control (Verb ID=708h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID=708h
EnableUnsol [7:0]
0’s for all nodes
‘EnableUnsol’ in Command Bit [7:0]
Bit
Description
31:8
Reserved. Read as 0’s.
7
Unsolicited Response.
0: Disable
1: Enable
6
Reserved. Read as 0’s.
5:0
Tag for Unsolicited Responses.
Tag[5:0] is defined by software to assign a 6-bit tag for nodes that are enabled to generate unsolicited
responses.
5.1 Channel High Definition Audio Codec
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ALC662 Series
Datasheet
8.24. Verb – Get Pin Sense (Verb ID=F09h)
Returns the Presence Detect status and the impedance of a device attached to the pin.
Table 59. Verb – Get Pin Sense (Verb ID=F09h)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Bit [19:8]
Verb ID= F09h
Codec Response Format
Response [31:0]
32-bit Response
Payload Bit [7:0]
0’s
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh
(Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2)
Bit
Description
31
Presence Detect Status.
0: No device is attached to the pin
1: Device is attached to the pin
30:0
Measured Impedance.
The ALC662 does not support hardware impedance detect. This field is read as 0s.
Codec Response for other NID
Bit
Description
31:0
Not Supported (returns 00000000h).
8.25. Verb – Execute Pin Sense (Verb ID=709h)
Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=Xh
Table 60. Verb – Execute Pin Sense (Verb ID=709h)
Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID= 709h
Right Channel[0]
0’s for all nodes
‘Payload’ in Command Bit[7:0] (for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh)
Bit
Description
7:1
Reserved. Read as 0’s.
0
Right (Ring) Channel Select.
0: Sense Left channel (Tip)
1: Sense Right channel (Ring)
The ALC662 does not support hardware impedance detect and will ignore this control bit.
5.1 Channel High Definition Audio Codec
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ALC662 Series
Datasheet
8.26. Verb – Get Configuration Default
(Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)
Reads the 32-bit sticky register for each Pin Widget configured by software.
Table 61. Verb – Get Configuration Default (Verb ID=F1Ch/F1Dh/F1Eh/F1Fh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Verb ID= F1Ch
0’s
32-bit Response
Codec Response for NID=14h, 15h, 16h, 18h, 19h, 1Ah, 1Bh, 1Ch, 1Dh, 1Eh
(Pin Widget: FRONT, SURR, CENLFE, MIC1, MIC2, LINE1, LINE2, CD-IN, PCBEEP, SPDIF-OUT)
Bit
Description
31:0
32-bit configuration information for each pin widget.
Note: The 32-bit registers for each Pin Widget are sticky and will not be reset by a LINK Reset or Codec Reset (Function
Reset Verb).
8.27. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
The BIOS can use this verb to figure out the default conditions (e.g., placement and expected default
device) for the Pin Widgets NID=0B~0Fh, 10h, 11h, 1Fh, 20h, and 12h.
Table 62. Verb – Set Configuration Default Bytes 0, 1, 2, 3
(Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes 0, 1, 2, 3)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=Xh
Label [7:0]
0’s for all nodes
Verb ID=71Ch,
71Dh, 71Eh, 71Fh
Note: Supported by Pin Widget NID=14h~16h, 18h~1Bh, 1Ch, 1Dh, and 1Eh. Other widgets will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.28. Verb – Get BEEP Generator (Verb ID=F0Ah)
Table 63. Verb – Get BEEP Generator (Verb ID= F0Ah)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID= F1Bh
0’s
Divider [7:0]
‘Response’ for NID=01h
Bit
Description
31:8
Reserved.
7:0
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.29. Verb – Set BEEP Generator (Verb ID=70Ah)
Table 64. Verb – Set BEEP Generator (Verb ID= 70Ah)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h Verb ID=71Bh
Divider [7:0]
0’s for all nodes
‘Divider’ in Set Command
Bit
Description
31:8
Reserved.
7:0
Frequency Divider, F[7:0].
The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in
F[7:0].
The lowest tone is 48kHz/(255*4)=47Hz. The highest tone is 48kHz/(1*4)=12kHz.
A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input.
Note: All nodes except BEEP generator (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.30. Verb – Get GPIO Data (Verb ID= F15h)
Table 65. Verb – Get GPIO Data (Verb ID= F15h)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=01h
Bit [19:8]
Verb ID=F15h
Codec Response Format
Response [31:0]
32-bit Response
Payload Bit [7:0]
0’s
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Data.
The value written (output) or sensed (input) on the corresponding pin if it is enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.31. Verb – Set GPIO Data (Verb ID= 715h)
Table 66. Verb – Set GPIO Data (Verb ID= 715h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=01h
Bit [19:8]
Verb ID=715h
Payload Bit [7:0]
Data [7:0]
Codec Response Format
Response [31:0]
0’s for all nodes
‘Data’ in Set command for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Output Data.
The value written determines the value driven on a pin that is configured as an output pin.
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
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ALC662 Series
Datasheet
8.32. Verb – Get GPIO Enable Mask (Verb ID=F16h)
Table 67. Verb – Get GPIO Enable Mask (Verb ID= F16h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=F16h
0’s
EnableMask [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.33. Verb – Set GPIO Enable Mask (Verb ID=716h)
Table 68. Verb – Set GPIO Enable Mask (Verb ID=716h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=716h
Enable Mask [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Enable Mask.
0: The corresponding GPIO pin is disabled and is in Hi-Z state
1: The corresponding GPIO pin is enabled. Its behavior is determined by the GPIO direction control
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for All NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
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ALC662 Series
Datasheet
8.34. Verb – Get GPIO Direction (Verb ID=F17h)
Get Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=01h
Table 69. Verb – Get GPIO Direction (Verb ID=F17h)
Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=F17h
0’s
Direction [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.35. Verb – Set GPIO Direction (Verb ID=717h)
Set Command Format
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=01h
Table 70. Verb – Set GPIO Direction (Verb ID=717h)
Codec Response Format
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
Verb ID=717h
Direction [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Direction Control.
0: The corresponding GPIO pin is configured as an input
1: The corresponding GPIO pin is configured as an output
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Datasheet
8.36. Verb – Get GPIO Unsolicited Response Enable Mask
(Verb ID=F19h)
Table 71. Verb – Get GPIO Unsolicited Response Enable Mask (Verb ID=F19h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=F19h
0’s
UnsolEnable [7:0]
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note: All nodes except Audio Function Group (NID=01h) will ignore this verb.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.37. Verb – Set GPIO Unsolicited Response Enable Mask
(Verb ID=719h)
Table 72. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h)
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=01h
Verb ID=719h
UnsolEnable [7:0]
0’s for all nodes
Codec Response for NID=01h (Audio Function Group)
Bit
Description
31:2
Reserved.
1:0
GPIO[1:0] Unsolicited Enable Mask.
0: Unsolicited response will not be sent on link
1: Unsolicited response will be sent on link when state of corresponding GPIO has been changed
Note 1: All nodes except the Audio Function Group (NID=01h) will ignore this verb.
Note 2: The unsolicited response of corresponding GPIO is enabled when it’s ‘Enable Mask’ and Verb-‘Unsolicited
Response’ for NID=01h are enabled.
Codec Response for Other NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Rev. 1.3
ALC662 Series
Datasheet
8.38. Verb – Get Digital Converter Control 1 & Control 2
(Verb ID= F0Dh, F0Eh)
Table 73. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID= F0Dh, F0Eh)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=06h Verb ID=F0Dh/F0Eh
0’s
Bit[31:16]=0’s, Bit[15:0] are SIC bit
NID=06h (SPDIF-OUT Converter) Response to ‘Get verb’ – F0Dh (Control for SIC bit[15:0])
Bit
Description – SIC (SPDIF IEC Control) Bit[7:0]
31:16
Read as 0’s.
15
Reserved. Read as 0’s.
14:8
CC[6:0] (Category Code).
7
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
1: Professional format
5
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
4
COPY (Copyright).
0: Asserted
1: Not asserted
3
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
VCFG for Validity Control (control V bit and data in Sub-Frame).
1
V for Validity Control (control V bit and data in Sub-Frame).
0
Digital Enable. DigEn.
0: OFF
1: ON
Codec Response for Other NID
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
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Rev. 1.3
ALC662 Series
Datasheet
8.39. Verb – Set Digital Converter Control 1 & Control 2
(Verb ID=70Dh, 70Eh)
Table 74. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh)
Set Command Format (Verb ID=70Dh, Set Control 1)
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Node ID=06h
Verb ID=70Dh
SIC [7:0]
0’s
Set Command Format (Verb ID=70Eh, Set Control 2)
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
CAd=X
Node ID=06h
Verb ID=70Eh
SIC [15:8]
Codec Response Format
Response [31:0]
0’s
‘Payload’ in Set Control 1 for NID=06h (SPDIF-OUT Converter)
Bit
Description – SIC (SPDIF IEC Control) Bit[7:0]
7
LEVEL (Generation Level).
6
PRO (Professional or Consumer Format).
0: Consumer format
1: Professional format
5
/AUDIO (Non-Audio Data Type).
0: PCM data
1: AC3 or other digital non-audio data
4
COPY (Copyright).
0: Asserted
1: Not asserted
3
PRE (Pre-Emphasis).
0: None
1: Filter pre-emphasis is 50/15 microseconds
2
VCFG for Validity Control (control V bit and data in Sub-Frame).
1
V for Validity Control (control V bit and data in Sub-Frame).
0
Digital Enable. DigEn.
0: OFF
1: ON
‘Payload’ in Set Control 2 for NID=06h (SPDIF-OUT Converter)
Bit
Description – SIC (SPDIF IEC Control) Bit[7:0]
7
Reserved. Read as 0’s.
6:0
CC[6:0] (Category Code).
5.1 Channel High Definition Audio Codec
59
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Rev. 1.3
ALC662 Series
Datasheet
8.40. Verb – Get Subsystem ID [31:0]
(Verb ID=F20h/F21h/D22h/F23h)
32-bit Read/Write register for Audio Function Group (NID=01h)
Table 75. Verb – Get Subsystem ID [31:0] (Verb ID=F20h/F21h/F22h/F23h)
Get Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h
Verb ID=F20h
0s
32-bit Response
Codec Response for NID=01h
Bit
Description
31:16
Subsystem ID[23:8] (Default=10ECh).
15:8
Subsystem ID[7:0] (Default=06h).
7:0
Assembly ID[7:0] (Default=62h).
8.41. Verb – Set Subsystem ID [31:0] (Verb ID=723h for [31:24],
722h for [23:16], 721h for [15:8], 720h for [7:0])
Table 76. Verb – Set Subsystem ID [31:0]
(Verb ID=723h for [31:24], 722h for [23:16], 721h for [15:8], 720h for [7:0])
Set Command Format
Codec Response Format
Bit [31:28]
Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd = X
Node ID=01h
Label [7:0]
0s for all nodes
Verb ID=723h,
722h, 721h, 720h
Codec Response for all NID
Bit
Description
31:0
0s.
5.1 Channel High Definition Audio Codec
60
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.42. Verb – Get EAPD Control (Verb ID=F0Ch)
Table 77. Verb – Get EAPD Control (Verb ID=F0Ch)
Get Command Format (NID=14h and 15h)
Codec Response Format
Bit [31:28] Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=F0Ch
0s
Bit[1] is EAPD Control
Node ID
=14h/15h
Codec Response for NID=14h (FRONT, port-D) and 15h (SURR, port-A)
Bit
Description
31:3
Reserved.
2
L-R Swap. The ALC662 does not support swapping left and right channels. Read as 0.
1
EAPD Value.
0: EAPD pin state is low
1: EAPD pin state is high
0
BTL Enable. The ALC662 does not support BTL output. Read as 0.
Codec Response for Other NID
Bit
Description
31:0
0’s.
8.43. Verb – Set EAPD Control (Verb ID=70Ch)
Table 78. Verb – Set EAPD Control (Verb ID=70Ch)
Set Command Format (NID=14h and 15h)
Codec Response Format
Bit [31:28] Bit [27:20]
Bit [19:8]
Payload Bit [7:0]
Response [31:0]
CAd=X
Verb ID=70Ch
Bit[1] is EAPD Control
0s
Node ID
=14h/15h
Payload in Set command for NID=14h (FRONT, port-D) and 15h (SURR, port-A)
Bit
Description
31:3
Reserved.
2
L-R Swap. The ALC662 does not support swapping left and right channels. Read as 0.
1
EAPD Value.
0: EAPD pin state is low
1: EAPD pin state is high.
Note: Only one physical logic for the EAPD signal.
0
BTL Enable. The ALC662 does not support BTL output. Read as 0.
Codec Response
Bit
Description
31:0
0’s.
5.1 Channel High Definition Audio Codec
61
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
8.44. Verb – Function Reset (Verb ID=7FFh)
Table 79. Verb – Function Reset (Verb ID=7FFh)
Command Format (NID=01h)
Bit [31:28]
Bit [27:20]
CAd=X
Node ID=01h
Bit [19:8]
Verb ID=7FFh
Payload Bit [7:0]
0’s
Codec Response Format
Response [31:0]
0’s
Codec Response
Bit
Description
31:0
Reserved. Read as 0’s.
Note: The Function Reset command causes all widgets to return to their power-on default state.
5.1 Channel High Definition Audio Codec
62
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Rev. 1.3
ALC662 Series
Datasheet
9.
9.1.
9.1.1.
Electrical Characteristics
DC Characteristics
Absolute Maximum Ratings
Parameter
Power Supply
Digital Power for Core
Digital Power for HDA Link
Analog
Ambient Operating Temperature
Storage Temperature
Table 80. Absolute Maximum Ratings
Symbol
Minimum
Typical
Maximum
Units
DVDD
3.0
3.3
3.6
V
DVDD-IO*
1.5
3.3
3.6
V
AVDD**
3.0
5.0
5.5
V
Ta
0
+70
°C
Ts
+125
°C
ESD (Electrostatic Discharge)
Susceptibility Voltage
Digital Pins
3500V
Analog Pins
4000V
*: The digital link power DVDD-IO must be lower than the digital core power DVDD.
**: The standard testing condition before shipping is AVDD = 5.0V unless specified. Customers designing with a different
AVDD should contact Realtek technical support representatives for special testing support.
9.1.2.
Threshold Voltage
DVDD=3.3V±5%, Tambient=25°C, with 50pF external load.
Parameter
Input Voltage Range
Low Level Input Voltage (HDA Link)
High Level Input Voltage (HDA Link)
Low Level Input Voltage (SPDIF-OUT)
High Level Input Voltage (SPDIF-OUT)
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Output Leakage Current (Hi-Z)
Output Buffer Drive Current
Internal Pull Up Resistance
5.1 Channel High Definition Audio Codec
Table 81. Threshold Voltage
Symbol
Minimum
Vin
-0.30
VIL
VIH
0.65*DVDDIO
VOL
VOH
0.56*DVDD (1.85)
VOH
0.9*DVDD
VOL
-10
-10
-
63
Typical
5
50k
Maximum
DVDD +0.30
0.35*DVDDIO
0.44*DVDD (1.45)
0.1*DVDD
10
10
100k
Track ID: JATR-1076-21
Units
V
V
V
V
V
V
V
µA
µA
mA
Ω
Rev. 1.3
ALC662 Series
Datasheet
9.1.3.
Digital Filter Characteristics
Filter
ADC Lowpass Filter
DAC Lowpass Filter
Table 82. Digital Filter Characteristics
Symbol
Minimum
Typical
Passband
0
Stopband
0.60*Fs
Stopband Rejection
-76.0
Passband Frequency Response
±0.05
Passband
0
Stopband
0.60*Fs
Stopband Rejection
-78.5
Passband Frequency Response
±0.05
Maximum
0.45*Fs
0.45*Fs
-
Units
kHz
kHz
dB
dB
kHz
kHz
dB
dB
Note: Fs=Sample rate.
9.1.4.
SPDIF Output Characteristics
DVDD= 3.3V, Tambient=25°C, with 75Ω external load.
Parameter
SPDIF-OUT High Level Output
SPDIF-OUT Low Level Output
Table 83. SPDIF Output Characteristics
Symbol
Minimum
Typical
VOH
3.0
3.3
VOL
0
5.1 Channel High Definition Audio Codec
64
Maximum
0.3
Units
V
V
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
9.2.
9.2.1.
AC Characteristics
Link Reset and Initialization Timing
Table 84. Link Reset and Initialization Timing
Parameter
Symbol
Minimum
Typical
RESET# Active Low Pulse Width
TRST
100.167
RESET# Inactive to BCLK
TPLL
100
Startup Delay for PLL Ready Time
SDI Initialization Request
TFRAME
-
4 BCLK
Maximum
-
Units
µs
µs
25
Frame Time
Initialization
Sequence
>= 4 BCLK
4 BCLK
BCLK
Normal Frame
SYNC
SYNC
SDO
Initialization
Request
SDI
RESET#
TRST
T FRAME
TPLL
Figure 14. Link Reset and Initialization Timing
5.1 Channel High Definition Audio Codec
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Rev. 1.3
ALC662 Series
Datasheet
9.2.2.
Link Timing Parameters at the Codec
Table 85. Link Timing Parameters at the Codec
Parameter
Symbol
Minimum
Typical
Maximum
BCLK Frequency
23.9976
24.0
24.0024
BCLK Period
Tcycle
41.163
41.67
42.171
BCLK Jitter
Tjitter
150
500
BCLK High Pulse Width
Thigh
17.5 (42%)
24.16 (58%)
BCLK Low Pulse Width
Tlow
17.5 (42%)
24.16 (58%)
Tsetup
5
SDO Setup Time at Both Rising
and Falling Edge of BCLK
Thold
5
SDO Hold Time at Both Rising and
Falling Edge of BCLK
Ttco
3
11
SDI Valid Time After Rising Edge
of BCLK (1:50pF external load)
SDI Flight Time
Tflight
0
7
Units
MHz
ns
ps
ns (%)
ns (%)
ns
ns
ns
ns
T _ c y c le
T _ h ig h
V I
BCLK
H
VT
V IL
T _ s e tu p
T _ h o ld
T _ lo w
SDO
T _ tc o
VO H
SDI
VOL
T _ f lig h t
Figure 15. Link Signal Timing
5.1 Channel High Definition Audio Codec
66
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
9.2.3.
SPDIF Output Timing
Table 86. SPDIF Output Timing
Symbol
Minimum
Typical
3.072
Tcycle
325.6
Tjitter
THigh
156.2 (48%)
162.8 (50%)
TLow
156.2 (48%)
162.8 (50%)
Trise
2.0
Tfall
2.0
Parameter
SPDIF-OUT Frequency
SPDIF-OUT Period
SPDIF-OUT Jitter
SPDIF-OUT High Level Width
SPDIF-OUT Low Level Width
SPDIF-OUT Rising Time
SPDIF-OUT Falling Time
Maximum
4
169.2 (52%)
169.2 (52%)
-
Units
MHz
ns
ns
ns (%)
ns (%)
ns
ns
T c y c le
T h ig h
T lo w
VOH
Vt
V OL
T r is e
T fa ll
Figure 16. Output Timing
9.2.4.
Test Mode
Codec test mode and Automatic Test Equipment (ATE) mode are not supported.
5.1 Channel High Definition Audio Codec
67
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Rev. 1.3
ALC662 Series
Datasheet
9.3.
Analog Performance
Standard Test Conditions
•
Tambient=25°C, DVDD= 3.3V ±5%, AVDD=5.0V±5%
•
1kHz input sine wave; Sampling frequency=48kHz; 0dB=1Vrms
•
10KΩ/50pF load; Test bench Characterization BW: 10Hz~22kHz
Table 87. Analog Performance
Parameter
Min
Typ
Full-Scale Input Voltage
All Inputs (Gain=0dB)
1.6
ADC
1.4
Full-Scale Output Voltage
DAC
1.4
S/N (A Weighted)
ADC
90
DAC
98
Headphone Amplifier
98
THD+N (-3dB Test Signal)
ADC
-85
DAC
-92
-75
Headphone Amplifier (32Ω Load)
THD+N (-1dB Test Signal for ALC662-VCx)
ADC
-83
DAC
-90
Magnitude Response
ADC (-3dB lower edge, -1dB higher edge)*
0
DAC (-3dB lower edge, -1dB higher edge)*
0
Passband ripple for DAC and ADC (ALC662)
-0.20
Passband ripple for DAC and ADC (ALC662-VCx)
-0.02
Power Supply Rejection Ratio
-40
Total Out-of-Band Noise (28.8kHz~100kHz)
-60
Crosstalk Between Output Channel (1kHz/20kHz)
Output Noise Level During System Activity
Output Inter-Channel Phase Delay
Input Impedance (Gain=0dB)
40
Output Impedance
Line Output
100
Amplified Output
1
Power Supply Current (Normal Operation)
AVDD=5V/DVDD=3.3V
38/23
Power Supply Current (Power Down Mode)
AVDD=5V/DVDD=3.3V
0.4/1.1
VREFOUTx Output Voltage (AVDD=5.0V)
2.5
VREFOUTx Output Current (AVDD=5.0V)
5
*: The higher edge of magnitudes for DAC and ADC are -0.6dB@20,000Hz.
5.1 Channel High Definition Audio Codec
68
Max
Units
-
Vrms
Vrms
-
Vrms
-
dB FSA
dB FSA
dBFS A
-
dB FS
dB FS
dB FS
-
dB FS
dB FS
>20,000
>20,000
+0.20
+0.02
-90/-80
110
0.2
-
Hz
Hz
dB
dB
dB
dB
dB
dB
Degree
KΩ
2
Ω
Ω
-
mA
3.2
-
mA
V
mA
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
10.
Application Circuits
The ALC662 series is fully pin to pin compatible with the ALC88x series. Please contact Realtek to get
the latest application circuits. To get the best compatibility in hardware design and software driver, any
modifications should be confirmed by Realtek. Realtek may update the latest application circuits onto our
website (www.realtek.com) without modifying this data sheet.
10.1. Filter Connection
Front panel header option-2
LINE2-JD
MIC2-JD
MIC1-VREFOR
LINE2-VREFO
Front panel header option-1
MIC1-VREFOL
+5VA
5.1K,1% (NC)
C17
FRONT-L
10u
26
25
AVDD1
28
29
30
31
27
VREF
MIC1-VREFO-L
NC
MIC2-VREFO
LINE2-VREFO
32
33
NC
MIC1-VREFO-R
35
34
Sense B
LINE2-R
EAPD
LINE2-L
SPDIFO
DVDD
48
NC
1
S/PDIF-OUT
Sense A
+3.3VD
24
LINE1-R
23
LINE1-L
22
MIC1-R
20
C26
1u
19
C29
1u
18
C32
1u
MIC2-R
16
MIC2-L
15
LINE2-R
14
LINE2-L
RESET#
SYNC
GPIO0
R13
1u
J1
CD-IN Header
13
C34 +
R16
22
4
3
2
1
17
C33
10u
MIC1-L
21
PCBEEP
47
MIC2-L
SYNC
46
EAPD
NC
10
SIDESURR-R
MIC2-R
DVDD-IO
45
CD-L
LFE
9
SIDESURR-L
ALC662
CENTER
SDATA-IN
44
CD-GND
8
43
LFE
AVSS2
DVSS
CEN
CD-R
BIT-CLK
42
LINE1-L
SURR-R
7
41
LINE1-R
MIC1-L
6
20K,1%
SURR-R
U2
JDREF
SDATA-OUT
R6
C18
10u
MIC1-R
DVSS
40
+
SURR-L
5
39
AVDD2
4
SURR-L
NC
GPIO1
38
3
37
GPIO0
+
10u
2
C21
FRONT-L
+5VA
FRONT-R
36
FRONT-R
AVSS1
10K,1%
RESET#
R3
11
R2 is for SIDE Output
not required for ALC662 R2
CEN-JD
MIC2-VREFO
FRONT-IO-JD
+
FRONT-IO-JD
12
Resistors placed
beside onboad
front panel header
R7
5.1K,1% FRONT-JD
R8
10K,1%
LINE1-JD
R9
20K,1%
MIC1-JD
R10
39.2K,1% SURR-JD
FRONT-JD
LINE1-JD
MIC1-JD
SURR-JD
10K
Ext. PCBEEP
C36
100P
R15
1K
SDIN
GPIO1
R17
22
BCLK
DGND
C40
22P
SDOUT
AGND
Tied at one point only under the
codec or near the codec
Figure 17. Filter Connection
5.1 Channel High Definition Audio Codec
69
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
10.2. Onboard Front Panel Header Connection and Front
Panel I/O
Option 1: Follow Intel's HD Audio front panle header design
(Two ports must be in the same jack detect group)
MIC2-VREFO
D3
D4
HD Audio Front Panel I/O Cable
1N4148
1N4148
R11
R12
4.7K
4.7K
+3.3VD
J2
FIO-PORT1-L
FIO-PORT1-R
FIO-PORT2-R
FIO-SENSE
FIO-PORT2-L
R14
MIC2-L
C35
1u
C37
1u
LINE2-R
C38
100u
+
MIC2-R
10K
C39
+
LINE2-L
100u
1
3
5
7
9
2
4
6
8
10
Key
MIC2-JD
2
4
6
8
10
FIO-PRESENCE#
PORT1-SENSE-RETURN
KEY
PORT2-SENSE-RETURN
CON10A
J3
FRONT-IO-JD
1
3
5
7
9
PRESENCE#
System GPI
FIO-SENSE
LINE2-JD
CON10A
Onboard front
panel header
R18
R19
JACK 7
20K,1%
39.2K,1%
FIO-PORT2-R
L14
FERB
FIO-PORT2-L
L15
FERB
Option 2: A more flexible front panel header
PORT2-SENSE-RETURN
4
3
5
2
1
C41
C42
100P
100P
FIO-PORT2 (Jack-E)
(Each port can be in different jack detect group)
MIC2-VREFO
D5
1u
MIC2-R
C46
1u
LINE2-R
C48
LINE2-L
C51
+
C44
100u
+
MIC2-L
100u
D6
1N4148
1N4148
R20
R21
4.7K
4.7K
FIO-SENSE
+3.3VD
JACK 8
PORT1-SENSE-RETURN
R23
10K
PRESENCE#
J5
1
3
5
7
9
2
4
6
8
10
R25
Key
CON10A
Onboard front
panel header
20K,1%
MIC2-JD
LINE2-JD
R26
FIO-PORT1-R
L16
FERB
FIO-PORT1-L
L17
FERB
2
1
System GPI
Sense B
4
3
5
C49
C50
100P
100P
FIO-PORT1 (Jack-F)
Sense B
39.2K,1%
Figure 18. Onboard Front Panel Header Connection and Front Panel I/O
5.1 Channel High Definition Audio Codec
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Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
10.3. Analog Input/Output Connection
JACK 2
JACK 1
FRONT-L
C1
C3
+
FRONT-R
100u
L1
FERB
+
FRONT-JD
100u
L3
FERB
SURR-JD
4
3
5
2
1
C5
C6
SURR-R
C2
1u
L2
FERB
SURR-L
C4
1u
L4
FERB
FRONT-OUT
100P 100P
C9
1u
L6
FERB
LINE1-L
C11
1u
L8
FERB
4
3
5
C8
100P
100P
CEN-JD
2
1
C15
2
1
C7
JACK 3
LINE1-JD
LINE1-R
C16
LFE
C10
1u
L7
FERB
CEN
C14
1u
L9
FERB
4
3
5
SURR-OUT
JACK 4
4
3
5
2
1
LINE-IN
100P 100P
C19
C20
100P
100P
CEN/LFE-OUT
MIC1-VREFO-L
MIC1-VREFO-R
R4
R5
4.7K
4.7K
MIC1-JD
MIC1-R
C22
1u
L10
FERB
MIC1-L
C24
1u
L12
FERB
C27
4
3
5
2
1
C28
JACK 5
100P 100P
MIC-IN
Figure 19. Analog Input/Output Connection
10.4. Optional SPDIF Output
S/PDIF module option 1: Optical
U3
Optical Transmitter
TOTX178
+5VD
J4
IN
VCC
4
S/PDIF OUTPUT
(Coaxial)
S/PDIF-OUT
R22
1
C45
R24
100P
100
200
C43
S/PDIF-OUT
0.01u
2
C47
0.1u
N.C
3
1
GND
N.C
2
5
S/PDIF module option 2: Coaxial
Figure 20. Optional SPDIF Output
5.1 Channel High Definition Audio Codec
71
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
11.
Mechanical Dimensions
L
L1
See the Mechanical Dimensions notes on the next page.
5.1 Channel High Definition Audio Codec
72
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
11.1. Mechanical Dimensions Notes
SYMBOL
A
A1
A2
c
D
D1
D2
E
E1
E2
b
e
TH
L
L1
MILLIMETER
INCH
MIN. TYP MAX. MIN.
TYP MAX
1.60
0.063
0.05
0.15
0.002
0.006
1.35 1.40
1.45
0.053 0.055 0.057
0.09
0.20
0.004
0.008
9.00 BSC
0.354 BSC
7.00 BSC
0.276 BSC
5.50
0.217
9.00 BSC
0.354 BSC
7.00BSC
0.276 BSC
5.50
0.217
0.17 0.20
0.27 0.007 0.008
0.011
0.50 BSC
0.0196 BSC
0o
3.5o
7o
0o
3.5o
7o
0.45 0.60
0.75 0.018 0.0236 0.030
1.00
0.0393
-
5.1 Channel High Definition Audio Codec
73
TITLE: LQFP-48 (7.0x7.0x1.6mm)
PACKAGE OUTLINE DRAWING,
FOOTPRINT 2.0mm
LEADFRAME MATERIAL
APPROVE
DOC. NO.
VERSION 02
CHECK
DWG NO. PKGC-065
DATE
REALTEK SEMICONDUCTOR CORP.
Track ID: JATR-1076-21
Rev. 1.3
ALC662 Series
Datasheet
12.
Ordering Information
Table 88. Ordering Information
Part Number
Package
Status
ALC662-GR
LQFP-48 ‘Green’ Package
Production
ALC662-VC0-GR
ALC662 Version C Stepping 0 Silicon, LQFP-48 ‘Green’ Package
Production
ALC662-VC1-GR
ALC662 Version C Stepping 1 Silicon, LQFP-48 ‘Green’ Package
Production
Note 1: See page 6 for Green package and version identification.
Note 2: Above parts are tested under AVDD=5.0V. If customers have lower AVDD request, please contact Realtek sales
representatives or agents.
Realtek Semiconductor Corp.
Headquarters
No. 2, Innovation Road II
Hsinchu Science Park, Hsinchu 300, Taiwan
Tel.: +886-3-578-0211. Fax: +886-3-577-6047
www.realtek.com
5.1 Channel High Definition Audio Codec
74
Track ID: JATR-1076-21
Rev. 1.3
