CMOS Shift Register TM74HC595
Characterization
TM74HC595 is an open-drain output CMOS shift register which is designed with controllable
tri-state output terminals and, when in serial output configuration, can control cascade chip of next
stage. This product is excellent in performance and reliable in quality.
Features
High-speed shift clock frequency Fmax> 25MHz
Standard SPI
CMOS serial output, capable of cascading multiple devices
Low power consumption: Icc = 4μA (MAX) when TA = 25 ℃
Block diagram of internal structure
1
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CMOS Shift Register TM74HC595
Pin arrangement
QB
QC
QD
QE
QF
QG
QH
GND
1
16
2
15
3
14
4
13
TOP VIEW
5
12
6
11
7
10
8
9
VCC
QA
SI
CE
RCK
SCK
SCLR
SQH
TM74HC595
Pin Function
Pin Name
QA—QH
Pin No.
Function Description
15、1、2、3、4、5、
6、7
Tri-state output pin
GND
8
Negative power
SQH
9
Serial data output pin
SCLR
SCK
10
11
Clear pin of shift register
Input pin of data shift clock
RCK
12
Input pin of Latch clock
OE
SI
13
14
Output enable pin
Input pin of serial data
VCC
16
Positive power
Input and output equivalent circuit
VCC
VCC
INPUT
OUTPUT
GND
GND
Output pins
输出管脚
Input pins
输入管脚
ESD protection
An integrated circuit is a static sensitive device. Since a considerable amount of static
electricity is likely to be generated in a dry season or a dry environment and electrostatic
discharge will damage integrated circuits, it is the advise of Titan that preventive measures
should be taken for all appropriate ICs are. Improper operation and welding may cause
ESD damage or performance degradation, and put the chip out of service.
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CMOS Shift Register TM74HC595
Recommended Operating Conditions
Tested at -45 ℃ ~ + 85 ℃ , unless
otherwise stated
Parameter
Parameter Symbol
Name
DC VDD
DC input voltage
DC output
voltage
Operating
temperature
TM74HC595
Test
Conditions
VCC
VIN
VOUT
TA
VCC =5V
Unit
Minimum
Maximum
2.0
0
0
5.5
5.5
VCC
V
V
V
-55
125
℃
Electrical Characteristics
Unless otherwise stated, tested at VDD = 3.0V ~
5.5V and the operating temperature of -40 ℃ ~ +
85 ℃
Test Conditions
Parameter Parameter
VDD
Name
Symbol
Input high
level
VIH
Input low
level
VIL
Output high
level
(SQH)
VOH
Output high
level
(QA- QH)
VOH
Output low
level
(SQH)
VOL
Output low
level
(QA- QH)
VOL
Quiescent
Current
ICC
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
TM74HC595
25℃
Min
1.46
3.23
4.30
Typ
Max
0.52
1.32
1.77
VI=VI
IO=-20μA
H
or VIL
IO=-4.0mA
IO=-5.2mA
VI=VI
IO=-20μA
H
or VIL
IO=-6.0mA
IO=-7.8mA
VI=VI
IO=20μA
1.9
4.4
5.9
4.18
5.68
1.9
4.4
5.9
4.18
5.68
H
or VIL
IO=4.0mA
IO=5.2mA
VI=VI
IO=20μA
H
or VIL
Unit
Value
IO=6.0mA
IO=7.8mA
VI=VCC or GND
2.0
4.5
6.0
4.31
5.8
2.0
4.5
6.0
4.31
5.8
0.0
0.0
0.0
0.17
0.18
0.0
0.0
0.0
0.17
0.18
0.1
0.1
0.1
0.26
0.26
0.1
0.1
0.1
0.26
0.26
4
-40℃—85
℃
Min
Max
1.46
3.23
4.30
0.52
1.32
1.77
1.9
4.4
5.9
4.13
5.63
1.9
4.4
5.9
4.13
5.63
0.1
0.1
0.1
0.33
0.33
0.1
0.1
0.1
0.33
0.33
40
-55℃—125
℃
Min
Max
1.46
3.23
4.30
0.52
1.32
1.77
1.9
4.4
5.9
4.10
5.60
1.9
4.4
5.9
4.10
5.60
0.1
0.1
0.1
0.40
0.40
0.1
0.1
0.1
0.40
0.40
80
V
V
V
V
V
V
μA
3
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CMOS Shift Register TM74HC595
Switching characteristics
Unless otherwise stated, tested at
VDD = 3.0V ~ 5.5V and the operating
temperature of -40 ℃ ~ + 85 ℃
Para
mete
Test
Parameter Name
r
Conditi
Sym
ons
bol
TM74HC595
TA=25℃
TA=–40 ~ 85℃
TA=-55 ~ 125℃
Range
Range
Range
Un
it
SI-to-SCK ON time
tsu
VDD=3.3
VDD=5.0
3.5
3.0
3.5
3.0
3.5
3.0
ns
SCK-to-RCK ON time
tsu(H)
VDD=3.3
VDD=5.0
8.0
5.0
8.5
5.0
8.5
5.0
ns
SCLR-to-RCK ON time
tsu(L)
VDD=3.3
VDD=5.0
9.0
5.0
9.0
5.0
9.0
5.0
ns
SI-to-SCK OFF time
th
VDD=3.3
VDD=5.0
1.5
2.0
1.5
2.0
1.5
2.0
ns
SCLR-to-RCK OFF time
th(L)
VDD=3.3
VDD=5.0
0
0
0
0
1.0
1.0
ns
SCLR-to-SCK recovery
time
trec
VDD=3.3
VDD=5.0
3.0
2.5
3.0
2.5
3.0
2.5
ns
Pulse width of SCK or
RCK
tW
VDD=3.3
VDD=5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
SCLR pulse width
tW(L)
VDD=3.3
VDD=5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
4
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V1.1
CMOS Shift Register TM74HC595
Timing Characteristics
Function Description
Input pin
Output pin
SI
SCK
SCLR
RCK
OE
X
X
X
X
H
QA-QH output high impedance
X
X
X
X
L
QA-QH output RMS
X
X
L
X
X
The shift register is cleared
H
X
X
L is stored into the shift register
H
X
X
H is stored into the shift register
H
X
X
Hold the shift register state
X
Output the status value latched in the shift register
X
Hold the output status of the shift register
L
H
X
Rising
edge
Rising
edge
Falling
edge
X
X
X
X
X
X
Rising
edge
Falling
edge
5
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©Titan Micro Electronics
V1.1
CMOS Shift Register TM74HC595
Schematic diagram of packaging (SOP16)
6
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©Titan Micro Electronics
V1.1
CMOS Shift Register TM74HC595
Schematic diagram of packaging (DIP16)
All specs and applications shown above are subject to change without prior notice.
7
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V1.1
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