VG-2864KSWEG01

Product Specification Part Name Customer Part ID TOPWIN Part ID TOPWIN Part ID TOPWIN Part ID : : : : : OEL Display Module VG-2864KSWEG01 VG-2864KLBEG01 VG-2864KMBEG01 Customer: Approved by * This product is only available for China market. From: Topwin Semiconductor Inc. Approved by Revised History Part Number VG-2864KSWEG01 Revision A Revision Content New Revised on June 16, 2015 Contents Revision History ................................................................................................................................i Contents ...........................................................................................................................................ii 1. Basic Specifications ................................................................................................................ 1~6 1.1 Display Specifications ....................................................................................................................1 1.2 Mechanical Specifications...............................................................................................................1 1.3 Active Area / Memory Mapping & Pixel Construction ........................................................................1 1.4 Mechanical Drawing.......................................................................................................................2 1.5 Pin Definition ................................................................................................................................3 2. Absolute Maximum Ratings ........................................................................................................5 3. Optics & Electrical Characteristics ....................................................................................... 6~12 3.1 Optics Characteristics ....................................................................................................................6 3.2 DC Characteristics .........................................................................................................................6 3.2.1 VCC Supplied Externally ........................................................................................................6 3.2.2 VCC Generated by Internal DC/DC Circuit...............................................................................7 3.3 AC Characteristics .........................................................................................................................8 3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics .....................................................8 3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics .....................................................9 3.3.3 Serial Interface Timing Characteristics (4-wire SPI) ............................................................. 10 3.3.4 Serial Interface Timing Characteristics (3-wire SPI) ............................................................. 11 3.3.5 I2C Interface Timing Characteristics.................................................................................... 12 4. Functional Specification ..................................................................................................... 13~27 4.1 Commands ................................................................................................................................. 13 4.2 Power down and Power up Sequence ........................................................................................... 13 4.2.1 Power up Sequence........................................................................................................... 13 4.2.2 Power down Sequence ...................................................................................................... 13 4.3 Reset Circuit ............................................................................................................................... 13 4.4 Application Circuit ....................................................................................................................... 14 4.4.1 68XX-Series MPU Parallel Interface and VCC Supplied Externally............................................ 14 4.4.2 68XX-Series MPU Parallel Interface and VCC Generated by Internal DC/DC Circuit .................. 15 4.4.3 80XX-Series MPU Parallel Interface and VCC Supplied Externally............................................ 16 4.4.4 80XX-Series MPU Parallel Interface and VCC Generated by Internal DC/DC Circuit .................. 17 4.4.5 4-wire Serial Interface and VCC Supplied Externally .............................................................. 18 4.4.6 4-wire Serial Interface and VCC Generated by Internal DC/DC Circuit..................................... 19 4.4.7 3-wire Serial Interface and VCC Supplied Externally .............................................................. 20 4.4.8 3-wire Serial Interface and VCC Generated by Internal DC/DC Circuit..................................... 21 4.4.9 I2C Interface and VCC Supplied Externally ............................................................................ 22 4.4.10 I2C Interface and VCC Generated by Internal DC/DC Circuit .................................................. 23 4.5 Actual Application Example .......................................................................................................... 24 4.4.1 VCC Supplied Externally ...................................................................................................... 24 4.4.2 VCC Generated by Internal DC/DC Circuit............................................................................. 26 5. Reliability ..................................................................................................................................28 5.1 Contents of Reliability Tests ......................................................................................................... 28 5.2 Failure Check Standard ................................................................................................................ 28 6. Outgoing Quality Control Specifications ............................................................................ 29~32 6.1 Environment Required ................................................................................................................. 29 6.2 Sampling Plan ............................................................................................................................. 29 6.3 Criteria & Acceptable Quality Level ............................................................................................... 29 6.3.1 Cosmetic Check (Display Off) in Non-Active Area................................................................. 29 6.3.2 Cosmetic Check (Display Off) in Active Area........................................................................ 31 6.3.3 Pattern Check (Display On) in Active Area........................................................................... 32 7. Package Specifications..............................................................................................................33 8. Precautions When Using These OEL Display Modules ....................................................... 34~36 8.1 Handling Precautions ................................................................................................................... 34 8.2 Storage Precautions..................................................................................................................... 34 8.3 Designing Precautions ................................................................................................................. 35 8.4 Precautions when disposing of the OEL display modules ................................................................ 35 8.5 Other Precautions........................................................................................................................ 35 Warranty ........................................................................................................................................36 Notice .............................................................................................................................................36 1. Basic Specifications 1.1 Display Specifications 1) 2) 3) Display Mode Display Color Drive Duty : Passive Matrix : Area Color (Light Blue/White) : 1/64 Duty 1.2 Mechanical Specifications 1) 2) 3) 4) 5) 6) 7) 8) Outline Drawing : Number of Pixels : Module Size : Panel Size : Active Area : Pixel Pitch : Pixel Size : Weight : According to the annexed outline drawing 128 × 64 26.70 × 19.26 × 1.45 (mm) 26.70 × 19.26 × 1.45 (mm) including “Anti-Glare Polarizer” 21.744 × 10.864 (mm) 0.17 × 0.17 (mm) 0.154 × 0.154 (mm) 1.54 (g) ± 10% 1.3 Active Area / Memory Mapping & Pixel Construction P0.17x128-0.016=21.744 ( 0, 0 ) Driver IC Memory Mapping ( Full 128 x 64 ) "A" Segment 127 ( Column 1 ) Common 32 ( Row 63 ) Common 63 ( Row 1 ) Segment 0 ( 127, 63 ) ( Column 128 ) Common 0 ( Row 64 ) 0.17 0.154 P0.17x64-0.016=10.864 0.17 0.154 Common 31 ( Row 2 ) Detail "A" Scale (10:1) 26.7±0.2 (Panel Size) 26.7±0.2 (Cap Size) 25.7±0.5 (Polarizer) 23.74 (V/A) 21.74 (A/A) (10) P0.17x128-0.016=21.744 "A" (10.69) (8) 0.1 0.8± Glue Segment 0 ( Column 1 ) ( Column 128 ) Common 32 Common 0 ( Row 63 ) ( Row 64 ) Common 63 Common 31 ( Row 1 ) ( Row 2 ) 0.17 0.154 N.C . (GND) VCC Segment 127 2±0.3 0.1 0.154 0.17 12±0.2 16±0.1 (Alignment Mark) P0.70x(30-1)=20.3±0.05 (W0.40±0.03) Contact Side VLSS D6 D4 D2 D0 IREF VC OMH D7 D5 D3 R/W# E/R D# D1 BS2 RES# D/C# CS# VSS BS0 VDD BS1 C1P C2P VDDB N.C. C1N C2N Contact Side Protective Tape 15x8x0.05mm 2- φ N.C. (GND) (1.6) Polarizer t=0.2mm (20.86) (4) 4.75±0.2 (6.89) (11) 12±0.3 30 1 (1.6) P0.17x64-0.016=10.864 10.86 (A/A) 12.86 (V/A) 14.4±0.5 (Polarizer) 15.5±0.2 (Cap Size) 19.26±0.2 (Panel Size) (31.26) Active Area 0.96" 128 x 64 Pixels (0.85) (2.35) Remark Original Drawing 1.4±0.1 (5) Remove Tape t=0.15mm Max (2.1) (1.1) 0.55±0.5 0.5±0.5 (1.48) (2.48) Date 20150224 1.4 Mechanical Drawing Item A Detail "A" Scale (10:1) 22±0.2 Notes: 1. Color: Light Blue/White 2. Driver IC: SSD1306 3. FPC Number: UT-0206-P05 4. Interface: 8-bit 68XX/80XX Parallel, 3-/4-wire SPI, I2C 5. General Tolerance: ±0.30 6. The total thickness (1.5 Max) is without polarizer protective film & remove tape. The actual assembled total thickness with above materials should be 1.75 Max. Topwin Semiconductor Inc. Customer Approval Signature Symbol N.C. (GND) C2P C2N C1P C1N VDDB N.C. VSS VDD BS0 BS1 BS2 CS# RES# D/C# R/W# E/RD# D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VCC VLSS N.C. (GND) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Drawing Number DMX2864SDGFDU Unless Otherwise Specified Unit mm Title General Roughness Tolerance Dimension ±0.3 Angle ±1 By Date VG-2864KxxEG01 Folding Type OEL Display Module Pixel Number: 128 x 64, Monochrome, COG Package Drawn Jamie Chen 20150224 E.E. Ting-Kuo Hu 20150224 Panel / E. Gary Lin 20150224 P.M. Cherry Lin 20150224 Rev. A Material Soda Lime / Polyimide Scale 1:1 Sheet 1 of 1 Size A3 1. Basic Specifications 1.1 Display Specifications 1) 2) 3) Display Mode Display Color Drive Duty : Passive Matrix : Area Color (Light Blue & Yellow) : 1/64 Duty 1.2 Mechanical Specifications 1) 2) 3) 4) 5) 6) 7) 8) Outline Drawing : Number of Pixels : Module Size : Panel Size : Active Area : Pixel Pitch : Pixel Size : Weight : According to the annexed outline drawing 128 × 64 26.70 × 19.26 × 1.45 (mm) 26.70 × 19.26 × 1.45 (mm) including “Anti-Glare Polarizer” 21.744 × 10.864 (mm) 0.17 × 0.17 (mm) 0.154 × 0.154 (mm) 1.54 (g) ± 10% 1.3 Active Area / Memory Mapping & Pixel Construction P0.17x128-0.016=21.744 "A" P0.17x(64+2)-0.016=11.204 P0.17x16-0.016=2.704 P0.17x48-0.016=8.144 0.17x2+0.016=0.356 (0, 0) Segment 127 ( Column 1 ) Common 32 ( Row 63 ) Common 57 ( Row 17 ) Common 56 ( Row 15 ) Common 63 ( Row 1 ) 0.17 0.154 0.17 0.154 Detail "A" Scale (10:1) Yellow 128 x 16 Light Blue 128 x 48 Driver IC Memory Mapping (Full 128 x 64) Segment 0 ( Column 128 ) Common 0 ( Row 64 ) Common 23 ( Row 18 ) Common 24 ( Row 16 ) Common 31 ( Row 2 ) (127, 63) Item A Remark Original Drawing 26.7±0.2 (Panel Size) 26.7±0.2 (Cap Size) 25.7±0.5 (Polarizer) 23.744 (V/A) 21.744 (A/A) (10) (5) 1.4±0.1 P0.17x128-0.016=21.744 30 VCC Glue Light Blue 128 x 48 Segment 0 ( Column 1 ) ( Column 128 ) Common 32 Common 0 ( Row 63 ) ( Row 64 ) Common 57 Common 23 ( Row 17 ) ( Row 18 ) Common 24 Common 56 ( Row 16 ) ( Row 15 ) Common 31 Common 63 ( Row 2 ) ( Row 1 ) N.C. (GND) 2±0.3 4.75±0.2 P0.70x(30-1)=20.3±0.05 (W0.40±0.03) 22±0.2 Contact Side D6 Segment 127 VLSS VCOMH D4 D2 D0 R/W# I REF D7 D5 D3 D1 E/RD# B S2 R ES# D/C# CS# VSS VBAT B S0 BS1 VDD N.C. C 2P C 1P C1N Contact Side 0.1 0.8± (4) N.C. (GND) Protective Tape 15x8x0.05mm 2-φ 16±0.1 1 (1.6) 0.17x2+0.016=0.356 P0.17x48-0.016=8.144 P0.17x16-0.016=2.704 P0.17x(64+2)-0.016=11.204 (6.89) (11) 12±0.3 12±0.2 (1.6) Polarizer t=0.2mm (20.86) Active Area 0.96" 128 x 64 Pixels C2N Yellow 128 x 16 "A" (10.5) (8) 11.204 (A/A) 13.204 (V/A) 14.4±0.5 (Polarizer) 15.5±0.2 (Cap Size) 19.26±0.2 (Panel Size) (31.26) Remove Tape t=0.15mm Max (2.1) (1.1) 0.5±0.5 0.5±0.5 (1.48) (2.48) (0.85) (2.35) Date 20150313 0.17 0.154 0.1±0.03 0.154 0.17 Detail "A" Scale (10:1) Notes: 1. Color: Light Blue & Yellow 2. Driver IC: SSD1306 3. FPC Number: UT-0206-P05 4. Interface: 8-bit 68XX/80XX Parallel, 3-/4-wire SPI, I2C 5. General Tolerance: ±0.30 6. The total thickness (1.50 Max) is without polarizer protective film & remove tape. The actual assembled total thickness with above materials should be 1.75 Max. Customer Approval Signature Symbol N.C. (GND) C2P C2N C1P C1N VDDB N.C. VSS VDD BS0 BS1 BS2 CS# RES# D/C# R/W# E/RD# D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VCC VLSS N.C. (GND) Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Drawing Number Topwin Semiconductor Inc. DMX2864SDGFDW Unit mm Title VG-2864KMBEG01 Folding Type OEL Display Module Pixel Number: 128 x 64, Area Color (2), COG Package General Roughness Tolerance Dimension ±0.3 Angle ±1 By Date Drawn Jamie Chen 20150313 E.E. Ting Kuo Hu 20150313 Panel / E. Gary Lin 20150313 P.M. Tiffany Hsu 20150313 Rev. A Material Unless Otherwise Specified Soda Lime / Polyimide Scale 1:1 Sheet 1 of 1 Size A3 1.5 Pin Definition Pin Number Symbol I/O 9 VDD P 8 VSS P 28 VCC P 29 VLSS P 26 IREF I 27 VCOMH O Function Power Supply Power Supply for Logic This is a voltage supply pin. It must be connected to external source. Ground of Logic Circuit This is a ground pin. It acts as a reference for the logic pins. It must be connected to external ground. Power Supply for OEL Panel This is the most positive voltage supply pin of the chip. A stabilization capacitor should be connected between this pin and VSS when the converter is used. It must be connected to external source when the converter is not used. Ground of Analog Circuit This is an analog ground pin. It should be connected to VSS externally. Driver Current Reference for Brightness Adjustment This pin is segment current reference pin. A resistor should be connected between this pin and VSS. Set the current at 12.5µA maximum. Voltage Output High Level for COM Signal This pin is the input pin for the voltage output high level for COM signals. A capacitor should be connected between this pin and VSS. DC/DC Converter 6 VDDB P 4/5 2/3 C1P / C1N C2P / C2N I Power Supply for DC/DC Converter Circuit This is the power supply pin for the internal buffer of the DC/DC voltage converter. It must be connected to external source when the converter is used. It should be connected to VDD when the converter is not used. Positive Terminal of the Flying Inverting Capacitor Negative Terminal of the Flying Boost Capacitor The charge-pump capacitors are required between the terminals. They must be floated when the converter is not used. Interface 10 11 12 BS0 BS1 BS2 I 14 RES# I 13 CS# I 15 D/C# I 17 E/RD# I Communicating Protocol Select These pins are MCU interface selection input. See the following table: BS0 BS1 BS2 I2C 0 1 0 3-wire SPI 1 0 0 4-wire SPI 0 0 0 8-bit 68XX Parallel 0 0 1 8-bit 80XX Parallel 0 1 1 Power Reset for Controller and Driver This pin is reset signal input. When the pin is low, initialization of the chip is executed. Keep this pin pull high during normal operation. Chip Select This pin is the chip select input. The chip is enabled for MCU communication only when CS# is pulled low. Data/Command Control This pin is Data/Command control pin. When the pin is pulled high, the input at D7~D0 is treated as display data. When the pin is pulled low, the input at D7~D0 will be transferred to the command register. When the pin is pulled high and serial interface mode is selected, the data at SDIN will be interpreted as data. When it is pulled low, the data at SDIN will be transferred to the command register. In I2C mode, this pin acts as SA0 for slave address selection. For detail relationship to MCU interface signals, please refer to the Timing Characteristics Diagrams. Read/Write Enable or Read This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as the Enable (E) signal. Read/write operation is initiated when this pin is pulled high and the CS# is pulled low. When connecting to an 80XX-microprocessor, this pin receives the Read (RD#) signal. Data read operation is initiated when this pin is pulled low and CS# is pulled low. When serial or I2C mode is selected, this pin must be connected to VSS. 1.5 Pin Definition (Continued) Pin Number Symbol I/O Function Interface (Continued) 16 R/W# I 18~25 D0~D7 I/O 7 N.C. - 1, 30 N.C. (GND) - Read/Write Select or Write This pin is MCU interface input. When interfacing to a 68XX-series microprocessor, this pin will be used as Read/Write (R/W#) selection input. Pull this pin to “High” for read mode and pull it to “Low” for write mode. When 80XX interface mode is selected, this pin will be the Write (WR#) input. Data write operation is initiated when this pin is pulled low and the CS# is pulled low. When serial or I2C mode is selected, this pin must be connected to VSS. Host Data Input/Output Bus These pins are 8-bit bi-directional data bus to be connected to the microprocessor’s data bus. When serial mode is selected, D1 will be the serial data input SDIN and D0 will be the serial clock input SCLK. When I2C mode is selected, D2 & D1 should be tired together and serve as SDAout & SDAin in application and D0 is the serial clock input SCL. Unused pins must be connected to VSS except for D2 in serial mode. Reserve Reserved Pin The N.C. pin between function pins are reserved for compatible and flexible design. Reserved Pin (Supporting Pin) The supporting pins can reduce the influences from stresses on the function pins. These pins must be connected to external ground as the ESD protection circuit. 2. Absolute Maximum Ratings Parameter Symbol Min Max Unit Notes Supply Voltage for Logic VDD -0.3 4 V 1, 2 Supply Voltage for Display VCC 0 11 V 1, 2 Supply Voltage for DC/DC VDDB -0.3 5 V 1, 2 Operating Temperature TOP -40 70 °C Storage Temperature TSTG -40 85 °C 3 10,000 - hour 4 2 Life Time (100 cd/m ) Note 1: All the above voltages are on the basis of “VSS = 0V”. Note 2: When this module is used beyond the above absolute maximum ratings, permanent breakage of the module may occur. Also, for normal operations, it is desirable to use this module under the conditions according to Section 3. “Optics & Electrical Characteristics”. If this module is used beyond these conditions, malfunctioning of the module can occur and the reliability of the module may deteriorate. Note 3: The defined temperature ranges do not include the polarizer. temperature of the polarizer should be 80°C. The maximum withstood Note 4: End of lifetime is specified as 50% of initial brightness reached. The reference average operation life time at room temperature is estimated by the accelerated at high temperature conditions 3. Optics & Electrical Characteristics 3.1 Optics Characteristics Characteristics Symbol Conditions Min Typ Max Unit Lbr Note 8 100 120 - cd/m2 Lbr Note 12 80 100 - cd/m2 C.I.E. (Light Blue) (x) (y) C.I.E. 1931 0.12 0.22 0.16 0.26 0.20 0.30 Dark Room Contrast CR - >10,000:1 - - Free - degree Min Typ Max Unit 1.65 2.8 3.3 V 8.5 9.0 9.5 V Brightness (VCC Supplied Externally) Brightness (VCC Generated by Internal DC/DC) Viewing Angle * Optical measurement is taken at 25°C. Software configuration follows Section 4.5 Initialization. 3.2 DC Characteristics 3.2.1 VCC Supplied Externally: Characteristics Symbol Supply Voltage for Logic VDD Supply Voltage for Display (Supplied Externally) VCC High Level Input VIH 0.8×VDD - VDD V Low Level Input VIL 0 - 0.2×VDD V High Level Output VOH IOUT = 100µA, 3.3MHz 0.9×VDD - VDD V Low Level Output VOL IOUT = 100µA, 3.3MHz 0 - 0.1×VDD V Operating Current for VDD IDD - 180 300 µA Note 6 - 5.1 6.4 mA Note 7 - 7.3 9.1 mA Note 8 - 12.3 15.4 mA Operating Current for VCC (VCC Supplied Externally) ICC Conditions Note 5 (Internal DC/DC Disable) Sleep Mode Current for VDD IDD, SLEEP - 1 5 µA Sleep Mode Current for VCC ICC, SLEEP - 2 10 µA Note 5: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request. Note 6: VDD = 2.8V, VCC = 9.0V, 30% Display Area Turn on. Note 7: VDD = 2.8V, VCC = 9.0V, 50% Display Area Turn on. Note 8: VDD = 2.8V, VCC = 9.0V, 100% Display Area Turn on. * Software configuration follows Section 4.5.1 Initialization. 3.2.2 VCC Generated by internal DC/DC Circuit: Characteristics Symbol Supply Voltage for Logic VDD Supply Voltage for DC/DC VDDB Supply Voltage for Display (Generated by Internal DC/DC) VCC High Level Input Min Typ Max Unit 1.65 2.8 3.3 V Internal DC/DC Enable 3.0 - 4.2 V Note 9 (Internal DC/DC Enable) - 7.5 - V VIH 0.8×VDD - VDD V Low Level Input VIL 0 - 0.2×VDD V High Level Output VOH IOUT = 100µA, 3.3MHz 0.9×VDD - VDD V Low Level Output VOL IOUT = 100µA, 3.3MHz 0 - 0.1×VDD V Operating Current for VDD IDD - 180 300 µA Note 10 - 13.0 16.3 mA Note 11 - 18.8 23.5 mA Note 12 - 25.6 32.0 mA Operating Current for VDDB (VCC Generated by Internal DC/DC) IDDB Conditions Sleep Mode Current for VDD IDD, SLEEP - 1 5 µA Sleep Mode Current for VCC IDDB, SLEEP - 2 10 µA Note 9: Brightness (Lbr) and Supply Voltage for Display (VCC) are subject to the change of the panel characteristics and the customer’s request. Note 10: VDD = 2.8V, VDDB = 3.5V, VCC Generated by internal DC/DC circuit, 30% Display Area Turn on. Note 11: VDD = 2.8V, VDDB = 3.5V, VCC Generated by internal DC/DC circuit, 50% Display Area Turn on. Note 12: VDD = 2.8V, VDDB = 3.5V, VCC Generated by internal DC/DC circuit, 100% Display Area Turn on. * Software configuration follows Section 4.5.2 Initialization. 3.3 AC Characteristics 3.3.1 68XX-Series MPU Parallel Interface Timing Characteristics: Symbol tcycle Description Min Max Unit Clock Cycle Time 300 - ns tAS Address Setup Time 5 - ns tAH Address Hold Time 0 - ns tDSW Write Data Setup Time 40 - ns tDHW Write Data Hold Time 7 - ns tDHR Read Data Hold Time 20 - ns tOH Output Disable Time - 70 ns tACC Access Time - 140 ns - ns - ns PWCSL PWCSH Chip Select Low Pulse Width (Read) 120 Chip Select Low Pulse width (Write) 60 Chip Select High Pulse Width (Read) 60 Chip Select High Pulse Width (Write) 60 tR Rise Time - 40 ns tF Fall Time - 40 ns * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) 3.3.2 80XX-Series MPU Parallel Interface Timing Characteristics: Symbol Description Min Max Unit Clock Cycle Time 300 - ns tAS Address Setup Time 10 - ns tAH Address Hold Time 0 - ns tDSW Write Data Setup Time 40 - ns tDHW Write Data Hold Time 7 - ns tDHR Read Data Hold Time 20 - ns tOH Output Disable Time - 70 ns tACC Access Time - 140 ns tPWLR Read Low Time 120 - ns tPWLW Write Low Time 60 - ns tPWHR Read High Time 60 - ns tPWHW Write High Time 60 - ns tCS Chip Select Setup Time 0 - ns tCSH Chip Select Hold Time to Read Signal 0 - ns tCSF Chip Select Hold Time 20 - ns tcycle tR Rise Time - 40 ns tF Fall Time - 40 ns * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) ( Read Timing ) ( Write Timing ) 3.3.3 Serial Interface Timing Characteristics: (4-wire SPI) Symbol Description Min Max Unit Clock Cycle Time 100 - ns tAS Address Setup Time 15 - ns tAH Address Hold Time 15 - ns tCSS Chip Select Setup Time 20 - ns tCSH Chip Select Hold Time 10 - ns tDSW Write Data Setup Time 15 - ns tDHW Write Data Hold Time 15 - ns tCLKL Clock Low Time 20 - ns tCLKH Clock High Time 20 - ns tcycle tR Rise Time - 40 ns tF Fall Time - 40 ns * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) 3.3.4 Serial Interface Timing Characteristics: (3-wire SPI) Symbol Description Min Max Unit tcycle Clock Cycle Time 100 - ns tCSS Chip Select Setup Time 20 - ns tCSH Chip Select Hold Time 10 - ns tDSW Write Data Setup Time 15 - ns tDHW Write Data Hold Time 15 - ns tCLKL Clock Low Time 20 - ns tCLKH Clock High Time 20 - ns tR Rise Time - 40 ns tF Fall Time - 40 ns * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) 3.3.5 I2C Interface Timing Characteristics: Symbol tcycle tHSTART Description Min Max Unit Clock Cycle Time 2.5 - µs Start Condition Hold Time 0.6 - µs - ns Data Hold Time (for “SDAOUT” Pin) 0 Data Hold Time (for “SDAIN” Pin) 300 Data Setup Time 100 - ns tSSTART Start Condition Setup Time (Only relevant for a repeated Start condition) 0.6 - µs tSSTOP Stop Condition Setup Time 0.6 - µs tHD tSD tR Rise Time for Data and Clock Pin 300 ns tF Fall Time for Data and Clock Pin 300 ns - µs tIDLE Idle Time before a New Transmission can Start * (VDD - VSS = 1.65V to 3.3V, Ta = 25°C) 1.3 4. Functional Specification 4.1 Commands Refer to the Technical Manual for the SSD1306 4.2 Power down and Power up Sequence To protect OEL panel and extend the panel life time, the driver IC power up/down routine should include a delay period between high voltage and low voltage power sources during turn on/off. It gives the OEL panel enough time to complete the action of charge and discharge before/after the operation. 4.2.1 Power up Sequence: Power up VDD / VDDB Send Display off command Initialization Clear Screen Power up VCC Delay 100ms (When VCC is stable) 7. Send Display on command 1. 2. 3. 4. 5. 6. V DD / V DDB on B B B B V CC on B B Display on V CC B V DD/V DDB B B V SS /Ground B B Display off 4.2.2 Power down Sequence: 1. Send Display off command 2. Power down VCC / VDDB 3. Delay 100ms (When VCC / VDDB is reach 0 and panel is completely discharges) 4. Power down VDD V CC / V DDB off B B B B V DD off B B V CC/V DDB B B V DD B V SS /Ground B B Note 13: 1) Since an ESD protection circuit is connected between VDD and VCC inside the driver IC, VCC becomes lower than VDD whenever VDD is ON and VCC is OFF. 2) VCC / VDDB should be kept float (disable) when it is OFF. 3) Power Pins (VDD, VCC, VDDB) can never be pulled to ground under any circumstance. 4) VDD should not be power down before VCC / VDDB power down. 4.3 Reset Circuit When RES# input is low, the chip is initialized with the following status: 1. Display is OFF 2. 128×64 Display Mode 3. Normal segment and display data column and row address mapping (SEG0 mapped to column address 00h and COM0 mapped to row address 00h) 4. Shift register data clear in serial interface 5. Display start line is set at display RAM address 0 6. Column address counter is set at 0 7. Normal scan direction of the COM outputs 8. Contrast control register is set at 7Fh 9. Normal display mode (Equivalent to A4h command) 4.4 Application Circuit 4.4.1 68XX-Series MPU Parallel Interface and VCC Supplied Externally 4.4.2 68XX-Series MPU Parallel Interface and VCC Generated by Internal DC/DC Circuit 4.4.3 80XX-Series MPU Parallel Interface and VCC Supplied Externally 4.4.4 80XX-Series MPU Parallel Interface and VCC Generated by Internal DC/DC Circuit 4.4.5 4-wire Serial Interface and VCC Supplied Externally 4.4.6 4-wire Serial Interface and VCC Generated by Internal DC/DC Circuit 4.4.7 3-wire Serial Interface and VCC Supplied Externally 4.4.8 3-wire Serial Interface and VCC Generated by Internal DC/DC Circuit 4.4.9 I2C Interface and VCC Supplied Externally 4.4.10 I2C Interface and VCC Generated by Internal DC/DC Circuit 4.5 Actual Application Example Command usage and explanation of an actual example 4.5.1 VCC Supplied Externally VDD/VCC off State Set Display Offset 0xD3, 0x00 Set Entire Display On/Off 0xA4 Power up VDD (RES# as Low State) Set Display Start Line 0x40 Set Normal/Inverse Display 0xA6 Power Stabilized (Delay Recommended) Set Charge Pump 0x8D, 0x10 Clear Screen Set RES# as High (3µs Delay Minimum) Set Segment Re-Map 0xA1 Power up VCC & Stabilized (Delay Recommended) Initialized State (Parameters as Default) Set COM Output Scan Direction 0xC8 Set Display On 0xAF Set Display Off 0xAE Set COM Pins Hardware Configuration 0xDA, 0x12 (100ms Delay Recommended) Initial Settings Configuration Set Contrast Control 0x81, 0x9F Display Data Sent Set Display Clock Divide Ratio/Oscillator Frequency 0xD5, 0x80 Set Pre-Charge Period 0xD9, 0x22 Set Multiplex Ratio 0xA8, 0x3F Set VCOMH Deselect Level 0xDB, 0x40 If the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function.  Normal Operation Power down V CC (100ms Delay Recommended) Set Display Off 0xAE Power down VDD B B VDD/VCC off State Normal Operation Power down VCC Set Display Off 0xAE Sleep Mode Sleep Mode Set Display On 0xAF Power up VCC & Stabilized (Delay Recommended) (100ms Delay Recommended) Normal Operation 4.5.2 VCC Generated by Internal DC/DC Circuit VDD/VDDB off State Set Multiplex Ratio 0xA8, 0x3F Set Entire Display On/Off 0xA4 Power up VDD (RES# as Low State) Set Display Offset 0xD3, 0x00 Set Normal/Inverse Display 0xA6 Power Stabilized (Delay Recommended) Set Display Start Line 0x40 Clear Screen Power up VDDB (100ms Delay Recommended) Set Segment Re-Map 0xA1 Set Charge Pump 0x8D, 0x14 Set RES# as High (3µs Delay Minimum) Set COM Output Scan Direction 0xC8 Set Display On 0xAF Initialized State (Parameters as Default) Set COM Pins Hardware Configuration 0xDA, 0x12 Power Stabilized (100ms Delay Recommended) Set Display Off 0xAE Set Contrast Control 0x81, 0xCF Display Data Sent Initial Settings Configuration Set Pre-Charge Period 0xD9, 0xF1 Set Display Clock Divide Ratio/Oscillator Frequency 0xD5, 0x80 Set VCOMH Deselect Level 0xDB, 0x40 If the noise is accidentally occurred at the displaying window during the operation, please reset the display in order to recover the display function.  Normal Operation Power Stabilized (100ms Delay Recommended) Set Display Off 0xAE Power down V DDB (50ms Delay Recommended) Set Charge Pump 0x8D, 0x10 Power down VDD VDD/VDDB off State B Normal Operation Set Charge Pump 0x8D, 0x10 Set Display Off 0xAE Power down VDDB Sleep Mode Sleep Mode Set Charge Pump 0x8D, 0x14 Power Stabilized (100ms Delay Recommended) Power up VDDB (100ms Delay Recommended) Set Display On 0xAF Normal Operation 5. Reliability 5.1 Contents of Reliability Tests Item Conditions High Temperature Operation 70°C, 240 hrs Low Temperature Operation -40°C, 240 hrs High Temperature Storage 85°C, 240 hrs Low Temperature Storage -40°C, 240 hrs High Temperature/Humidity Operation 60°C, 90% RH, 120 hrs Thermal Shock -40°C ⇔ 85°C, 24 cycles 60 mins dwell Criteria The operational functions work. * The samples used for the above tests do not include polarizer. * No moisture condensation is observed during tests. 5.2 Failure Check Standard After the completion of the described reliability test, the samples were left at room temperature for 2 hrs prior to conducting the failure test at 23±5°C; 55±15% RH. 6. Outgoing Quality Control Specifications 6.1 Environment Required Customer’s test & measurement are required to be conducted under the following conditions: Temperature: 23 ± 5°C Humidity: 55 ± 15% RH Fluorescent Lamp: 30W Distance between the Panel & Lamp: ≥ 50cm Distance between the Panel & Eyes of the Inspector: ≥ 30cm Finger glove (or finger cover) must be worn by the inspector. Inspection table or jig must be anti-electrostatic. 6.2 Sampling Plan Level II, Normal Inspection, Single Sampling, MIL-STD-105E 6.3 Criteria & Acceptable Quality Level Partition AQL Definition Major 0.65 Defects in Pattern Check (Display On) Minor 1.0 Defects in Cosmetic Check (Display Off) 6.3.1 Cosmetic Check (Display Off) in Non-Active Area Check Item Classification Criteria X > 6 mm (Along with Edge) Y > 1 mm (Perpendicular to edge) X Panel General Chipping Y Minor X Y 6.3.1 Cosmetic Check (Display Off) in Non-Active Area (Continued) Check Item Classification Criteria Any crack is not allowable. Panel Crack Minor Copper Exposed (Even Pin or Film) Minor Film or Trace Damage Minor Terminal Lead Prober Mark Acceptable Glue or Contamination on Pin (Couldn’t Be Removed by Alcohol) Minor Ink Marking on Back Side of panel (Exclude on Film) Acceptable Not Allowable by Naked Eye Inspection Ignore for Any 6.3.2 Cosmetic Check (Display Off) in Active Area It is recommended to execute in clear room environment (class 10k) if actual in necessary. Check Item Classification Criteria Any Dirt & Scratch on Polarizer’s Protective Film Acceptable Ignore for not Affect the Polarizer Scratches, Fiber, Line-Shape Defect (On Polarizer) Minor Dirt, Black Spot, Foreign Material, (On Polarizer) Minor Dent, Bubbles, White spot (Any Transparent Spot on Polarizer) Minor Fingerprint, Flow Mark (On Polarizer) Minor W ≤ 0.1 Ignore W > 0.1 n≤1 L≤2 L>2 n=0 Φ ≤ 0.1 Ignore 0.1 < Φ ≤ 0.25 n≤1 0.25 < Φ n=0 Φ ≤ 0.5
Ignore if no Influence on Display 0.5 < Φ n=0 Not Allowable * Protective film should not be tear off when cosmetic check. ** Definition of W & L & Φ (Unit: mm): Φ = (a + b) / 2 L b: Minor Axis W a: Major Axis 6.3.3 Pattern Check (Display On) in Active Area Check Item Classification No Display Major Missing Line Major Pixel Short Major Darker Pixel Major Wrong Display Major Un-uniform Major Criteria 7. Package Specifications x 1 pcs (Empty) B pcs Tray with Vacuum Packing Module Sponge Protective x A pcs Staggered Stacking mm Tray (420mm x 285mm) C Set Primary Box Wrapped with Adhesive Tape x B pcs Vacuum Packing Bag Sponge Protective (370mm x 280mm x 20mm) Carton Box Primary Box (L450mm x W296mm x H110mm, B wave) x C Set Label Carton Box (Major / Maximum: L464mm x W313mm x H472mm, AB wave) Item Quantity Module 1080 per Primary Box Holding Trays (A) 20 per Primary Box Total Trays (B) 21 per Primary Box (Including 1 Empty Tray) Primary Box (C) 1~4 per Carton (4 as Major / Maximum) 8. Precautions When Using These OEL Display Modules 8.1 Handling Precautions 1) 2) 3) 4) 5) 6) Since the display panel is being made of glass, do not apply mechanical impacts such us dropping from a high position. If the display panel is broken by some accident and the internal organic substance leaks out, be careful not to inhale nor lick the organic substance. If pressure is applied to the display surface or its neighborhood of the OEL display module, the cell structure may be damaged and be careful not to apply pressure to these sections. The polarizer covering the surface of the OEL display module is soft and easily scratched. Please be careful when handling the OEL display module. When the surface of the polarizer of the OEL display module has soil, clean the surface. It takes advantage of by using following adhesion tape. * Scotch Mending Tape No. 810 or an equivalent Never try to breathe upon the soiled surface nor wipe the surface using cloth containing solvent such as ethyl alcohol, since the surface of the polarizer will become cloudy. Also, pay attention that the following liquid and solvent may spoil the polarizer: * Water * Ketone * Aromatic Solvents Hold OEL display module very carefully when placing OEL display module into the system housing. Do not apply excessive stress or pressure to OEL display module. And, do not over bend the film with electrode pattern layouts. These stresses will influence the display performance. Also, secure sufficient rigidity for the outer cases. 7) 8) 9) 10) Do not apply stress to the driver IC and the surrounding molded sections. Do not disassemble nor modify the OEL display module. Do not apply input signals while the logic power is off. Pay sufficient attention to the working environments when handing OEL display modules to prevent occurrence of element breakage accidents by static electricity. * Be sure to make human body grounding when handling OEL display modules. * Be sure to ground tools to use or assembly such as soldering irons. * To suppress generation of static electricity, avoid carrying out assembly work under dry environments. * Protective film is being applied to the surface of the display panel of the OEL display module. Be careful since static electricity may be generated when exfoliating the protective film. 11) Protection film is being applied to the surface of the display panel and removes the protection film before assembling it. At this time, if the OEL display module has been stored for a long period of time, residue adhesive material of the protection film may remain on the surface of the display panel after removed of the film. In such case, remove the residue material by the method introduced in the above Section 5). 12) If electric current is applied when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful to avoid the above. 8.2 Storage Precautions 1) When storing OEL display modules, put them in static electricity preventive bags avoiding exposure to direct sun light nor to lights of fluorescent lamps. and, also, avoiding high temperature and high 2) humidity environment or low temperature (less than 0°C) environments. (We recommend you to store these modules in the packaged state when they were shipped from Topwin Semiconductor Inc.) At that time, be careful not to let water drops adhere to the packages or bags nor let dewing occur with them. If electric current is applied when water drops are adhering to the surface of the OEL display module, when the OEL display module is being dewed or when it is placed under high humidity environments, the electrodes may be corroded and be careful about the above. 8.3 Designing Precautions 1) 2) 3) 4) 5) 6) 7) 8) The absolute maximum ratings are the ratings which cannot be exceeded for OEL display module, and if these values are exceeded, panel damage may be happen. To prevent occurrence of malfunctioning by noise, pay attention to satisfy the VIL and VIH specifications and, at the same time, to make the signal line cable as short as possible. We recommend you to install excess current preventive unit (fuses, etc.) to the power circuit (VDD). (Recommend value: 0.5A) Pay sufficient attention to avoid occurrence of mutual noise interference with the neighboring devices. As for EMI, take necessary measures on the equipment side basically. When fastening the OEL display module, fasten the external plastic housing section. If power supply to the OEL display module is forcibly shut down by such errors as taking out the main battery while the OEL display panel is in operation, we cannot guarantee the quality of this OEL display module. The electric potential to be connected to the rear face of the IC chip should be as follows: SSD1306 * Connection (contact) to any other potential than the above may lead to rupture of the IC. 8.4 Precautions when disposing of the OEL display modules 1) Request the qualified companies to handle industrial wastes when disposing of the OEL display modules. Or, when burning them, be sure to observe the environmental and hygienic laws and regulations. 8.5 Other Precautions 1) 2) 3) 4) 5) When an OEL display module is operated for a long of time with fixed pattern may remain as an after image or slight contrast deviation may occur. Nonetheless, if the operation is interrupted and left unused for a while, normal state can be restored. Also, there will be no problem in the reliability of the module. To protect OEL display modules from performance drops by static electricity rapture, etc., do not touch the following sections whenever possible while handling the OEL display modules. * Pins and electrodes * Pattern layouts such as the FPC With this OEL display module, the OEL driver is being exposed. Generally speaking, semiconductor elements change their characteristics when light is radiated according to the principle of the solar battery. Consequently, if this OEL driver is exposed to light, malfunctioning may occur. * Design the product and installation method so that the OEL driver may be shielded from light in actual usage. * Design the product and installation method so that the OEL driver may be shielded from light during the inspection processes. Although this OEL display module stores the operation state data by the commands and the indication data, when excessive external noise, etc. enters into the module, the internal status may be changed. It therefore is necessary to take appropriate measures to suppress noise generation or to protect from influences of noise on the system design. We recommend you to construct its software to make periodical refreshment of the operation statuses (re-setting of the commands and re-transference of the display data) to cope with catastrophic noise.