S-5712A/B/C Series
www.ablic.com
LOW VOLTAGE OPERATION
OMNIPOLAR / UNIPOLAR DETECTION TYPE
HALL EFFECT SWITCH IC
Rev.5.2_00
© ABLIC Inc., 2010-2021
This IC, developed by CMOS technology, is a high-accuracy Hall effect switch IC that operates at a low voltage and low
current consumption. The output voltage changes when this IC detects the intensity level of magnetic flux density. Using this
IC with a magnet makes it possible to detect the open / close in various devices.
High-density mounting is possible by using the small SOT-23-3 or the super-small SNT-4A package.
Due to its low voltage operation and low current consumption, this IC is suitable for battery-operated portable devices. Also,
due to its high-accuracy magnetic characteristics, this IC can make operation's dispersion in the system combined with
magnet smaller.
ABLIC Inc. offers a "magnetic simulation service" that provides the ideal combination of magnets and our Hall ICs for
customer systems. Our magnetic simulation service will reduce prototype production, development period and development
costs. In addition, it will contribute to optimization of parts to realize high cost performance.
For more information regarding our magnetic simulation service, contact our sales representatives.
Features
• Pole detection*1:
• Output logic*1:
• Output form*1:
• Magnetic sensitivity*1:
• Operating cycle (current consumption)*1:
• Power supply voltage range:
• Operation temperature range:
• Lead-free (Sn 100%), halogen-free
Detection of omnipolar, S pole or N pole
Active "L", active "H"
Nch open-drain output, CMOS output
BOP = 1.8 mT typ.
BOP = 3.0 mT typ.
BOP = 4.5 mT typ.
BOP = 7.0 mT typ.
Product with omnipolar detection
tCYCLE = 5.70 ms (IDD = 12.0 μA) typ.
tCYCLE = 50.50 ms (IDD = 2.0 μA) typ.
tCYCLE = 204.10 ms (IDD = 1.0 μA) typ.
Product with S pole or N pole detection
tCYCLE = 6.05 ms (IDD = 6.0 μA) typ.
tCYCLE = 50.85 ms (IDD = 1.4 μA) typ.
tCYCLE = 204.05 ms (IDD = 1.0 μA) typ.
VDD = 1.6 V to 3.5 V
Ta = −40°C to +85°C
*1. The option can be selected.
Applications
• Mobile phone, smart phone
• Notebook PC, tablet PC
• Digital video camera
• Plaything, portable game
• Home appliance
Packages
• SOT-23-3
• SNT-4A
1
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Block Diagrams
1. Nch open-drain output product
VDD
OUT
Sleep / Awake logic
*1
*1
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 1
2. CMOS output product
VDD
Sleep / Awake logic
*1
*1
OUT
Chopping
stabilized amplifier
VSS
*1. Parasitic diode
Figure 2
2
*1
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Product Name Structure
1. Product name
S-5712
x
x
x
x
x
-
xxxx
U
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package abbreviation and packing specifications*1
M3T1: SOT-23-3, Tape
I4T1:
SNT-4A, Tape
Magnetic sensitivity
0: BOP = 1.8 mT typ.
1: BOP = 3.0 mT typ.
2: BOP = 4.5 mT typ.
3: BOP = 7.0 mT typ.
Output logic
L: Active "L"
H: Active "H"
Pole detection
D: Detection of omnipolar
S: Detection of S pole
N: Detection of N pole
Output form
N: Nch open-drain output
C: CMOS output
Operating cycle
A: tCYCLE = 50.50 ms typ.
(Product with omnipolar detection)
tCYCLE = 50.85 ms typ.
(Product with S pole or N pole detection)
B: tCYCLE = 204.10 ms typ.
(Product with omnipolar detection)
tCYCLE = 204.05 ms typ.
(Product with S pole or N pole detection)
C: tCYCLE = 5.70 ms typ.
(Product with omnipolar detection)
tCYCLE = 6.05 ms typ.
(Product with S pole or N pole detection)
*1. Refer to the tape drawing.
2. Packages
Table 1 Package Drawing Codes
Package Name
SOT-23-3
SNT-4A
Dimension
MP003-C-P-SD
PF004-A-P-SD
Tape
MP003-C-C-SD
PF004-A-C-SD
Reel
MP003-Z-R-SD
PF004-A-R-SD
Land
−
PF004-A-L-SD
3
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
3. Product name list
3. 1 SOT-23-3
3. 1. 1 Nch open-drain output product
Table 2
Product Name
Operating Cycle
(tCYCLE)
S-5712ANDL0-M3T1U
S-5712ANDL1-M3T1U
S-5712ANDL2-M3T1U
S-5712ANSL1-M3T1U
S-5712ANSL2-M3T1U
S-5712ANSH1-M3T1U
S-5712BNDL2-M3T1U
S-5712BNDH2-M3T1U
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
204.10 ms typ.
204.10 ms typ.
Output Form
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Pole Detection
Omnipolar
Omnipolar
Omnipolar
S pole
S pole
S pole
Omnipolar
Omnipolar
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "L"
Active "H"
Magnetic Sensitivity
(BOP)
1.8 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
4.5 mT typ.
Remark Please contact our sales representatives for products other than the above.
3. 1. 2 CMOS output product
Table 3
Product Name
Operating Cycle
(tCYCLE)
S-5712ACDL0-M3T1U
S-5712ACDL1-M3T1U
S-5712ACDL2-M3T1U
S-5712ACDH1-M3T1U
S-5712ACDH2-M3T1U
S-5712ACSL1-M3T1U
S-5712ACSL2-M3T1U
S-5712ACNL1-M3T1U
S-5712ACNL2-M3T1U
S-5712BCDH2-M3T1U
S-5712CCDL1-M3T1U
S-5712CCSL1-M3T1U
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
204.10 ms typ.
5.70 ms typ.
6.05 ms typ.
Output Form
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
Pole Detection
Omnipolar
Omnipolar
Omnipolar
Omnipolar
Omnipolar
S pole
S pole
N pole
N pole
Omnipolar
Omnipolar
S pole
Remark Please contact our sales representatives for products other than the above.
4
Output Logic
Active "L"
Active "L"
Active "L"
Active "H"
Active "H"
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "L"
Active "L"
Magnetic Sensitivity
(BOP)
1.8 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
4.5 mT typ.
3.0 mT typ.
3.0 mT typ.
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
3. 2 SNT-4A
3. 2. 1 Nch open-drain output product
Table 4
Product Name
S-5712ANDL0-I4T1U
S-5712ANDL1-I4T1U
S-5712ANDL2-I4T1U
S-5712ANSL1-I4T1U
S-5712ANSL2-I4T1U
S-5712BNDL2-I4T1U
S-5712BNDH2-I4T1U
S-5712BNDH3-I4T1U
Operating Cycle
(tCYCLE)
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.85 ms typ.
50.85 ms typ.
204.10 ms typ.
204.10 ms typ.
204.10 ms typ.
Output Form
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Nch open-drain output
Pole Detection
Omnipolar
Omnipolar
Omnipolar
S pole
S pole
Omnipolar
Omnipolar
Omnipolar
Output Logic
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "H"
Magnetic Sensitivity
(BOP)
1.8 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
4.5 mT typ.
4.5 mT typ.
7.0 mT typ.
Remark Please contact our sales representatives for products other than the above.
3. 2. 2 CMOS output product
Table 5
Product Name
S-5712ACDL0-I4T1U
S-5712ACDL1-I4T1U
S-5712ACDL2-I4T1U
S-5712ACDL3-I4T1U
S-5712ACDH1-I4T1U
S-5712ACDH2-I4T1U
S-5712ACSL1-I4T1U
S-5712ACSL2-I4T1U
S-5712ACSL3-I4T1U
S-5712ACSH1-I4T1U
S-5712ACSH2-I4T1U
S-5712ACNL1-I4T1U
S-5712ACNL2-I4T1U
S-5712ACNL3-I4T1U
S-5712ACNH1-I4T1U
S-5712BCDL1-I4T1U
S-5712BCDL2-I4T1U
S-5712BCDH1-I4T1U
S-5712BCDH2-I4T1U
S-5712BCSL2-I4T1U
S-5712CCDL1-I4T1U
S-5712CCDL2-I4T1U
S-5712CCDH1-I4T1U
S-5712CCSL1-I4T1U
S-5712CCNL1-I4T1U
Operating Cycle
(tCYCLE)
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.50 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
50.85 ms typ.
Output Form
Pole Detection
Output Logic
Magnetic Sensitivity
(BOP)
5.70 ms typ.
5.70 ms typ.
5.70 ms typ.
6.05 ms typ.
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
CMOS output
Omnipolar
Omnipolar
Omnipolar
Omnipolar
Omnipolar
Omnipolar
S pole
S pole
S pole
S pole
S pole
N pole
N pole
N pole
N pole
Omnipolar
Omnipolar
Omnipolar
Omnipolar
S pole
Omnipolar
Omnipolar
Omnipolar
S pole
Active "L"
Active "L"
Active "L"
Active "L"
Active "H"
Active "H"
Active "L"
Active "L"
Active "L"
Active "H"
Active "H"
Active "L"
Active "L"
Active "L"
Active "H"
Active "L"
Active "L"
Active "H"
Active "H"
Active "L"
Active "L"
Active "L"
Active "H"
Active "L"
1.8 mT typ.
3.0 mT typ.
4.5 mT typ.
7.0 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
7.0 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
7.0 mT typ.
3.0 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
4.5 mT typ.
3.0 mT typ.
4.5 mT typ.
3.0 mT typ.
3.0 mT typ.
6.05 ms typ.
CMOS output
N pole
Active "L"
3.0 mT typ.
50.85 ms typ.
204.10 ms typ.
204.10 ms typ.
204.10 ms typ.
204.10 ms typ.
204.05 ms typ.
Remark Please contact our sales representatives for products other than the above.
5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Pin Configurations
1. SOT-23-3
Table 6
Top view
Pin No.
1
2
Symbol
Pin Description
1
VSS
GND pin
2
VDD
Power supply pin
3
OUT
Output pin
3
Figure 3
2. SNT-4A
Table 7
Top view
1
2
4
3
Figure 4
Pin No.
Symbol
1
VDD
Power supply pin
2
VSS
GND pin
3
NC*1
No connection
4
OUT
Output pin
*1. The NC pin is electrically open.
The NC pin can be connected to the VDD pin or the VSS pin.
6
Pin Description
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Absolute Maximum Ratings
Table 8
Item
Symbol
Power supply voltage
VDD
Output current
IOUT
Nch open-drain output product
Output voltage
VOUT
(Ta = +25°C unless otherwise specified)
Absolute Maximum Rating
Unit
VSS − 0.3 to VSS + 7.0
V
±1.0
mA
VSS − 0.3 to VSS + 7.0
V
VSS − 0.3 to VDD + 0.3
V
Operation ambient temperature
Topr
−40 to +85
°C
Storage temperature
Tstg
−40 to +125
°C
CMOS output product
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Thermal Resistance Value
Table 9
Item
Symbol
Condition
Board A
Board B
Board C
SOT-23-3
Board D
Board E
Junction-to-ambient thermal resistance*1 θJA
Board A
Board B
SNT-4A
Board C
Board D
Board E
*1. Test environment: compliance with JEDEC STANDARD JESD51-2A
Remark
Min.
−
−
−
−
−
−
−
−
−
−
Typ.
200
165
−
−
−
300
242
−
−
−
Max.
−
−
−
−
−
−
−
−
−
−
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Refer to " Power Dissipation" and "Test Board" for details.
7
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Electrical Characteristics
1. Product with omnipolar detection
1. 1 S-5712AxDxx
Table 10
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
2.0
3.50
4.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.10
50.40
50.50
−
−
100.00
ms
ms
ms
−
−
−
Average value
Nch open-drain
output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
1. 2 S-5712BxDxx
Table 11
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
8
Average value
Nch open-drain
output product
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
1.0
3.50
2.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.10
204.00
204.10
−
−
400.00
ms
ms
ms
−
−
−
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
1. 3 S-5712CxDxx
Table 12
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
12.0
3.50
22.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.10
5.60
5.70
−
−
12.00
ms
ms
ms
−
−
−
Average value
Nch open-drain
output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
2. Product with S pole or N pole detection
2. 1 S-5712AxSxx, S-5712AxNxx
Table 13
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Average value
Nch open-drain
output product
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
1.4
3.50
3.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
50.80
50.85
−
−
100.00
ms
ms
ms
−
−
−
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
9
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
2. 2 S-5712BxSxx, S-5712BxNxx
Table 14
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
1.0
3.50
2.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
204.00
204.05
−
−
400.00
ms
ms
ms
−
−
−
Average value
Nch open-drain
output product
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
2. 3 S-5712CxSxx, S-5712CxNxx
Table 15
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Symbol
Power supply voltage VDD
Current consumption IDD
Output voltage
VOUT
Leakage current
ILEAK
Awake mode time
Sleep mode time
Operating cycle
tAW
tSL
tCYCLE
10
Average value
Nch open-drain
output product
Condition
Min.
Typ.
Max.
Unit
−
1.60
−
1.85
6.0
3.50
11.0
V
μA
Test
Circuit
−
1
−
−
0.4
V
2
−
−
0.4
V
2
VDD −
0.4
−
−
V
3
−
−
1
μA
4
−
−
−
0.05
6.00
6.05
−
−
12.00
ms
ms
ms
−
−
−
Output transistor Nch,
IOUT = 0.5 mA
Output transistor Nch,
IOUT = 0.5 mA
CMOS output
product
Output transistor Pch,
IOUT = −0.5 mA
Nch open-drain output product
Output transistor Nch, VOUT = 3.5 V
−
−
tAW + tSL
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Magnetic Characteristics
1. Product with omnipolar detection
1. 1 Product with BOP = 1.8 mT typ.
Table 16
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
Release point*2
Hysteresis width*3
S pole
N pole
S pole
N pole
S pole
N pole
Symbol
BOPS
BOPN
BRPS
BRPN
BHYSS
BHYSN
Condition
−
−
−
−
BHYSS = BOPS − BRPS
BHYSN = |BOPN − BRPN|
Min.
0.6
−3.0
0.1
−2.4
−
−
Typ.
1.8
−1.8
1.1
−1.1
0.7
0.7
Max.
3.0
−0.6
2.4
−0.1
−
−
Unit
mT
mT
mT
mT
mT
mT
Test Circuit
5
5
5
5
5
5
1. 2 Product with BOP = 3.0 mT typ.
Table 17
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
Release point*2
Hysteresis width*3
S pole
N pole
S pole
N pole
S pole
N pole
Symbol
BOPS
BOPN
BRPS
BRPN
BHYSS
BHYSN
Condition
−
−
−
−
BHYSS = BOPS − BRPS
BHYSN = |BOPN − BRPN|
Min.
1.4
−4.0
1.1
−3.7
−
−
Typ.
3.0
−3.0
2.2
−2.2
0.8
0.8
Max.
4.0
−1.4
3.7
−1.1
−
−
Unit
mT
mT
mT
mT
mT
mT
Test Circuit
5
5
5
5
5
5
1. 3 Product with BOP = 4.5 mT typ.
Table 18
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
Release point*2
Hysteresis width*3
S pole
N pole
S pole
N pole
S pole
N pole
Symbol
BOPS
BOPN
BRPS
BRPN
BHYSS
BHYSN
Condition
−
−
−
−
BHYSS = BOPS − BRPS
BHYSN = |BOPN − BRPN|
Min.
2.5
−6.0
2.0
−5.5
−
−
Typ.
4.5
−4.5
3.5
−3.5
1.0
1.0
Max.
6.0
−2.5
5.5
−2.0
−
−
Unit
mT
mT
mT
mT
mT
mT
Test Circuit
5
5
5
5
5
5
1. 4 Product with BOP = 7.0 mT typ.
Table 19
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
Release point*2
Hysteresis width*3
S pole
N pole
S pole
N pole
S pole
N pole
Symbol
BOPS
BOPN
BRPS
BRPN
BHYSS
BHYSN
Condition
−
−
−
−
BHYSS = BOPS − BRPS
BHYSN = |BOPN − BRPN|
Min.
5.0
−8.5
3.7
−7.2
−
−
Typ.
7.0
−7.0
5.2
−5.2
1.8
1.8
Max.
8.5
−5.0
7.2
−3.7
−
−
Unit
mT
mT
mT
mT
mT
mT
Test Circuit
5
5
5
5
5
5
11
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
2. Product with S pole detection
2. 1 Product with BOP = 1.8 mT typ.
Table 20
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
Release point*2
S pole
Hysteresis width*3
S pole
Symbol
BOPS
BRPS
BHYSS
Condition
−
−
BHYSS = BOPS − BRPS
Min.
0.6
0.1
−
Typ.
1.8
1.1
0.7
Max.
3.0
2.4
−
Unit
mT
mT
mT
Test Circuit
5
5
5
2. 2 Product with BOP = 3.0 mT typ.
Table 21
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
*2
Release point
S pole
Hysteresis width*3
S pole
Symbol
BOPS
BRPS
BHYSS
Condition
−
−
BHYSS = BOPS − BRPS
Min.
1.4
1.1
−
Typ.
3.0
2.2
0.8
Max.
4.0
3.7
−
Unit
mT
mT
mT
Test Circuit
5
5
5
2. 3 Product with BOP = 4.5 mT typ.
Table 22
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
Release point*2
S pole
*3
Hysteresis width
S pole
Symbol
BOPS
BRPS
BHYSS
Condition
−
−
BHYSS = BOPS − BRPS
Min.
2.5
2.0
−
Typ.
4.5
3.5
1.0
Max.
6.0
5.5
−
Unit
mT
mT
mT
Test Circuit
5
5
5
2. 4 Product with BOP = 7.0 mT typ.
Table 23
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
S pole
Release point*2
S pole
Hysteresis width*3
S pole
12
Symbol
BOPS
BRPS
BHYSS
Condition
−
−
BHYSS = BOPS − BRPS
Min.
5.0
3.7
−
Typ.
7.0
5.2
1.8
Max.
8.5
7.2
−
Unit
mT
mT
mT
Test Circuit
5
5
5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
3. Product with N pole detection
3. 1 Product with BOP = 1.8 mT typ.
Table 24
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
N pole
Release point*2
N pole
Hysteresis width*3
N pole
Symbol
BOPN
BRPN
BHYSN
Condition
−
−
BHYSN = |BOPN − BRPN|
Min.
−3.0
−2.4
−
Typ.
−1.8
−1.1
0.7
Max.
−0.6
−0.1
−
Unit
mT
mT
mT
Test Circuit
5
5
5
3. 2 Product with BOP = 3.0 mT typ.
Table 25
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
N pole
Release point*2
N pole
Hysteresis width*3
N pole
Symbol
BOPN
BRPN
BHYSN
Condition
−
−
BHYSN = |BOPN − BRPN|
Min.
−4.0
−3.7
−
Typ.
−3.0
−2.2
0.8
Max.
−1.4
−1.1
−
Unit
mT
mT
mT
Test Circuit
5
5
5
3. 3 Product with BOP = 4.5 mT typ.
Table 26
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
N pole
Release point*2
N pole
*3
Hysteresis width
N pole
Symbol
BOPN
BRPN
BHYSN
Condition
−
−
BHYSN = |BOPN − BRPN|
Min.
−6.0
−5.5
−
Typ.
−4.5
−3.5
1.0
Max.
−2.5
−2.0
−
Unit
mT
mT
mT
Test Circuit
5
5
5
3. 4 Product with BOP = 7.0 mT typ.
Table 27
(Ta = +25°C, VDD = 1.85 V, VSS = 0 V unless otherwise specified)
Item
Operation point*1
N pole
Release point*2
N pole
Hysteresis width*3
N pole
Symbol
BOPN
BRPN
BHYSN
Condition
−
−
BHYSN = |BOPN − BRPN|
Min.
−8.5
−7.2
−
Typ.
−7.0
−5.2
1.8
Max.
−5.0
−3.7
−
Unit
mT
mT
mT
Test Circuit
5
5
5
*1. BOPN, BOPS: Operation points
BOPN and BOPS are the values of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux
density applied to this IC by the magnet (N pole or S pole) is increased (by moving the magnet closer).
Even when the magnetic flux density exceeds BOPN or BOPS, VOUT retains the status.
*2. BRPN, BRPS: Release points
BRPN and BRPS are the values of magnetic flux density when the output voltage (VOUT) changes after the magnetic flux
density applied to this IC by the magnet (N pole or S pole) is decreased (the magnet is moved further away).
Even when the magnetic flux density falls below BRPN or BRPS, VOUT retains the status.
*3. BHYSN, BHYSS: Hysteresis widths
BHYSN and BHYSS are the difference between BOPN and BRPN, and BOPS and BRPS, respectively.
Remark
The unit of magnetic density mT can be converted by using the formula 1 mT = 10 Gauss.
13
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Test Circuits
A
*1
R
100 kΩ
VDD
S-5712A/B/C
OUT
Series
VSS
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 5 Test Circuit 1
VDD
S-5712A/B/C
OUT
Series
VSS
A
V
Figure 6 Test Circuit 2
VDD
S-5712A/B/C
OUT
Series
VSS
A
V
Figure 7 Test Circuit 3
14
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
VDD
S-5712A/B/C
OUT
Series
VSS
A
V
Figure 8 Test Circuit 4
R*1
100 kΩ
VDD
S-5712A/B/C
Series OUT
VSS
V
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 9 Test Circuit 5
15
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Standard Circuit
R*1
100 kΩ
VDD
CIN
0.1 μF
S-5712A/B/C
OUT
Series
VSS
*1. Resistor (R) is unnecessary for the CMOS output product.
Figure 10
Caution The above connection diagram and constants will not guarantee successful operation. Perform
thorough evaluation using the actual application to set the constants.
16
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Operation
1. Direction of applied magnetic flux
This IC detects the flux density which is vertical to the marking surface.
Figure 11 and Figure 12 show the direction in which magnetic flux is being applied.
1. 1 SOT-23-3
1. 2 SNT-4A
N
S
N
S
Marking surface
Marking surface
Figure 11
Figure 12
2. Position of Hall sensor
Figure 13 and Figure 14 show the position of Hall sensor.
The center of this Hall sensor is located in the area indicated by a circle, which is in the center of a package as
described below.
The following also shows the distance (typ. value) between the marking surface and the chip surface of a package.
2. 1 SOT-23-3
2. 2 SNT-4A
Top view
Top view
The center of Hall sensor;
in this φ 0.3 mm
1
2
1
The center of Hall sensor;
in this φ 0.3 mm
4
2
3
3
0.16 mm typ.
0.7 mm typ.
Figure 13
Figure 14
17
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
3. Basic operation
This IC changes the output voltage level (VOUT) according to the level of the magnetic flux density (N pole or S pole)
applied by a magnet.
The following explains the operation when the output logic is active "L".
3. 1 Product with omnipolar detection
When the magnetic flux density vertical to the marking surface exceeds the operation point (BOPN or BOPS) after
the S pole or N pole of a magnet is moved closer to the marking surface of this IC, VOUT changes from "H" to "L".
When the S pole or N pole of a magnet is moved further away from the marking surface of this IC and the
magnetic flux density is lower than the release point (BRPN or BRPS), VOUT changes from "L" to "H".
Figure 15 shows the relationship between the magnetic flux density and VOUT.
VOUT
BHYSN
BHYSS
H
L
N pole
BOPN
BRPN
BRPS
0
BOPS
S pole
Magnetic flux density (B)
Figure 15
3. 2 Product with S pole detection
When the magnetic flux density vertical to the marking surface exceeds BOPS after the S pole of a magnet is
moved closer to the marking surface of this IC, VOUT changes from "H" to "L". When the S pole of a magnet is
moved further away from the marking surface of this IC and the magnetic flux density is lower than BRPS, VOUT
changes from "L" to "H".
Figure 16 shows the relationship between the magnetic flux density and VOUT.
VOUT
BHYSS
H
L
N pole
0
BRPS
Magnetic flux density (B)
Figure 16
18
BOPS
S pole
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
3. 3
Product with N pole detection
When the magnetic flux density vertical to the marking surface exceeds BOPN after the N pole of a magnet is
moved closer to the marking surface of this IC, VOUT changes from "H" to "L". When the N pole of a magnet is
moved further away from the marking surface of this IC and the magnetic flux density is lower than BRPN, VOUT
changes from "L" to "H".
Figure 17 shows the relationship between the magnetic flux density and VOUT.
VOUT
BHYSN
H
L
N pole
BOPN
0
BRPN
S pole
Magnetic flux density (B)
Figure 17
19
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
4. Time dependency in the current consumption
This IC performs the intermittent operation, and operates at low current consumption due to repeating the sleep mode
(tSL) and the awake mode (tAW).
Figure 18 shows the time dependency in the current consumption.
Operating cycle (tCYCLE)
Current consumption
Sleep mode time (tSL)
Awake mode time (tAW)
At awake mode
640 μA typ.
At sleep mode
0.72 μA typ.
Time
Figure 18
20
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
5. Timing chart
Figure 19 shows the operation timing of this IC.
BOPS
BRPS
Magnetic flux density
applied to this IC
BRPN
BOPN
Current consumption (IDD)
Output voltage (VOUT)
(Omnipolar detection,
active "L" product)
Output voltage (VOUT)
(S pole detection,
active "L" product)
Output voltage (VOUT)
(N pole detection,
active "L" product)
Output voltage (VOUT)
(Omnipolar detection,
active "H" product)
Figure 19
21
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
Precautions
• If the impedance of the power supply is high, the IC may malfunction due to a supply voltage drop caused by feedthrough current. Take care with the pattern wiring to ensure that the impedance of the power supply is low.
• Note that the IC may malfunction if the power supply voltage rapidly changes.
• Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
• Large stress on this IC may affect the magnetic characteristics. Avoid large stress which is caused by the handling
during or after mounting the IC on a board.
• ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
22
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Characteristics (Typical Data)
1. S-5712AxDxx
1. 1 Operation point, release point (BOP, BRP) vs. Temperature (Ta)
1. 1. 1 S-5712AxDx0
1. 1. 2 S-5712AxDx1
4.0
BOPS
2.0
BRPS
0.0
BRPN
−2.0
BOPN
−4.0
−6.0
−40 −25
0
25
Ta [°C]
50
BRPS
BRPN
0.0
−2.0
−4.0
BOPN
−40 −25
0
+25
Ta [°C]
4.0
2.0
BRPS
0.0
BRPN
−2.0
−4.0
BOPN
0
+25
Ta [°C]
+50
10.0
7.5
5.0
2.5
0.0
−2.5
−5.0
−7.5
−10.0
+50
+75 +85
+75 +85
VDD = 1.85 V
BOPS
BOP, BRP [mT]
6.0
BOP, BRP [mT]
2.0
1. 1. 4 S-5712AxDx3
VDD = 1.85 V
BOPS
−40 −25
BOPS
4.0
−6.0
75 85
1. 1. 3 S-5712AxDx2
−6.0
VDD = 1.85 V
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
BRPS
BRPN
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
1. 2 Operation point, release point (BOP, BRP) vs. Power supply voltage (VDD)
1. 2. 1 S-5712AxDx0
°C
4.0
BOPS
2.0
BRPS
0.0
−2.0
BOPN
−4.0
−6.0
BRPN
1.5
2.0
2.5
VDD [V]
3.0
2.0
BRPS
0.0
BRPN
−2.0
−4.0
BOPN
2.0
BRPS
BRPN
0.0
−2.0
−4.0
BOPN
1.5
2.0
2.5
VDD [V]
2.5
VDD [V]
3.0
10.0
7.5
5.0
2.5
0.0
−2.5
−5.0
−7.5
−10.0
3.5
3.0
3.5
Ta = +25°C
BOPS
BOP, BRP [mT]
BOP, BRP [mT]
BOPS
4.0
1.5
2.0
1. 2. 4 S-5712AxDx3
Ta = +25°C
6.0
−6.0
BOPS
4.0
−6.0
3.5
1. 2. 3 S-5712AxDx2
Ta = +25°C
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
1. 2. 2 S-5712AxDx1
BRPS
BRPN
BOPN
1.5
2.0
2.5
VDD [V]
3.0
3.5
23
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
1. 3 Current consumption (IDD)
vs. Temperature (Ta)
6.0
1. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
6.0
5.0
4.0
VDD = 3.0 V
3.0
2.0
VDD = 1.85 V
1.0
0.0
−40 −25
0
+25
Ta [°C]
+50
VDD = 3.0 V
1. 7
0
+25
Ta [°C]
+50
+25
Ta [°C]
3.5
+50
+75 +85
Ta = +25°C
Ta = +85°C
1.5
2.0
2.5
VDD [V]
3.0
3.5
1. 8 Sleep mode time (tSL)
vs. Power supply voltage (VDD)
100
Ta = −40°C
Ta = +25°C
60
40
Ta = +85°C
20
0
3.0
0
tSL [ms]
tSL [ms]
VDD = 3.0 V
−40 −25
2.5
VDD [V]
Ta = −40°C
80
20
24
2.0
100
VDD = 1.85 V
60
0
1.5
+75 +85
100
40
Ta = −40°C
50
Sleep mode time (tSL) vs. Temperature (Ta)
80
2.0
150
100
−40 −25
Ta = +25°C
1. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
VDD = 1.85 V
50
Ta = +85°C
3.0
0.0
tAW [μs]
tAW [μs]
150
4.0
1.0
+75 +85
1. 5 Awake mode time (tAW)
vs. Temperature (Ta)
200
0
IDD [μA]
IDD [μA]
5.0
0
1.5
2.0
2.5
VDD [V]
3.0
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
2. S-5712AxSxx, S-5712AxNxx
2. 1 Operation point, release point (BOP, BRP) vs. Temperature (Ta)
2. 1. 1 S-5712AxSx1
2. 1. 2 S-5712AxSx2
VDD = 1.85 V
4.0
BOPS
2.0
0.0
BRPS
−40 −25
0
+25
Ta [°C]
+50
BOPS
4.0
0.0
4.0
BRPS
2.0
0
+25
Ta [°C]
+50
+75 +85
BOP, BRP [mT]
6.0
−40 −25
+75 +85
VDD = 1.85 V
BRPN
−6.0
−40 −25
+25
Ta [°C]
0
+50
+75 +85
2. 1. 6 S-5712AxNx3
0.0
−2.0
BRPN
−4.0
BOPN
0
BOPN
−4.0
VDD = 1.85 V
−40 −25
+50
−2.0
+25
Ta [°C]
+50
+75 +85
VDD = 1.85 V
0.0
BOP, BRP [mT]
BOP, BRP [mT]
BOPS
2. 1. 5 S-5712AxNx2
BOP, BRP [mT]
+25
Ta [°C]
0
0.0
8.0
−6.0
−40 −25
2. 1. 4 S-5712AxNx1
10.0
0.0
BRPS
2.0
+75 +85
2. 1. 3 S-5712AxSx3
VDD = 1.85 V
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
−2.5
BRPN
−5.0
−7.5
−10.0
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
25
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
2. 2 Operation point, release point (BOP, BRP) vs. Power supply voltage (VDD)
2. 2. 1 S-5712AxSx1
2. 2. 2 S-5712AxSx2
Ta = +25°C
BOPS
4.0
2.0
BRPS
0.0
2.0
2.5
VDD [V]
3.0
2.0
2.5
VDD [V]
6.0
4.0
BRPS
2.0
0.0
2.0
2.5
VDD [V]
3.0
BOPN
−4.0
1.5
2.0
2.5
VDD [V]
3.0
3.5
2. 2. 6 S-5712AxNx3
Ta = +25°C
−2.0
BRPN
−4.0
BOPN
2.5
VDD [V]
3.0
3.5
Ta = +25°C
0.0
BOP, BRP [mT]
0.0
2.0
BRPN
−2.0
−6.0
3.5
2. 2. 5 S-5712AxNx2
1.5
3.5
Ta = +25°C
0.0
BOPS
8.0
1.5
3.0
2. 2. 4 S-5712AxNx1
BOP, BRP [mT]
BOP, BRP [mT]
1.5
°C
10.0
BOP, BRP [mT]
BRPS
2.0
3.5
2. 2. 3 S-5712AxSx3
26
BOPS
4.0
0.0
1.5
−6.0
Ta = +25°C
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
−2.5
BRPN
−5.0
−7.5
−10.0
BOPN
1.5
2.0
2.5
VDD [V]
3.0
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
2. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
6.0
5.0
5.0
4.0
4.0
3.0
VDD = 3.0 V
2.0
1.0
0.0
IDD [μA]
IDD [μA]
2. 3 Current consumption (IDD)
vs. Temperature (Ta)
6.0
0
+25
Ta [°C]
+50
2. 5 Awake mode time (tAW) vs. Temperature (Ta)
200
1.5
tAW [μs]
tAW [μs]
2. 7
VDD = 1.85 V
VDD = 3.0 V
−40 −25
0
+25
Ta [°C]
+50
3.5
Ta = +25°C
VDD = 3.0 V
−40 −25
0
+25
Ta [°C]
+50
+75 +85
3.0
3.5
Ta = +25°C
60
40
Ta = +85°C
20
20
2.5
VDD [V]
Ta = −40°C
80
60
2.0
2. 8 Sleep mode time (tSL)
vs. Power supply voltage (VDD)
100
VDD = 1.85 V
40
Ta = +85°C
1.5
tSL [ms]
tSL [ms]
Ta = −40°C
100
0
+75 +85
100
0
3.0
50
Sleep mode time (tSL) vs. Temperature (Ta)
80
2.5
VDD [V]
150
50
0
2.0
2. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
150
100
Ta = −40°C
0.0
+75 +85
Ta = +25°C
2.0
1.0
VDD = 1.85 V
−40 −25
Ta = +85°C
3.0
0
1.5
2.0
2.5
VDD [V]
3.0
3.5
27
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
3. S-5712BxDxx
3. 1 Operation point, release point (BOP, BRP) vs. Temperature (Ta)
3. 1. 1 S-5712BxDx1
3. 1. 2 S-5712BxDx2
VDD = 1.85 V
BOPS
4.0
2.0
BRPS
BRPN
0.0
−2.0
−4.0
−6.0
BOPN
−40 −25
0
+25
Ta [°C]
+50
VDD = 1.85 V
BOPS
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
4.0
2.0
BRPN
−2.0
−4.0
−6.0
+75 +85
BRPS
0.0
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
3. 1. 3 S-5712BxDx3
BOP, BRP [mT]
10.0
7.5
5.0
2.5
0.0
−2.5
−5.0
−7.5
−10.0
BOPS
BRPS
BRPN
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
3. 2 Operation point, release point (BOP, BRP) vs. Power supply voltage (VDD)
3. 2. 1 S-5712BxDx1
3. 2. 2 S-5712BxDx2
Ta = +25°C
4.0
2.0
BRPS
BRPN
0.0
−2.0
−4.0
−6.0
BOPN
1.5
2.0
2.5
VDD [V]
3.0
BOP, BRP [mT]
3. 2. 3 S-5712BxDx3
28
10.0
7.5
5.0
2.5
0.0
−2.5
−5.0
−7.5
−10.0
3.5
°C
BOPS
BRPS
BRPN
BOPN
1.5
2.0
2.5
VDD [V]
3.0
3.5
Ta = +25°C
6.0
BOPS
BOP, BRP [mT]
BOP, BRP [mT]
6.0
BOPS
4.0
2.0
BRPS
0.0
BRPN
−2.0
−4.0
−6.0
BOPN
1.5
2.0
2.5
VDD [V]
3.0
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
3. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
6.0
5.0
5.0
4.0
4.0
3.0
VDD = 3.0 V
2.0
1.0
0.0
−40 −25
0
+25
Ta [°C]
+50
100
VDD = 3.0 V
50
0
+25
Ta [°C]
+50
VDD = 3.0 V
VDD = 1.85 V
−40 −25
0
+25
Ta [°C]
+50
+75 +85
°C
2.0
2.5
VDD [V]
3.0
3.5
Ta = −40°C
Ta = +25°C
100
Ta = +85°C
0
+75 +85
Sleep mode time (tSL) vs. Temperature (Ta)
400
350
300
250
200
150
100
50
0
1.5
50
1.5
2.0
2.5
VDD [V]
3.0
3. 8 Sleep mode time (tSL)
vs. Power supply voltage (VDD)
400
350
− °C
300
250
200
150
100
50
0
1.5
2.0
2.5
3.0
VDD [V]
tSL [ms]
tSL [ms]
3. 7
−40 −25
+
−
150
VDD = 1.85 V
°C
3. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
tAW [μs]
tAW [μs]
150
+
2.0
0.0
+75 +85
200
3.0
1.0
VDD = 1.85 V
3. 5 Awake mode time (tAW) vs. Temperature (Ta)
0
IDD [μA]
IDD [μA]
3. 3 Current consumption (IDD)
vs. Temperature (Ta)
6.0
3.5
°C
°C
3.5
29
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
4. S-5712BxSxx, S-5712BxNxx
4. 1 Operation point, release point (BOP, BRP)
vs. Temperature (Ta)
4. 1. 1 S-5712BxSx2
4. 2. 1 S-5712BxSx2
VDD = 1.85 V
BOPS
4.0
BRPS
2.0
−40 −25
0
+25
Ta [°C]
+50
IDD [μA]
IDD [μA]
VDD = 3.0 V
2.0
1.0
−40 −25
0
+25
Ta [°C]
+50
tAW [μs]
tAW [μs]
VDD = 1.85 V
°C
+
°C
−
1.5
2.0
2.5
VDD [V]
150
50
3.0
3.5
Ta = −40°C
100
Ta = +25°C
50
VDD = 3.0 V
−40 −25
0
+25
Ta [°C]
+50
+75 +85
Sleep mode time (tSL) vs. Temperature (Ta)
1.5
4. 8
VDD = 3.0 V
VDD = 1.85 V
−40 −25
0
+25
Ta [°C]
+50
+75 +85
Ta = +85°C
0
tSL [ms]
tSL [ms]
+
2.0
4. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
150
30
4.0
3.0
0.0
+75 +85
200
400
350
300
250
200
150
100
50
0
3.5
3.0
1.0
VDD = 1.85 V
4. 5 Awake mode time (tAW) vs. Temperature (Ta)
4. 7
2.5
VDD [V]
5.0
3.0
0
2.0
4. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
6.0
4.0
100
BRPS
2.0
1.5
5.0
0.0
BOPS
4.0
0.0
+75 +85
4. 3 Current consumption (IDD)
vs. Temperature (Ta)
6.0
Ta = +25°C
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
0.0
4. 2 Operation point, release point (BOP, BRP)
vs. Power supply voltage (VDD)
2.0
2.5
VDD [V]
3.0
Sleep mode time (tSL)
vs. Power supply voltage (VDD)
400
350
− °C
300
250
+
200
150
+
100
50
0
1.5
2.0
2.5
3.0
VDD [V]
3.5
°C
°C
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
5. S-5712CxDxx
5. 1 Operation point, release point (BOP, BRP) vs. Temperature (Ta)
5. 1. 1 S-5712CxDx1
5. 1. 2 S-5712CxDx2
VDD = 1.85 V
BOPS
4.0
2.0
BRPS
BRPN
0.0
−2.0
−4.0
−6.0
BOPN
−40 −25
0
+25
Ta [°C]
+50
VDD = 1.85 V
BOPS
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
4.0
2.0
0.0
BRPN
−2.0
−4.0
−6.0
+75 +85
BRPS
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
5. 2 Operation point, release point (BOP, BRP) vs. Power supply voltage (VDD)
5. 2. 1 S-5712CxDx1
5. 2. 2 S-5712CxDx2
Ta = +25°C
2.0
BOP, BRP [mT]
BOPS
4.0
BRPS
BRPN
0.0
−2.0
−4.0
−6.0
BOPN
1.5
2.0
2.5
VDD [V]
3.5
3.0
5. 3 Current consumption (IDD)
vs. Temperature (Ta)
25
IDD [μA]
20
15
VDD = 1.85 V
2.0
BRPS
0.0
BRPN
−2.0
−4.0
−6.0
BOPN
1.5
2.0
−40 −25
0
+25
Ta [°C]
+50
2.5
VDD [V]
3.0
3.5
15
10
Ta = −40°C
5
5
0
BOPS
4.0
5. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
25
Ta = +85°C
Ta = +25°C
20
VDD = 3.0 V
10
Ta = +25°C
6.0
IDD [μA]
BOP, BRP [mT]
6.0
+75 +85
0
1.5
2.0
2.5
VDD [V]
3.0
3.5
31
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
5. 5 Awake mode time (tAW) vs. Temperature (Ta)
200
100
VDD = 3.0 V
50
0
5. 7
−40 −25
0
+25
Ta [°C]
+50
10
6
VDD = 3.0 V
2
32
2.0
0
+25
Ta [°C]
+50
+75 +85
3.0
3.5
Ta = −40°C
Ta = +25°C
8
6
4
Ta = +85°C
2
−40 −25
2.5
VDD [V]
5. 8 Sleep mode time (tSL)
vs. Power supply voltage (VDD)
12
VDD = 1.85 V
4
0
1.5
tSL [ms]
tSL [ms]
8
Ta = +85°C
0
+75 +85
12
Ta = +25°C
100
50
Sleep mode time (tSL) vs. Temperature (Ta)
10
Ta = −40°C
150
VDD = 1.85 V
tAW [μs]
tAW [μs]
150
5. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
0
1.5
2.0
2.5
VDD [V]
3.0
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
6. S-5712CxSxx, S-5712CxNxx
6. 1 Operation point, release point (BOP, BRP) vs. Temperature (Ta)
6. 1. 1 S-5712CxSx1
6. 1. 2 S-5712CxSx2
VDD = 1.85 V
4.0
BOPS
2.0
0.0
BRPS
−40 −25
0
+25
Ta [°C]
+50
VDD = 1.85 V
−2.0
BOPN
−4.0
0
−40 −25
0
+25
Ta [°C]
+50
+75 +85
+25
Ta [°C]
+50
VDD = 1.85 V
0.0
BOP, BRP [mT]
BOP, BRP [mT]
BRPN
−40 −25
BRPS
2.0
6. 1. 4 S-5712CxNx2
0.0
−6.0
BOPS
4.0
0.0
+75 +85
6. 1. 3 S-5712CxNx1
VDD = 1.85 V
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
−2.0
−4.0
−6.0
+75 +85
BRPN
BOPN
−40 −25
0
+25
Ta [°C]
+50
+75 +85
6. 2 Operation point, release point (BOP, BRP) vs. Power supply voltage (VDD)
6. 2. 1 S-5712CxSx1
6. 2. 2 S-5712CxSx2
Ta = +25°C
BOPS
4.0
2.0
BRPS
0.0
2.0
2.5
VDD [V]
3.0
BRPS
2.0
3.5
6. 2. 3 S-5712CxNx1
1.5
Ta = +25°C
−2.0
BOPN
−4.0
2.0
2.5
VDD [V]
3.0
3.5
2.5
VDD [V]
3.0
3.5
Ta = +25°C
0.0
BOP, BRP [mT]
BRPN
1.5
2.0
6. 2. 4 S-5712CxNx2
0.0
BOP, BRP [mT]
BOPS
4.0
0.0
1.5
−6.0
Ta = +25°C
6.0
BOP, BRP [mT]
BOP, BRP [mT]
6.0
−2.0
BRPN
−4.0
BOPN
−6.0
1.5
2.0
2.5
VDD [V]
3.0
3.5
33
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
S-5712A/B/C Series
Rev.5.2_00
10
VDD = 3.0 V
5
0
6. 4 Current consumption (IDD)
vs. Power supply voltage (VDD)
15
VDD = 1.85 V
−40 −25
0
+25
Ta [°C]
+50
IDD [μA]
IDD [μA]
6. 3 Current consumption (IDD)
vs. Temperature (Ta)
15
200
1.5
tAW [μs]
tAW [μs]
VDD = 1.85 V
−40 −25
0
+25
Ta [°C]
+50
3.5
Ta = +25°C
6
VDD = 3.0 V
−40 −25
0
+25
Ta [°C]
+50
+75 +85
3.0
3.5
Ta = +25°C
8
6
4
Ta = +85°C
2
2
2.5
VDD [V]
Ta = −40°C
10
8
2.0
6. 8 Sleep mode time (tSL)
vs. Power supply voltage (VDD)
12
VDD = 1.85 V
4
Ta = +85°C
1.5
tSL [ms]
tSL [ms]
Ta = −40°C
100
0
+75 +85
12
34
3.0
50
VDD = 3.0 V
Sleep mode time (tSL) vs. Temperature (Ta)
0
2.5
VDD [V]
150
100
10
2.0
6. 6 Awake mode time (tAW)
vs. Power supply voltage (VDD)
200
50
6. 7
5
0
150
0
Ta = +25°C
Ta = −40°C
+75 +85
6. 5 Awake mode time (tAW) vs. Temperature (Ta)
Ta = +85°C
10
0
1.5
2.0
2.5
VDD [V]
3.0
3.5
LOW VOLTAGE OPERATION OMNIPOLAR / UNIPOLAR DETECTION TYPE HALL EFFECT SWITCH IC
Rev.5.2_00
S-5712A/B/C Series
Power Dissipation
SOT-23-3
SNT-4A
Tj = +125°C max.
0.8
B
0.6
A
0.4
0.2
0.0
0
25
50
75
100
125
150
175
Tj = +125°C max.
1.0
Power dissipation (PD) [W]
Power dissipation (PD) [W]
1.0
0.8
0.6
B
0.4
A
0.2
0.0
0
25
Ambient temperature (Ta) [°C]
Board
A
B
C
D
E
Power Dissipation (PD)
0.50 W
0.61 W
−
−
−
50
75
100
125
150
175
Ambient temperature (Ta) [°C]
Board
A
B
C
D
E
Power Dissipation (PD)
0.33 W
0.41 W
−
−
−
35
SOT-23-3/3S/5/6 Test Board
IC Mount Area
(1) Board A
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
No. SOT23x-A-Board-SD-2.0
ABLIC Inc.
SNT-4A Test Board
IC Mount Area
(1) Board A
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
1
2
3
4
Thermal via
Specification
114.3 x 76.2 x t1.6
FR-4
2
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.070
-
(2) Board B
Item
Size [mm]
Material
Number of copper foil layer
Copper foil layer [mm]
Thermal via
1
2
3
4
Specification
114.3 x 76.2 x t1.6
FR-4
4
Land pattern and wiring for testing: t0.070
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.035
74.2 x 74.2 x t0.070
-
No. SNT4A-A-Board-SD-1.0
ABLIC Inc.
2.9±0.2
1
2
3
+0.1
0.16 -0.06
0.95±0.1
1.9±0.2
0.4±0.1
No. MP003-C-P-SD-1.1
TITLE
SOT233-C-PKG Dimensions
No.
MP003-C-P-SD-1.1
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.1
+0.25
ø1.0 -0
0.23±0.1
4.0±0.1
1.4±0.2
3.2±0.2
1
2
3
Feed direction
No. MP003-C-C-SD-2.0
TITLE
SOT233-C-Carrier Tape
No.
MP003-C-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.2±0.5
Enlarged drawing in the central part
ø13±0.2
No. MP003-Z-R-SD-1.0
SOT233-C-Reel
TITLE
MP003-Z-R-SD-1.0
No.
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
3,000
1.2±0.04
3
4
+0.05
0.08 -0.02
2
1
0.65
0.48±0.02
0.2±0.05
No. PF004-A-P-SD-6.0
TITLE
SNT-4A-A-PKG Dimensions
No.
PF004-A-P-SD-6.0
ANGLE
UNIT
mm
ABLIC Inc.
+0.1
ø1.5 -0
4.0±0.1
2.0±0.05
0.25±0.05
+0.1
1.45±0.1
2
1
3
4
ø0.5 -0
4.0±0.1
0.65±0.05
Feed direction
No. PF004-A-C-SD-2.0
TITLE
SNT-4A-A-Carrier Tape
No.
PF004-A-C-SD-2.0
ANGLE
UNIT
mm
ABLIC Inc.
12.5max.
9.0±0.3
Enlarged drawing in the central part
ø13±0.2
(60°)
(60°)
No. PF004-A-R-SD-1.0
TITLE
SNT-4A-A-Reel
No.
PF004-A-R-SD-1.0
QTY.
ANGLE
UNIT
mm
ABLIC Inc.
5,000
0.52
1.16
2
0.52
0.35
1.
2.
0.3
1
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
0.03 mm
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.10 mm to 1.20 mm).
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1.
2.
(0.25 mm min. / 0.30 mm typ.)
(1.10 mm ~ 1.20 mm)
TITLE
SNT-4A-A
-Land Recommendation
PF004-A-L-SD-4.1
No.
No. PF004-A-L-SD-4.1
ANGLE
UNIT
mm
ABLIC Inc.
Disclaimers (Handling Precautions)
1.
All the information described herein (product data, specifications, figures, tables, programs, algorithms and
application circuit examples, etc.) is current as of publishing date of this document and is subject to change without
notice.
2.
The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the reasons other than the products
described herein (hereinafter "the products") or infringement of third-party intellectual property right and any other
right due to the use of the information described herein.
3.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by the incorrect information described
herein.
4.
Be careful to use the products within their ranges described herein. Pay special attention for use to the absolute
maximum ratings, operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by failures and / or accidents, etc. due to
the use of the products outside their specified ranges.
5.
Before using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6.
When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7.
The products are strictly prohibited from using, providing or exporting for the purposes of the development of
weapons of mass destruction or military use. ABLIC Inc. is not liable for any losses, damages, claims or demands
caused by any provision or export to the person or entity who intends to develop, manufacture, use or store nuclear,
biological or chemical weapons or missiles, or use any other military purposes.
8.
The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses by
ABLIC, Inc. Do not apply the products to the above listed devices and equipments.
ABLIC Inc. is not liable for any losses, damages, claims or demands caused by unauthorized or unspecified use of
the products.
9.
In general, semiconductor products may fail or malfunction with some probability. The user of the products should
therefore take responsibility to give thorough consideration to safety design including redundancy, fire spread
prevention measures, and malfunction prevention to prevent accidents causing injury or death, fires and social
damage, etc. that may ensue from the products' failure or malfunction.
The entire system in which the products are used must be sufficiently evaluated and judged whether the products are
allowed to apply for the system on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc. The information
described herein does not convey any license under any intellectual property rights or any other rights belonging to
ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any part of this
document described herein for the purpose of disclosing it to a third-party is strictly prohibited without the express
permission of ABLIC Inc.
14. For more details on the information described herein or any other questions, please contact ABLIC Inc.'s sales
representative.
15. This Disclaimers have been delivered in a text using the Japanese language, which text, despite any translations into
the English language and the Chinese language, shall be controlling.
2.4-2019.07
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