Single-Chip 3-Axis Accelerometer
QMA6981
Advanced Information
The QMA6981 is a single chip three-axis accelerometer. This surface-mount, small
sized chip has an integrated acceleration transducer with signal conditioning ASIC,
sensing tilt, motion, shock and vibration. It is targeted for applications such as screen
rotation, step counting, sleep quality, gaming and personal navigation in mobile and
wearable smart devices.
The QMA6981 is based on our state-of-the-art, high resolution single crystal silicon
MEMS technology. Along with custom-designed 10-bit ADC ASIC, it offers the
advantages of low noise, high accuracy, low power consumption, and offset trimming.
The I²C serial bus allows for easy interface.
The QMA6981 is in a 2mmx2mmx0.95mm surface mount 12-pin land grid array (LGA) package.
FEATURES
BENEFIT
3
3-Axis Accelerometer in a 2x2x0.95 mm
Land Grid Array Package (LGA),
guaranteed to operate over a temperature
range of -40 °C to +85 °C.
Small size for highly integrated products.
Signals have been digitized and factory
trimmed.
10-Bit ADC with low noise accelerometer
sensor
High resolution allows for motion and tilt
sensing
2
I C Interface with Standard and Fast
modes.
High-Speed Interfaces for fast data
communications.
Built-In Self-Test
Enables low-cost functionality test after
assembly in production
Wide range operation voltage (2.4V To
3.6V) and low power consumption
(27-50A low power conversion current)
maintains
sensor’s
Automatically
sensitivity under wide operation voltage
range and compatible with battery
powered applications
Integrated FIFO with a depth of 32 frames
High Data-Read rate
RoHS compliant , halogen-free
Environmental
applications
Built–in motion algorithm
Low power and easy applications
including step counting, sleep quality,
gaming and personal navigation
protection
and
wide
矽睿
QMA6981
Datasheet
Rev: C
CONTENTS
CONTENTS .................................................................................................................................................................................... 2
1 INTERNAL SCHEMATIC DIAGRAM ................................................................................................................................ 3
1.1
Internal Schematic Diagram................................................................................................................................... 3
2 SPECIFICATIONS AND I/O CHARACTERISTICS ........................................................................................................... 4
2.1
Product Specifications ........................................................................................................................................... 4
2.2
Absolute Maximum Ratings .................................................................................................................................. 5
2.3
I/O Characteristics ................................................................................................................................................. 5
3 PACKAGE PIN CONFIGURATIONS .................................................................................................................................. 5
3.1
Package 3-D View ................................................................................................................................................. 5
3.2
Package Outlines .................................................................................................................................................... 6
4 EXTERNAL CONNECTION ................................................................................................................................................ 9
4.1
Dual Supply Connection ........................................................................................................................................ 9
4.2
Single Supply connection....................................................................................................................................... 9
5 BASIC DEVICE OPERATION ........................................................................................................................................... 10
5.1
Acceleration Sensors ................................................................................................................................................ 10
5.2
Power Management ............................................................................................................................................. 10
5.3
Power On/Off Time ............................................................................................................................................. 10
5.4
Communication Bus Interface I2C and Its Addresses .......................................................................................... 11
6 MODES OF OPERATION................................................................................................................................................... 12
6.1
Modes Transition ................................................................................................................................................. 12
6.2
Description of Modes ........................................................................................................................................... 13
7 Functions and interrupts ....................................................................................................................................................... 14
7.1
POL_INT ............................................................................................................................................................. 14
7.2
FOB_INT ............................................................................................................................................................. 14
7.3
STEP/STEP_QUIT INT....................................................................................................................................... 15
7.4
TAP_INT ............................................................................................................................................................. 16
7.5
LOW-G_INT ....................................................................................................................................................... 18
7.6
HIGH-G_INT....................................................................................................................................................... 18
7.7
DRDY_INT ......................................................................................................................................................... 18
7.8
FIFO_INT ............................................................................................................................................................ 19
7.9
Interrupt configuration ......................................................................................................................................... 20
8 I2C COMMUNICATION PROTOCOL ............................................................................................................................... 22
8.1
I2C Timings .......................................................................................................................................................... 22
8.2
I2C R/W Operation ............................................................................................................................................... 22
9 REGISTERS ......................................................................................................................................................................... 23
9.1
Register Map ........................................................................................................................................................ 23
9.2
Register Definition ............................................................................................................................................... 25
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
2 / 34
QMA6981
Datasheet
矽睿
1
Rev: C
INTERNAL SCHEMATIC DIAGRAM
1.1 Internal Schematic Diagram
Sinc
OS
GAIN
SDM
Transducer
CVA
INT1
Interrupt
LPF
INT2
VPM
OSC
AD0
BG
FIFO
I2C
SDA
SCL
RESV0
FSM
Reg File
GND
POWER
NVM
RESV1
POR
RESV2
VDD
GND
VDDIO
GNDIO
Figure 1.
Block Diagram
Table 1. Block Function
Block
Transducer
CVA
Interrupt
FIFO
FSM
I2C
OSC
Power
Function
3-axis acceleration sensor
Charge-to-Voltage amplifier for sensor signals
Digital interrupt engine, to generate interrupt signal on data conversion,
FIFO, and motion function
Embedded 32-level FIFO
Finite state machine, to control device in different mode
Interface logic data I/O
Internal oscillator for internal operation
Power block, including LDO
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
3 / 34
QMA6981
Datasheet
矽睿
Rev: C
2 SPECIFICATIONS AND I/O CHARACTERISTICS
2.1
Product Specifications
Table 2. Specifications (* Tested and specified at 25°C and 3.0V VDD except stated otherwise.)
Parameter
Supply voltage VDD
I/O voltage VDDIO
Standby current
Low power current
Low power current
Low power current
Low power current
Low power current
Full run current
Sleep current
Deep sleep current
BW
Data output rate
(ODR)
Conversion time
Startup time
Wakeup time
Conditions
VDD, for internal blocks
VDDIO, for IO only
VDD and VDDIO on
BW=500 Hz, ODR=1 Hz
BW=500 Hz, ODR=10 Hz
BW=500 Hz, ODR=20 Hz
BW=500 Hz, ODR=40 Hz
BW=500 Hz, ODR=100 Hz
All blocks on, device in run state
For analog, AFE is off, BG, Transducer
and oscillator are on or in low power
mode
For digital, only counter and FSM are
on
For analog, only BG and oscillator are
on
For digital, only counter and FSM are
on
Programmable bandwidth
Typ
3.3
2
27
29
31
37
50
220
4*BW (ODRH=1)
Max
3.6
VDD
300
From the time device enters into active
mode to the time device is ready for
conversion
Unit
V
V
μA
μA
μA
μA
μA
μA
μA
55
μA
26
μA
3.9~500
1/(4*BW)
Hz
Samples
/sec
ms
2
ms
1
ms
15.6~2000
in full speed
From the time when VDD reaches to
90% of final value to the time when
device is ready for conversion
Operating
temperature
-40
85
℃
±2
±4
±8
256
128
64
LSB/g
LSB/g
LSB/g
FS=±2g, Normal VDD Supplies
±0.02
%/℃
Gain accuracy
FS=±2g, Normal VDD Supplies
±5
±80
%
mg
FS=±2g, Normal VDD Supplies
±2
mg/℃
600
±0.5
μg/sqrtHz
%FS
Acceleration Full
Range
Sensitivity
Sensitivity
Sensitivity
Sensitivity
Temperature Drift
Sensitivity tolerance
Zero-g offset
Zero-g offset
Temperature Drift
Noise density
Nonlinearity
Min
2.4
1.7
FS=±2g
FS=±4g
FS=±8g
FS=±2g, run state
FS=±2g, Best fit straight line,
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
g
4 / 34
QMA6981
Datasheet
矽睿
Parameter
Cross Axis
Sensitivity
2.2
Conditions
Rev: C
Min
Typ
Max
Unit
1
%
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings (Tested at 25°C except stated otherwise.)
Parameters
VDD
VDDIO
ESD
Shock Immunity
Storage temperature
Condition
Min
-0.3
-0.3
HBM
Duration < 200μS
-50
Max
5.4
5.4
2
10000
150
Units
V
V
kV
g
℃
2.3 I/O Characteristics
Table 4. I/O Characteristics
Parameter
Voltage Input
High Level 1
Voltage Input
Low Level 1
Voltage Output
High Level
Voltage Output
Low Level
Symbol
VIH1
Pin
SDA, SCL
VIL1
SDA, SCL
VOH
INT1, INT2
VOL
INT1, INT2,
SDA
Condition
Output Current
≥-100μA
Output Current
≤100μA(INT)
Output Current
≤1mA (SDA)
Min.
0.7*VD
DIO
-0.3
TYP.
Max.
VDDIO+
0.3
0.3*VD
DIO
0.8*VD
DIO
Unit
V
V
V
0.2*VD
DIO
V
3 PACKAGE PIN CONFIGURATIONS
3.1 Package 3-D View
Arrow indicates direction of g field that generates a positive output reading in normal measurement configuration.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
5 / 34
QMA6981
Datasheet
矽睿
Rev: C
Z
X
QMA6981
1
AD0
VDD
IO
4
RES
V0
SCL
RES
V2
QMA6981
Y
11
Top View
SDA
12
INT
1
INT
2
5
6
RES
V1
10
GND
GND
IO
7
VDD
Figure 2. Package View
Table 5. Pin Configurations
PIN
No.
1
2
3
4
5
6
7
8
9
10
11
12
PIN
NAME
AD0
SDA
VDDIO
RESV0
INT1
INT2
VDD
GNDIO
GND
RESV1
RESV2
SCL
I/O
I
IO
I
O
O
IO
IO
I
Power
Supply
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDD
GND
GND
VDDIO
VDDIO
VDDIO
TYPE
Function
CMOS
CMOS
Power
CMOS
CMOS
CMOS
Power
Power
Power
CMOS
CMOS
CMOS
LSB of I2C address
Serial data for I2C
Power supply to digital interface
Reserved. Float or connect to GND
Interrupt 1
Interrupt 2
Power supply to internal block
Ground to digital interface
Ground to internal block
Reserved
Reserved
Serial clock for I2C
3.2 Package Outlines
3.2.1
Package Type
LGA (Land Grid Array)
3.2.2
Package Outline Drawing:
2.0mm (Length)*2.0mm (Width)*0.95mm (Height)
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
6 / 34
QMA6981
Datasheet
矽睿
TOP VIEW
Rev: C
DETAIL A
SIDE VIEW
BOTTOM VIEW
DETAIL B
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
7 / 34
QMA6981
Datasheet
矽睿
Rev: C
Figure 3. Package Outline Drawing
3.2.3
Marking:
Figure 4. Marking Format
Marking Text
Description
Comments
Line 1
Product Name
“6981” stand for QMA6981
Y: the last digital of year
CCC: lot code
Lot code: 3 alphanumeric digits, variable to generate mass
production trace-code
P: Part number
P: 1 alphanumeric digit, variable to identify part number
S: Sub-con ID
S: 1 alphanumeric digit, variable identify sub-con
Pin 1 identifier
--
Line 2
Line3
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
8 / 34
QMA6981
Datasheet
矽睿
4
4.1
Rev: C
EXTERNAL CONNECTION
Dual Supply Connection
Digital Power
1.7~3.6V
Power
2.2Kohm
SCL
SDA
SDA
VDD
IO
RES
V0
INT
1
RES
V2
QMA6981
C3=10nF
SCL
Top View
2.2Kohm
AD0
INT
2
Analog Power
2.4~3.6V
RES
V1
GND
GND
IO
VDD
C1=0.1uF
C2=2.2uF
Interrupt
Figure 5.
4.2
Dual Supply Connection
Single Supply connection
Figure 6. Single Supply Connection
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
9 / 34
QMA6981
Datasheet
矽睿
Rev: C
5 BASIC DEVICE OPERATION
5.1
Acceleration Sensors
The QMA6981 acceleration sensor circuit consists of tri-axial sensors and application specific support circuits to
measure the acceleration of device. When a DC power supply is applied to the sensor, the sensor converts any
accelerating incident in the sensitive axis directions to charge output.
5.2
Power Management
Device has two power supply pins. VDD is the main power supply for all of the internal blocks, including analog and
digital. VDDIO is a separate power supply, for digital interface only.
The device contains a power-on-reset generator. It generates reset pulse as power on, which can load the
register’s default value, for the device to function properly.
To make sure the POR block functions well, we should have such constrains on the timing of VDD and VDDIO.
The device should turn-on both power pins in order to operate properly. When the device is powered on, all
registers are reset by POR, then the device transits to the standby mode and waits for further commends.
Table 6 provides references for four power states.
Table 6． Power States
5.3
Power State
1
2
VDD
0V
0V
VDDIO
0V
1.7v~3.6v
3
4
2.4v~3.6v
2.4v~3.6v
0
1.7v~VDD
Power State description
Device Off, No Power Consumption
Not allowed. User need to make sure that VDDIO is
less than VDD. Otherwise, there will be leakage from
VDDIO to VDD through internal ESD devices
Device Off, Same Current as Standby Mode
Device On, Normal Operation Mode, Enters Standby
Mode after POR
Power On/Off Time
After the device is powered on, some time periods are required for the device fully functional. The external power
supply requires a time period for voltage to ramp up (PSUP), typically 50 milli-second. However it isn’t controlled
by the device. The Power–On–Reset time period (PORT) includes time to reset all the logics, load values in NVM
to proper registers, enter the standby mode and get ready for analogy measurements. The power on/off time
related to the device is in Table 7
Table 7. Time Required for Power On/Off
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
10 / 34
QMA6981
Datasheet
矽睿
Parameter
POR
Completion
Time
Symbol
PORT
Power off
Voltage
Power on
Interval
SDV
Power on Time
PSUP
PINT
Condition
Time Period After VDD and
VDDIO at Operating Voltage to
Ready for I2C Commend and
Analogy Measurement.
Voltage that Device Considers
to be Power Down.
Time Period Required for
Voltage Lower Than SDV to
Enable Next POR
Time Period Required for
Voltage from SDV to 90% of
final value
Rev: C
Min.
Typ.
Max.
250
Unit
μs
0.2
V
100
μs
50
ms
Figure 7. Power On/Off Timing
5.4
Communication Bus Interface I2C and Its Addresses
This device will be connected to a serial interface bus as a slave device under the control of a master device, such
as the processor. Control of this device is carried out via I²C.
This device is compliant with I²C -Bus Specification, document number: 9398 393 40011. As an I²C compatible
device, this device has a 7-bit serial address and supports I²C protocols. This device supports standard and fast
speed modes, 100 kHz and 400 kHz, respectively. External pull-up resistors are required to support all these
modes.
There are two I2C addresses selected by connecting pin 1 (AD0) to GND or VDDIO. The first six MSB are
hardware configured to “001001” and the LSB can be configured by AD0.
Table 8. I2C Address Options
AD0 (pin 1)
Connect to GND
Connect to VDDIO
I2C Slave Address(HEX)
12
13
I2C Slave Address(BIN)
0010010
0010011
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
11 / 34
QMA6981
Datasheet
矽睿
Rev: C
6 MODES OF OPERATION
6.1
Modes Transition
QMA6981 has two different operational modes, controlled by register (0x11), MODE_BIT. The main purpose of
these modes is for power management. The modes can be transited from one to another, as shown below, through
I2C commands. The default mode after power-on is standby mode.
Power Off
Reset
(POR or Soft Reset)
NVM Load
0x36=0xB6
Standby
0x11=1
0x33=1
Active
0x11=0
0x36=0xB6
Figure 8. Basic operation flow after power-on
The default mode after power on is standby mode. Through I2C instruction, device can switch between standby
mode and active mode. With SOFTRESET by writing 0xB6 into register 0x36, all of the registers will get default
values. SOFTRESET can be done both in active mode and in standby mode. Also, by writing 1 in NVM_LOAD
(0x33) when device is in active mode, the NVM related image registers will get default value from NVM,
however, other registers will keep the values of their own.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
12 / 34
QMA6981
Datasheet
矽睿
Rev: C
Reset
(POR or Soft Reset)
NVM Load
0x36=0xB6
Standby
0x11=1
0x33=1
Active
0x11=0
0x36=0xB6
Figure 9. The work mode transferring
6.2 Description of Modes
6.2.1
Active Mode
In active mode, there are two states, run state, and sleep state.
6.2.1.1
Sleep State
In sleep state, whole signal chain is off, including analog and digital signal conditioning, and the rest blocks are on.
6.2.1.2
Run State
In run state, the ADC digitizes the charge signals from transducer, and digital signal processor conditions these
signals in digital domain, processes the interrupts, and send data to FIFO (accessible through register 0x3F) and
Data registers (0x01~0x06). After the signal conditioning, the signal chain will be off and device enters back into
sleep state, leaves timer and FSM on. Also in sleep state, reference and power blocks are on.
This mode can also be called as power cycling. The power cycling duty is configurable through state registers
SLEEP_DUR (0x11). Device can enter into active mode by setting MODE_BIT (0x11) to logic 1.
Besides the power cycling, device can also be configured as FULLRUN, by setting SLEEP_DUR=0000b. In this
setting, no sleep state in the active mode, and device consumes most power, deliver the data most frequently.
6.2.2
Standby Mode
In standby mode, most of the blocks are off, while device is ready for access through I2C. Standby mode is the
default mode after power on or soft reset. Device can enter into this mode by set the soft reset register (0x36) to
0xB6 or set the MODE_BIT (0x11) to logic 0.
Besides the above two modes, the device also contains NVM loading state. This state is used to reset the value of
the NVM related image registers. There are two bits related to this state. When NVM_LOAD (0x33) is set to 1,
NVM loading starts. When the device is in NVM loading state, NVM_RDY (0x33) is set to logic 0 by device.
After NVM loading is finished, NVM_RDY (0x33) is set back to logic 1 by device, and NVM_LOAD is reset to 0
by device automatically. NVM loading can only happen when NVM_LOAD is set to 1 in active mode. If the user
sets this NVM_LOAD bit to 1 in standby mode, the device will not take the action until it enters into active state by
setting MODE_BIT (0x11) to logic 1.
After loading NVM, the device will enter into standby mode directly.
The loading time for NVM is about 100uS.
The information contained herein is the exclusive property of QST, and shall not be distributed,
reproduced, or disclosed in whole or in part without prior written permission of QST.
13 / 34
QMA6981
Datasheet
矽睿
Rev: C
7 Functions and interrupts
ASIC support interrupts, such as POL_INT, FOB_INT, STEP_INT, TAP_INT, LOW-G, HIGH-G, DRDY_INT, and
FIFO_INT.
7.1 POL_INT
The POL_INT stands for Portrait or Landscape interrupt. It responds to the device in portrait direction or landscape
direction. It includes 4 different event types, left, right, up and down events. The different type event stored and can
be read from register ORIENT (0x0D).
POLA(0x0D)
000
001
010
101
110
Left
0
1
0
0
0
Right
0
0
1
0
0
Down
0
0
0
1
0
Up
0
0
0
0
1
comments
unknown
Left/Landscape
Right/Landscape
Down/portrait
Up/portrait
All different events can be detected by comparing the threshold set by register UD_X_TH(0x2D),RL_Y_TH(0x2F)
with the sensor data , also have dependency on comparing result between the Z sensor readings and the register
UD_Z_TH(0x2C) and RL_Z_TH(0x2E). Hysteresis can be introduced to the angle by decreasing a small offset for
the threshold registers. All angle data inside the Hysteresis area will be regarded as unknown status in the orient
status register (0x0D).
Below Table shows the condition four kinds of orient events generation, the default threshold for X, Y is set to 40
degrees
Event
Up
Down
Right
Left
X
|X|>UD_X_TH
|X|>UD_X_TH
Y
X 0
|Y|>RL_Y_TH
|Y|>RL_Y_TH
Y 0
Z
|Z|
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