PT24C02

PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Features Wide Voltage Operation 1 MHz (5V), 400 kHz (1.7V, 2.5V, 2.7V) Compatibility - VCC = 1.7V to 5.5V Write Protect Pin for Hardware Data Protection Operating Ambient Temperature: -40℃ to +85℃ 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes Internally Organized: Partial Page Writes Allowed - PT24 C02, 256 X 8 (2K bits) Self-timed Write Cycle (5 ms max) - PT24 C04, 512 X 8 (4K bits) High-reliability - PT24 C08, 1024 X 8 (8K bits) - Endurance: 1 Million Write Cycles - PT24 C16, 2048 X 8 (16K bits) - Data Retention: 100 Years Two-wire Serial Interface 8-lead PDIP/SOP/TSSOP Packages Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol General Description The PT24 C02/PT24 C04/PT24 C08/PT24 C16 provides 2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The PT24 C02/PT24 C04/PT24 C08/PT24 C16 is available in space-saving 8-lead PDIP, 8-lead SOP, 8-lead TSSOP packages and is accessed via a two-wire serial interface. Pin Configuration Table 1: Pin Configuration Pin Name Founctions A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground VCC Power Supply 8- le ad P DI P 8- le ad S O P 8- l ea d TS S O P A0 1 8 VCC A0 1 8 VCC A0 1 8 VCC A1 2 7 WP A1 2 7 WP A1 2 7 WP A2 3 6 SCL A2 3 6 SCL A2 3 6 SCL GND 4 5 SDA GND 4 5 SDA GND 4 5 SDA - 1- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Block Diagram VCC GND WP SCL START STOP LOGIC SDA EN SERIAL CONTROL LOGIC HIGH VOLTAGE PUMP/TIMING LOAD COMP DATA RECOVERY DEVICE ADDRESS COMPARATOR INC A1 DATA WORD ADDRESS COUNTER A2 Y DECODER DIN X DECODER LOAD A0 EEPROM SERIAL MUX DOUT/ACKNOWLEDGE DOUT - 2- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Pin Descriptions DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the PT24 C02. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The PT24 C04 uses the A2 and A1 inputs for hard wire addressing and a total of four 4K devices may be addressed on a single bus system. The A0 pin is a no connect and can be connected to ground. The PT24 C08 only uses the A2 input for hardwire addressing and a total of two 8K devices may be addressed on a single bus system. The A0 and A1 pins are no connects and can be connected to ground. The PT24 C16 does not use the device address pins, which limits the number of devices on a single bus to one. The A0, A1, and A2 pins are no connects and can be connected to ground. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The PT24 C02/PT24 C04/PT24 C08/PT24 C16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in the following Table 2: Write Protect Part of the Array Protected WP Pin Status At VCC PT24 C02 Full (2K) Array At GND PT24 C04 PT24 C08 PT24 C16 Full (4K) Array Full (8K) Array Full (16K) Array Normal Read / Write Operations Memory Organization PT24 C02, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. PT24 C04, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. PT24C08, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. PT24 C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. - 3- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see to Figure 1 on page 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2 on page 4). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 2 on page 4). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The PT24 C02/PT24 C04/PT24 C08/PT24 C16 features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: 1. Clock up to 9 cycles. 2. Look for SDA high in each cycle while SCL is high. 3. Create a start condition. Figure 1: Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Figure 2: Start and Stop Definition SDA SCL START STOP - 4- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Figure 3: Output Acknowledge 1 SCL 8 9 DATA IN DATA OUT START ACKNOWLEDGE Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corresponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 bit must compare to its corresponding hard-wired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. - 5- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7). The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last accessed address, and incremented by one.* This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). * For 16K EEPROM, we also provide special addressing product for certain applications, that is, . only lower 8 bits of the internal data word address counter maintains the last the device address input at each current address read. accessed address, the higher 3 bits (P2, P1, P0) will follow So, please contact y our dealer for special ordering. - 6- 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Read Operations RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 8 on page 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9 on page 8). Figure 4: Device Address 2K 1 0 1 0 A2 A1 A0 R/W MSB LSB 4K 1 0 1 0 A2 A1 P0 R/W 8K 1 0 1 0 A2 P1 P0 R/W 16K 1 0 1 0 P2 P1 P0 R/W Figure 5: Byte Write S T A R DEVICE T ADDRESS W R I T E WORD ADDRESS S T O P DATA SDA LINE M S B L R AM S / CS B WK B LA SC BK A C K Figure 6: Page Write W S T R A I R DEVICE T ADDRESS T E WORD ADDRESS DATA ( n ) S T O P DATA ( n+x ) DATA ( n+1 ) SDA LINE M S B L R AM S / CS BWK B LA SC BK A C K - 7- A C K A C K 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Figure 7: Current Address Read S T A R DEVICE T ADDRESS R E A D S T O P DATA SDA LINE N O LRA S/C BWK M S B A C K Figure 8: Random Read S W T R A I R DEVICE T T ADDRESS E S T A R DEVICE T ADDRESS WORD ADDRESS R E A D S T O P DATA SDA LINE M S B L R AM S / CS BWK B LA SC BK M S B N O LRA S /C BWK A C K DUMMY WRITE Figure 9: Sequential Read R E DEVICE A ADDRESS D DATA ( n ) DATA ( n+1 ) DATA ( n+2 ) S T O P DATA ( n+x ) SDA LINE RA /C WK A C K A C K - 8- A C K N O A C K 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Electrical Characteristics Absolute Maximum Stress Ratings Comments Stresses above those listed under "Absolute Maximum Ratings" DC Supply Voltage . . . . . . . . . . . . . . . . .-0.3V to +6.5V may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any Input / Output Voltage . . . . . . . .GND-0.3V to VCC+0.3V other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the Operating Ambient Temperature . . . . . -40℃ to +85℃ absolute maximum rating conditions for extended periods may affect device reliability. Storage Temperature . . . . . . . . . . . . -65℃ to +150℃ DC Electrical Characteristics Applicable over recommended operating range from: TA = -40℃ to +85℃,VCC = +1.7V to +5.5V (unless otherwise noted) Symbol Min. Typ. Max. Unit Supply Voltage Parameter VCC 1.7 - 5.5 V Condition Supply Current V CC = 5.0V ICC1 - 0.4 1.0 mA READ at 400 kHz Supply Current V CC = 5.0V ICC2 - 2.0 3.0 mA WRITE at 400 kHz Standby Current ISB - - 3.0 A VIN = VCC or GND Input Leakage Current ILI - - 3.0 A VIN = VCC or GND Output Leakage Current ILO - 0.05 3.0 A VOUT = VCC or GND Input Low Level VIL1 -0.3 - VCC x 0.3 V VCC = 1.8V to 5.5V Input High Level VIH1 VCC x 0.7 - VCC + 0.3 V VCC = 1.8V to 5.5V Input Low Level VIL2 -0.3 - VCC x 0.2 V Input High Level VIH2 VCC x 0.7 - VCC + 0.3 V Output Low Level V CC =5.0V VOL3 - - 0.4 V IOL = 3.0 mA Output Low Level V CC =3.0V VOL2 - - 0.4 V IOL = 2.1 mA Output Low Level V CC =1.7V VOL1 - - 0.2 V IOL = 0.15 mA V CC = 1.7V V CC = 1.7V Pin Capacitance Applicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Input/Output Capacitance (SDA) CI/O Input Capacitance (A0, A1, A2, SCL) CIN Min. - Typ. - - 9- Max. Unit Condition 8 pF VI/O = 0V 6 pF VIN = 0V 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) AC Electrical Characteristics Applicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.7v < Vcc < 2.5v Parameter Symbol 2.5v < Vcc < 5.5v Units Min. Typ. Max. Min. Typ. Max. fSCL - - 400 - - 1000 kHz Clock Pulse Width Low tLOW 1.2 - - 0.6 - - s Clock Pulse Width High tHIGH 0.6 - - 0.4 - - s Noise Suppression Time tI - - 50 - - 40 ns Clock Low to Data Out Valid tAA 0.05 - 0.9 0.05 - 0.55 s Time the bus must be free before a new transmission can start tBUF 1.2 - - 0.5 - - s tHD.STA 0.6 - - 0.25 - - s Start Setup Time tSU.STA 0.6 - - 0.25 - - s Data In Hold Time tHD.DAT 0 - - 0 - - s Data In Setup Time tSU.DAT 100 - - 100 - - ns Inputs Rise Time(1) tR - - 0.3 - - 0.3 s Clock Frequency, SCL Start Hold Time tF - - 300 - - 100 ns tSU.STO 0.6 - - 0.25 - - s Data Out Hold Time tDH 50 - - 50 - - ns Write Cycle Time tWR - 1.5 5 - 1.5 5 ms Endurance 1M - - - - - Write Cycles Inputs Fall Time(1) Stop Setup Time 5.0V, 25℃, Byte Mode Note - 10 - 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) Bus Timing Figure 10: SCL: Serial Clock, SDA: Serial Data I/O tHIGH tF tLOW tR tLOW SCL tSU.STA tHD.STA tHD.DAT tSU.DAT tSU.STO SDA_IN tAA tDH tBUF SDA_OUT Write Cycle Timing Figure 11: SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK tWR(1) START CONDITION STOP CONDITION Note 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. - 11 - 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) 8-lead PDIP package diagram D 1 eA E1 eC c eB N Top View End View COMMON DIMENSIONS A3 (Unit of Measure = mm) A2 SYMBOL A1 B b L B e B1 MIN MAX A 3.60 4.00 A1 0.51 - A2 3.10 3.50 A3 1.50 1.70 b 0.44 0.53 b1 0.43 0.48 B Side View 1.52 BSC c 0.25 0.31 c1 0.24 0.26 D 9.05 9.45 E1 6.15 6.55 e b eA b1 eB eC L c1 c Base Metal 2.54 BSC 7.62 BSC 7.62 9.50 0 0.94 3.00 - With Plating Section B-B - 12 - 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) 8-lead SOP package diagram C 1 E E1 N L q Top View End View COMMON DIMENSIONS (Unit of Measure = mm) e B SYMBOL A A1 MIN A 1.35 1.75 A1 0.10 0.25 b 0.31 0.51 C 0.17 0.25 D 4.70 5.10 E1 3.80 4.00 E 5.79 6.20 e D MAX 1.27 BSC L 0.40 1.27 q 0° 8° Side View - 13 - 2012-7-8 PT24C02/PT24C04/PT24C08/PT24C16 Two-wire Serial EEPROM 2K bits(256×8)/4K bits(512×8)/8K bits(1024×8)/16K bits(2048×8) 8-lead TSSOP package diagram 3 2 1 E E1 L1 N q Top View L End View COMMON DIMENSIONS (Unit of Measure = mm) A b e MIN MAX D 2.80 3.20 E 6.20 6.60 E1 4.20 4.60 A – 1.20 A2 0.80 1.15 b 0.19 0.30 SYMBOL A2 D e L Side View 0.65 BSC 0.45 L1 q - 14 - 0.75 1.00 BSC 0° 8° 2012-7-8