FP6601QS6

FP6601Q USB Dedicated Charging Port Controller for Fast Charging Protocol and QC 2.0/3.0 Description Features The FP6601Q is a fast charge protocol controller for HiSilicon Fast Charging Protocol (FCP) and ® Qualcomm Quick ChargeTM 2.0/3.0 (QC 2.0/3.0) USB interface. The device can fast charging FCP or QC 2.0/3.0 powered device (PD). The protocol feature monitors USB D+/D- data line voltage or D- data line transmission and automatically adjusts output voltage of power bank and wall adaptor to optimize charge time. ● Support HiSilicon Fast Charging Protocol (FCP) for Output Voltage and Current Communication ® ● Support Qualcomm Quick ChargeTM 2.0/3.0 ● Class A : 3.6V up to 12V Output Voltage ● Automatic Selection FCP and QC2.0/3.0 Protocols ● Supports USB DCP Shorting D+ Line to D- Line per USB Battery Charging Specification, Revision 1.2 ● Meets Chinese Telecommunication Industrial Standard YD/T 1591-2009 ● Supports USB DCP Applying 2.7V on D+ Line and 2.7V on D- Line ● Supports USB DCP Applying 1.2V on D+ and DLines ● SOT-23-6 Package ● UL Certification No. 4787452994-2 FP6601Q can support not only USB BC compliant devices, but also Apple / Samsung / HUAWEI devices and automatically detects whether a connected powered device is QC 2.0/3.0 or FCP capable before enabling output voltage adjustment. If a PD not compliant to QC 2.0/3.0 or FCP is detected the FP6601Q disables output voltage adjustment to ensure safe operation with legacy 5 V only USB PDs. The FP6601Q is available in a space-saving SOT-23-6 package. Pin Assignments Applications ● Wall-Adapter, Smart Phones, Tablets, Notebooks ● Mobile / Tablet Power Bank ● Car Charger ● USB Power Output Ports Ordering Information SFP6601Q□ S6 Package(SOT-23-6) Package Type S6: SOT-23-6 D- VDD QC_EN 6 5 4 (Marking) 1 2 3 SOT-23-6 Marking D+ GND FBO Part Number Product Code FP6601QS6 FT4 Figure 1. Pin Assignment of FP6601Q FP6601Q-Preliminary 0.1-AUG-2016 1 FP6601Q Typical Application Circuit VOUT RVDD 100KΩ 2.2kΩ R1 ON Feedback Node 4 OFF QC_EN VDD VDD 5 470nF 3 R2 2 CVDD FBO VOUT D- GND USB Port D+ 6 D- 1 D+ GND Figure 2. Typical Application Schematic Output Voltage Lookup Table(QC 2.0/3.0) FP6601Q-Preliminary 0.1-AUG-2016 D+ D- Output Voltage 0.6V 0.6V 12V 3.3V 0.6V 9V 0.6V 3.3V Continuous mode 0.6V High-Z 5V (Default) 2 FP6601Q Functional Pin Description Pin Name Pin No. (SOT-23-6) D+ 1 USB D+ data line input pin. Recommended this pin connect without resistors(open) or with a resistor higher than 1MΩ connect to GND. GND 2 Ground pin. FBO 3 Feedback output pin. Current Sink/Source FB Node. QC_EN 4 QC_Enable: High-Z with QC2.0/3.0 and FCP function; logic low disable QC2.0/3.0 and FCP function. VDD 5 Power supply input pin. D- 6 USB D- data line input pin. Pin Function Block Diagram VDD VDD 6.4 V 2.0V UVLO& POR D+ 0. 325V 1.5μA QC_EN Control Logic SW1 500KΩ Auto Detection VDD FBO Up/Down Current Step 2.0V D0.325V . 20KΩ SW2 Figure 3. Block Diagram of FP6601Q FP6601Q-Preliminary 0.1-AUG-2016 3 FP6601Q Absolute Maximum Ratings (Note 1) ● Input Supply Voltage VDD ------------------------------------------------------------------------------ - 0.3V to + 6.5V ● All Other Pins Voltage ----------------------------------------------------------------------------------- - 0.3V to + 6.5V ● Maximum Junction Temperature (TJ)----------------------------------------------------------------- + 150℃ ● Storage Temperature (TS)------------------------------------------------------------------------------- - 65℃ to + 150℃ ● Lead Temperature (Soldering, 10sec.) -------------------------------------------------------------- +260°C ● Power Dissipation @TA=25℃, (PD) SOT-23-6---------------------------------------------------------------------------------------- 0.5W ● Package Thermal Resistance, (θJA) (Note 2) SOT-23-6---------------------------------------------------------------------------------------- 250°C/W ● Package Thermal Resistance, (θJC) SOT-23-6---------------------------------------------------------------------------------------- 110°C/W Note 1：Stresses beyond this listed under “Absolute Maximum Ratings" may cause permanent damage to the device. Note 2：θJA is measured at 25°C ambient with the component mounted on a high effective thermal conductivity test board of JEDEC-51-7. Recommended Operating Conditions ● Input Supply Voltage (VDD)---------------------------------------------------------------------------- 3.2V to 6.4V ● Operation Temperature Range (TOPR) -------------------------------------------------------------- -40°C to +85°C Note 3：Over operating free-air temperature range (unless otherwise noted) FP6601Q-Preliminary 0.1-AUG-2016 4 FP6601Q Electrical Characteristics (VDD=5V, TA=25℃ and the recommended supply voltage range, unless otherwise specified.) Parameter Symbol Conditions Min Typ Max Unit 3.2 6.4 V 2.5 2.9 V Input Power VDD Input Voltage Range VDD Input UVLO Threshold VUVLO(VTH) VDD Supply Current VDD Falling VDD =5V, Measure VDD VDD(SHUNT) VDD Shunt Voltage IVDD = 3mA μA 200 5.9 6.4 6.8 V High Voltage Dedicated Charging Port (HVDCP) Data Detect Voltage VDAT(REF) 0.25 0.325 0.4 V Output Voltage Selection Reference VSEL_REF 1.8 2.0 2.2 V 1000 1250 1500 ms TGLITCH(BC)- D+ High Glitch Filter Time D+_H TGLITCH(BC)- D- Low Glitch Filter Time ms 1 D-_L TGLITCH(V) Output Voltage Glitch Filter Time 20 40 60 CHANGE D- Pull-Down Resistance Continuous Mode Glitch Filter Time RD-(DWN) (Note 4) kΩ 20 TGLITCH-CON 100 200 μs 800 kΩ 40 Ω T-CHANGE D+ Leakage Resistance RDAT-LKG VDD =3.2-6.4V,VD+=0.6-3.6V Switch SW1=Off Switch SW1 On-Resistance RDS_ON_N1 VDD =5V,SW1= 200μA Up/Down Current Step IUP, IDOWN IUP = 40μA (9V), 70μA (12V), IDOWN = 14μA (3.6V) 300 500 ms μA 2 DCP 1.2V Charging Mode D+_1.2V/D-_1.2V Line Output Voltage 1.08 D+_1.2V/D-_1.2V Line Output Impedance 1.2 1.32 V kΩ 100 Apple 2.4A Mode D+_2.7V/D-_2.7V Line Output Voltage 2.57 D+_2.7V/D-_2.7V Line Output Impedance 2.7 2.84 V kΩ 33.6 D- SECTION (FCP) D- FCP Tx Valid Output High VTX-VOH D- FCP Tx Valid Output Low VTX-VOL D- FCP Rx Valid Output High VRX-VIH D- FCP Rx Valid Output Low VRX-VIL FP6601Q-Preliminary 0.1-AUG-2016 2.55 1.4 3.6 V 0.3 V 3.6 V 1.0 V 5 FP6601Q Electrical Characteristics (Continued) (VDD=5V, TA=25℃ and the recommended supply voltage range, unless otherwise specified.) Parameter D- Output Pull-Low Resistance (FCP) Symbol (Note 4) Unit Interval For FCP PHY Communication Conditions RPD UI fCLK = 125kHz Min Typ Max Unit 400 500 600 Ω 144 160 180 μs Note 4：Not production tested. FP6601Q-Preliminary 0.1-AUG-2016 6 FP6601Q Application Information Function Description The FP6601Q is a USB high voltage dedicated ® charging port interface IC for Qualcomm Quick TM Charge 2.0/3.0 class A, HiSilicon FCP specification. The FP6601Q is a USB Dedicated Charging Port Controller can fast charge most of the handheld devices. It can be like the original charging adapter. The FP6601Q can support BC1.2, Apple, Samsung and HUAWEI. It also supports full output voltage range of QC 3.0 Class A(3.6V to 12V) or QC 2.0 Class A(5V,9V,12V) Quick Charge 2.0/3.0 Interface Power up D+/D- is supply 2.7V to Apple Device and then supply D+ short to D- into BC1.2. Set the output voltage level 5V. If D+ continuous above 0.325V and keep 1.25 seconds FP6601Q can automatic choose into Quick Charge 2.0/3.0, FCP operation mode. When VDAT(REF)< D+ VSEL_REF , the FP6601Q enter continuous mode. Each step D+ from 1V to 3V Pulse-width during 200us cause current sink 2uA by FBO. The maximum output sink current is 70uA for output voltage reach to 12V. Each step D- from 3V to 1V Pulse-width during 200us cause current source 2uA by FBO. The minimum output source current is 14uA for output voltage reach to 3.6V. If PD without QC 2.0 the device will keep output voltage level 5V guarantee safe operation for only 5V USB PD. When USB cable unplug the D+ voltage < VDAT(REF) and output voltage recovery default mode 5V. Shunt Regulator The wide power supply output voltage through external resistor from RVDD to VDD. The internal with Zener-Diode clamp VDD pin at 6.4V. Recommend RVDD =2.2kΩ and CVDD=470nF. QC_EN Function When QC_EN pin disable QC 2.0/3.0,FCP function by connect to GND. Otherwise, enable function by connect to VDD or floating. QC_EN signal need to be ready before FP6601Q start detection. When FP6601Q already access QC2.0/3.0 or FCP mode, the mode won’t be changed by setting QC_EN pin signal (High to Low). FP6601Q-Preliminary 0.1-AUG-2016 7 FP6601Q Outline Information SOT-23-6 Package (Unit: mm) SYMBOLS UNIT A DIMENSION IN MILLIMETER MIN MAX 0.90 1.45 A1 0.00 0.15 A2 0.90 1.30 B 0.30 0.50 D 2.80 3.00 E 2.60 3.00 E1 1.50 1.70 e 0.90 1.00 e1 1.80 2.00 L 0.30 0.60 Note：Followed From JEDEC MO-178-C. Carrier Dimensions Life Support Policy Fitipower’s products are not authorized for use as critical components in life support devices or other medical systems. FP6601Q-Preliminary 0.1-AUG-2016 8