ES8323S

ES8323S FEATURES Low Power Audio CODEC DAC System • • • • • • • • High performance and low power multibit delta-sigma audio ADC and DAC I2S/PCM master or slave serial data port Two pairs of analog input with differential input option 256/384Fs and USB 12/24 MHz system clocks Sophisticated analog input and output routing, mixing and gain I2C interface • • • • Low Power • • ADC • • • 24-bit, 8 to 96 kHz sampling frequency 93 dB signal to noise ratio, -85 dB THD+N Headphone driver capless mode Bass or treble Stereo enhancement Pop and click noise suppression 24-bit, 8 to 96 kHz sampling frequency 92 dB signal to noise ratio, -85 dB THD+N Auto level control (ALC) and noise gate 1.8V to 3.3V operation 7 mW playback; 16 mW playback and record APPLICATIONS • • MID/Tablet Portable audio ORDERING INFORMATION ES8323S -40°C ~ +85°C QFN-28 1 Everest Semiconductor 1. 2. 3. 4. 5. 6. 7. 8. Confidential ES8323S BLOCK DIAGRAM ................................................................................................................... 4 PIN OUT AND DESCRIPTION ................................................................................................ 5 TYPICAL APPLICATION CIRCUIT.......................................................................................... 6 POWER ON RESET ................................................................................................................ 7 CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 7 MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 8 DIGITAL AUDIO INTERFACE................................................................................................ 10 ELECTRICAL CHARACTERISTICS ...................................................................................... 11 ABSOLUTE MAXIMUM RATINGS................................................................................................ 11 RECOMMENDED OPERATING CONDITIONS .............................................................................. 11 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 11 DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 12 POWER CONSUMPTION CHARACTERISTICS .............................................................................. 12 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ................................................................... 13 I2C SWITCHING SPECIFICATIONS ............................................................................................... 13 9. CONFIGURATION REGISTER DEFINITION ........................................................................ 15 REGISTER 0 – CHIP CONTROL 1, DEFAULT 0000 0100 ............................................................... 15 REGISTER 1 – CHIP CONTROL 2, DEFAULT 0001 1111 ............................................................... 15 REGISTER 2 – CHIP POWER MANAGEMENT, DEFAULT 1100 0011 ........................................... 15 REGISTER 3 – ADC POWER MANAGEMENT, DEFAULT 1010 1100 ............................................ 16 REGISTER 4 – DAC POWER MANAGEMENT, DEFAULT 1100 0000 ............................................ 16 REGISTER 5 – CHIP LOW POWER 1, DEFAULT 0000 0000.......................................................... 16 REGISTER 6 – CHIP LOW POWER 2, DEFAULT 0000 0000.......................................................... 16 REGISTER 7 – ANALOG VOLTAGE MANAGEMENT, DEFAULT 1111 1100 .................................. 16 REGISTER 8 – MASTER MODE CONTROL, DEFAULT 1000 0000................................................. 17 REGISTER 9 – ADC CONTROL 1, DEFAULT 0000 0000 ................................................................ 17 REGISTER 10 – ADC CONTROL 2, DEFAULT 0000 0000 .............................................................. 17 REGISTER 11 – ADC CONTROL 3, DEFAULT 0000 0000 .............................................................. 17 REGISTER 12 – ADC CONTROL 4, DEFAULT 0000 0000 .............................................................. 18 REGISTER 13 – ADC CONTROL 5, DEFAULT 0000 0110 .............................................................. 18 REGISTER 14 – ADC CONTROL 6, DEFAULT 0010 0000 .............................................................. 18 REGISTER 15 – ADC CONTROL 7, DEFAULT 0010 0000 .............................................................. 19 REGISTER 16 – ADC CONTROL 8, DEFAULT 1100 0000 .............................................................. 19 REGISTER 18 – ADC CONTROL 10, DEFAULT 0011 1000 ............................................................ 20 REGISTER 19 – ADC CONTROL 11, DEFAULT 1011 0000 ............................................................ 20 Revision 9.0 2 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S REGISTER 20 – ADC CONTROL 12, DEFAULT 0011 0010 ............................................................ 20 REGISTER 21 – ADC CONTROL 13, DEFAULT 0000 0110 ............................................................ 21 REGISTER 22 – ADC CONTROL 14, DEFAULT 0000 0000 ............................................................ 21 REGISTER 23 – DAC CONTROL 1, DEFAULT 0000 0000 .............................................................. 21 REGISTER 24 – DAC CONTROL 2, DEFAULT 0000 0110 .............................................................. 22 REGISTER 25 – DAC CONTROL 3, DEFAULT 0010 0010 .............................................................. 22 REGISTER 26 – DAC CONTROL 4, DEFAULT 1100 0000 .............................................................. 22 REGISTER 27 – DAC CONTROL 5, DEFAULT 1100 0000 .............................................................. 23 REGISTER 28 – DAC CONTROL 6, DEFAULT 0000 1000 .............................................................. 23 REGISTER 29 – DAC CONTROL 7, DEFAULT 0000 0000 .............................................................. 23 REGISTER 30 – DAC CONTROL 8, DEFAULT 0001 1111 .............................................................. 23 REGISTER 31 – DAC CONTROL 9, DEFAULT 1111 0111 .............................................................. 24 REGISTER 32 – DAC CONTROL 10, DEFAULT 1111 1101 ............................................................ 24 REGISTER 33 – DAC CONTROL 11, DEFAULT 1111 1111 ............................................................ 24 REGISTER 34 – DAC CONTROL 12, DEFAULT 0001 1111 ............................................................ 24 REGISTER 35 – DAC CONTROL 13, DEFAULT 1111 0111 ............................................................ 24 REGISTER 36 – DAC CONTROL 14, DEFAULT 1111 1101 ............................................................ 24 REGISTER 37 – DAC CONTROL 15, DEFAULT 1111 1111 ............................................................ 24 REGISTER 38 – DAC CONTROL 16, DEFAULT 0000 0000 ............................................................ 24 REGISTER 39 – DAC CONTROL 17, DEFAULT 0011 1000 ............................................................ 25 REGISTER 42 – DAC CONTROL 20, DEFAULT 0011 1000 ............................................................ 25 REGISTER 43 – DAC CONTROL 21, DEFAULT 0001 0000 ............................................................ 25 REGISTER 44 – DAC CONTROL 22, DEFAULT 0000 0000 ............................................................ 26 REGISTER 45 – DAC CONTROL 23, DEFAULT 0000 0000 ............................................................ 26 REGISTER 48 – DAC CONTROL 26, DEFAULT 0000 0000 ............................................................ 26 REGISTER 49 – DAC CONTROL 27, DEFAULT 0000 0000 ............................................................ 26 REGISTER 53 – TEST MODE, DEFAULT 0000 0000 ..................................................................... 26 REGISTER 56 – ADC TEST CONTROL 2, DEFAULT 0000 0000 ..................................................... 26 10. 11. PACKAGE .......................................................................................................................... 27 CORPORATE INFORMATION .......................................................................................... 28 Revision 9.0 3 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 1. BLOCK DIAGRAM DSDIN ASDOUT SCLK LRCK CDATA CCLK CE MCLK 2 2 IC Clock Mgr I S/PCM LIN1 LIN2 LIN2 LIN1 PGA PGA PGA RIN1 RIN2 Mono ADC PGA RIN2 RIN1 ADC ALC DAC PEQ DAC SE Mixer HP Driver LOUT Stereo DAC HP Driver Analog Reference Power Supply ADCVREF DACVREF VMID DVDD PVDD DGND AVDD AGND HPVDD HPGND HPCOM Revision 9.0 Mixer 4 Latest datasheet: www.everest-semi.com or info@everest-semi.com ROUT July 2018 Everest Semiconductor Confidential ES8323S 2. PIN OUT AND DESCRIPTION LIN1 RIN2 LIN2 NC CE CDATA CCLK 22 23 24 25 26 27 28 MCLK DVDD PVDD DGND SCLK DSDIN LRCK 1 2 3 4 5 6 7 ES8323S 21 20 19 18 17 16 15 RIN1 VMID ADCVREF AGND AVDD HPVDD LOUT 14 13 12 11 10 9 8 ROUT HPGND HPCOM NC DACVREF NC ASDOUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Revision 9.0 NAME MCLK DVDD PVDD DGND SCLK DSDIN LRCK ASDOUT NC DACVREF NC HPCOM HPGND ROUT LOUT HPVDD AVDD AGND ADCVREF VMID RIN1 LIN1 RIN2 LIN2 NC CE CDATA CCLK I/O I Supply Supply Supply I/O I I/O O O O Supply O O Supply Supply Supply O O I I I I I I/O I DESCRIPTION Master clock Digital core supply Digital IO supply Digital ground Audio data bit clock DAC audio data Audio data left and right clock ADC audio data No connect Decoupling capacitor No connect No connect or bias for capless mode Ground for headphone output drivers Right analog output Left analog output Supply for headphone output drivers Analog supply Analog ground Decoupling capacitor Decoupling capacitor Right analog input Left analog input Right analog input Left analog input No connect I2C device address selection I2C data input or output I2C clock input 5 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 3. TYPICAL APPLICATION CIRCUIT R25 100R AVDD ADCVREF R26 100R C34 4.7uF I2C Chip Address = 0x10(7bit) / 0x20(8bit) if CEpin is pulled down to ground I2C Chip Address = 0x11(7bit) / 0x22(8bit) if CEpin is pulled up to DVDD R27 2K AU_GND C30 1 2 DVDD C31 1uF R23 10K 1uF R24 10K AU_GND AU_GND I2C_SCL R28 100R R29 100R C35 4.7uF AVDD R22 33R I2C_SDA ADCVREF R21 33R C28 20pF C29 20pF 1 2 3 4 5 6 7 AU_GND I2S_SCLK I2S_DSDIN I2S_LRCK 29 28 27 26 25 24 23 22 MCLK DVDD PVDD DGND SCLK DSDIN LRCK RIN1 VMID ADCVREF AGND AVDD HPVDD LOUT C37 4.7uF 21 20 19 18 17 16 15 ADCVREF AU_GND AVDD C39 4.7uF AU_GND PHONEJACK STEREO 1 R31 33R R32 33R C40 22uF C41 22uF I2S_ASDOUT C36 4.7uF AU_GND C38 4.7uF AU_GND 8 9 10 11 12 13 14 AU_GND U2 ES8323S MK3 MICROPHONE AU_GND PAD_GND CCLK CDATA CE NC LIN2 RIN2 LIN1 C27 0.1uF ASDOUT NC DACVREF NC HPCOM HPGND ROUT AU_GND 1 2 C32 1uF C33 1uF AU_GND I2S_MCLK R30 2K AU_GND DVDD R44 3.3K MK2 MICROPHONE 2 3 J2 AU_GND AU_GND AU_GND L2 AVDD DVDD R33 100R AVDD ADCVREF R34 100R C42 4.7uF I2C Chip Address = 0x10(7bit) / 0x20(8bit) if CEpin is pulled down to ground I2C Chip Address = 0x11(7bit) / 0x22(8bit) if CEpin is pulled up to DVDD AU_GND C43 R35 2K 1 2 DVDD R36 10K 1uF C44 1uF R37 10K AU_GND AU_GND R38 100R R40 100R C45 4.7uF AVDD R39 33R I2C_SDA I2C_SCL ADCVREF R41 33R C46 20pF C47 20pF AU_GND DVDD 1 2 3 4 5 6 7 AU_GND I2S_SCLK I2S_DSDIN I2S_LRCK 29 28 27 26 25 24 23 22 U3 ES8323S RIN1 VMID ADCVREF AGND AVDD HPVDD LOUT 21 20 19 18 17 16 15 C51 4.7uF ADCVREF AU_GND AVDD C53 4.7uF AU_GND AU_GND PHONEJACK STEREO 1 2 3 I2S_ASDOUT J3 C56 4.7uF AU_GND Revision 9.0 MK5 MICROPHONE AU_GND C52 4.7uF 8 9 10 11 12 13 14 AU_GND MCLK DVDD PVDD DGND SCLK DSDIN LRCK PAD_GND CCLK CDATA CE NC LIN2 RIN2 LIN1 I2S_MCLK 1 2 AU_GND ASDOUT NC DACVREF NC HPCOM HPGND ROUT AU_GND C50 0.1uF R42 2K C48 1uF C49 1uF AU_GND R43 3.3K MK4 MICROPHONE AU_GND AVDD L1 DVDD 6 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 4. POWER ON RESET The device resets itself when DVDD (pin 2) ramp from ground voltage to supply voltage. The ground voltage needs to be less than 0.2V for proper reset. When DVDD voltage is removed, it is important to let it drop below 0.2V before next power up. An optional discharge resistor (3.3K, for example) can be placed between DVDD and DGND (pin 4). 5. CLOCK MODES AND SAMPLING FREQUENCIES The device supports two types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc), and USB clocks (12/24 MHz). According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally. LRCK and SCLK must be synchronously derived from the system clock with specific rates. The device can auto detect MCLK/LRCK ratio according to Table 1. The device supports the MCLK/LRCK ratios listed in Table 1. The LRCK/SCLK ratio is normally 64. Table 1 Slave Mode Sampling Frequencies and MCLK/LRCK Ratio Speed Mode Single Speed Double Speed Sampling Frequency 8kHz – 50kHz 50kHz – 100kHz MCLK/LRCK Ratio 256, 384, 512, 768, 1024 128, 192, 256, 384, 512 In master mode, LRCK and SCLK are derived internally from MCLK. The available MCLK/LRCK ratios and SCLK/LRCK ratios are listed in Table 2. Table 2 Master Mode Sampling Frequencies and MCLK/LRCK Ratio MCLK MCLK ADC Sample Rate CLKDIV2=0 CLKDIV2=1 (ALRCK) Normal Mode 12.288 MHz 24.576MHz 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 11.2896 MHz 22.5792MHz 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 11.025 kHz (MCLK/1024) Revision 9.0 ADCFsRatio DAC Sample Rate [4:0] (DLRCK) DACFsRatio SCLK [4:0] Ratio 01010 01010 00111 00110 00100 00011 00010 00010 00000 01001 01001 00111 01010 00010 00111 00110 00100 00011 01010 00010 00000 01001 00010 00111 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 11.025 kHz (MCLK/1024) 7 Latest datasheet: www.everest-semi.com or info@everest-semi.com MCLK/6 MCLK/4 MCLK/4 MCLK/6 MCLK/4 MCLK/6 MCLK/4 MCLK/4 MCLK/2 MCLK/4 MCLK/4 MCLK/4 July 2018 Everest Semiconductor Confidential 22.05 kHz (MCLK/512) 44.1 kHz (MCLK/256) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128) 18.432 MHz 36.864MHz 8 kHz (MCLK/2304) 8 kHz (MCLK/2304) 12 kHz (MCLK/1536) 16 kHz (MCLK/1152) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 48 kHz (MCLK/384) 48 kHz (MCLK/384) 96 kHz (MCLK/192) 16.9344 MHz 33.8688MHz 8.0182 kHz (MCLK/2112) 8.0182 kHz (MCLK/2112) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 44.1 kHz (MCLK/384) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192) USB Mode 12 MHz 24MHz 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 8.0214 kHz (MCLK/1496) 8.0214 kHz (MCLK/1496) 11.0259 kHz (MCLK/1088) 12 kHz (MCLK/1000) 16 kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24 kHz (MCLK/500) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 48 kHz (MCLK/250) 88.235 kHz (MCLK/136) 96 kHz (MCLK/125) ES8323S 00100 00010 00010 00000 01100 01100 01010 01000 00110 00101 00011 00011 00001 01011 01011 01010 00110 00011 00011 00001 22.05 kHz (MCLK/512) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128) 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 12 kHz (MCLK/1536) 16 kHz (MCLK/1152) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 96 kHz (MCLK/192) 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192) 00100 01001 00010 00000 01100 00011 01010 01000 00110 00101 01100 00011 00001 01011 00011 01010 00110 01011 00011 00001 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3 11011 11011 11010 11010 11001 11000 10111 10110 10101 10100* 10011 10011 10010 10010 10001 10000 8 kHz (MCLK/1500) 11011 48 kHz (MCLK/250) 10010 8.0214 kHz (MCLK/1496) 11010 44.118 kHz (MCLK/272) 10011 11.0259 kHz (MCLK/1088) 11001 12 kHz (MCLK/1000) 11000 16 kHz (MCLK/750) 10111 22.0588 kHz (MCLK/544) 10110 24 kHz (MCLK/500) 10101 32 kHz (MCLK/375) 10100* 8.0214 kHz (MCLK/1496) 11010 44.118 kHz (MCLK/272) 10011 8 kHz (MCLK/1500) 11011 48 kHz (MCLK/250) 10010 88.235 kHz (MCLK/136) 10001 96 kHz (MCLK/125) 10000 MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK 6. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1a and Figure 1b. Data are transmitted synchronously to SCL clock on the SDA line on a byte-byRevision 9.0 8 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 400 kbps. A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high. In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 3 Write Data to Register in I2C Interface Mode start Chip Address 001000 AD0 R/W 0 ACK Register Address RAM ACK Data to be written DATA ACK Stop Figure 1a I2C Write Timing Table 4 Read Data from Register in I2C Interface Mode Start Start Revision 9.0 Chip Address 001000 AD0 Chip Address 001000 AD0 R/W 0 R/W 1 ACK ACK Register Address RAM Data to be read Data ACK NACK Stop 9 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S Figure 1b I2C Read Timing 7. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are I2S, left justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through Figure 2 to Figure 5. 1 SCLK SDATA 1 2 1 SCLK 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LEFT CHANNEL LRCK RIGHT CHANNEL Figure 2 I2S Serial Audio Data Format Up To 24-bit SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK LEFT CHANNEL RIGHT CHANNEL Figure 3 Left Justified Serial Audio Data Format Up To 24-bit Revision 9.0 10 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S Figure 4 DSP/PCM Mode A Figure 5 DSP/PCM Mode B 8. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V DGND-0.3V -40°C -65°C MAX +5.0V +5.0V DVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level MIN 2.0 1.6 TYP 3.3 1.8 MAX 3.6 3.6 UNIT V V ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Revision 9.0 MIN TYP MAX UNIT 85 -88 80 92 -85 85 0.1 95 -75 90 dB dB dB dB % ±5 11 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance ES8323S 0 0.5465 0.4535 Fs Fs dB dB ±0.05 50 0 0.5833 0.4167 Fs Fs dB dB ±0.005 50 AVDD/3.3 20 Vrms KΩ DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER MIN DAC Performance Signal to Noise ratio (A-weigh) 83 THD+N -85 Channel Separation (1KHz) 80 Interchannel Gain Mismatch Filter Frequency Response – Single Speed Passband 0 Stopband 0.5465 Passband Ripple Stopband Attenuation 40 Filter Frequency Response – Double Speed Passband 0 Stopband 0.5833 Passband Ripple Stopband Attenuation 40 De-emphasis Error at 1 KHz (Single Speed Mode Only) Fs = 32KHz Fs = 44.1KHz Fs = 48KHz Analog Output Full Scale Output Level TYP MAX UNIT 93 -83 85 0.05 95 -75 90 dB dB dB dB 0.4535 Fs Fs dB dB ±0.05 0.4167 ±0.005 0.002 0.013 0.0009 AVDD/3.3 Fs Fs dB dB dB Vrms POWER CONSUMPTION CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=1.8V, PVDD=1.8V, AVDD=1.8V: Revision 9.0 MIN TYP MAX 12 Latest datasheet: www.everest-semi.com or info@everest-semi.com UNIT mW July 2018 Everest Semiconductor Confidential ES8323S Play back Play back and record DVDD=3.3V, PVDD=3.3V, AVDD=3.3V: Play back Play back and record Power Down Mode DVDD=1.8V, PVDD=1.8V, AVDD=1.8V DVDD=3.3V, PVDD=3.3V, AVDD=3.3V 7 16 31 59 TBD TBD mW SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO TSDIS TSDIH 15 15 –10 0 10 10 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns ns ns Figure 8 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS PARAMETER SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Revision 9.0 Symbol FSCL TTWID TTWSTH TTWCL MIN 1.3 0.6 1.3 MAX 400 13 Latest datasheet: www.everest-semi.com or info@everest-semi.com UNIT KHz us us us July 2018 Everest Semiconductor Confidential Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling SDA Setup time to SCL Rising Rise Time of SCL Fall Time SCL ES8323S TTWCH TTWSTS TTWDH TTWDS TTWR TTWF 0.4 0.6 us us ns ns ns ns 900 100 300 300 SDA TTWSTS TTWSTH TTWCL SCL TTWDH TTWID TTWDS TTWCH S TTWF TTWR P S Figure 10 I2C Timing Revision 9.0 14 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 9. CONFIGURATION REGISTER DEFINITION REGISTER 0 – CHIP CONTROL 1, DEFAULT 0000 0100 Bit Name SCPReset Bit 7 LRCM 6 DACMCLK 5 SameFs 4 SeqEn 3 EnRef 2 VMIDSEL 1:0 Description 0 – normal (default) 1 – reset control port register to default 0 – ALRCK disabled when both ADC disabled; DLRCK disabled when both DAC disabled (default) 1 – ALRCK and DLRCK disabled when all ADC and DAC disabled 0 – when SameFs=1, ADCMCLK is the chip master clock source (default) 1 – when SameFs=1, DACMCLK is the chip master clock source 0 – ADC Fs differs from DAC Fs (default) 1 – ADC Fs is the same as DAC Fs 0 – internal power up sequence disable (default) 1 – internal power up sequence enable 0 – disable reference 1 – enable reference (default) 00 – Vmid disabled (default) 01 – 50 kΩ divider enabled 10 – 500 kΩ divider enabled 11 – 5 kΩ divider enabled REGISTER 1 – CHIP CONTROL 2, DEFAULT 0001 1111 Bit Name LPVcmMod Bit 5 LPVrefBuf 4 PdnAna 3 PdnIbiasgen 2 VrefLo 1 PdnVrefbuf 0 Description 0 – normal (default) 1 – low power 0 – normal 1 – low power (default) 0 – normal 1 – entire analog power down (default) 0 – normal 1 – ibiasgen power down (default) 0 – normal 1 – low power (default) 0 – normal 1 – power down (default) REGISTER 2 – CHIP POWER MANAGEMENT, DEFAULT 1100 0011 Bit Name adc_DigPDN Bit 7 dac_DigPDN 6 adc_stm_rst 5 dac_stm_rst 4 adcVref_PDN 1 dacVref_PDN 0 Revision 9.0 Description 0 – normal 1 – resets ADC DEM, filter and serial data port (default) 0 – normal 1 – resets DAC DSM, DEM, filter and serial data port (default) 0 – normal (default) 1 – reset ADC state machine to power down state 0 – normal (default) 1 – reset DAC state machine to power down state 0 – ADC analog reference power up 1 – ADC analog reference power down (default) 0 – DAC analog reference power up 1 – DAC analog reference power down (default) 15 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S REGISTER 3 – ADC POWER MANAGEMENT, DEFAULT 1010 1100 Bit Name PdnAINL Bit 7 PdnADCL 5 PdnADCBiasgen 2 flashLP 1 intLP 0 Description 0 – normal 1 – left analog input power down (default) 0 – left ADC power up 1 – left ADC power down (default) 0 – normal 1 – power down (default) 0 – normal (default) 1 – ADC low power 0 – normal (default) 1 – low power REGISTER 4 – DAC POWER MANAGEMENT, DEFAULT 1100 0000 Bit Name PdnDACL Bit 7 PdnDACR 6 HPCOM 5 LOUT 3 ROUT 2 Description 0 – left DAC power up 1 – left DAC power down (default) 0 – right DAC power up 1 – right DAC power down (default) 0 – HPCOM disable (default) 1 – HPCOM enable 0 – LOUT disabled (default) 1 – LOUT enabled 0 – ROUT disabled (default) 1 – ROUT enabled REGISTER 5 – CHIP LOW POWER 1, DEFAULT 0000 0000 Bit Name LPDACL Bit 7 LPDACR 6 LPHPCOM 5 LPLOUT1 3 Description 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power REGISTER 6 – CHIP LOW POWER 2, DEFAULT 0000 0000 Bit Name LPPGA Bit 7 LPLMIX 6 LPADCvrp 1 LPDACvrp 0 Description 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power 0 – normal (default) 1 – low power REGISTER 7 – ANALOG VOLTAGE MANAGEMENT, DEFAULT 1111 1100 Bit Name Bit Revision 9.0 Description 16 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor VSEL 7:0 Confidential ES8323S 11111100 – normal (default) REGISTER 8 – MASTER MODE CONTROL, DEFAULT 1000 0000 Bit Name MSC Bit 7 MCLKDIV2 6 BCLK_INV 5 BCLKDIV 4:0 Description 0 – slave serial port mode 1 – master serial port mode (default) 0 – MCLK not divide (default) 1 – MCLK divide by 2 0 – normal (default) 1 – BCLK inverted 00000 – master mode BCLK generated automatically based on the clock table (default) 00001 – MCLK/1 00010 – MCLK/2 00011 – MCLK/3 00100 – MCLK/4 00101 – MCLK/6 00110 – MCLK/8 00111 – MCLK/9 01000 – MCLK/11 01001 – MCLK/12 01010 – MCLK/16 01011 – MCLK/18 01100 – MCLK/22 01101 – MCLK/24 01110 – MCLK/33 01111 – MCLK/36 10000 – MCLK/44 10001 – MCLK/48 10010 – MCLK/66 10011 – MCLK/72 10100 – MCLK/5 10101 – MCLK/10 10110 – MCLK/15 10111 – MCLK/17 11000 – MCLK/20 11001 – MCLK/25 11010 – MCLK/30 11011 – MCLK/32 11100 – MCLK/34 Others – MCLK/4 REGISTER 9 – ADC CONTROL 1, DEFAULT 0000 0000 Bit Name MicAmpL Bit 7:4 Description Left channel PGA gain 0000 – 0 dB (default) 0001 – +3 dB 0010 – +6 dB 0011 – +9 dB 0100 – +12 dB 0101 – +15 dB 0110 – +18 dB 0111 – +21 dB 1000 – +24 dB REGISTER 10 – ADC CONTROL 2, DEFAULT 0000 0000 Bit Name LINSEL Bit 7:6 capmode 0 Description Channel input select 00 – LIN2/RIN2 (default) 01 – LIN1/RIN1 10 – reserved 11 – L-R differential input, L/R selection refer to DS (reg0xB[7]) 0 – cap mode disabled (default) 1 – cap mode enabled REGISTER 11 – ADC CONTROL 3, DEFAULT 0000 0000 Bit Name DS Bit 7 Revision 9.0 Description Differential input select 0 – from input LIN2-RIN2 (default) 17 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor LDCM 6 TRI 2 Confidential ES8323S 1 – from input LIN1-RIN1 ADC DC measure 0 – disable (default) 1 – enable 0 – ASDOUT is ADC normal output (default) 1 – ASDOUT tri-stated, ALRCK, DLRCK and SCLK are inputs REGISTER 12 – ADC CONTROL 4, DEFAULT 0000 0000 Bit Name ADCLRP Bit 5 ADCWL 4:2 ADCFORMAT 1:0 Description I2S or left justified mode: 0 – left and right normal polarity 1 – left and right inverted polarity DSP/PCM mode: 0 – MSB is available on 2nd BCLK rising edge after ALRCK rising edge 1 – MSB is available on 1st BCLK rising edge after ALRCK rising edge 000 – 24-bit serial audio data word length(default) 001 – 20-bit serial audio data word length 010 – 18-bit serial audio data word length 011 – 16-bit serial audio data word length 100 – 32-bit serial audio data word length 00 – I2S serial audio data format(default) 01 – left justify serial audio data format 10 – reserved 11 – DSP/PCM mode serial audio data format REGISTER 13 – ADC CONTROL 5, DEFAULT 0000 0110 Bit Name adc_ratio_sel Bit 6 ADCFsMode 5 ADCFsRatio 4:0 Description ADC ratio selection for slave mode 0 – ADC ratio auto detect (default) 1 – ADC ratio use ADCFsRatio 0 – single speed mode (default) 1 – double speed mode Master mode ADC MCLK to sampling frequency ratio 00000 – 128 00001 – 192 00010 – 256 00011 – 384 00100 – 512 00101 – 576 00110 – 768 (default) 00111 – 1024 01000 – 1152 01001 – 1408 01010 – 1536 01011 – 2112 01100 – 2304 Other – reserved 10000 – 125 10001 – 136 10010 – 250 10011 – 272 10100 – 375 10101 – 500 10110 – 544 10111 – 750 11000 – 1000 11001 – 1088 11010 – 1496 11011 – 1500 REGISTER 14 – ADC CONTROL 6, DEFAULT 0010 0000 Bit Name Bit Revision 9.0 Description 18 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor ADC_invL 7 ADC_HPF_L 5 MAXGAIN[1:0] 3:2 MINGAIN[1:0] 1:0 Confidential ES8323S 0 – normal (default) 1 – left channel polarity inverted 0 – disable ADC left channel high pass filter 1 – enable ADC left channel high pass filter (default) ALC MAXGAIN[1:0] for PGA max gain 00000 – -6.5dB 01111– +16dB 00001 – -5 dB 10000 – +17.5dB 00010 – -3.5dB 10001 – +19dB 00011 – -2dB 10010 – +20.5dB 00100 – -0.5dB 10011 – +22dB 00101 – +1dB 10100 – +23.5dB 00100 – +2.5dB 10101 – +25dB 00111 – +4dB 10110 – +26.5dB 01000 – +5.5dB 10111 – +28dB 01001 – +7dB 11000 – +29.5dB 01010 – +8.5dB 11001 – +31dB 01011 – +10dB 11010 – +32.5dB 01100 – +11.5dB 11011 – +34dB 01101 – +13dB others – +35.5dB 01110 – +14.5dB ALC MINGAIN[1:0] for PGA min gain 00000 – -12dB 01111– +10.5dB 00001 – -10.5 dB 10000 – +12dB 00010 – -9dB 10001 – +13.5dB 00011 – -7.5dB 10010 – +15dB 00100 – -6dB 10011 – +16.5dB 00101 – -4.5dB 10100 – +18dB 00100 – -3dB 10101 – +19.5dB 00111 – -1.5dB 10110 – +21dB 01000 – 0dB 10111 – +22.5dB 01001 – +1.5dB 11000 – +24dB 01010 – +3dB 11001 – +25.5dB 01011 – +4.5dB 11010 – +27dB 01100 – +6dB 11011 – +28.5dB 01101 – +7.5dB others – +30dB 01110 – +9dB REGISTER 15 – ADC CONTROL 7, DEFAULT 0010 0000 Bit Name ADCRampRate Bit 7:6 ADCSoftRamp 5 ADCMute 2 Description 00 – 0.5 dB per 4 LRCK digital volume control ramp rate (default) 01 – 0.5 dB per 8 LRCK digital volume control ramp rate 10 – 0.5 dB per 16 LRCK digital volume control ramp rate 11 – 0.5 dB per 32 LRCK digital volume control ramp rate 0 – disabled digital volume control soft ramp 1 – enabled digital volume control soft ramp (default) 0 – normal (default) 1 – mute ADC digital output REGISTER 16 – ADC CONTROL 8, DEFAULT 1100 0000 Bit Name LADCVOL Bit 7:0 Revision 9.0 Description Digital volume control attenuates the signal in 0.5 dB incremental from 0 to –96 dB. 19 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 00000000 – 0 dB 00000001 – -0.5 dB 00000010 – -1 dB … 11000000 – -96 dB (default) REGISTER 18 – ADC CONTROL 10, DEFAULT 0011 1000 Bit Name ALCSEL Bit 7:6 MAXGAIN[4:2] 5:3 MINGAIN[4:2] 2:0 Description 00 – ALC off other – ALC on Set maximum gain of PGA 000 – -6.5 dB 001 – -0.5 dB 010 – 5.5 dB 011 – 11.5 dB Set minimum gain of PGA 000 – -12 dB 001 – -6 dB 010 – 0 dB 011 – +6 dB 100 – 17.5 dB 101 – 23.5 dB 110 – 29.5 dB 111 – 35.5 dB 100 – +12 dB 101 – +18 dB 110 – +24 dB 111 – +30 dB REGISTER 19 – ADC CONTROL 11, DEFAULT 1011 0000 Bit Name ALCLVL Bit 7:4 ALCHLD 3:0 Description ALC target 0000 – -16.5 dB 0001 – -15 dB 0010 – -13.5 dB …… 0111 – -6 dB 1000 – -4.5 dB 1001 – -3 dB 1010-1111 – -1.5 dB ALC hold time before gain is increased 0000 – 0ms 0001 – 2.67ms 0010 – 5.33ms …… (time doubles with every step) 1001 – 0.68s 1010 or higher – 1.36s REGISTER 20 – ADC CONTROL 12, DEFAULT 0011 0010 Bit Name ALCDCY Bit 7:4 ALCATK 3:0 Revision 9.0 Description ALC decay (gain ramp up) time, ALC mode/limiter mode: 0000 – 410 us/90.8 us 0001 – 820 us/182us 0010 – 1.64 ms/363us …… (time doubles with every step) 1001 – 210 ms/46.5 ms 1010 or higher – 420 ms/93 ms ALC attack (gain ramp down) time, ALC mode/limiter mode: 0000 – 104 us/22.7 us 20 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 0001 – 208 us/45.4 us 0010 – 416 us/90.8 us …… (time doubles with very step) 1001 – 53.2 ms/11.6 ms 1010 or higher – 106 ms/23.2 ms REGISTER 21 – ADC CONTROL 13, DEFAULT 0000 0110 Bit Name ALCMODE Bit 7 ALCZC 6 TIME_OUT 5 WIN_SIZE 4:0 Description Determines the ALC mode of operation: 0 – ALC mode (Normal Operation) 1 – Limiter mode. ALC uses zero cross detection circuit. 0 – disable (recommended) 1 – enable Zero Cross time out 0 – disable (default) 1 – enable Windows size for peak detector，set the window size to N*16 samples 00110 – 96 samples (default) 00111 – 102 samples ….. 11111 – 496 samples REGISTER 22 – ADC CONTROL 14, DEFAULT 0000 0000 Bit Name NGTH Bit 7:3 NGG 2:1 NGAT 0 Description Noise gate threshold 00000 – -76.5 dBFS 00001 – -75 dBFS …… 11110 – -31.5 dBFS 11111 – -30 dBFS Noise gate type x0 – PGA gain held constant 01 – mute ADC output 11 – reserved Noise gate function enable 0 – disable 1 – enable REGISTER 23 – DAC CONTROL 1, DEFAULT 0000 0000 Bit Name DACLRSWAP Bit 7 DACLRP 6 DACWL 5:3 Revision 9.0 Description 0 – normal 1 – left and right channel data swap I2S or left justified mode: 0 – left and right normal polarity 1 – left and right inverted polarity DSP/PCM mode: 0 – MSB is available on 2nd BCLK rising edge after ALRCK rising edge 1 – MSB is available on 1st BCLK rising edge after ALRCK rising edgeLRCK Polarity 000 – 24-bit serial audio data word length 21 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor DACFORMAT 2:1 Confidential ES8323S 001 – 20-bit serial audio data word length 010 – 18-bit serial audio data word length 011 – 16-bit serial audio data word length 100 – 32-bit serial audio data word length 00 – I2S serial audio data format 01 – left justify serial audio data format 10 – reserved 11 – DSP/PCM mode serial audio data format REGISTER 24 – DAC CONTROL 2, DEFAULT 0000 0110 Bit Name MODE_NOTCH Bit 7 dac_ratio_sel 6 DACFsMode 5 DACFsRatio 4:0 Description Notch mode, there is 2Fs OSR for input data 0 – notch mode disable (default) 1 – notch mode enable DAC ratio selection for slave mode 0 – DAC ratio auto detect (default) 1 – DAC ratio use DACFsRatio 0 – single speed mode (default) 1 – double speed mode Master mode DAC MCLK to sampling frequency ratio 00000 — 128; 00001 — 192; 00010 — 256; 00011 — 384; 00100 — 512; 00101 — 576; 00110 — 768; (default) 00111 — 1024; 01000 — 1152; 01001 — 1408; 01010 — 1536; 01011 — 2112; 01100 — 2304; Other — Reserved. 10000 — 125; 10001 — 136; 10010 — 250; 10011 — 272; 10100 — 375; 10101 — 500; 10110 — 544; 10111 — 750; 11000 — 1000; 11001 — 1088; 11010 — 1496; 11011 — 1500; REGISTER 25 – DAC CONTROL 3, DEFAULT 0010 0010 Bit Name DACRampRate Bit 7:6 DACSoftRamp 5 DACLeR 3 DACMute 2 Description 00 – 0.5 dB per 4 LRCK digital volume control ramp rate (default) 01 – 0.5 dB per 32 LRCK digital volume control ramp rate 10 – 0.5 dB per 64 LRCK digital volume control ramp rate 11 – 0.5 dB per 128 LRCK digital volume control ramp rate 0 – disabled digital volume control soft ramp 1 – enabled digital volume control soft ramp (default) 0 – normal (default) 1 – both channel gain control is set by DAC left gain control register 0 – normal (default) 1 – mute analog outputs for both channels REGISTER 26 – DAC CONTROL 4, DEFAULT 1100 0000 Bit Name Bit Revision 9.0 Description 22 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor LDACVOL 7:0 Confidential ES8323S Digital volume control attenuates the signal in 0.5 dB incremental from 0 to –96 dB. 00000000 – 0 dB 00000001 – -0.5 dB 00000010 – -1 dB … 11000000 – -96 dB (default) REGISTER 27 – DAC CONTROL 5, DEFAULT 1100 0000 Bit Name RDACVOL Bit 7:0 Description Digital volume control attenuates the signal in 0.5 dB incremental from 0 to –96 dB. 00000000 – 0 dB 00000001 – -0.5 dB 00000010 – -1 dB … 11000000 – -96 dB (default) REGISTER 28 – DAC CONTROL 6, DEFAULT 0000 1000 Bit Name DeemphasisMode (DEEMP) Bit 7:6 Description 00 – de-emphasis frequency disabled (default) 01 – 32 KHz de-emphasis frequency in single speed mode 10 – 44.1 KHz de-emphasis frequency in single speed mode 11 – 48 KHz de-emphasis frequency in single speed mode 0 – normal DAC left channel analog output no phase inversion (default) 1 – normal DAC left channel analog output 180 degree phase inversion DAC_invL 5 DAC_invR 4 0 – normal DAC right channel analog output no phase inversion (default) 1 – normal DAC right analog output 180 degree phase inversion ClickFree 3 0 – disable digital click free power up and down 1 – enable digital click free power up and down (default) REGISTER 29 – DAC CONTROL 7, DEFAULT 0000 0000 Bit Name ZeroL Bit 7 ZeroR 6 Mono 5 SE 4:2 Vpp_scale 1:0 Description 0 – normal (default) 1 – set left channel DAC output all zero 0 – normal (default) 1 – set right channel DAC output all zero 0 – stereo (default) 1– mono (L+R)/2 into DACL and DACR SE strength 000 – 0 (default) …… 111 – 7 00 – Vpp set at 3.5V (0.7 modulation index) (default) 01 – Vpp set at 4.0V 10 – Vpp set at 3.0V 11 – Vpp set at 2.5V REGISTER 30 – DAC CONTROL 8, DEFAULT 0001 1111 Bit Name Shelving_a[29:24] Bit 5:0 Revision 9.0 Description 30-bit a coefficient for shelving filter 23 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 31 – DAC CONTROL 9, DEFAULT 1111 0111 Bit Name Shelving_a[23:16] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 32 – DAC CONTROL 10, DEFAULT 1111 1101 Bit Name Shelving_a[15:8] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 33 – DAC CONTROL 11, DEFAULT 1111 1111 Bit Name Shelving_a[7:0] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 34 – DAC CONTROL 12, DEFAULT 0001 1111 Bit Name Shelving_b[29:24] Bit 5:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 35 – DAC CONTROL 13, DEFAULT 1111 0111 Bit Name Shelving_b[23:16] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 36 – DAC CONTROL 14, DEFAULT 1111 1101 Bit Name Shelving_b[15:8] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 37 – DAC CONTROL 15, DEFAULT 1111 1111 Bit Name Shelving_b[7:0] Bit 7:0 Description 30-bit a coefficient for shelving filter Default value is {5'h0f, 5'h1f, 5'h0f, 5'h1f, 5'h0f, 5'h1f} REGISTER 38 – DAC CONTROL 16, DEFAULT 0000 0000 Bit Name LMIXSEL Bit 5:3 RMIXSEL 2:0 Revision 9.0 Description Left input select for output mix 000 – reserved (default) 001 – LIN1 010 – DF2SE out 011 – ADC input (after mic amplifier) others – reserved Right input select for output mix 000 – reserved (default) 001 – RIN1 010 – DF2SE out 24 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 011 – ADC input (after mic amplifier) others – reserved REGISTER 39 – DAC CONTROL 17, DEFAULT 0011 1000 Bit Name LD2LO Bit 7 LI2LO 6 LI2LOVOL 5:3 MIXBOTH 2 Description 0 – left DAC to left mixer disable (default) 1 – left DAC to left mixer enable 0 – LIN signal to left mixer disable (default) 1 – LIN signal to left mixer enable LIN signal to left mixer gain 000 – 6 dB 001 – 3 dB 010 – 0 dB 011 – -3 dB 100 – -6 dB 101 – -9 dB 110 – -12 dB 111 – -15 dB (default) 0 – normal (default) 1 – RI2ROVOL use LI2LOVOL REGISTER 42 – DAC CONTROL 20, DEFAULT 0011 1000 Bit Name RD2RO Bit 7 RI2RO 6 RI2ROVOL 5:3 Description 0 – right DAC to right mixer disable (default) 1 – right DAC to right mixer enable 0 – RIN signal to right mixer disable (default) 1 – RIN signal to right mixer enable RIN signal to right mixer gain 000 – 6 dB 001 – 3 dB 010 – 0 dB 011 – -3 dB 100 – -6 dB 101 – -9 dB 110 – -12 dB 111 – -15 dB (default) REGISTER 43 – DAC CONTROL 21, DEFAULT 0001 0000 Bit Name slrck Bit 7 lrck_sel 6 offset_dis 5 mclk_dis 4 pdn_adc_anaclk 3 pdn_dac_anaclk 2 Revision 9.0 Description 0 – DACLRC and ADCLRC separate (default) 1 – DACLRC and ADCLRC same Master mode, if slrck = 1 then 0 – use DAC LRCK (default) 1 – use ADC LRCK 0 – disable offset (default) 1 – enable offset 0 – normal 1 – disable MCLK input from PAD (default) 0 – normal (default) 1 – power down ADC anaclk 0 – normal (default) 25 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 1 – power down DAC anaclk REGISTER 44 – DAC CONTROL 22, DEFAULT 0000 0000 Bit Name offset Bit 7:0 Description DC offset REGISTER 45 – DAC CONTROL 23, DEFAULT 0000 0000 Bit Name VROI Bit 4 Description 0 – 1.5k VREF to analog output resistance (default) 1 – 40k VREF to analog output resistance REGISTER 48 – DAC CONTROL 26, DEFAULT 0000 0000 Bit Name LRBOTH Bit 6 LOUTVOL 5:0 Description 0 – normal (default) 1 – ROUTVOL use LOUTVOL LOUT volume 000000 – -45dB (default) 000001 – -43.5dB 000010 – -42dB … 011110 – 0dB 011111 – 1.5dB … 100001 – 4.5dB REGISTER 49 – DAC CONTROL 27, DEFAULT 0000 0000 Bit Name ROUTVOL Bit 5:0 Description ROUT volume 000000 – -45dB (default) 000001 – -43.5dB 000010 – -42dB … 011110 – 0dB 011111 – 1.5dB … 100001 – 4.5dB REGISTER 53 – TEST MODE, DEFAULT 0000 0000 Bit Name TestModeEnable Bit 7 Description Writing a0 to this register enables the test mode REGISTER 56 – ADC TEST CONTROL 2, DEFAULT 0000 0000 Bit Name DF2SE_10dB Bit 1 Revision 9.0 Description DF2SE 10 dB enable 0 – disable (default) 1 – enable 26 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 Everest Semiconductor Confidential ES8323S 27 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018 10.PACKAGE Revision 9.0 Everest Semiconductor Confidential ES8323S 11.CORPORATE INFORMATION Everest Semiconductor Co., Ltd. No. 1355 Jinjihu Drive, Suzhou Industrial Park, Jiangsu, P.R. China, Zip Code 215021 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com Revision 9.0 28 Latest datasheet: www.everest-semi.com or info@everest-semi.com July 2018