FM24C256A-SO-T-G

FM24C256A 2-Wire Serial EEPROM Data Sheet Oct. 2016 FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 1 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION; THEY DO NOT CONVEY ANY LICENSE UNDER ANY INTELLECTUAL PROPERTY RIGHTS, OR ANY OTHER RIGHTS, BELONGING TO SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD OR A THIRD PARTY. WHEN USING THE INFORMATION CONTAINED IN THIS DOCUMENTS, PLEASE BE SURE TO EVALUATE ALL INFORMATION AS A TOTAL SYSTEM BEFORE MAKING A FINAL DECISION ON THE APPLICABILITY OF THE INFORMATION AND PRODUCTS. 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FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 2 Description Packaging Type The FM24C256A provides 262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each. The device’s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. Features z z z z z z z z z z z z Low Operation Voltage: VCC = 1.7V to 5.5V Internally Organized: 32,768 x 8 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1MHz (2.5V, 5.5V) and 400 kHz (1.7V) Compatibility Write Protect Pin for Hardware Data Protection 64-byte Page Write Modes (Partial Page Writes are Allowed) Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1,000,000 Write Cycles – Data Retention: 40 Years PDIP8 Package (RoHS Compliant) SOP8, TSSOP8, MSOP8, TDFN8 Packages (RoHS Compliant and Halogen-free) Absolute Maximum Ratings Operating Temperature (Plastic Package) Operating Temperature (Module Package) Storage Temperature (Plastic Package) Storage Temperature (Module Package) Voltage on Any Pin with Respect to Ground Maximum Operating Voltage DC Output Current -55°C to +125°C -20°C to +60°C Pin Configurations -65°C to +150°C -25°C to +70°C -1.0V to +7.0V 6.25V 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. FM24C256A 2-Wire Serial EEPROM Ver 1.3 Pin Name Function A0~A2 SDA SCL WP VCC GND NC Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Power Supply Ground Not Connect Data Sheet 3 Figure 1．Block Diagram FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 4 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other FM24CXX devices. When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is 3pF, FMSH recommends connecting the address pins to GND. WRITE PROTECT (WP): The FM24C256A has a Write Protect pin that provides hardware data protection. The WP pin allows normal write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, all write operations to the memory are inhibited. Write Protect Description WP Pin Status Part of the Memory Protected FM 24C256A WP=VCC WP=GND Full (256K) Memory Normal Read/Write Operations Memory Organization FM24C256A, 256K SERIAL EEPROM: Internally organized with 512 pages of 64 bytes each. Random word addressing requires a 15-bit data word address. FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 5 Pin Capacitance SYMBOL CIN(1) COUT(1) PARAMETER Input Capacitance Output Capacitance CONDITIONS Max Units VIN = 0V, f = 1MHz VOUT = 0V, f = 1MHz 6 8 pF pF Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = +1.7V to +5.5V, (unless otherwise noted). Symbol Parameter VCC ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VOL2 VOL1 Supply Voltage Supply Current Supply Current Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Level Input High Level Output Low Level 2 Output Low Level 1 Test Condition Min Typ 1.7 VCC = 5.0V, Read at 400KHz VCC = 5.0V, Write at 400KHz VCC = 1.7V, VIN = VCC/ VSS VCC = 5.5V, VIN = VCC/ VSS VIN = VCC/VSS VOUT = VCC/ VSS 0.4 2.0 0.10 0.05 -0.6 VCC x 0.7 VCC = 3.0V, IOL = 2.1 mA VCC =1.7V, IOL = 0.15 mA Max Units 5.5 1.0 3.0 1.0 6.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 V mA mA µA µA µA µA V V V V Note: 1. VIL min and VIH max are reference only and are not tested. FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 6 AC Characteristics Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. Symbol Parameter fSCL tLOW tHIGH tI 1 tAA Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can Start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time 1 Inputs Fall Time 1 Stop Setup Time Data Out Hold Time Write Cycle Time tBUF 1 tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR 1.7-volt Min Max 2.5-volt Min Max 5.5-volt Min Max 400 1000 1000 1.3 0.6 0.05 0.40 0.40 100 0.9 0.05 0.4 0.4 50 0.55 0.05 50 0.55 Units kHz µs µs ns µs 1.3 0.5 0.5 µs 0.6 0.6 0 100 0.25 0.25 0 100 0.25 0.25 0 100 µs µs µs ns µs ns µs ns ms Write Cycles 0.3 300 0.6 50 0.3 100 0.25 50 5 Endurance 1 3.3V, 25°C, Page Mode 0.25 50 5 1,000,000 0.3 100 5 Notes: 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ Input pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Input and output timing reference voltages: 0.5 VCC FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 7 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Figure 5). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 5). ACKNOWLEDGE: All address and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The FM24C256A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. Memory RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset in following these steps: 1. Clock up to 9 Cycles, 2. Look for SDA high in each cycle while SCL is high and then, 3. Create a start condition as SDA is high. Bus Timing Figure 2．SCL: Serial Clock, SDA: Serial Data I/O tHIGH tF tLOW SCL tSU.STA tHD.STA tR tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 8 Write Cycle Timing Figure 3．SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4．Data Validity Figure 5．Start and Stop Definition SDA SCL START FM24C256A 2-Wire Serial EEPROM STOP Ver 1.3 Data Sheet 9 Figure 6．Output Acknowledge Device Addressing The 256K EEPROM device requires a 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. The 256K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. DATA SECURITY: The FM24C256A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. The Module package device address word also consists of a mandatory one, zero sequence for the first four most significant bits. The next 3 bits are all zero. FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 10 Write Operations Read Operations BYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 8). Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 9). The data word address lower six bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 10). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 11). ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 12). FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 11 Figure 7．Device Address MSB LSB Plastic Package 1 0 1 0 A2 A1 A0 R/W Module Package 1 0 1 0 0 0 0 R/W Figure 8．Byte Write Note: 1. * = Don’t CARE bits Figure 9．Page Write Note: 1. * = Don’t CARE bits FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 12 Figure 10．Current Address Read Figure 11． Random Read Note: 1. * = Don’t CARE bits. Figure 12． Sequential Read DEVICE ADDRESS R E A D DATA n+1 DATA n S T O P DATA(n+x) DATA n+2 SDA LINE RA / C WK FM24C256A 2-Wire Serial EEPROM A C K A C K Ver 1.3 A C K N O A C K Data Sheet 13 Ordering Information FM 24C 256 A -PP -C -H Company Prefix FM = Fudan Microelectronics Group Co.,ltd Product Family 24C = 2-Wire Serial EEPROM Product Density 256 = 256K-bit Supply Voltage A = 1.7V to 5.5V Package Type (1) M2F or M2P = 8-pin Module Package (2) PD = 8-pin PDIP SO = 8-pin SOP TS = 8-pin TSSOP MS = 8-Pin MSOP DN = 8-pin TDFN Product Carrier U = Tube T = Tape and Reel R = Module Reel HSF ID Code (3) R = RoHS Compliant G = RoHS Compliant, Halogen-free, Antimony-free Note: 1. For SO, TS, DN package, MSL1 package are available, for detail please contact local sales office. 2. For the details of Module package please contact local sales office. 3. For PD, M2F, M2P package: R class only. For SO, TS, MS and DN package: G class only. FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 14 Part Marking Scheme PDIP8 SOP8 TSSOP8 FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 15 MSOP8 TDFN8 FM24C256A 2-Wire Serial EEPROM Ver 1.3 Data Sheet 16 Packaging Information PDIP 8 Symbol MIN ‐‐‐ A A1 0.380 b 0.380 b2 1.300 C 0.200 D 9.000 E1 6.100 E 7.320 e L 2.920 ‐‐‐ eB NOTE: 1. Dimensions are in Millimeters. FM24C256A 2-Wire Serial EEPROM MAX 5.000 --0.570 1.700 0.360 10.000 7.000 8.250 2.540(BSC) 3.810 10.900 Ver 1.3 Data Sheet 17 SOP 8 Symbol MIN A 1.350 A1 0.050 b 0.330 c 0.150 D 4.700 E1 3.700 E 5.800 e L 0.400 θ 0° NOTE: 1. Dimensions are in Millimeters. FM24C256A 2-Wire Serial EEPROM MAX 1.750 0.250 0.510 0.260 5.150 4.100 6.200 1.270(BSC) 1.270 8° Ver 1.3 Data Sheet 18 TSSOP8 Symbol MIN D 2.900 E1 4.300 b 0.190 c 0.090 E 6.200 A A1 0.050 e L 0.450 θ 0° NOTE: 1. Dimensions are in Millimeters. FM24C256A 2-Wire Serial EEPROM MAX 3.100 4.500 0.300 0.200 6.600 1.200 0.150 0.650 (BSC) 0.750 8° Ver 1.3 Data Sheet 19 MSOP8 Symbol MIN A 0.820 A1 0.020 b 0.220 c 0.080 D 2.900 e E 2.900 E1 4.750 L 0.400 θ 0° NOTE: 1. Dimensions are in Millimeters. FM24C256A 2-Wire Serial EEPROM MAX 1.100 0.150 0.380 0.230 3.100 0.650 (BSC) 3.100 5.050 0.800 8° Ver 1.3 Data Sheet 20 TDFN8 Symbol MIN A 0.700 A1 0.000 D 1.900 E 2.900 D2 1.400 E2 1.400 k b 0.200 e L 0.200 NOTE: 1. Dimensions are in Millimeters. FM24C256A 2-Wire Serial EEPROM MAX 0.800 0.050 2.100 3.100 1.600 1.700 0.150(MIN) 0.300 0.500(TYP) 0.500 Ver 1.3 Data Sheet 21 Revision History Version 1.0 1.1 Publication Pages date May. 2011 22 Jun. 2011 Paragraph or Illustration Revise Description Initial Document Release. 23 Ordering Information Part Marking Scheme Packaging Information 1.2 Apr. 2013 23 Disclaimer Ordering Information Part Marking Scheme Packaging Information 1.3 Oct. 2016 23 Ordering Information Part Marking Scheme Packaging Information FM24C256A 2-Wire Serial EEPROM Added the MSOP8 packaging type. 1. Modified the Disclaimer. 2. Removed 6-Pin module package offering 3. Updated the “Ordering Information” 4. Updated the “Part Marking Scheme” 5. Updated the “Packaging Information”. 1. Updated the “Ordering Information” 2. Updated the “Part Marking Scheme” 3. Updated the “Packaging Information”. Ver 1.3 Data Sheet 22 Sales and Service Shanghai Fudan Microelectronics Group Co., Ltd. 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