FM24C256E-SO-T-G

FM24C256E 2-Wire Serial EEPROM With Unique ID and Security Sector Data Sheet Jun. 2017 Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 1 INFORMATION IN THIS DOCUMENT IS INTENDED AS A REFERENCE TO ASSIST OUR CUSTOMERS IN THE SELECTION OF SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD PRODUCT BEST SUITED TO THE CUSTOMER'S APPLICATION; THEY DO NOT CONVEY ANY LICENSE UNDER ANY INTELLECTUAL PROPERTY RIGHTS, OR ANY OTHER RIGHTS, BELONGING TO SHANGHAI FUDAN MICROELECTRONICS GROUP CO., LTD OR A THIRD PARTY. WHEN USING THE INFORMATION CONTAINED IN THIS DOCUMENTS, PLEASE BE SURE TO EVALUATE ALL INFORMATION AS A TOTAL SYSTEM BEFORE MAKING A FINAL DECISION ON THE APPLICABILITY OF THE INFORMATION AND PRODUCTS. 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Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 2 Description The FM24C256E provides 262,144 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 32,768 words of 8 bits each, with 128-bit UID and 64-byte Security Sector, and much improved the reliability by an internal ECC logic. The device‟s cascadable feature allows up to 8 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Packaging Type SOP 8           1 2 8 7 VCC WP A2 GND 3 4 6 5 SCL SDA TSSOP8 Features     A0 A1 A0 A1 A2 GND Low Operation Voltage: VCC = 1.7V to 5.5V Internally Organized: 32,768 x 8 2-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bi-directional Data Transfer Protocol 1MHz (2.5V~5.5V) and 400 kHz (1.7V) Compatibility Write Protect Pin for Hardware Data Protection 64-Byte Page Write Modes (Partial Page Writes are Allowed) Lockable 64-Byte Security Sector 128-Bit Unique ID for each device Self-timed Write Cycle (5 ms max) Enhanced ESD protection High-reliability – Endurance: 1,000,000 Write Cycles – Data Retention:40 Years SOP8, TSSOP8, MSOP8, TDFN8, Thin 6-ball WLCSP and Thin 4-ball WLCSP Packages (RoHS Compliant and Halogen-free) VCC WP SCL SDA MSOP8 A0 A1 A2 GND 8 7 6 5 1 2 3 4 VCC WP SCL SDA TDFN8 A0 A1 A2 GND 1 2 3 4 8 7 6 5 Vcc WP SCL SDA Module package (8 Pin) VCC C1 C5 GND NC C2 C6 NC SCL C3 C7 SDA NC C4 C8 NC Thin 4-ball WLCSP (CT) Pin1 Pin2 VCC GND Pin4 Pin3 SCL SDA (TOP VIEW) Thin 6-ball WLCSP (CTB) Absolute Maximum Ratings Operating Temperature (Plastic Package) Operating Temperature (Module Package) Storage Temperature (Plastic Package) Storage Temperature (Module Package) Voltage on Any Pin with Respect to Ground Maximum Operating Voltage DC Output Current VESD(HBM) 8 7 6 5 1 2 3 4 Pin1 Pin2 WP A2 SDA Pin6 Pin5 Pin4 VCC SCL GND Pin3 (TOP VIEW) -55°C to +130°C -20°C to +60°C Pin Configurations -65°C to +150°C -25°C to +70°C -0.5V to +7.0V 6.25V 5.0 mA 4000V Pin Name Function A0~A2 SDA SCL WP VCC GND NC Device Address Inputs Serial Data Input/Output Serial Clock Input Write Protect Power Supply Ground Not Connect *NOTICE: Stresses beyond those listed under “Absolute Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 3 Figure 1．Block Diagram WP WRITE PROTECT LOGIC EN HV PUMP & TIMING CONTROL LOGIC HV A0 A1 DATA BUFFER DEVICE ADDRESS COMPARATOR DATA WORD ADDRESS COUNTER 128-bit Unique ID SCL START STOP LOGIC SDA X DECODER A2 EEPROM ACK SEC SECTOR Din Dout DATA SERIAL MUX DATA & ACK INPUT/OUTPUT LOGIC Y DECODER OD OUTPUT Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 4 Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hardwired or left not connected for hardware compatibility with other FM24CXX devices. When the pins are hardwired, as many as eight 256K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capacitive coupling to the circuit board V CC plane is 3pF, FMSH recommends connecting the address pins to GND. WRITE PROTECT (WP): The FM24C256E has a Write Protect pin that provides hardware data protection. The WP pin allows normal write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive coupling to the circuit board Vcc plane is 3pF, FMSH recommends connecting the WP to GND. Switching WP to VCC prior to a write operation creates a software write protected function. Write Protect Description WP Pin Status Part of the Memory Protected WP=VCC WP=GND Full Memory Protected No Protected Memory Organization FM24C256E, 256K SERIAL EEPROM: Internally organized with 512 pages of 64 bytes each, the 256K requires a 15-bit data word address for random word addressing. Security Sector: The FM24C256E offers 64-byte Security Sectors which can be written and (later) permanently locked in Read-only mode. This memory may be used by the system manufacturers to store security and other important information separately from the main memory array. Unique ID: The FM24C256E utilizes a separate memory block containing a factory programmed read-only 128-bit unique ID. Byte Number Device ADDR Page ADDR 63 ··· 0 0 1 1010 2 Data Memory (512P X 64B) ··· 511 xxxx x00x 1011 Security Sector (64 Bytes) xxxx xxxx1 xxxx x01x 1011 Unique ID（128 Bits） xxxx xxxx2 Note: 1. Address bits ADDR must be 00, ADDR define byte address, other bits are don‟t care 2. Address bits ADDR must be 01, ADDR define byte address, other bits are don‟t care Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 5 Pin Capacitance SYMBOL 1 CIN COUT1 PARAMETER Input Capacitance Output Capacitance CONDITIONS Max Units VIN = 0V, f = 1MHz VOUT = 0V, f = 1MHz 6 8 pF pF Note: 1. This parameter is characterized and is not 100% tested. Cycling Performance By Groups Of Four Bytes PARAMETER SYMBOL Write cycle endurance Ncycle Test Condition TA ≤ 25 °C, VCC(min) < VCC < VCC(max) Max Units 1,000,000 Write cycle Note: 1. This parameter is characterized and qualification. It is not 100% tested. 2. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3] where N is an integer. 3. A Write cycle is executed when either a Page Write, a Byte Write, a Write Security Sector or a Lock Security instruction is decoded. When using these instructions, refer also to Section: Cycling with Error Correction Code (ECC) on page 14. Data Retention PARAMETER Data retention Test Condition TA = 55 °C Min 40 Units Year Note: 1. This parameter is characterized and qualification. It is not 100% tested. DC Characteristics Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = +1.7V to +5.5V, (unless otherwise noted). Symbol Parameter VCC ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 Supply Voltage Supply Current Supply Current Standby Current Standby Current Input Leakage Current Output Leakage Current Input Low Level Test Condition Min Typ 1.7 VCC = 5.0V, Read at 400KHz VCC = 5.0V, Write at 400KHz VCC = 1.7V, VIN = VCC/ VSS VCC = 5.5V, VIN = VCC/ VSS VIN = VCC/VSS VOUT = VCC/ VSS 0.4 2.0 0.1 0.05 -0.6 Max Units 5.5 1.0 3.0 1.0 6.0 3.0 3.0 VCC x 0.3 V mA mA µA µA µA µA V Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 6 Symbol Parameter 1 VIH VOL2 VOL1 Input High Level Output Low Level 2 Output Low Level 1 Test Condition Min VCC x 0.7 VCC = 3.0V, IOL = 2.1 mA VCC =1.7V, IOL = 0.15 mA Typ Max Units VCC + 0.5 0.4 0.2 V V V Note: 1. VIL min and VIH max are reference only and are not tested. AC Characteristics 400 kHz AC characteristics Recommended operating conditions: TA = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. Symbol Parameter Min Max Units fSCL tLOW tHIGH tI 1 tAA B B B B B B B B B B tBUF 1 B B tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR B B B B B B B B B B B B B B B B B Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can Start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time 1 Inputs Fall Time 1 Stop Setup Time Data Out Hold Time Write Cycle Time 400 1.3 0.6 0.1 80 0.9 kHz µs µs ns µs 1.3 µs 0.6 0.6 0 100 µs µs µs ns ns ns µs ns ms 300 300 0.6 100 5 1 MHz AC characteristics Recommended operating conditions: TA = -40°C to +85°C, VCC = +2.5V to +5.5V, CL = 100 pF (unless otherwise noted). Test conditions are listed in Note 2. Symbol Parameter Min Max Units fSCL tLOW tHIGH tI 1 tAA B B B B B B B B B B tBUF 1 B B tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF B B B B B B B B B B B Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time Clock Low to Data Out Valid Time the bus must be free before a new transmission can Start Start Hold Time Start Setup Time Data In Hold Time Data In Setup Time Inputs Rise Time 1 Inputs Fall Time 1 1 500 320 100 80 450 MHz ns ns ns ns 500 ns 250 250 0 50 ns ns ns ns ns ns 120 120 Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 7 tSU.STO tDH tWR B B B B B B Stop Setup Time Data Out Hold Time Write Cycle Time 250 100 5 ns ns ms Notes: 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3 kΩ Input pulse voltages: 0.3 VCC to 0.7 VCC Input and output timing reference voltages: 0.3 VCC to 0.7 VCC Input rise and fall times: ≤ 50 ns Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 8 Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Figure 4). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Figure 5). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Figure 5). ACKNOWLEDGE: All address and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The FM24C256E features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the stop bit and the completion of any internal operations. Memory RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset in following these steps: 1. Clock up to 9 Cycles, 2. Look for SDA high in each cycle while SCL is high and then, 3. Create a start condition as SDA is high. Bus Timing Figure 2．SCL: Serial Clock, SDA: Serial Data I/O tHIGH tF tLOW SCL tSU.STA tHD.STA tR tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 9 Write Cycle Timing Figure 3．SCL: Serial Clock, SDA: Serial Data I/O SCL SDA 8th BIT ACK tWR1 WORD n STOP CONDITION START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4．Data Validity SDA SCL DATA STABLE DATA STABLE DATA CHANGE Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 10 Figure 5．Start and Stop Definition SDA SCL START STOP Figure 6．Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 11 Device Addressing Data Memory Access: The 256K EEPROM device requires a 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Table 1~3). The device address word consists of a mandatory „1010‟(Ah) sequence for the first four most significant bits as shown in Table 1. This is common to all the EEPROM devices. The 256K EEPROM uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The A2, A1 and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The Module package device address word also consists of a mandatory „1010‟(Ah) sequence for the first four most significant bits. The next 3 bits are all zero. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Unique ID Access: The FM24C256E utilizes a separate memory block containing a factory programmed 128-bit unique ID. Access to this memory location is obtained by beginning the device address word with a „1011‟(Bh) sequence (refer to Table 1). The behavior of the next three bits (A2, A1 and A0) remains the same as during a standard memory addressing sequence. The eighth bit of the device address needs be set to a one to read the Serial Number. Writing or altering the 128-bit unique ID is not possible. For more details on accessing this special feature, See Read Operations on page 15. Security Sector Access: The FM24C256E offers 64-byte Security Sector which can be written and (later) permanently locked in Read-only mode. Access to this memory location is obtained by beginning the device address word with a „1011‟(Bh) sequence (refer to Table 1). The behavior of the next three bits (A2, A1 and A0) remains the same as during a standard memory addressing sequence. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. For more details on accessing this special feature, See Write Operations and Read Operations on page 14,15. ECC Error Status Register Access: The FM24C256E offers 1-bit ECC Error Status Register (EESR) to indicate whether there is a single error bit in a group of four bytes during a Read operation. Access to EESR is obtained by beginning the device address word with a „1011‟(Bh) sequence (refer to Table 1). The behavior of the next three bits (A2, A1 and A0) remains the same as during a standard memory addressing sequence. The eighth bit of the device address needs be set to a one to read the EESR. For more details on accessing this special feature, See Write Operations and Read Operations on page 14,15. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. DATA SECURITY: The Device has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 12 Table 1．Device Address Access Area Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data Memory Security Sector Security Sector Lock Bit 0 0 0 0 1 1 1 1 0 1 1 1 A2 A2 A2 A2 A1 A1 A1 A1 A0 A0 A0 A0 R/W R/W R/W Unique ID Number 1 1 1 1 Ecc Error status Register 1 0 1 1 A2 A1 A0 1 MSB 1 LSB Table 2．First Word Address Access Area Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data Memory Security Sector Security Sector Lock Bit Unique ID Number Ecc Error status Register x x x x x A14 x x x x A13 x x x x A12 x x x x A11 x x x x A10 0 1 0 1 A9 0 0 1 1 A8 x X x x MSB LSB NOTE: x = Don`t care bit. Table 3．Second Word Address Access Area Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Data Memory Security Sector Security Sector Lock Bit Unique ID Number Ecc Error status Register A7 x x x x A6 x x x x A5 A5 x x x A4 A4 x x x A3 A3 x 0 x A2 A2 x 0 x A1 A1 x 0 x A0 A0 x 0 x MSB LSB NOTE: x = Don`t care bit. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 13 Write Operations BYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7 on page 16). PAGE WRITE: The 256K EEPROM is capable of 64-byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 63 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8 on page 16). The data word address lower seven bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 64 data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. WRITE SECURITY SECTOR: Write the Security Sector is similar to the page write but requires use of device address, and the special word address seen in Table 1~3 on page 13. The higher address bits ADDR are don‟t care except for address bits ADDR，which must be equal to „00b‟. Lower address bits ADDR define the byte address inside the Security Sector (see Figure 12 on page 18). If the Security Sector is locked, the data bytes transferred during the Write Security Sector operation are not acknowledged (NoAck). LOCK SECURITY SECTOR: Lock the Security Sector is similar to the byte write but requires use of device address, and special word address seen in Table 1~3 on page 13. The word address bits ADDR must be „10b‟, all other word address bits are don‟t care. The data byte must be equal to the binary value xxxx xx1x, where x is don't care (see Figure 14 on page 19). If the Security Sector is locked, the data bytes transferred during the Lock Security Sector operation are not acknowledged (NoAck). Cycling with Error Correction Code (ECC): The FM24C256E offer an Error Correction Code (ECC) logic. The ECC is an internal logic function which is transparent for the 2-wire Serial communication protocol. The ECC logic is implemented on each group(1) of four EEPROM bytes. Inside a group, if a single bit out of the four bytes happens to be erroneous during a Read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group(1). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the four bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined in Section Cycling Performance By Groups Of Four Bytes on Page 6. Note： 1. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 14 Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 9 on page 17). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (see Figure 10 on page 17). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 11 on page 17) UNIQUE ID READ: Reading the serial number is similar to the sequential read but requires use of the device address, a dummy write, and the use of specific word address seen in Table 1~3 on page 13. The higher address bits ADDR are don‟t care except for address bits ADDR，which must be equal to „01b‟. Lower address bits ADDR define the byte address inside the UID. If the application desires to read the first byte of the UID, the lower address bits ADDR would need to be „0000b‟. When the end of the 128-bit UID number is reached (16 bytes of data), the data word address will roll-over back to the beginning of the 128-bit UID number. The Unique ID Read operation is terminated when the microcontroller does not respond with a zero (ACK) and instead issues a Stop condition (see Figure 16 on page 20). READ SECURITY SECTOR ： Read the Security Sector is similar to the random read but requires use of device address, a dummy write, and the use of specific word address seen in Table 1~3 on page 13. The higher address bits ADDR are don‟t care except for address bits ADDR，which must be equal to „00b‟. The lower address bits ADDR define the byte address inside the Security Sector. The internal byte address is automatically incremented to the next byte address after each byte of data is clocked out. When the last byte (3Fh) is reached, it will roll over to 00h, the first byte of the Security Sector, and continue to increment. (see Figure 13 on page 18). READ LOCK STATUS：There are two ways to check the lock status of the Security Sector. 1. The first way is initiated by a Security Sector Write, the EEPROM will acknowledge if the Security Sector is unlocked, while it will not acknowledge if the Security Sector is locked. Once the acknowledge bit is read, it is recommended to generate a Start condition followed by a Stop condition, so that:  Start: the truncated command is not executed because the Start condition resets the device internal logic  Stop: the device is then set back into Standby mode by the Stop condition. 2. The second way is initiated by a Lock Status Read. Lock Status Read is similar to the random read but requires use of device address seen in Table 1~3 on page 13, a dummy write, and the use of specific word address. The address bits ADDR must be „10b‟, all other address bits are Don't Care. The Lock bit is the BIT1 of the byte read on SDA. It is at “1” when the lock is active and at “0” when the lock is not active. The same data is shifted out repeatedly until the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 15 on page 19). Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 15 READ ECC ERROR STATUS REGISTER: Due to the ECC is an internal logic function which is transparent for the 2-wire Serial communication protocol, the microcontroller will not find out if there is a single error bit issue during Read operation. The device offers 1-bit volatile ECC Error Status Register (EESR) to find whether there are error bits after a Read operation. Reading the EESR bit is similar to the random read but requires use of device address seen in Table 1~3 on page 13, a dummy write, and the use of specific word address. The address bits ADDR must be „11b‟, all other address bits are Don't Care. The EESR is indicated by the whole byte read on SDA. It is at “FFh” when there are one or more error bits and at “00h” when the group of four bytes all correct. The same data is shifted out repeatedly until the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 17 on page 20). If the users want to find the group address contains the error bit, according to the following steps:  Start reading from the address of the user concerned. The Read operation must by group address, and then following the Read EESR operation. If current group address is no error, then reading the next group address.  Reading by group address and Read EESR operation must be executed alternately until the error group address is found.  The EESR bit will be reset to „0b‟ at the end of each Read EESR operation. Figure 7．Byte Write S T A R T W R I T E DEVICE ADDRESS SDA LINE FIRST WORD ADDRESS SECOND WORD ADDRESS S T O P DATA * M S B LRA S / C BW K L A S C BK M S B A C K A C K Note: 1. * = Don’t CARE bits Figure 8．Page Write S T A R T DEVICE ADDRESS W R I FIRST SECOND T E WORD ADDRESS (n) WORD ADDRESS (n) SDA LINE DATA (n) S T O P DATA(n+x) * M S B LRA S / C BW K A C K A C K A C K A C K Note: 1. * = Don’t CARE bits Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 16 Figure 9．Current Address Read S T A R T DEVICE ADDRESS R E A D S T O P DATA SDA LINE M S B L R A S / C BWK N O A C K Figure 10． Random Read S T A R T DEVICE ADDRESS W R I T E SECOND WORD ADDRESS n FIRST WORD ADDRESS n SDA LINE S T A R T DEVICE ADDRESS R E A D S T O P DATA n * M S B A C K LRA S / C BW K A C K A C K N O A C K DUMMY WRITE Note: 1. * = Don’t CARE bits. Figure 11． Sequential Read DEVICE ADDRESS R E A D DATA n+1 DATA n S T O P DATA(n+x) DATA n+2 SDA LINE RA / C WK A C K A C K A C K N O A C K Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 17 Figure 12． Write Security Sector S T A R T W R I T E DEVICE ADDRESS FIRST WORD ADDRESS n SDA LINE ** ** * M S B SECOND WORD ADDRESS n * ** A C K LRA S / C BW K A C K DATA n+1 DATA n A C K DATA n+2 A C K S T O P DATA n+x A C K A C K Note: 1. * = Don’t CARE bits. Figure 13． Read Security Sector S T A R T DEVICE ADDRESS W R I T E SDA LINE FIRST WORD ADDRESS n ** ** * M S B S T A R T SECOND WORD ADDRESS n * * * A C K LRA S / C BW K R E A D DEVICE ADDRESS A C K A C K DUMMY WRITE DATA n DATA n+1 A C K DATA n+2 A C K S T O P DATA n+x A C K N O A C K Note: 1. * = Don’t CARE bits. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 18 Figure 14． Lock Security Sector S T A R T DEVICE ADDRESS W R I T E SDA LINE ** ** * M S B SECOND WORD ADDRESS n FIRST WORD ADDRESS n * ** * * ** ** A C K LRA S / C BW K S T O P DATA 0 A C K A C K Note: 1. * = Don’t CARE bits. Figure 15． Read Lock Status S T A R T DEVICE ADDRESS W R I T E SDA LINE FIRST WORD ADDRESS n ** ** * M S B S T A R T SECOND WORD ADDRESS n * ** * * ** ** A C K LRA S / C BW K R E A D DEVICE ADDRESS A C K A C K DUMMY WRITE LOCK BYTE LOCK BYTE « LOCK BYTE A C K A C K LOCK BYTE « « S T O P « A C K N O A C K Note: 1. * = Don’t CARE bits. 2. « = LOCK bits. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 19 Figure 16．Read Unique ID S T A R T DEVICE ADDRESS W R I T E SECOND WORD ADDRESS n FIRST WORD ADDRESS n SDA LINE ** ** * M S B S T A R T * Serial Number Data 0 ** * * A C K LRA S / C BW K R E A D DEVICE ADDRESS A C K A C K A C K DUMMY WRITE Serial Number Data 1 Serial Number Data 2 A C K Serial Number Data 3 A C K S T O P Serial Number Data F N O A C K A C K Note: 1. * = Don’t CARE bits. Figure 17． Read EESR S T A R T DEVICE ADDRESS W R I T E SDA LINE FIRST WORD ADDRESS n ** ** * M S B S T A R T SECOND WORD ADDRESS n * DEVICE ADDRESS ** * * ** ** A C K LRA S / C BW K R E A D A C K A C K DUMMY WRITE EESR BYTE EESR BYTE EESR BYTE A C K A C K S T O P EESR BYTE A C K N O A C K Note: 1. * = Don’t CARE bits. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 20 Ordering Information FM 24C 256 E -PP -C -H Company Prefix FM = Shanghai Fudan Microelectronics Group Co.,ltd Product Family 24C = 2-Wire Serial EEPROM Product Density 256 = 256K-bit Device Type E = with 128-bit Unique ID with 64-byte Security Sector with ECC(Error Correction Code) Logic Package Type 1 SO = 8-pin SOP TS = 8-pin TSSOP MS =8-pin MSOP 2 DN= 8-pin TDFN (2x3mm) 3 CT = Thin 4-ball WLCSP CTB = Thin 6-ball WLCSP 3 M2F or M2P = 8-pin Module Package 3 Product Carrier U = Tube T = Tape and Reel R = Module Reel HSF ID Code 4 Blank or R = RoHS Compliant G = RoHS Compliant, Halogen-free, Antimony-free Note: 1. For SO, TS, DN package, MSL1 package are available, for detail please contact local sales office. 2. For Thinner package please contact local sales office. 3. For the details of WLCSP package and Module package please contact local sales office. 4. For SO, TS, MS, DN CT and CTB package: G class only. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 21 Part Marking Scheme SOP8 FM24C256E YYWWALHM Moisture Sensitivity Level 1 = MSL1 Blank=MSL3 HSF ID Code R = RoHS Compliant G = RoHS Compliant, Halogen-free, Antimony-free Lot Number（just with 0~9、A~Z） Assembly’s Code Work week during which the product was molded (eg..week 12) The last two digits of the year In which the product was sealed / molded. TSSOP8 FM24C256E YYWWALHM Moisture Sensitivity Level 1=MSL1 Blank=MSL3 HSF ID Code R = RoHS Compliant G = RoHS Compliant, Halogen-free, Antimony-free Lot Number（just with 0~9、A~Z） Assembly’s Code Work week during which the product was molded (eg..week 12) The last two digits of the year In which the product was sealed / molded. MSOP8 FM24C256E YYWWALHM Moisture Sensitivity Level 1=MSL1 Blank=MSL3 HSF ID Code G = RoHS Compliant, Halogen-free, Antimony-free Lot Number（just with 0~9、A~Z） Assembly’s Code Work week during which the products was molded (eg..week 12) The last two digits of the year In which the product was sealed / molded. Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 22 TDFN8 4 C 8 E X W A L H Product Density Code The month (hexadecimal digit) in which the product was molded. The last one digit of the year In which the product was sealed / molded. HSF ID Code S G = RoHS Compliant, Halogen-free, Antimony-free Moisture Sensitivity Level 1=MSL1 Blank=MSL3 Lot Number（just with 0~9、A~Z） Assembly’s Code Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 23 Packaging Information SOP 8 Symbol MIN A 1.350 A1 0.050 b 0.330 c 0.150 D 4.700 E1 3.700 E 5.800 e L 0.400 θ 0° NOTE: 1. Dimensions are in Millimeters. MAX 1.750 0.250 0.510 0.260 5.150 4.100 6.200 1.270(BSC) 1.270 8° Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 24 TSSOP8 Symbol MIN D 2.900 E1 4.300 b 0.190 c 0.090 E 6.200 A A1 0.050 e L 0.450 θ 0° NOTE: 1. Dimensions are in Millimeters. MAX 3.100 4.500 0.300 0.200 6.600 1.200 0.150 0.650 (BSC) 0.750 8° Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 25 MSOP8 Symbol MIN A 0.820 A1 0.020 b 0.220 c 0.080 D 2.900 e E 2.900 E1 4.750 L 0.400 θ 0° NOTE: 1. Dimensions are in Millimeters. MAX 1.100 0.150 0.380 0.230 3.100 0.650 (BSC) 3.100 5.050 0.800 8° Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 26 TDFN8 Symbol MIN A 0.700 A1 0.000 D 1.900 E 2.900 D2 1.400 E2 1.400 k b 0.200 e L 0.200 NOTE: 1. Dimensions are in Millimeters. MAX 0.800 0.050 2.100 3.100 1.600 1.700 0.150(MIN) 0.300 0.500(TYP) 0.500 Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 27 Revision History Publication Pages date Preliminary Jan 2017 29 Version 1.0 Jun.2017 29 Paragraph or Illustration Revise Description Initial document Release. 1. Added 4-ball WLCSP package in Packaging Type 2. Updated endurance and data retention spec. 3. Updated Packaging Information Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 28 Sales and Service Shanghai Fudan Microelectronics Group Co., Ltd. Address: Bldg No. 4, 127 Guotai Rd, Shanghai City China. Postcode: 200433 Tel: (86-021) 6565 5050 Fax: (86-021) 6565 9115 Shanghai Fudan Microelectronics (HK) Co., Ltd. Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road, Tsimshatsui East, Kowloon, Hong Kong Tel: (852) 2116 3288 2116 3338 Fax: (852) 2116 0882 Beijing Office Address: Room 423, Bldg B, Gehua Building, 1 QingLong Hutong, Dongzhimen Alley north Street, Dongcheng District, Beijing City, China. Postcode: 100007 Tel: (86-010) 8418 6608 Fax: (86-010) 8418 6211 Shenzhen Office Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel, Huaqiang Rd (North), Shenzhen City, China. Postcode: 518028 Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611 Fax: (86-0755) 8335 9011 Shanghai Fudan Microelectronics (HK) Ltd Taiwan Representative Office Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist., Taipei City 114, Taiwan Tel : (886-2) 7721 1889 Fax: (886-2) 7722 3888 Shanghai Fudan Microelectronics (HK) Ltd Singapore Representative Office Address : 237, Alexandra Road, #07-01 The Alexcier, Singapore 159929 Tel : (65) 6472 3688 Fax: (65) 6472 3669 Shanghai Fudan Microelectronics Group Co., Ltd NA Office Address :2490 W. Ray Road Suite#2 Chandler, AZ 85224 USA Tel : (480) 857-6500 ext 18 Web Site: http://www.fmsh.com/ Data Sheet FM24C256E 2-Wire Serial EEPROM V1.0 29