ML54SD1AE

ML51/ML54/ML56 1T 8051 8-bit Microcontroller NuMicro® Family ML51/ML54/ML56 Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro® microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Sep. 1, 2020 Page 1 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. ML51/ML54/ML56 TABLE OF CONTENTS 1 GENERAL DESCRIPTION ............................................................................ 10 2 FEATURES .................................................................................................... 11 3 PART INFORMATION ................................................................................... 16 3.1 ML51/ML54/ML56 Series Package Type ................................................................. 16 3.2 ML51/ML54/ML56 Series Selection Guide .............................................................. 17 3.2.1 ML51 Series .................................................................................................................... 17 3.2.2 ML54 Series .................................................................................................................... 20 3.2.3 ML56 Series .................................................................................................................... 21 3.3 ML51/ML54/ML56 Series Selection Code ............................................................... 22 4 PIN CONFIGURATION .................................................................................. 23 4.1 Pin Configuration ......................................................................................................... 23 4.1.1 ML51/ML54/ML56 Series Pin Diagram ....................................................................... 23 4.1.2 ML51/ML54/ML56 Series Multi Function Pin Diagram ............................................. 31 4.2 Pin Description ............................................................................................................. 71 4.2.1 ML51/ML54/ML56 Series Pin Mapping ....................................................................... 71 4.2.2 ML51/ML54/ML56 Series Pin Functional Description ............................................... 73 5 BLOCK DIAGRAM ......................................................................................... 78 5.1 ML51/ML54/ML56 Series Full Function Block ........................................................ 78 ML51/ML54/ML56 SERIES DATASHEET 6 FUNCTIONAL DESCRIPTION ....................................................................... 79 6.1 Memory Organization.................................................................................................. 79 6.2 System Manager ......................................................................................................... 80 6.3 Flash Memory Control ................................................................................................ 81 6.3.1 In-application-programming (IAP) ................................................................................ 81 6.3.2 In-Circuit-Programming (ICP) ....................................................................................... 81 6.3.3 On-Chip-Debugger (ICE)............................................................................................... 81 6.4 GPIO Port Structure and Operation.......................................................................... 82 6.4.1 GPIO Mode ..................................................................................................................... 82 6.5 Timer.............................................................................................................................. 83 6.5.1 Overview .......................................................................................................................... 83 6.6 Watchdog Timer (WDT) .............................................................................................. 84 6.7 Self Wake-up Timer (WKT) ........................................................................................ 85 6.7.1 Overview .......................................................................................................................... 85 6.8 Pulse Width Modulated (PWM) ................................................................................. 86 6.8.1 Overview .......................................................................................................................... 86 6.8.2 Features ........................................................................................................................... 86 6.9 Serial Port (UART0 & UART1) .................................................................................. 87 Sep. 1, 2020 Page 2 of 164 Rev 2.00 ML51/ML54/ML56 6.9.1 Overview .......................................................................................................................... 87 6.9.2 Features ........................................................................................................................... 87 6.10 Smart Card Interface (SC) ................................................................................... 88 6.10.1 Overview .......................................................................................................................... 88 6.10.2 Features ........................................................................................................................... 88 6.11 Serial Peripheral Interface (SPI) ......................................................................... 89 6.11.1 Overview .......................................................................................................................... 89 6.11.2 Features ........................................................................................................................... 89 6.12 2 Inter-Integrated Circuit (I C) ................................................................................. 90 6.12.1 Overview .......................................................................................................................... 90 6.12.2 Features ........................................................................................................................... 90 6.13 12-bit Analog-to-digital Converter (ADC) ........................................................... 91 6.13.1 Overview .......................................................................................................................... 91 6.14 Voltage Reference (VREF)................................................................................... 92 6.15 Analog Comparator Controller (ACMP).............................................................. 93 6.15.1 Overview .......................................................................................................................... 93 6.15.2 Feature ............................................................................................................................. 93 6.16 PDMA Controller (PDMA) ..................................................................................... 94 6.16.1 Overview .......................................................................................................................... 94 6.16.2 Feature ............................................................................................................................. 94 6.17 LCD Driver .............................................................................................................. 95 6.17.2 Features ........................................................................................................................... 95 6.18 Real Time Clock (RTC) ......................................................................................... 96 6.18.1 Overview .......................................................................................................................... 96 6.18.2 Features ........................................................................................................................... 96 6.19 Touch Key (TK) ...................................................................................................... 97 6.19.1 Overview .......................................................................................................................... 97 6.19.2 Features ........................................................................................................................... 97 6.20 Auxiliary Features .................................................................................................. 98 6.20.1 Dual DPTRs .................................................................................................................... 98 6.20.2 96-Bit Unique Code (UID) ........................................................................................... 102 6.21 Instruction Set ...................................................................................................... 103 6.21.1 Instruction Set And Addressing Modes ..................................................................... 103 6.21.2 Read-Modify-Write Instructions .................................................................................. 105 6.21.3 Instruction Set ............................................................................................................... 105 7 APPLICATION CIRCUIT .............................................................................. 109 7.1 Power Supply Scheme ............................................................................................. 109 7.2 Peripheral Application Scheme ............................................................................... 110 Sep. 1, 2020 Page 3 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 6.17.1 Overview .......................................................................................................................... 95 ML51/ML54/ML56 8 ELECTRICAL CHARACTERISTICS............................................................ 111 8.1 General Operating Conditions ................................................................................. 111 8.1.1 ML51 32KB/16KB Flash Series .................................................................................. 111 8.1.2 ML51 64KB Flash/ML54/ML56 Series ...................................................................... 111 8.2 DC Electrical Characteristics ................................................................................... 112 8.2.1 Supply Current Characteristics ................................................................................... 112 8.2.2 On-Chip Peripheral Current Consumption ................................................................ 120 8.2.3 Wakeup Time from Low-Power Modes ..................................................................... 122 8.2.4 I/O DC Characteristics ................................................................................................. 123 8.3 AC Electrical Characteristics ................................................................................... 125 8.3.1 24 MHz Internal High Speed RC Oscillator (HIRC) ................................................. 125 8.3.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) ................................................ 126 8.3.3 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics 127 8.3.4 External 4~24 MHz High Speed Clock Input Signal Characteristics .................... 129 8.3.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics 130 8.3.6 I/O AC Characteristics ................................................................................................. 131 8.4 Analog Characteristics .............................................................................................. 132 8.4.1 Reset and Power Control Block Characteristics ...................................................... 132 8.4.2 12-bit SAR ADC ............................................................................................................ 133 8.4.3 Analog Comparator Controller (ACMP)..................................................................... 135 ML51/ML54/ML56 SERIES DATASHEET 8.4.4 Internal Voltage Reference ......................................................................................... 136 8.4.5 Temperature Sensor .................................................................................................... 137 8.4.6 LCD Controller .............................................................................................................. 138 8.5 Flash DC Electrical Characteristics ........................................................................ 142 8.6 Absolute Maximum Ratings ..................................................................................... 143 8.6.1 Voltage Characteristics ................................................................................................ 143 8.6.2 Current Characteristics ................................................................................................ 144 8.6.3 Thermal Characteristics............................................................................................... 145 8.6.4 EMC Characteristics .................................................................................................... 146 8.6.5 Package Moisture Sensitivity(MSL) ........................................................................... 148 8.6.6 Soldering Profile ........................................................................................................... 149 9 PACKAGE DIMENSIONS ............................................................................ 150 9.1 LQFP 64L-pin (7.0 x 7.0 x 1.4 mm) ........................................................................ 150 9.2 LQFP 48-pin (7.0 x 7.0 x 1.4 mm)........................................................................... 151 9.3 LQFP 44-pin (10 x 10 x 1.4mm ............................................................................... 152 9.4 QFN 33-pin (4.0 x 4.0 x 0.8 mm) ............................................................................ 153 9.5 LQFP 32-pin (7.0 x 7.0 x 1.4 mm)........................................................................... 154 9.6 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ....................................................................... 155 Sep. 1, 2020 Page 4 of 164 Rev 2.00 ML51/ML54/ML56 9.7 SOP 28-pin (300mil).................................................................................................. 156 9.8 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ...................................................................... 157 9.9 SOP 20-pin (300 mil) ................................................................................................ 158 10 9.10 QFN 20-pin ( 3.0 x 3.0 x 0.8 mm ) .................................................................... 159 9.11 TSSOP 14-pin (4.4 x 5.0 x 0.9 mm).................................................................. 160 9.12 MSOP 10-pin (3.0 x 3.0 x 0.85 mm) ................................................................. 161 ABBREVIATIONS ........................................................................................ 162 10.1 11 Abbreviations........................................................................................................ 162 REVISION HISTORY ................................................................................... 163 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 5 of 164 Rev 2.00 ML51/ML54/ML56 LIST OF FIGURES Figure 4.1-1 ML51SD1AE Pin Assignment .................................................................................... 23 Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment ............................................................ 24 Figure 4.1-3 ML51LD1AE Pin Assignment .................................................................................... 24 Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment ............................................................. 25 Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment ........................................................... 25 Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment ..................................... 26 Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment ............................................................ 27 Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment ............................................................ 27 Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment ............................................................ 28 Figure 4.1-10 ML51FB9AE Pin Assignment .................................................................................. 28 Figure 4.1-11 ML51OB9AE Pin Assignment.................................................................................. 29 Figure 4.1-12 ML51XB9AE Pin Assignment .................................................................................. 29 Figure 4.1-13 ML51DB9AE Pin Assignment .................................................................................. 30 Figure 4.1-14 ML51BB9AE Pin Assignment .................................................................................. 30 Figure 4.1-15 ML51SD1AE Multi-Function Pin assignment .......................................................... 31 Figure 4.1-16 ML54SD1AE Multi-Function Pin assignment .......................................................... 34 Figure 4.1-17 ML56SD1AE Multi-Function Pin assignment .......................................................... 37 Figure 4.1-18 ML51LD1AE Multi-Function Pin assignment ........................................................... 40 Figure 4.1-19 ML54LD1AE Multi-Function Pin assignment ........................................................... 43 ML51/ML54/ML56 SERIES DATASHEET Figure 4.1-20 ML56LD1AE Multi-Function Pin assignment ........................................................... 46 Figure 4.1-21 ML54MD1AE Multi-Function Pin assignment .......................................................... 49 Figure 4.1-22 ML56MD1AE Multi-Function Pin assignment .......................................................... 52 Figure 4.1-23 ML51TD1AE Multi-Function Pin assignment ........................................................... 55 Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment .................................. 57 Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment .................................. 59 Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment ................................. 61 Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment .................................. 63 Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment ........................................................... 65 Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment .......................................................... 66 Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment .......................................................... 67 Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment .......................................................... 69 Figure 4.1-32 ML51BB9AE Pin Assignment .................................................................................. 70 Figure 5.1-1 Functional Block Diagram .......................................................................................... 78 Figure 6.2-1 Clock System Block Diagram .................................................................................... 80 ® Figure 7.1-1 NuMicro ML51/ML54/ML56 Series Power supply circuit ....................................... 109 ® Figure 7.2-1 NuMicro ML51/ML54/ML56 Series Peripheral interface circuit ............................. 110 Sep. 1, 2020 Page 6 of 164 Rev 2.00 ML51/ML54/ML56 Figure 8.4-1 Typical Connection With Internal Voltage Reference .............................................. 136 Figure 8.6-1 Soldering Profile From J-STD-020C ........................................................................ 149 Figure 9.1-1 LQFP 64L Package Dimension ............................................................................... 150 Figure 9.2-1 LQFP-48 Package Dimension ................................................................................ 151 Figure 9.3-1 LFP44 Package Dimension .................................................................................... 152 Figure 9.4-1 QFN-33 Package Dimension .................................................................................. 153 Figure 9.5-1 LQFP-32 Package Dimension ................................................................................. 154 Figure 9.6-1 TSSOP-28 Package Dimension .............................................................................. 155 Figure 9.7-1 SOP-28 Package Dimension .................................................................................. 156 Figure 9.8-1 TSSOP-20 Package Dimension .............................................................................. 157 Figure 9.9-1 SOP-20 Package Dimension ................................................................................... 158 Figure 9.10-1 QFN-20 Package Dimension ................................................................................. 159 Figure 9.11-1 TSSOP-14 Package Dimension ............................................................................ 160 Figure 9.12-1 MSOP-10 Package Dimension .............................................................................. 161 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 7 of 164 Rev 2.00 ML51/ML54/ML56 List of Tables Table 6.4-1 Configuration for Different I/O Modes ......................................................................... 82 Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars.......................................... 84 Table 6.21-1 Instruction Set And Addressing Modes .................................................................. 103 Table 6.21-2 Instructions Affect Flag Settings ............................................................................ 104 Table 6.21-3 Instruction Set ........................................................................................................ 108 Table 8.1-1 ML51 32KB/16KB Flash Series General Operating Conditions ............................... 111 Table 8.1-2 ML56/ML54/ML51 64KB Flash Series General Operating Conditions ..................... 111 Table 8.2-1 ML51 32KB / 16KB Series Current Consumption In Normal Run Mode .................. 113 Table 8.2-2 ML51 32KB/16KB Flash Series Current Consumption In Low Power Run Mode .... 113 Table 8.2-3 ML51 32KB/16KB Flash Series Current Consumption In Idle Mode ........................ 114 Table 8.2-4 ML51 32KB/16KB Flash Series Current Consumption In Low Power Idle Mode ..... 114 Table 8.2-5 ML51 32KB/16KB Flash Series Chip Current Consumption in Power down mode . 115 Table 8.2-6 ML56/ML54/ML51 64KB Flash Series Current Consumption In Normal Run Mode 117 Table 8.2-7 ML56/ML54/ML51 64KB Flash Series Current Consumption In Low Power Run Mode .............................................................................................................................................. 117 Table 8.2-8 ML56/ML54/ML51 64KB Flash Series Current Consumption In Idle Mode.............. 118 Table 8.2-9 ML56/ML54/ML51 64KB Flash Series Current consumption in Low Power Idle mode .............................................................................................................................................. 118 Table 8.2-10 ML56/ML54/ML51 64KB Flash Series Series Chip Current Consumption In Power Down Mode ........................................................................................................................... 119 ML51/ML54/ML56 SERIES DATASHEET Table 8.2-11 Peripheral Current Consumption ............................................................................ 121 Table 8.2-12 Low-Power Mode Wakeup Timings ........................................................................ 122 Table 8.2-13I/O Input Characteristics .......................................................................................... 123 Table 8.2-14 nRESET Input Characteristics ................................................................................ 124 Table 8.3-1 24 MHz Internal High Speed RC Oscillator(HIRC) Characteristic ............................ 125 Table 8.3-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics .......................... 126 Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator ........................................ 127 Table 8.3-4 Typical Crystal Application ....................................................................................... 128 Table 8.3-5 External 4~24 MHz High Speed Clock Input Signal ................................................. 129 Table 8.3-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Characteristics ............... 130 Table 8.3-7 Typical 32.768 kHz Crystal Application Circuit ......................................................... 130 Table 8.3-8 I/O AC characteristics ............................................................................................... 131 Table 8.4-1 Reset And Power Control Unit .................................................................................. 132 Table 8.4-2 ADC Characteristics.................................................................................................. 133 Table 8.4-3 ACMP Characteristics ............................................................................................... 135 Table 8.4-4 Voltage Reference Character ................................................................................... 136 Table 8.4-5 Temperature Sensor Character ................................................................................ 137 Sep. 1, 2020 Page 8 of 164 Rev 2.00 ML51/ML54/ML56 Table 8.4-6 LCD Digital Characteristics ....................................................................................... 139 Table 8.4-7 Current Consumption In Power Down Mode With LCD Voltage Source From Internal Charge Pump ........................................................................................................................ 140 Table 8.4-8 Current Consumption In Power Down Mode With LCD Voltage Source From AVDD 140 Table 8.4-9 Current Consumption In Power Down Mode With LCD Voltage Source From External VLCD pin ............................................................................................................................... 141 Table 8.5-1 Flash Memory Characteristics .................................................................................. 142 Table 8.6-1 ML51 32KB/16KB Flash Series Voltage Characteristics .......................................... 143 Table 8.6-2 ML51 64KB Flash/ML54/ML56 Series Voltage Characteristics ................................ 143 Table 8.6-3 Current Characteristics ............................................................................................. 144 Table 8.6-4 Thermal Characteristics ............................................................................................ 145 Table 8.6-5 ML51 32KB/16KB Flash Series EMC Characteristics .............................................. 146 Table 8.6-6 ML51 64KB Flash/ML54/ML56 Series EMC Characteristics .................................... 147 Table 8.6-7 Package Moisture Sensitivity(MSL) .......................................................................... 148 Table 8.6-8 Soldering Profile........................................................................................................ 149 Table 10.1-1 List of Abbreviations................................................................................................ 162 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 9 of 164 Rev 2.00 ML51/ML54/ML56 1 GENERAL DESCRIPTION The NuMicro® ML51/ML54/ML56 series is a Flash embedded 1T 8051-based microcontroller. The instruction set of the ML51 series is fully compatible with the standard 80C51 with enhanced performance; This series is a three-to-one single microcontrollers, intergrated with up to 14 channels of capacitive touch and LCD driver. The ML51/ML54/ML56 series is 1T 8051 core based low-power microcontrollers running at less 80µA/MHz in normal run mode, and power down current is below 1uA. It Provides operating frequency up to 24 MHz. 16KB and 32KB Flash of ML51 series voltage range supports 1.8V to 5.5V, and 64KB Flash of ML51 series supports 1.8 to 3.6V voltage range. The ML51/ML54/ML56 series microcontroller provides 3 power modes to reduce power consumption －Low power run mode, Low power Idle mode, and Power-down mode. In Low power run mode, the power consumption can be down to 15 uA at 38.4 kHz LIRC. In Low power idle mode, CPU processing is suspended by holding the Program Counter. No program code is fetched and run in low power idle mode if the power consumption does not exceed 13 uA. Power-down mode stops the whole system clock for minimum power consumption with the leakage current less than 1 uA. The system clock of the ML51 series can also be slowed down by software clock divider, which allows for flexibility between execution performance and power consumption. The ML51/ML54/ML56 series provides rich peripherals including 256 bytes of SRAM, 4 Kbytes of auxiliary RAM (XRAM), up to 56 general purpose I/O, two 16-bit Timers/Counters 0/1, one 16-bit Timer2 with three-channel input capture module, one Watchdog Timer (WDT), one Self Wake-up Timer (WKT), one 16-bit auto-reload Timer3 for general purpose or baud rate generator, two UARTs with frame error detection and automatic address recognition, two ISO7816 Smartcard interface, two SPI, two I2C, 6 enhanced PWM output channels with dead zone control, 6 PWM output channels with 3 individual configurable period, two analog comparators, eight-channel shared pin interrupt for all I/O ports, and one 12-bit ADC at 500 ksps. There are a total of 31 sources with 4-level-priority interrupts capability. ML51/ML54/ML56 SERIES DATASHEET All series contains up to 64 Kbytes Flash, called APROM designed for programming. Flash supports In-Application-Programming (IAP) function, which supports on-chip firmware upgrade. Partial flash can be configured as Data Flash programmed by IAP and read by IAP or MOVC instruction. The ML51/ML54/ML56 series includes an additional configurable up to 4/3/2/1 Kbytes Flash area called LDROM, in which the Boot Code normally resides for carrying out the In-System-Programming (ISP). To facilitate mass production programming and verification, the Flash is allowed to be programmed and read electronically by parallel Writer/Programmer or In-Circuit-Programming (ICP) with Nu-Link. Once programmed and verified, the programmed code can be protected by the Flash lock mechanism from being read out by external programming tool. Through the high performance and low power features of ML51/ML54/ML56 series, this series benefits for low-power, battery powered devices, general purpose, home appliances, and motor control system. Series VDD Voltage LCD Driver Touch Key ML51 32/16KB Flash Series 1.8 ~ 5.5 V - - ML51 64KB Flash Series 1.8 ~3.6 V - - ML54 Series 1.8 ~3.6 V  - ML56 Series 1.8 ~3.6 V   Sep. 1, 2020 Page 10 of 164 Rev 2.00 ML51/ML54/ML56 2 FEATURES Core and System  Fully static design 8-bit high performance 1T 8051-based CMOS microcontroller.  Instruction set fully compatible with MCS-51.  4-priority-level interrupts capability.  Dual Data Pointers (DPTRs). Power on Reset (POR)  POR with 1.55V threshold voltage level Brown-out Detector (BOD)  7-level selection, with brown-out interrupt and reset option. (4.4V / 3.7V / 3.0V / 2.7V / 2.4V / 2.0V / 1.8V) Low Voltage Reset (LVR)  LVR with 1.63V threshold voltage level  96-bit Unique ID (UID)  128-bit Unique Customer ID (UCID)  128-bytes security protection memory SPROM  Up to 64 KBytes of APROM for User Code.  4/3/2/1 Kbytes of Flash for loader (LDROM) configure from APROM for In-System-Programmable (ISP)  Flash Memory accumulated with pages of 128 Bytes from APROM by In-Application-Programmable (IAP) means whole APROM can be use as Data Flash  An additional 128 bytes security protection memory SPROM  Code lock for security by CONFIG  256 Bytes on-chip RAM.  Additional 4 KBytes on-chip auxiliary RAM (XRAM) accessed by MOVX instruction.  Three modes: peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer.  Source address and destination address must be word alignment in all modes.  Memory-to-memory mode: transfer length must be word alignment.  4~24 MHz High-speed external crystal oscillator (HXT) for precise timing operation 8051 Security Memories SRAM PDMA: Clocks External Clock Source Sep. 1, 2020 Page 11 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET Flash ML51/ML54/ML56  32.768 kHz High-speed external crystal oscillator (LXT) for RTC operation  Default 24 MHz high-speed internal oscillator (HIRC) trimmed to ±1% (accuracy at 25 °C, 3.3 V), ±2% in 20~105°C.  38.4 kHz low-speed internal oscillator (LIRC) calibrating to ±2% by software from high-speed internal oscillator  Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051.  One 16-bit Timer 2 with three-channel input capture module and 9 input pin can be selected.  One 16-bit auto-reload Timer 3, which can be the baud rate clock source of UARTs.  6-bit free running up counter for WDT time-out interval.  Selectable time-out interval is 1.66 ms ~ 3413.12 ms since WDT_CLK = 38.4 kHz (LIRC).  Able to wake up from Power-down or Idle mode  Interrupt or reset selectable on watchdog time-out  16-bit free running up counter for time-out interval.  Clock sources from LIRC  Able self Wake-up wake up from Power-down or Idle mode, and auto reload count value.  Supports Interrupt  Up To 12 output pins can be selected  Supports maximum clock source frequency up to 24 MHz  Supports up to Three PWM modules, each module provides 6 output channels.  Supports independent mode for PWM output  Supports complementary mode for 3 complementary paired PWM output channels  Dead-time insertion with 8-bit resolution  Supports 16-bit resolution PWM counter  Supports mask function and tri-state enable for each PWM pin  Supports brake function  Supports trigger ADC on the following events  Supports real time counter and calendar counter for RTC time and calendar check.  Supports alarm time and calendar settings Internal Clock Source Timers 16-bit Timer Watchdog ML51/ML54/ML56 SERIES DATASHEET Wake-up Timer PWM RTC Sep. 1, 2020 Page 12 of 164 Rev 2.00 ML51/ML54/ML56  Supports alarm time and calendar mask enable settings.  Selectable 12-hour or 24-hour time scale setting.  Supports Leap Year indication setting.  Supports Day of the Week counter setting.  Frequency of RTC clock source compensate by RTC_FREQADJ register.  All time and calendar message expressed in BCD format.  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.  Supports RTC Time Tick and Alarm Match interrupt.  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated.  Support clock source selectable from LXT or LIRC.  Analog input voltage range: 0 ~ AVDD.  External or internal Voltage reference input selectable.  12-bit resolution and 10-bit accuracy is guaranteed.  Up to 16 single-end analog input channels  1 internal channels, they are band-gap voltage (VBG).  Maximum ADC peripheral clock frequency is 1 MHz.  Up to 500 KSPS sampling rate.  Software Write 1 to ADCS bit to trig ADC start.  External pin (STADC) trigger  PWM trigger.  Supports up to 2 UARTs: UART0, UART1  Supports 2 Smart Card configuration as UART function as UART2 and UART3.  UART baud rate clock from HIRC or HXT.  Full-duplex asynchronous communications  Programmable 9 bit.  TXD and RXD pins of UART0 exchangeable via software.  2 sets of I C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  7-bit addressing mode Analog Interfaces Analog-to-Digital Converter (ADC) UART 2 IC Sep. 1, 2020 th 2 Page 13 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET Communication Interfaces ML51/ML54/ML56 SPI ISO 7816-3 ML51/ML54/ML56 SERIES DATASHEET GPIO LCD Driver Touch Key Sep. 1, 2020  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I C interrupt if 2 the I C bus hangs up and timer-out counter overflows  Multiple address recognition (four slave addresses with mask option)  Supports hold time programmable  2 sets of SPI devices  Supports Master or Slave mode operation  Supports MSB first or LSB first transfer sequence  Slave mode up to 12 Mhz  Two sets ISO 7816-3 device  Supports ISO 7816-3 compliant T=0, T=1  Supports full-duplex UART mode.  Four I/O modes:  Quasi-bidirectional mode  Push-Pull Output mode  Open-Drain Output mode  Input only with high impendence mode  Schmitt trigger input / TTL mode selectable.   Each I/O pin configured as interrupt source with edge/level trigger setting Standard interrupt pins ̅̅̅̅̅̅̅ INT0 and ̅̅̅̅̅̅̅ INT1.  Supports high drive and high sink current I/O  I/O pin internal pull-up or pull-down resistor enabled in input mode.  Maximum I/O Speed is 24 MHz  Enabling the pin interrupt function will also enable the wakeup function  Supports 5V-tolerance function for  ML51 Series: ML51TD1AE/ML51LD1AE/ML51SD1AD  ML54 Series: ML54MD1AE/ML54LD1AE/ML54SD1AE  ML56 Series: ML56MD1AE/ML56LD1AEML56SD1AE  Support Internal resistor bias, capacitor bias  Support programmable internal VLCD charge pump mode  1/2, 1/3, 1/4 bias selectable  4 COM x 32 SEG, 6 COM x 30 SEG, 8 COM x 28 SEG  Support 2.8V to 5.5V LCD operating voltage  Supports up to 14 touch key + 1 reference pin. 2 Page 14 of 164 Rev 2.00 ML51/ML54/ML56  Programmable sensitivity levels for each channel.  Programmable scanning speed for different applications.  Supports effect when in power down mode.  Supports single key-scan and programmable periodic keyscan.  Programmable interrupt options for key-scan complete with/without threshold control.  HBM 8 kV for ML51 32KB/16KB Flash Series pass  HBM 7 kV for ML51 64KB Flash/ML54/ML56 Series pass  > ± 4.4 kV  150 mA for ML51 32KB/16KB Flash Series pass  200 mA for ML51 64KB Flash/ML54/ML56 Series pass ESD & EFT ESD EFT Latch-up ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 15 of 164 Rev 2.00 ML51/ML54/ML56 3 PART INFORMATION 3.1 ML51/ML54/ML56 Series Package Type Package ML51 ML51xB ML51xC ML51/ML54/ML56 SERIES DATASHEET MSOP10 ML51BB9AE TSSOP14 ML51DB9AE TSSOP20 ML51FB9AE SOP20 ML51OB9AE QFN20(3x3) ML51XB9AE TSSOP28 ML51EB9AE ML51EC0AE SOP28 ML51UB9AE ML51UC0AE LQFP32 ML51PB9AE ML51PC0AE QFN33(4x4) ML51TB9AE ML51TC0AE ML51xD ML54 ML56 ML54xD ML56xD ML54MD1AE ML56MD1AE ML51TD1AE LQFP44 LQFP48 ML51LD1AE ML54LD1AE ML56LD1AE LQFP64 ML51SD1AE ML54SD1AE ML56SD1AE Sep. 1, 2020 Page 16 of 164 Rev 2.00 ML51/ML54/ML56 3.2 ML51/ML54/ML56 Series Selection Guide 3.2.1 ML51 Series ML51 16KB Flash Series ML51 Part Number FB9AE OB9AE XB9AE EB9AE UB9AE PB9AE Flash (KB) 16 16 16 16 16 16 16 16 SRAM (KB) 1 1 1 1 1 1 2 2 ISP ROM (KB) 4 4 4 4 4 4 4 4 SPROM (bytes) 128 128 128 128 128 128 128 128 System Frequency ( MHz) 24 24 24 24 24 24 24 24 GPIO 7 11 16 16 17 24 24 28 16-bit Timer 4 4 4 4 4 4 4 4 PWM 5 6 6 6 6 6 6 6 Analog Comparator - - - - - - 2 2 Internal Voltage Reference - - - - - - Y Y PDMA 2 2 2 2 2 2 2 2 RTC - - - - - - - - LCD - - - - - - - - ISO 7816-3 - 1 1 1 1 1 1 1 UART 2 2 2 2 2 2 2 2 SPI - 1 1 1 1 1 1 1 2 IC 1 2 2 2 2 2 2 2 12-bit SAR ADC 2 3 6 6 6 8 8 8 SOP20 QFN20 TSSOP28 SOP28 LQFP32 Connectivity DB9AE Package MSOP10 TSSOP14 TSSOP20 Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as standard UART function. Sep. 1, 2020 Page 17 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET BB9AE ML51/ML54/ML56 ML51 32KB Flash Series ML51 Part Number UC0AE PC0AE TC0AE TC1AE LC1AE Flash (KB) 32 32 32 32 32 32 SRAM (KB) 2 2 2 2 2 2 ISP ROM (KB) 4 4 4 4 4 4 SPROM (bytes) 128 128 128 128 128 128 System Frequency ( MHz) 24 24 24 24 24 24 GPIO 24 24 28 28 28 43 16-bit Timer 4 4 4 4 4 4 PWM 6 6 6 6 6 6 Analog Comparator 2 2 2 2 2 2 Internal Voltage Reference Y Y Y Y Y Y PDMA 2 2 2 2 2 2 RTC - - - - - - LCD - - - - - - ISO 7816-3 1 1 1 1 2 2 UART 2 2 2 2 2 2 SPI 2[3] 2[3] 2 2 2 2 2 IC 2 2 2 2 2 2 12-bit SAR ADC 8 8 8 8 9 10 TSSOP28 SOP28 LQFP32 QFN33 QFN33 LQFP48 Connectivity EC0AE ML51/ML54/ML56 SERIES DATASHEET Package Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as standard UART function. 3. SPI0 and SPI1 share with same SS pin in 28pin package. Sep. 1, 2020 Page 18 of 164 Rev 2.00 ML51/ML54/ML56 ML51 64KB Flash Series ML51 Part Number TD1AE LD1AE SD1AE 64 64 64 SRAM (KB) 4 4 4 ISP ROM (KB) 4 4 4 SPROM (bytes) 128 128 128 System Frequency ( MHz) 24 24 24 GPIO 28 43 56 16-bit Timer 4 4 4 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y LCD - - - ISO 7816-3 2 2 2 UART 2 2 2 SPI 2 2 2 2 IC 2 2 2 12-bit SAR ADC 9 10 14 QFN33 LQFP48 LQFP64 Connectivity PWM Package ML51/ML54/ML56 SERIES DATASHEET Flash (KB) Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as standard UART function. Sep. 1, 2020 Page 19 of 164 Rev 2.00 ML51/ML54/ML56 3.2.2 ML54 Series ML54 Part Number MD1AE LD1AE SD1AE Flash (KB) 64 64 64 SRAM (KB) 4 4 4 ISP ROM (KB) 4 4 4 SPROM (bytes) 128 128 128 System Frequency ( MHz) 24 24 24 GPIO 38 42 55 16-bit Timer 4 4 4 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y 8x17 8x18 8x28 6x19 6x20 6x30 4x21 4x22 4x32 ISO 7816-3 2 2 2 UART 2 2 2 SPI 2 2 2 2 IC 2 2 2 12-bit SAR ADC 10 10 14 LQFP44 LQFP48 LQFP64 PWM ML51/ML54/ML56 SERIES DATASHEET Connectivity LCD Package Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as standard UART function. Sep. 1, 2020 Page 20 of 164 Rev 2.00 ML51/ML54/ML56 3.2.3 ML56 Series ML56 Part Number LD1AE SD1AE Flash (KB) 64 64 64 SRAM (KB) 4 4 4 ISP ROM (KB) 4 4 4 SPROM (bytes) 128 128 128 System Frequency ( MHz) 24 24 24 GPIO 38 42 55 16-bit Timer 4 4 4 6+2+2+2 6+2+2+2 6+2+2+2 Analog Comparator 2 2 2 Internal Voltage Reference Y Y Y PDMA 4 4 4 RTC Y Y Y 8x17 8x18 8x28 6x19 6x20 6x30 4x21 4x22 4x32 Touch Key 6+1 9+1 14+1 ISO 7816-3 2 2 2 UART 2 2 2 SPI 2 2 2 2 IC 2 2 2 12-bit SAR ADC 10 10 14 LQFP44 LQFP48 LQFP64 PWM Connectivity LCD Package ML51/ML54/ML56 SERIES DATASHEET MD1AE Note: 1. ISP ROM programmable 1K/2K/3K/4KB Flash for user program loader (LDROM) share from ARPOM. 2. ISO 7816-3 configurable as standard UART function. 3.Touch key should define 1 key as reference pin. Sep. 1, 2020 Page 21 of 164 Rev 2.00 ML51/ML54/ML56 3.3 ML51/ML54/ML56 Series Selection Code ML 51 F B 9 A E Core Line Package Flash SRAM Reserve Temperature 1T 8051 51: Base B: MSOP10 (3x3 mm) A: 8 KB 0: 2 KB Low power 54: LCD D: TSSOP14 (4.4x5.0 mm) B: 16 KB 1: 4 KB 56: Touch E: TSSOP28 (4.4x9.7 mm) C: 32 KB 2: 8/12 KB F: TSSOP20 (4.4x6.5 mm) D: 64 KB 3: 16 KB L: LQFP48 (7x7 mm) 6: 32 KB M: LQFP44(10x10 mm) 8: 64 KB O: SOP20 (300 mil) 9: 1 KB P: LQFP32 (7x7 mm) A: 96 KB E:-40 ~ 105°C S: LQFP64 (7x7 mm) T: QFN33 (4x4 mm) U: SOP28 (300 mil) X: QFN20 (3x3mm) ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 22 of 164 Rev 2.00 ML51/ML54/ML56 4 PIN CONFIGURATION 4.1 Pin Configuration Users can find pin configuaration informations in chapter 4 or by using NuTool - PinConfigure. The ® NuTool - PinConfigure contains all Nuvoton NuMicro Family chip series with all part number, and helps users configure GPIO multi-function correctly and handily. 4.1.1 4.1.1.1 ML51/ML54/ML56 Series Pin Diagram LQFP64 Package Corresponding Part Number: ML51SD1AE/ ML54SD1AE / ML56SD1AE P1.7 P1.6 P1.5 P1.4 P6.0 P6.1 P6.2 P6.3 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.1 P5.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ML51SD1AE 49 32 nRESET 50 31 P5.6 VDD 51 30 P0.0 P4.7 52 29 P0.1 P3.3 53 28 P0.2 P3.2 54 27 P0.3 P3.1 55 26 P0.4 P3.0 56 25 P0.5 AVDD 57 24 P3.6 VREF 58 23 VDD AVSS 59 22 VSS P6.7 60 21 P0.6 P6.6 61 20 P0.7 P6.5 62 19 P3.4 P6.4 63 18 P3.5 P2.7 64 17 P5.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 P3.7 P5.7 P5.5 P5.4 P5.3 LQFP64 ML51/ML54/ML56 SERIES DATASHEET VSS P4.6 Figure 4.1-1 ML51SD1AE Pin Assignment Sep. 1, 2020 Page 23 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 P1.6 P1.5 P1.4 P6.0 P6.1 P6.2 P6.3 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.1 P5.0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ML54SD1AE / ML56SD1AE VSS 49 32 nRESET P4.6 50 31 P5.6 VDD 51 30 P0.0 P4.7 52 29 P0.1 P3.3 53 28 P0.2 P3.2 54 27 P0.3 P3.1 55 26 P0.4 P3.0 56 25 P0.5 AVDD 57 24 P3.6 VREF 58 23 VDD AVSS 59 22 VSS P6.7 60 21 P0.6 P6.6 61 20 P0.7 P6.5 62 19 P3.4 P6.4 63 18 P3.5 P2.7 64 17 P5.2 16 P5.3 15 P5.4 14 9 P1.2 P5.5 8 P1.3 13 7 P2.0 P5.7 6 P2.1 12 5 P2.2 VLCD 4 P2.3 11 3 P2.4 P1.0 2 P2.5 P1.1 1 P2.6 10 LQFP64 Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment 4.1.1.2 LQFP48 Package Corresponding Part Number: ML51LD1AE/ ML54LD1AE / ML56LD1AE P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.1 P5.0 35 34 33 32 31 30 29 28 27 26 25 VSS 37 24 nRESET P4.6 38 23 P5.6 VDD 39 22 P0.0 P4.7 40 21 P0.1 P3.3 41 20 P0.2 P3.2 42 19 P0.3 P3.1 43 18 P0.4 P3.0 44 17 P0.5 VREF 45 16 P0.6 AVSS 46 15 P0.7 P2.7 47 14 P5.2 P2.6 48 13 P5.3 3 4 5 6 7 8 9 10 11 12 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 P1.0 P5.5 P5.4 2 P2.4 P2.3 1 LQFP48 P2.5 ML51/ML54/ML56 SERIES DATASHEET 36 ML51LD1AE Figure 4.1-3 ML51LD1AE Pin Assignment Sep. 1, 2020 Page 24 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.1 P5.0 36 35 34 33 32 31 30 29 28 27 26 25 ML54LD1AE / ML56LD1AE VSS 37 24 nRESET P4.6 38 23 P5.6 VDD 39 22 P0.0 P4.7 40 21 P0.1 P3.3 41 20 P0.2 P3.2 42 19 P0.3 P3.1 43 18 P0.4 P3.0 44 17 P0.5 VREF 45 16 P0.6 AVSS 46 15 P0.7 P2.7 47 14 P5.2 P2.6 48 13 P5.3 7 8 9 10 11 P1.3 P1.2 P1.1 VLCD P5.5 12 6 P2.0 P5.4 5 P2.1 4 P2.2 3 P2.3 2 P2.4 P2.5 1 LQFP48 Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment 4.1.1.3 LQFP44 Package Corresponding Part Number: ML54MD1AE / ML56MD1AE P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P5.1 33 32 31 30 29 28 27 26 25 24 23 ML54MD1AE / ML56MD1AE 34 22 P5.0 35 21 nRESET VDD 36 20 P0.0 P3.3 37 19 P0.1 P3.2 38 18 P0.2 P3.1 39 17 P0.3 P3.0 40 16 P0.6 VREF 41 15 P0.7 AVSS 42 14 P5.2 P2.7 43 13 P5.3 P2.6 44 12 P5.4 1 2 3 4 5 6 7 8 9 10 11 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 P1.3 P1.2 P1.1 VLCD P5.5 LQFP44 ML51/ML54/ML56 SERIES DATASHEET VSS P4.6 Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment Sep. 1, 2020 Page 25 of 164 Rev 2.00 ML51/ML54/ML56 4.1.1.4 QFN33 Package Corresponding Part Number: ML51TD1AE / ML51TC0AE / ML51TB9AE P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P5.1 P5.0 24 23 22 21 20 19 18 17 ML51TD1AE / ML51TC0AE / ML51TB9AE VSS 25 16 nRESET P4.6 26 15 P5.6 VDD 27 14 P0.0 P3.3 28 13 P0.1 P3.2 29 12 P0.2 P3.1 30 11 P0.3 P3.0 31 10 P5.2 VREF 32 9 P5.3 Top transparent view QFN33 2 3 4 5 6 7 8 P2.3 P2.2 P2.1 P2.0 P5.5 P5.4 1 P2.5 P2.4 33 VSS Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 26 of 164 Rev 2.00 ML51/ML54/ML56 4.1.1.5 LQFP32 Package Corresponding Part Number: ML51PC0AE / ML51PB9AE P1.7 P1.6 P1.5 P1.4 P4.0 P4.1 P5.1 P5.0 24 23 22 21 20 19 18 17 ML51PC0AE / ML51PB9AE VSS 25 16 nRESET P4.6 26 15 P5.6 VDD 27 14 P0.0 P3.3 28 13 P0.1 P3.2 29 12 P0.2 P3.1 30 11 P0.3 P3.0 31 10 P5.2 VREF 32 9 P5.3 3 4 5 6 7 P2.3 P2.2 P2.1 P2.0 P5.5 8 2 P2.4 P5.4 1 P2.5 LQFP32 Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment 4.1.1.6 TSSOP28 Package Corresponding Part Number: ML51EC0AE / ML51EB9AE ML51/ML54/ML56 SERIES DATASHEET ML51EC0AE / ML51EB9AE 1 28 P4.0 P1.5 2 27 P4.1 P1.6 3 26 P5.1 P1.7 4 25 P5.0 VSS 5 24 nRESET P4.6 6 23 P0.0 VDD 7 22 P0.1 P3.2 8 21 P0.2 P3.1 9 20 P0.3 TSSOP28 P1.4 P3.0 10 19 P5.2 VREF 11 18 P5.3 P2.5 12 17 P2.0 P2.4 13 16 P2.1 P2.3 14 15 P2.2 Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment Sep. 1, 2020 Page 27 of 164 Rev 2.00 ML51/ML54/ML56 4.1.1.7 SOP28 Package Corresponding Part Number: ML51UC0AE / ML51UB9AE ML51UC0AE / ML51UB9AE P1.4 1 28 P4.0 P1.5 2 27 P4.1 P1.6 3 26 P5.1 P1.7 4 25 P5.0 5 24 nRESET 6 23 P0.0 VDD 7 22 P0.1 P3.2 8 21 P0.2 P3.1 9 20 P0.3 P3.0 10 19 P5.2 VREF 11 18 P5.3 P2.5 12 17 P2.0 P2.4 13 16 P2.1 P2.3 14 15 P2.2 SOP28 VSS P4.6 Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment 4.1.1.8 TSSOP20 Package Corresponding Part Number: ML51FB9AE VSS 1 20 P5.1 P4.6 2 19 P5.0 VDD 3 18 nRESET P3.2 4 17 P0.0 P3.1 5 16 P0.1 15 P0.2 14 P0.3 TSSOP20 ML51/ML54/ML56 SERIES DATASHEET ML51FB9AE P3.0 6 VREF 7 P2.5 8 13 P5.2 P2.4 9 12 P5.3 P2.3 10 11 P2.2 Figure 4.1-10 ML51FB9AE Pin Assignment Sep. 1, 2020 Page 28 of 164 Rev 2.00 ML51/ML54/ML56 4.1.1.9 SOP20 Package Corresponding Part Number: ML51OB9AE ML51OB9AE 1 20 P5.1 P4.6 2 19 P5.0 VDD 3 18 nRESET P3.2 4 17 P0.0 P3.1 5 16 P0.1 P3.0 6 15 P0.2 VREF 7 14 P0.3 P2.5 8 13 P5.2 P2.4 9 12 P5.3 P2.3 10 11 P2.2 SOP20 VSS Figure 4.1-11 ML51OB9AE Pin Assignment 4.1.1.10 QFN20 Package Corresponding Part Number: ML51XB9AE P5.0 P5.1 P4.1 P4.0 P1.7 ML51XB9AE 15 14 13 12 11 16 10 nRESET 17 9 P0.0 VDD 18 8 P0.1 P3.1 19 7 P0.2 P3.0 20 6 P0.3 QFN20 1 2 3 4 5 P2.5 P2.4 P2.3 P2.2 P2.1 NC ML51/ML54/ML56 SERIES DATASHEET VSS P4.6 Figure 4.1-12 ML51XB9AE Pin Assignment Sep. 1, 2020 Page 29 of 164 Rev 2.00 ML51/ML54/ML56 4.1.1.11 TSSOP14 Package Corresponding Part Number: ML51DB9AE ML51DB9AE VSS 1 14 P5.1 P4.6 2 13 P5.0 VDD 3 12 nRESET P3.1 4 11 P0.2 P3.0 5 10 P0.3 P2.5 6 9 P5.2 P2.4 7 8 P5.3 TSSOP14 Figure 4.1-13 ML51DB9AE Pin Assignment 4.1.1.12 MSOP10 Package Corresponding Part Number: ML51BB9AE ML51BB9AE P5.0 ML51/ML54/ML56 SERIES DATASHEET P5.1 1 10 VSS 2 9 nRESET P4.6 3 8 P0.0 VDD 4 7 P0.1 P2.3 5 6 P2.0 MSOP10 Figure 4.1-14 ML51BB9AE Pin Assignment Sep. 1, 2020 Page 30 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2 ML51/ML54/ML56 Series Multi Function Pin Diagram 4.1.2.1 LQFP64 Package Corresponding Part Number: ML51SD1AE / ML54SD1AE / ML56SD1AE P1.7 / UART0_RXD P1.6 / UART0_TXD P1.5 / I2C1_SDA P1.4 / I2C1_SCL P6.0 / SPI0_MOSI P6.1 / UART3_RXD / SPI0_MISO P6.2 / UART3_TXD / SPI0_CLK / UART0_RXD P6.3 / SPI0_SS / UART0_TXD P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / PWM2_CH1 P4.3 / PWM2_CH0 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ML51SD1AE Pin Function VSS 49 32 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 50 31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 51 30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / P4.7 52 29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3 53 28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 54 27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 55 26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0 56 25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 P3.6 / PWM0_CH5 / INT1 VREF 58 23 VDD AVSS 59 22 VSS I2C1_SCL / ADC_CH11 / P6.7 60 21 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 I2C1_SDA / ADC_CH12 / P6.6 61 20 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 UART0_TXD / ADC_CH13 / P6.5 62 19 P3.4 / PWM2_CH1 / T1 UART0_RXD / ADC_CH14 / P6.4 63 18 P3.5 / PWM2_CH0 / T0 ACMP0_O / PWM3_CH0 / UART1_TXD / ADC_CH15 / P2.7 64 17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 15 16 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 XT1_IN / I2C0_SCL / UART0_TXD / P5.3 9 IC1 / UART3_TXD / P1.2 13 8 IC0 / P1.3 CLKO / PWM0_CH4 / PWM0_BRAKE / P5.7 7 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0 12 6 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 SPI1_MOSI / P3.7 5 PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 11 4 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 IC0 / UART1_RXD / P1.0 3 10 2 IC2 / UART1_TXD / UART3_RXD / P1.1 1 ACMP1_O / PWM3_CH1 / UART1_RXD / P2.6 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 ML51/ML54/ML56 SERIES DATASHEET INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 LQFP64 Figure 4.1-15 ML51SD1AE Multi-Function Pin assignment Pin ML51SD1AE Pin Function 1 P2.6 / UART1_RXD / PWM3_CH1 / ACMP1_O 2 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 3 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 4 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE Sep. 1, 2020 Page 31 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51SD1AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 5 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 6 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE 7 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE 8 P1.3 / IC0 9 P1.2 / UART3_TXD / IC1 10 P1.1 / UART3_RXD / UART1_TXD / IC2 11 P1.0 / UART1_RXD / IC0 12 P3.7 / SPI1_MOSI 13 P5.7 / PWM0_BRAKE / PWM0_CH4 / CLKO 14 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 15 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 16 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 18 P3.5 / PWM2_CH0 / T0 19 P3.4 / PWM2_CH1 / T1 20 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 21 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 22 VSS 23 VDD 24 P3.6 / PWM0_CH5 / INT1 25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 32 nRESET 33 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 36 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 Sep. 1, 2020 Page 32 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51SD1AE Pin Function P4.3 / PWM2_CH0 38 P4.2 / PWM2_CH1 39 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O 40 P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 41 P6.3 / SPI0_SS / UART0_TXD 42 P6.2 / UART3_TXD / SPI0_CLK / UART0_RXD 43 P6.1 / UART3_RXD / SPI0_MISO 44 P6.0 / SPI0_MOSI 45 P1.4 / I2C1_SCL 46 P1.5 / I2C1_SDA 47 P1.6 / UART0_TXD 48 P1.7 / UART0_RXD 49 VSS 50 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 51 VDD 52 P4.7 / T1 53 P3.3 / SPI1_SS / PWM1_CH0 / IC0 / PWM0_BRAKE 54 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO 55 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 56 P3.0 / ADC_CH10 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 57 AVDD 58 VREF 59 AVSS 60 P6.7 / ADC_CH11 / I2C1_SCL 61 P6.6 / ADC_CH12 / I2C1_SDA 62 P6.5 / ADC_CH13 / UART0_TXD 63 P6.4 / ADC_CH14 / UART0_RXD 64 P2.7 / ADC_CH15 / UART1_TXD / PWM3_CH0 / ACMP0_O Sep. 1, 2020 Page 33 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 37 ML51/ML54/ML56 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P6.0 / LCD_SEG22 / SPI0_MOSI P6.1 / LCD_SEG23 / UART3_RXD / SPI0_MISO P6.2 / LCD_SEG24 / UART3_TXD / SPI0_CLK / UART0_RXD P6.3 / LCD_SEG25 / SPI0_SS / UART0_TXD P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ML54SD1AE Pin Function VSS 49 32 nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 50 31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 51 30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 52 29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 53 28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 54 27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 55 26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 56 25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 AVDD 57 24 P3.6 / PWM0_CH5 / INT1 VREF 58 23 VDD AVSS 59 22 VSS I2C1_SCL / LCD_SEG11 / ADC_CH11 / P6.7 60 21 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 I2C1_SDA / LCD_V1 / LCD_SEG10 / ADC_CH12 / P6.6 61 20 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 UART0_TXD / LCD_V2 / LCD_SEG9 / ADC_CH13 / P6.5 62 19 P3.4 / LCD_SEG2 / PWM2_CH1 / T1 UART0_RXD / LCD_V3 / LCD_SEG8 / ADC_CH14 / P6.4 63 18 P3.5 / LCD_SEG3 / PWM2_CH0 / T0 ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 64 17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 15 16 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 XT1_IN / I2C0_SCL / UART0_TXD / P5.3 9 IC1 / UART3_TXD / LCD_DH2 / P1.2 13 8 IC0 / P1.3 CLKO / PWM0_CH4 / PWM0_BRAKE / P5.7 7 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 12 6 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 VLCD 5 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 11 4 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 IC0 / UART1_RXD / P1.0 3 10 2 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 1 ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 ML51/ML54/ML56 SERIES DATASHEET INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 LQFP64 Figure 4.1-16 ML54SD1AE Multi-Function Pin assignment Pin ML54SD1AE Pin Function 1 P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O 2 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 3 P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 4 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 / PWM0_BRAKE Sep. 1, 2020 Page 34 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML54SD1AE Pin Function P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 6 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE 7 P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE 8 P1.3 / IC0 9 P1.2 / LCD_DH2 / UART3_TXD / IC1 10 P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2 11 P1.0 / UART1_RXD / IC0 12 VLCD 13 P5.7 / PWM0_BRAKE / PWM0_CH4 / CLKO 14 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 15 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 16 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 17 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 18 P3.5 / LCD_SEG3 / PWM2_CH0 / T0 19 P3.4 / LCD_SEG2 / PWM2_CH1 / T1 20 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 21 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 22 VSS 23 VDD 24 P3.6 / PWM0_CH5 / INT1 25 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 26 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 31 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 32 nRESET 33 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 34 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 35 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 Sep. 1, 2020 Page 35 of 164 ML51/ML54/ML56 SERIES DATASHEET 5 Rev 2.00 ML51/ML54/ML56 Pin ML54SD1AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 36 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 37 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 38 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 39 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O 40 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 41 P6.3 / LCD_SEG25 / SPI0_SS / UART0_TXD 42 P6.2 / LCD_SEG24 / UART3_TXD / SPI0_CLK / UART0_RXD 43 P6.1 / LCD_SEG23 / UART3_RXD / SPI0_MISO 44 P6.0 / LCD_SEG22 / SPI0_MOSI 45 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 46 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 47 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 48 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 49 VSS 50 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0 51 VDD 52 P4.7 / LCD_SEG16 / LCD_COM0 / T1 53 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE 54 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO 55 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 56 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 57 AVDD 58 VREF 59 AVSS 60 P6.7 / ADC_CH11 / LCD_SEG11 / I2C1_SCL 61 P6.6 / ADC_CH12 / LCD_SEG10 / LCD_V1 / I2C1_SDA 62 P6.5 / ADC_CH13 / LCD_SEG9 / LCD_V2 / UART0_TXD 63 P6.4 / ADC_CH14 / LCD_SEG8 / LCD_V3 / UART0_RXD 64 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O Sep. 1, 2020 Page 36 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P6.0 / LCD_SEG22 / SPI0_MOSI / TK11 P6.1 / LCD_SEG23 / UART3_RXD / SPI0_MISO / TK10 P6.2 / LCD_SEG24 / UART3_TXD / SPI0_CLK / UART0_RXD / TK9 P6.3 / LCD_SEG25 / SPI0_SS / UART0_TXD / TK8 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / TK14 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / TK13 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / TK12 / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ML56SD1AE Pin Function VSS 49 32 nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 50 31 P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 51 30 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 52 29 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 53 28 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 54 27 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 55 26 P0.4 / UART0_RXD / I2C0_SDA / TK5 / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 56 25 P0.5 / UART0_TXD / I2C0_SCL / TK6 / PWM0_CH0 AVDD 57 24 P3.6 / TK7 / PWM0_CH5 / INT1 VREF 58 23 VDD AVSS 59 22 VSS LQFP64 11 12 13 14 15 16 IC0 / UART1_RXD / P1.0 VLCD CLKO / PWM0_CH4 / PWM0_BRAKE / P5.7 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 XT1_IN / I2C0_SCL / UART0_TXD / P5.3 IC1 / UART3_TXD / LCD_DH2 / P1.2 10 9 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 8 ML51/ML54/ML56 SERIES DATASHEET IC0 / P1.3 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 7 17 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 64 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 P3.5 / LCD_SEG3 / PWM2_CH0 / T0 ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 6 18 5 63 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 P3.4 / LCD_SEG2 / PWM2_CH1 / T1 UART0_RXD / LCD_V3 / LCD_SEG8 / ADC_CH14 / P6.4 4 19 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 62 3 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 UART0_TXD / LCD_V2 / LCD_SEG9 / ADC_CH13 / P6.5 2 20 1 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 61 ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 21 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 60 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 I2C1_SCL / LCD_SEG11 / ADC_CH11 / P6.7 I2C1_SDA / LCD_V1 / LCD_SEG10 / ADC_CH12 / P6.6 Figure 4.1-17 ML56SD1AE Multi-Function Pin assignment Pin ML56SD1AE Pin Function 1 P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O 2 P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0 3 P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1 4 P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE 5 P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3 6 P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK Sep. 1, 2020 Page 37 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML56SD1AE Pin Function E ML51/ML54/ML56 SERIES DATASHEET 7 P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE 8 P1.3/IC0 9 P1.2/LCD_DH2/UART3_TXD/IC1 10 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 11 P1.0/UART1_RXD/IC0 12 VLCD 13 P5.7/PWM0_BRAKE/PWM0_CH4/CLKO 14 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC 15 P5.4/UART2_TXD/PWM0_CH1/X32_OUT 16 P5.3/UART0_TXD/I2C0_SCL/XT1_IN 17 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT 18 P3.5/LCD_SEG3/PWM2_CH0/T0 19 P3.4/LCD_SEG2/PWM2_CH1/T1 20 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 21 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 22 VSS 23 VDD 24 P3.6/TK7/PWM0_CH5/INT1 25 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0 26 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1 27 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO 28 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 29 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 30 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 31 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO 32 nRESET 33 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT 34 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK 35 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 36 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 37 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 38 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 39 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O 40 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 Sep. 1, 2020 Page 38 of 164 Rev 2.00 ML51/ML54/ML56 ML56SD1AE Pin Function 41 P6.3/LCD_SEG25/SPI0_SS/UART0_TXD/TK8 42 P6.2/LCD_SEG24/UART3_TXD/SPI0_CLK/UART0_RXD/TK9 43 P6.1/LCD_SEG23/UART3_RXD/SPI0_MISO/TK10 44 P6.0/LCD_SEG22/SPI0_MOSI/TK11 45 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 46 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 47 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 48 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 49 VSS 50 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 51 VDD 52 P4.7/LCD_SEG16/LCD_COM0/T1 53 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE 54 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO 55 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 56 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 57 AVDD 58 VREF 59 AVSS 60 P6.7/ADC_CH11/LCD_SEG11/I2C1_SCL 61 P6.6/ADC_CH12/LCD_SEG10/LCD_V1/I2C1_SDA 62 P6.5/ADC_CH13/LCD_SEG9/LCD_V2/UART0_TXD 63 P6.4/ADC_CH14/LCD_SEG8/LCD_V3/UART0_RXD 64 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O Sep. 1, 2020 Page 39 of 164 ML51/ML54/ML56 SERIES DATASHEET Pin Rev 2.00 ML51/ML54/ML56 4.1.2.2 LQFP48 Package Corresponding Part Number: ML51LD1AE P1.7 / UART0_RXD P1.6 / UART0_TXD P1.5 / I2C1_SDA P1.4 / I2C1_SCL P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / PWM2_CH1 P4.3 / PWM2_CH0 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 ML51LD1AE Pin Function VSS 37 24 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 38 23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 39 22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / P4.7 40 21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3 41 20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 42 19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 43 18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0 44 17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 VREF 45 16 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 LQFP48 11 12 IC0 / UART1_RXD / P1.0 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 9 IC2 / UART1_TXD / UART3_RXD / P1.1 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 8 10 7 IC0 / P1.3 6 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0 IC1 / UART3_TXD / P1.2 5 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 4 13 PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 48 3 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / PWM3_CH1 / UART1_RXD / P2.6 2 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 14 1 15 47 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 46 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 AVSS ACMP0_O / PWM3_CH0 / UART1_TXD / ADC_CH15 / P2.7 Figure 4.1-18 ML51LD1AE Multi-Function Pin assignment Pin ML51LD1AE Pin Function 1 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 4 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 Sep. 1, 2020 Page 40 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51LD1AE Pin Function P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE 6 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE 7 P1.3 / IC0 8 P1.2 / UART3_TXD / IC1 9 P1.1 / UART3_RXD / UART1_TXD / IC2 10 P1.0 / UART1_RXD / IC0 11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 15 P0.7 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 16 P0.6 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 24 nRESET 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 P4.5 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 P4.4 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 P4.3 / PWM2_CH0 30 P4.2 / PWM2_CH1 31 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O 32 P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 33 P1.4 / I2C1_SCL 34 P1.5 / I2C1_SDA 35 P1.6 / UART0_TXD 36 P1.7 / UART0_RXD Sep. 1, 2020 Page 41 of 164 ML51/ML54/ML56 SERIES DATASHEET 5 Rev 2.00 ML51/ML54/ML56 Pin ML51LD1AE Pin Function 37 VSS 38 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 39 VDD 40 P4.7 / T1 41 P3.3 / SPI1_SS / PWM1_CH0 / IC0 / PWM0_BRAKE 42 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO 43 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 44 P3.0 / ADC_CH10 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 45 VREF 46 AVSS 47 P2.7 / ADC_CH15 / UART1_TXD / PWM3_CH0 / ACMP0_O 48 P2.6 / UART1_RXD / PWM3_CH1 / ACMP1_O ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 42 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 ML54LD1AE Pin Function VSS 37 24 nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 38 23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 39 22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 40 21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 41 20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 42 19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 43 18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 44 17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 VREF 45 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 AVSS 46 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 47 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 48 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 8 9 IC1 / UART3_TXD / LCD_DH2 / P1.2 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 12 7 IC0 / P1.3 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 6 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 11 5 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 4 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 10 3 VLCD 2 1 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 LQFP48 Figure 4.1-19 ML54LD1AE Multi-Function Pin assignment Pin ML54LD1AE Pin Function 1 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 / PWM0_BRAKE Sep. 1, 2020 Page 43 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML54LD1AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 4 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 5 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE 6 P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE 7 P1.3 / IC0 8 P1.2 / LCD_DH2 / UART3_TXD / IC1 9 P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2 10 VLCD 11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 17 P0.5 / UART0_TXD / I2C0_SCL / PWM0_CH0 18 P0.4 / UART0_RXD / I2C0_SDA / PWM0_CH1 19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 23 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 24 nRESET 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 28 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 29 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 30 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 31 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O 32 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 33 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 34 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 Sep. 1, 2020 Page 44 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML54LD1AE Pin Function 35 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 36 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 37 VSS 38 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0 39 VDD 40 P4.7 / LCD_SEG16 / LCD_COM0 / T1 41 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE 42 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO 43 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 44 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 45 VREF 46 AVSS 47 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O 48 P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 45 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / TK14 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / TK13 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / TK12 / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 36 35 34 33 32 31 30 29 28 27 26 25 ML56LD1AE Pin Function VSS 37 24 nRESET INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 38 23 P5.6 / TK0 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 39 22 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 T1 / LCD_COM0 / LCD_SEG16 / P4.7 40 21 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 41 20 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 42 19 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 43 18 P0.4 / UART0_RXD / I2C0_SDA / TK5 / PWM0_CH1 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 44 17 P0.5 / UART0_TXD / I2C0_SCL / TK6 / PWM0_CH0 VREF 45 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 AVSS 46 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 47 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 48 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 8 9 IC1 / UART3_TXD / LCD_DH2 / P1.2 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 12 7 IC0 / P1.3 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 6 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 11 5 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 4 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 10 3 VLCD 2 1 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 LQFP48 Figure 4.1-20 ML56LD1AE Multi-Function Pin assignment Pin ML56LD1AE/ML56LC1AE Pin Function 1 P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0 2 P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1 3 P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE 4 P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3 5 P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK E Sep. 1, 2020 Page 46 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML56LD1AE/ML56LC1AE Pin Function P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE 7 P1.3/IC0 8 P1.2/LCD_DH2/UART3_TXD/IC1 9 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 10 VLCD 11 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC 12 P5.4/UART2_TXD/PWM0_CH1/X32_OUT 13 P5.3/UART0_TXD/I2C0_SCL/XT1_IN 14 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT 15 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 16 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 17 P0.5/UART0_TXD/I2C0_SCL/TK6/PWM0_CH0 18 P0.4/UART0_RXD/I2C0_SDA/TK5/PWM0_CH1 19 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO 20 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 21 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 22 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 23 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO 24 nRESET 25 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT 26 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK 27 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 28 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 29 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 30 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 31 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O 32 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 33 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 34 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 35 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 36 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 37 VSS 38 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 39 VDD Sep. 1, 2020 Page 47 of 164 ML51/ML54/ML56 SERIES DATASHEET 6 Rev 2.00 ML51/ML54/ML56 Pin ML56LD1AE/ML56LC1AE Pin Function 40 P4.7/LCD_SEG16/LCD_COM0/T1 41 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE 42 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO 43 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 44 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 45 VREF 46 AVSS 47 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O 48 P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 48 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.3 LQFP44 Package P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / TK14 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / TK13 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / TK12 / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 33 32 31 30 29 28 27 26 25 24 23 ML54MD1AE Pin Function VSS 34 22 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 35 21 nRESET VDD 36 20 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 37 19 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 38 18 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3 IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 39 17 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 40 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 VREF 41 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 AVSS 42 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 43 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 44 12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 6 7 8 9 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 IC0 / P1.3 IC1 / UART3_TXD / LCD_DH2 / P1.2 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 11 5 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 4 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 10 3 VLCD 2 1 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 LQFP44 Figure 4.1-21 ML54MD1AE Multi-Function Pin assignment Pin ML54MD1AE Pin Function 1 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / LCD_COM0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / ACMP0_N0 / LCD_COM1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / LCD_COM2 / UART1_TXD / PWM0_CH2 / PWM0_BRAKE Sep. 1, 2020 Page 49 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML54MD1AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 4 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / LCD_COM3 / UART1_RXD / PWM0_CH3 5 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / LCD_SEG5 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM3_CH0 / PWM0_BRAKE 6 P2.0 / ADC_CH5 / ACMP0_N1 / LCD_SEG4 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM3_CH1 / PWM0_BRAKE 7 P1.3 / IC0 8 P1.2 / LCD_DH2 / UART3_TXD / IC1 9 P1.1 / LCD_DH1 / UART3_RXD / UART1_TXD / IC2 10 VLCD 11 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 17 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 18 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 19 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 20 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 21 nRESET 22 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 23 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 24 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 25 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / PWM1_CH1 26 P4.3 / LCD_SEG29 / LCD_COM6 / PWM2_CH0 27 P4.2 / LCD_SEG28 / LCD_COM7 / PWM2_CH1 28 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O 29 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 30 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 31 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 32 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 33 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 34 VSS Sep. 1, 2020 Page 50 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML54MD1AE Pin Function 35 P4.6 / LCD_SEG17 / PWM0_CH0 / T0 / CLKO / INT0 36 VDD 37 P3.3 / LCD_SEG15 / SPI1_SS / LCD_COM1 / PWM1_CH0 / IC0 / PWM0_BRAKE 38 P3.2 / ADC_CH7 / ACMP1_N1 / LCD_SEG14 / SPI1_CLK / UART3_RXD / PWM1_CH1 / IC1 / CLKO 39 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / LCD_SEG13 / SPI1_MISO / UART3_TXD / UART0_TXD / PWM2_CH0 / IC2 40 P3.0 / ADC_CH10 / LCD_SEG12 / SPI1_MOSI / UART0_RXD / PWM2_CH1 / IC0 41 VREF 42 AVSS 43 P2.7 / ADC_CH15 / LCD_SEG7 / UART1_TXD / PWM3_CH0 / ACMP0_O 44 P2.6 / LCD_SEG6 / UART1_RXD / PWM3_CH1 / ACMP1_O ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 51 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 / LCD_SEG18 / UART0_RXD / LCD_COM7 P1.6 / LCD_SEG19 / UART0_TXD / LCD_COM6 P1.5 / LCD_SEG20 / I2C1_SDA / LCD_COM5 P1.4 / LCD_SEG21 / I2C1_SCL / LCD_COM4 P4.0 / LCD_SEG26 / LCD_COM3 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / LCD_SEG27 / LCD_COM2 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P4.2 / LCD_SEG28 / LCD_COM7 / TK14 / PWM2_CH1 P4.3 / LCD_SEG29 / LCD_COM6 / TK13 / PWM2_CH0 P4.4 / LCD_SEG30 / LCD_COM5 / UART2_RXD / I2C1_SDA / TK12 / PWM1_CH1 P4.5 / LCD_SEG31 / LCD_COM4 / UART2_TXD / I2C1_SCL / PWM1_CH0 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 33 32 31 30 29 28 27 26 25 24 23 ML56MD1AE Pin Function VSS 34 22 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT INT0 / CLKO / T0 / PWM0_CH0 / LCD_SEG17 / P4.6 35 21 nRESET VDD 36 20 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / TK1 / PWM0_CH5 PWM0_BRAKE / IC0 / PWM1_CH0 / LCD_COM1 / SPI1_SS / LCD_SEG15 / P3.3 37 19 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / TK2 / PWM0_CH4 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / LCD_SEG14 / ACMP1_N1 / ADC_CH7 / P3.2 38 18 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / TK3 / PWM0_CH3 IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / LCD_SEG13 / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 39 17 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / TK4 / STADC / PWM0_CH2 / CLKO IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / LCD_SEG12 / ADC_CH10 / P3.0 40 16 P0.6 / LCD_SEG0 / UART0_RXD / I2C1_SDA / PWM3_CH1 / INT0 VREF 41 15 P0.7 / LCD_SEG1 / UART0_TXD / I2C1_SCL / PWM3_CH0 / INT1 AVSS 42 14 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT ACMP0_O / PWM3_CH0 / UART1_TXD / LCD_SEG7 / ADC_CH15 / P2.7 43 13 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN ACMP1_O / PWM3_CH1 / UART1_RXD / LCD_SEG6 / P2.6 44 12 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 6 7 8 9 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / LCD_SEG4 / ACMP0_N1 / ADC_CH5 / P2.0 IC0 / P1.3 IC1 / UART3_TXD / LCD_DH2 / P1.2 IC2 / UART1_TXD / UART3_RXD / LCD_DH1 / P1.1 11 5 PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / LCD_SEG5 / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 4 PWM0_CH3 / UART1_RXD / LCD_COM3 / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 10 3 VLCD 2 1 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / LCD_COM1 / ACMP0_N0 / ADC_CH1 / P2.4 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / LCD_COM0 / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM0_CH2 / UART1_TXD / LCD_COM2 / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 LQFP44 Figure 4.1-22 ML56MD1AE Multi-Function Pin assignment Pin ML56MD1AE Pin Function 1 P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0 2 P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1 3 P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE 4 P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3 5 P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK E Sep. 1, 2020 Page 52 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML56MD1AE Pin Function P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE 7 P1.3/IC0 8 P1.2/LCD_DH2/UART3_TXD/IC1 9 P1.1/LCD_DH1/UART3_RXD/UART1_TXD/IC2 10 VLCD 11 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC 12 P5.4/UART2_TXD/PWM0_CH1/X32_OUT 13 P5.3/UART0_TXD/I2C0_SCL/XT1_IN 14 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT 15 P0.7/LCD_SEG1/UART0_TXD/I2C1_SCL/PWM3_CH0/INT1 16 P0.6/LCD_SEG0/UART0_RXD/I2C1_SDA/PWM3_CH1/INT0 17 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO 18 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 19 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 20 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 21 nRESET 22 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT 23 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK 24 P4.5/LCD_SEG31/LCD_COM4/UART2_TXD/I2C1_SCL/PWM1_CH0 25 P4.4/LCD_SEG30/LCD_COM5/UART2_RXD/I2C1_SDA/TK12/PWM1_CH1 26 P4.3/LCD_SEG29/LCD_COM6/TK13/PWM2_CH0 27 P4.2/LCD_SEG28/LCD_COM7/TK14/PWM2_CH1 28 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O 29 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 30 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 31 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 32 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 33 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 34 VSS 35 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 36 VDD 37 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE 38 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO 39 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 Sep. 1, 2020 Page 53 of 164 ML51/ML54/ML56 SERIES DATASHEET 6 Rev 2.00 ML51/ML54/ML56 Pin ML56MD1AE Pin Function 40 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 41 VREF 42 AVSS 43 P2.7/ADC_CH15/LCD_SEG7/UART1_TXD/PWM3_CH0/ACMP0_O 44 P2.6/LCD_SEG6/UART1_RXD/PWM3_CH1/ACMP1_O ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 54 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.4 QFN33 Package P1.7 / UART0_RXD P1.6 / UART0_TXD P1.5 / I2C1_SDA P1.4 / I2C1_SCL P4.0 / UART2_RXD / I2C0_SDA / PWM3_CH1 / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / PWM3_CH0 / ACMP0_O P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 ML51TD1AE Pin Function VSS 25 16 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 26 15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 27 14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART2_TXD / UART0_RXD / PWM0_CH5 13 P0.1 / SPI0_MISO / SPI1_MISO / UART2_RXD / UART0_TXD / PWM0_CH4 12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 / CLKO 10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 9 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN Top transparent view 6 7 8 PWM0_BRAKE / PWM3_CH1 / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 ML51/ML54/ML56 SERIES DATASHEET PWM0_BRAKE / PWM3_CH0 / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 33 VSS 5 VREF 32 4 31 PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 IC0 / PWM2_CH1 / UART0_RXD / SPI1_MOSI / ADC_CH10 / P3.0 3 30 2 IC2 / PWM2_CH0 / UART0_TXD / UART3_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 QFN33 1 29 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 28 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 PWM0_BRAKE / IC0 / PWM1_CH0 / SPI1_SS / P3.3 CLKO / IC1 / PWM1_CH1 / UART3_RXD / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 Figure 4.1-23 ML51TD1AE Multi-Function Pin assignment Pin ML56TD1AE Pin Function 1 P2.5/ADC_CH0/ACMP0_P0/ACMP1_P0/LCD_COM0/I2C0_SCL/PWM0_CH0/UART2_TXD/T0/INT0 2 P2.4/ADC_CH1/ACMP0_N0/LCD_COM1/I2C0_SDA/PWM0_CH1/UART2_RXD/T1/INT1 3 P2.3/ADC_CH2/ACMP0_P1/ACMP1_P1/I2C1_SCL/LCD_COM2/UART1_TXD/PWM0_CH2/PWM0_BRAKE 4 P2.2/ADC_CH3/ACMP1_N0/I2C1_SDA/LCD_COM3/UART1_RXD/PWM0_CH3 5 P2.1/ADC_CH4/ACMP0_P2/ACMP1_P2/LCD_SEG5/UART2_TXD/I2C1_SCL/PWM0_CH4/PWM3_CH0/PWM0_BRAK E 6 P2.0/ADC_CH5/ACMP0_N1/LCD_SEG4/UART2_RXD/I2C1_SDA/PWM0_CH5/PWM3_CH1/PWM0_BRAKE Sep. 1, 2020 Page 55 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML56TD1AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 7 P5.5/UART2_RXD/PWM0_CH0/X32_IN/STADC 8 P5.4/UART2_TXD/PWM0_CH1/X32_OUT 9 P5.3/UART0_TXD/I2C0_SCL/XT1_IN 10 P5.2/UART0_RXD/I2C0_SDA/XT1_OUT 11 P0.3/SPI0_SS/SPI1_SS/UART1_TXD/I2C1_SCL/TK4/STADC/PWM0_CH2/CLKO 12 P0.2/SPI0_CLK/SPI1_CLK/UART1_RXD/I2C1_SDA/TK3/PWM0_CH3 13 P0.1/SPI0_MISO/SPI1_MISO/UART2_RXD/UART0_TXD/TK2/PWM0_CH4 14 P0.0/SPI0_MOSI/SPI1_MOSI/UART2_TXD/UART0_RXD/TK1/PWM0_CH5 15 P5.6/TK0/PWM0_BRAKE/PWM0_CH1/CLKO 16 nRESET 17 P5.0/UART1_TXD/I2C1_SCL/UART0_TXD/ICE_DAT 18 P5.1/UART1_RXD/I2C1_SDA/UART0_RXD/ICE_CLK 19 P4.1/LCD_SEG27/LCD_COM2/UART2_TXD/I2C0_SCL/PWM3_CH0/ACMP0_O 20 P4.0/LCD_SEG26/LCD_COM3/UART2_RXD/I2C0_SDA/PWM3_CH1/ACMP1_O/INT1 21 P1.4/LCD_SEG21/I2C1_SCL/LCD_COM4 22 P1.5/LCD_SEG20/I2C1_SDA/LCD_COM5 23 P1.6/LCD_SEG19/UART0_TXD/LCD_COM6 24 P1.7/LCD_SEG18/UART0_RXD/LCD_COM7 25 VSS 26 P4.6/LCD_SEG17/PWM0_CH0/T0/CLKO/INT0 27 VDD 28 P3.3/LCD_SEG15/SPI1_SS/LCD_COM1/PWM1_CH0/IC0/PWM0_BRAKE 29 P3.2/ADC_CH7/ACMP1_N1/LCD_SEG14/SPI1_CLK/UART3_RXD/PWM1_CH1/IC1/CLKO 30 P3.1/ADC_CH6/ACMP0_P3/ACMP1_P3/LCD_SEG13/SPI1_MISO/UART3_TXD/UART0_TXD/PWM2_CH0/IC2 31 P3.0/ADC_CH10/LCD_SEG12/SPI1_MOSI/UART0_RXD/PWM2_CH1/IC0 32 VREF 33 VSS Sep. 1, 2020 Page 56 of 164 Rev 2.00 ML51/ML54/ML56 P1.7 / UART0_RXD P1.6 / UART0_TXD P1.5 / I2C1_SDA P1.4 / I2C1_SCL P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 ML51TC0AE / ML51TB9AE Pin Function VSS 25 16 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 26 15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 27 14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 PWM0_BRAKE / IC0 / SPI1_SS / P3.3 28 13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 29 12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 30 11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 IC0 / UART0_RXD / SPI1_MOSI / P3.0 31 10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT QFN33 33 VSS 2 3 4 5 6 7 8 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 PWM0_BRAKE / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 PWM0_BRAKE / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN ML51/ML54/ML56 SERIES DATASHEET 1 9 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 32 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 AVDD Top transparent view Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment Pin ML51TC0AE / ML51TB9AE Pin Function 1 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 4 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 5 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE Sep. 1, 2020 Page 57 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51TC0AE / ML51TB9AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 6 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE 7 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 8 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 9 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 16 nRESET 17 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 18 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 19 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O 20 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 21 P1.4 / I2C1_SCL 22 P1.5 / I2C1_SDA 23 P1.6 / UART0_TXD 24 P1.7 / UART0_RXD 25 VSS 26 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 27 VDD 28 P3.3 / SPI1_SS / IC0 / PWM0_BRAKE 29 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 30 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 31 P3.0 / SPI1_MOSI / UART0_RXD / IC0 32 AVDD 33 VSS Sep. 1, 2020 Page 58 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.5 LQFP32 Package P1.7 / UART0_RXD P1.6 / UART0_TXD P1.5 / I2C1_SDA P1.4 / I2C1_SCL P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 24 23 22 21 20 19 18 17 ML51PC0AE / ML51PB9AE Pin Function VSS 25 16 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 26 15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO VDD 27 14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 PWM0_BRAKE / IC0 / SPI1_SS / P3.3 28 13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 29 12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 30 11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 IC0 / UART0_RXD / SPI1_MOSI / P3.0 31 10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 32 9 2 3 4 5 6 7 8 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 PWM0_CH3 / UART1_RXD / I2C1_SDA / ACMP1_N0 / ADC_CH3 / P2.2 PWM0_BRAKE / PWM0_CH4 / I2C1_SCL / UART2_TXD / ACMP1_P2 / ACMP0_P2 / ADC_CH4 / P2.1 PWM0_BRAKE / PWM0_CH5 / I2C1_SDA / UART2_RXD / ACMP0_N1 / ADC_CH5 / P2.0 STADC / X32_IN / PWM0_CH0 / UART2_RXD / P5.5 X32_OUT / PWM0_CH1 / UART2_TXD / P5.4 1 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN ML51/ML54/ML56 SERIES DATASHEET INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 LQFP32 Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment Pin ML51PC0AE Pin Function 1 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 4 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 Sep. 1, 2020 Page 59 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51PC0AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 5 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE 6 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE 7 P5.5 / UART2_RXD / PWM0_CH0 / X32_IN / STADC 8 P5.4 / UART2_TXD / PWM0_CH1 / X32_OUT 9 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 10 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 11 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 12 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 13 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 14 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 15 P5.6 / PWM0_BRAKE / PWM0_CH1 / CLKO 16 nRESET 17 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 18 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 19 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O 20 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 21 P1.4 / I2C1_SCL 22 P1.5 / I2C1_SDA 23 P1.6 / UART0_TXD 24 P1.7 / UART0_RXD 25 VSS 26 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 27 VDD 28 P3.3 / SPI1_SS / IC0 / PWM0_BRAKE 29 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 30 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 31 P3.0 / SPI1_MOSI / UART0_RXD / IC0 32 AVDD Sep. 1, 2020 Page 60 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.6 TSSOP28 Package ML51EC0AE / ML51EB9AE Pin Function 1 28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 2 27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O UART0_TXD / P1.6 3 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / P1.7 4 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VSS 5 24 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 6 23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 VDD 7 22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 8 21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 9 20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 IC0 / UART0_RXD / SPI1_MOSI / P3.0 10 19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 11 18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 12 17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 13 16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 14 15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 TSSOP28 I2C1_SCL / P1.4 I2C1_SDA / P1.5 Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment Pin ML51EC0AE / ML51EB9AE Pin Function P1.4 / I2C1_SCL 2 P1.5 / I2C1_SDA 3 P1.6 / UART0_TXD 4 P1.7 / UART0_RXD 5 VSS 6 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 7 VDD 8 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 9 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 10 P3.0 / SPI1_MOSI / UART0_RXD / IC0 11 AVDD 12 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 13 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 14 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE 17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE 18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 Sep. 1, 2020 Page 61 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 1 ML51/ML54/ML56 Pin ML51EC0AE / ML51EB9AE Pin Function 22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 24 nRESET 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O 28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 62 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.7 SOP28 Package Corresponding Part Number: ML51UC0AE / ML51UB9AE 1 28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 2 27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O UART0_TXD / P1.6 3 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK UART0_RXD / P1.7 4 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VSS 5 24 nRESET INT0 / CLKO / T0 / PWM0_CH0 / P4.6 6 23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 VDD 7 22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 8 21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 9 20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 IC0 / UART0_RXD / SPI1_MOSI / P3.0 10 19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT AVDD 11 18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ACMP1_P0 / ACMP0_P0 / ADC_CH0 / P2.5 12 17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ACMP0_N0 / ADC_CH1 / P2.4 13 16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ACMP1_P1 / ACMP0_P1 / ADC_CH2 / P2.3 14 15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 SOP28 I2C1_SCL / P1.4 I2C1_SDA / P1.5 Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment ML51UC0AE / ML51UB9AE Pin Function Pin ML51UC0AE / ML51UB9AE Pin Function P1.4 / I2C1_SCL 2 P1.5 / I2C1_SDA 3 P1.6 / UART0_TXD 4 P1.7 / UART0_RXD 5 VSS 6 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 7 VDD 8 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 9 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 10 P3.0 / SPI1_MOSI / UART0_RXD / IC0 11 AVDD 12 P2.5 / ADC_CH0 / ACMP0_P0 / ACMP1_P0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 13 P2.4 / ADC_CH1 / ACMP0_N0 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 14 P2.3 / ADC_CH2 / ACMP0_P1 / ACMP1_P1 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 15 P2.2 / ADC_CH3 / ACMP1_N0 / I2C1_SDA / UART1_RXD / PWM0_CH3 16 P2.1 / ADC_CH4 / ACMP0_P2 / ACMP1_P2 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE 17 P2.0 / ADC_CH5 / ACMP0_N1 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE 18 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 19 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 20 P0.3 / SPI0_SS / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 Sep. 1, 2020 Page 63 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 1 ML51/ML54/ML56 Pin ML51UC0AE / ML51UB9AE Pin Function 21 P0.2 / SPI0_CLK / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 22 P0.1 / SPI0_MISO / SPI1_MISO / UART0_TXD / PWM0_CH4 23 P0.0 / SPI0_MOSI / SPI1_MOSI / UART0_RXD / PWM0_CH5 24 nRESET 25 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 26 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 27 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O 28 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 64 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.8 TSSOP20 Package ML51FB9AE Pin Function 1 20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VDD 3 18 nRESET CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 4 17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 5 16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 IC0 / UART0_RXD / SPI1_MOSI / P3.0 6 15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 AVDD 7 14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5 8 13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4 9 12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3 10 11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3 TSSOP20 VSS INT0 / CLKO / T0 / PWM0_CH0 / P4.6 Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment Pin ML51FB9AE Pin Function VSS 2 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 3 VDD 4 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 5 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 6 P3.0 / SPI1_MOSI / UART0_RXD / IC0 7 AVDD 8 P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 9 P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 10 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3 12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 18 nRESET 19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK Sep. 1, 2020 Page 65 of 164 ML51/ML54/ML56 SERIES DATASHEET 1 Rev 2.00 ML51/ML54/ML56 4.1.2.9 SOP20 Package ML51OB9AE Pin Function 1 20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VDD 3 18 nRESET CLKO / IC1 / SPI1_CLK / ACMP1_N1 / ADC_CH7 / P3.2 4 17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 5 16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 IC0 / UART0_RXD / SPI1_MOSI / P3.0 6 15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 AVDD 7 14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5 8 13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4 9 12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3 10 11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3 SOP20 VSS INT0 / CLKO / T0 / PWM0_CH0 / P4.6 Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment Pin ML51OB9AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 1 VSS 2 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 3 VDD 4 P3.2 / ADC_CH7 / ACMP1_N1 / SPI1_CLK / IC1 / CLKO 5 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 6 P3.0 / SPI1_MOSI / UART0_RXD / IC0 7 AVDD 8 P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 9 P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 10 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 11 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3 12 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 13 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 14 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 15 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 16 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 17 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 18 nRESET 19 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 20 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK Sep. 1, 2020 Page 66 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.10 QFN20 Package P1.7 / UART0_RXD P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 15 14 13 12 11 ML51XB9AE Pin Function Top transparent view VSS 16 INT0 / CLKO / T0 / PWM0_CH0 / P4.6 17 VDD 18 IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 19 QFN 20 N/C 1 2 3 4 5 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3 PWM0_CH3 / UART1_RXD / I2C1_SDA / ADC_CH3 / P2.2 PWM0_BRAKE / PWM0_CH4 / I2C1_SCL / UART2_TXD / ADC_CH4 / P2.1 nRESET 9 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 8 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 7 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 6 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 ML51/ML54/ML56 SERIES DATASHEET INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5 20 INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4 IC0 / UART0_RXD / SPI1_MOSI / P3.0 10 Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment Pin ML51XB9AE Pin Function 1 P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 2 P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 3 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 4 P2.2 / ADC_CH3 / I2C1_SDA / UART1_RXD / PWM0_CH3 5 P2.1 / ADC_CH4 / UART2_TXD / I2C1_SCL / PWM0_CH4 / PWM0_BRAKE 6 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 7 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 8 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 Sep. 1, 2020 Page 67 of 164 Rev 2.00 ML51/ML54/ML56 Pin ML51XB9AE Pin Function 9 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 10 nRESET 11 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 12 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 13 P4.1 / UART2_TXD / I2C0_SCL / ACMP0_O 14 P4.0 / UART2_RXD / I2C0_SDA / ACMP1_O / INT1 15 P1.7 / UART0_RXD 16 VSS 17 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 18 VDD 19 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 20 P3.0 / SPI1_MOSI / UART0_RXD / IC0 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 68 of 164 Rev 2.00 ML51/ML54/ML56 4.1.2.11 TSSOP14 Package ML51DB9AE Pin Function 1 14 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 13 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT VDD 3 12 nRESET IC2 / UART0_TXD / SPI1_MISO / ACMP1_P3 / ACMP0_P3 / ADC_CH6 / P3.1 4 11 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 IC0 / UART0_RXD / SPI1_MOSI / P3.0 5 10 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 INT0 / T0 / UART2_TXD / PWM0_CH0 / I2C0_SCL / ADC_CH0 / P2.5 6 9 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT INT1 / T1 / UART2_RXD / PWM0_CH1 / I2C0_SDA / ADC_CH1 / P2.4 7 8 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN TSSOP14 VSS INT0 / CLKO / T0 / PWM0_CH0 / P4.6 Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment Pin ML51DB9AE Pin Function VSS 2 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 3 VDD 4 P3.1 / ADC_CH6 / ACMP0_P3 / ACMP1_P3 / SPI1_MISO / UART0_TXD / IC2 5 P3.0 / SPI1_MOSI / UART0_RXD / IC0 6 P2.5 / ADC_CH0 / I2C0_SCL / PWM0_CH0 / UART2_TXD / T0 / INT0 7 P2.4 / ADC_CH1 / I2C0_SDA / PWM0_CH1 / UART2_RXD / T1 / INT1 8 P5.3 / UART0_TXD / I2C0_SCL / XT1_IN 9 P5.2 / UART0_RXD / I2C0_SDA / XT1_OUT 10 P0.3 / SPI1_SS / UART1_TXD / I2C1_SCL / STADC / PWM0_CH2 11 P0.2 / SPI1_CLK / UART1_RXD / I2C1_SDA / PWM0_CH3 12 nRESET 13 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 14 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK Sep. 1, 2020 Page 69 of 164 ML51/ML54/ML56 SERIES DATASHEET 1 Rev 2.00 ML51/ML54/ML56 4.1.2.12 MSOP10 Package ML51BB9AE Pin Function 1 VSS 2 INT0 / CLKO / T0 / PWM0_CH0 / P4.6 3 VDD 4 PWM0_BRAKE / PWM0_CH2 / UART1_TXD / I2C1_SCL / ADC_CH2 / P2.3 5 MSOP10 ICE_CLK / UART0_RXD / I2C1_SDA / UART1_RXD / P5.1 10 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT 9 nRESET 8 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 7 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 6 P2.0 / ADC_CH5 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE Figure 4.1-32 ML51BB9AE Pin Assignment Pin ML51BB9AE Pin Function ML51/ML54/ML56 SERIES DATASHEET 1 P5.1 / UART1_RXD / I2C1_SDA / UART0_RXD / ICE_CLK 2 VSS 3 P4.6 / PWM0_CH0 / T0 / CLKO / INT0 4 VDD 5 P2.3 / ADC_CH2 / I2C1_SCL / UART1_TXD / PWM0_CH2 / PWM0_BRAKE 6 P2.0 / ADC_CH5 / UART2_RXD / I2C1_SDA / PWM0_CH5 / PWM0_BRAKE 7 P0.1 / SPI1_MISO / UART0_TXD / PWM0_CH4 8 P0.0 / SPI1_MOSI / UART0_RXD / PWM0_CH5 9 nRESET 10 P5.0 / UART1_TXD / I2C1_SCL / UART0_TXD / ICE_DAT Sep. 1, 2020 Page 70 of 164 Rev 2.00 ML51/ML54/ML56 4.2 Pin Description 4.2.1 ML51/ML54/ML56 Series Pin Mapping ML54/ML56 ML51 Pin Number 64 48 44 64 48 33/32 28 20 QFN20 14 P2.6 1 48 44 1 48 P2.5 2 1 1 2 1 1 12 8 1 6 P2.4 3 2 2 3 2 2 13 9 2 7 P2.3 4 3 3 4 3 3 14 10 3 P2.2 5 4 4 5 4 4 15 11 4 P2.1 6 5 5 6 5 5 16 P2.0 7 6 6 7 6 6 17 P1.3 8 7 7 8 7 P1.2 9 8 8 9 8 P1.1 10 9 9 10 9 P1.0 11 11 10 VLCD 12 10 10 5 5 6 10 P3.7 12 13 P5.5 14 11 11 14 11 7 P5.4 15 12 12 15 12 8 P5.3 16 13 13 16 13 9 18 12 8 P5.2 17 14 14 17 14 10 19 13 9 P3.5 18 18 P3.4 19 19 P0.7 20 15 15 20 15 P0.6 21 16 16 21 16 VSS 22 22 VDD 23 23 P3.6 24 24 P0.5 25 17 25 17 P0.4 26 18 26 18 P0.3 27 19 17 27 19 11 20 14 6 10 P0.2 28 20 18 28 20 12 21 15 7 11 P0.1 29 21 19 29 21 13 22 16 8 7 P0.0 30 22 20 30 22 14 23 17 9 8 P5.6 31 23 31 23 15 nRESET 32 24 32 24 16 24 18 10 Sep. 1, 2020 13 21 ML51/ML54/ML56 SERIES DATASHEET P5.7 33 Page 71 of 164 12 9 Rev 2.00 ML51/ML54/ML56 ML54/ML56 ML51 ML51/ML54/ML56 SERIES DATASHEET Pin Number 64 48 44 64 48 33/32 28 20 QFN20 14 10 P5.0 33 25 22 33 25 17 25 19 11 13 10 P5.1 34 26 23 34 26 18 26 20 12 14 1 P4.5 35 27 24 35 27 P4.4 36 28 25 36 28 P4.3 37 29 26 37 29 P4.2 38 30 27 38 30 P4.1 39 31 28 39 31 19 27 13 P4.0 40 32 29 40 32 20 28 14 P6.3 41 41 P6.2 42 42 P6.1 43 43 P6.0 44 44 P1.4 45 33 30 45 33 21 1 P1.5 46 34 31 46 34 22 2 P1.6 47 35 32 47 35 23 3 P1.7 48 36 33 48 36 24 4 VSS 49 37 34 49 37 25 5 1 16 1 2 P4.6 50 38 35 50 38 26 6 2 17 2 3 VDD 51 39 36 51 39 27 7 3 18 3 4 P4.7 52 40 52 40 P3.3 53 41 37 53 41 28 P3.2 54 42 38 54 42 29 8 4 P3.1 55 43 39 55 43 30 9 5 19 4 P3.0 56 44 40 56 44 31 10 6 20 5 AVDD 57 39 36 57 39 27 7 VREF 58 45 41 58 45 32 11 AVSS 59 46 42 59 46 P6.7 60 60 P6.6 61 61 P6.5 62 62 P6.4 63 63 P2.7 64 Sep. 1, 2020 47 43 64 15 7 16 47 Page 72 of 164 Rev 2.00 ML51/ML54/ML56 4.2.2 ML51/ML54/ML56 Series Pin Functional Description As default all GPIO type is defined as input mode. User should setting the GPIO Mode by PxMx register. A: Analog suggest disable digial function O: output, I: input, I/O: bi-direction (Quasi) Group Pin Name Type ACMP0_N0 Description Analog comparator 0 negative input 0 pin. A ACMP0_N1 ACMP0_O ACMP0 Analog comparator 0 negative input 1 pin. O ACMP0_P0 Analog comparator 0 output pin. Analog comparator 0 positive input 0 pin. ACMP0_P1 Analog comparator 0 positive input 1 pin. A ACMP0_P2 Analog comparator 0 positive input 2 pin. ACMP0_P3 Analog comparator 0 positive input 3 pin. ACMP1_N0 Analog comparator 1 negative input 0 pin. A ACMP1_N1 ACMP1_O ACMP1 Analog comparator 1 negative input 1 pin. O ACMP1_P0 Analog comparator 1 output pin. Analog comparator 1 positive input 0 pin. ACMP1_P1 Analog comparator 1 positive input 1 pin. A Analog comparator 1 positive input 2 pin. ACMP1_P3 Analog comparator 1 positive input 3 pin. ADC_CH0 ADC_ channel analog input. ADC_CH1 ADC_ channel analog input. ADC_CH2 ADC_ channel analog input. ADC_CH3 ADC_ channel analog input. ADC_CH4 ADC_ channel analog input. ADC_CH5 ADC_ channel analog input. ADC_CH6 ADC ADC_ channel analog input. A ADC_CH7 ADC_ channel analog input. ADC_CH10 ADC_ channel analog input. ADC_CH11 ADC_ channel analog input. ADC_CH12 ADC_ channel analog input. ADC_CH13 ADC_ channel analog input. ADC_CH14 ADC_ channel analog input. ADC_CH15 ADC_ channel analog input. CLKO CLKO O Clock Out I2C0 I2C0_SCL I/O I2C0 clock pin. Sep. 1, 2020 ML51/ML54/ML56 SERIES DATASHEET ACMP1_P2 Page 73 of 164 Rev 2.00 ML51/ML54/ML56 Group Pin Name Type Description I2C0_SDA I/O I2C0 data input/output pin. I2C1_SCL I/O I2C1 clock pin. I2C1_SDA I/O I2C1 data input/output pin. IC0 IC0 I/O Input Capture channel 0 IC1 IC1 I/O Input Capture channel 1 IC2 IC2 I/O Input Capture channel 2 I2C1 Serial wired debugger clock pin. ICE_CLK I ICE_DAT O Note: It is recommended to use 100 kΩ pull-up resistor on ICE_DAT pin INT0 INT0 I External interrupt 0 input pin. INT1 INT1 I External interrupt 1 input pin. LCD_COM0 O LCD Common 0 output. LCD_COM1 O LCD Common 1 output. LCD_COM2 O LCD Common 2 output. LCD_COM3 O LCD Common 3 output. LCD_COM4 O LCD Common 4 output. LCD_COM5 O LCD Common 5 output. LCD_COM6 O LCD Common 6 output. LCD_COM7 O LCD Common 7 output. LCD_DH1 O LCD external capacitor pin of charge pump circuit. LCD_DH2 O LCD external capacitor pin of charge pump circuit. LCD_SEG0 O LCD segment 0 output LCD_SEG1 O LCD segment 1 output LCD_SEG2 O LCD segment 2 output LCD_SEG3 O LCD segment 3 output LCD_SEG4 O LCD segment 4 output LCD_SEG5 O LCD segment 5 output LCD_SEG6 O LCD segment 6 output LCD_SEG7 O LCD segment 7 output LCD_SEG8 O LCD segment 8 output LCD_SEG9 O LCD segment 9 output LCD_SEG10 O LCD segment 10 output LCD_SEG11 O LCD segment 11 output Note: It is recommended to use 100 kΩ pull-up resistor on ICE_CLK pin ICE Serial wired debugger data pin. ML51/ML54/ML56 SERIES DATASHEET LCD Sep. 1, 2020 Page 74 of 164 Rev 2.00 ML51/ML54/ML56 Group PWM0 Type Description LCD_SEG12 O LCD segment 12 output LCD_SEG13 O LCD segment 13 output LCD_SEG14 O LCD segment 14 output LCD_SEG15 O LCD segment 15 output LCD_SEG16 O LCD segment 16 output LCD_SEG17 O LCD segment 17 output LCD_SEG18 O LCD segment 18 output LCD_SEG19 O LCD segment 19 output LCD_SEG20 O LCD segment 20 output LCD_SEG21 O LCD segment 21 output LCD_SEG22 O LCD segment 22 output LCD_SEG23 O LCD segment 23 output LCD_SEG24 O LCD segment 24 output LCD_SEG25 O LCD segment 25 output LCD_SEG26 O LCD segment 26 output LCD_SEG27 O LCD segment 27 output LCD_SEG28 O LCD segment 28 output LCD_SEG29 O LCD segment 29 output LCD_SEG30 O LCD segment 30 output LCD_SEG31 O LCD segment 31 output LCD_V1 I Input pin of the 1st most positive LCD level. LCD_V2 I Input pin of the 2nd most positive LCD level. LCD_V3 I Input pin of the 3rd most positive LCD level. nRESET I PWM0_BRAKE I External reset input: active LOW, with an internal pull-up. Set this pin low reset to initial state. Note: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. PWM0 Brake input pin. PWM0_CH0 I/O PWM0 channel 0 output/capture input. PWM0_CH1 I/O PWM0 channel 1 output/capture input. PWM0_CH2 I/O PWM0 channel 2 output/capture input. PWM0_CH3 I/O PWM0 channel 3 output/capture input. PWM0_CH4 I/O PWM0 channel 4 output/capture input. PWM0_CH5 I/O PWM0 channel 5 output/capture input. PWM1_CH0 I/O PWM1 channel 0 output/capture input. PWM1_CH1 I/O PWM1 channel 1 output/capture input. PWM1 Sep. 1, 2020 Page 75 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET nRESET Pin Name ML51/ML54/ML56 Group Pin Name Type Description PWM2_CH0 I/O PWM2 channel 0 output/capture input. PWM2_CH1 I/O PWM2 channel 1 output/capture input. PWM3_CH0 I/O PWM3 channel 0 output/capture input. PWM3_CH1 I/O PWM3 channel 1 output/capture input. SPI0_CLK I/O SPI0 serial clock pin. SPI0_MISO I/O SPI0 MISO (Master In, Slave Out) pin. SPI0_MOSI I/O SPI0 MOSI (Master Out, Slave In) pin. SPI0_SS I/O SPI0 slave select pin. SPI1_CLK I/O SPI1 serial clock pin. SPI1_MISO I/O SPI1 MISO (Master In, Slave Out) pin. SPI1_MOSI I/O SPI1 MOSI (Master Out, Slave In) pin. SPI1_SS I/O SPI1 slave select pin. PWM2 PWM3 SPI0 SPI1 STADC STADC I ADC external trigger input. T0 T0 I/O External count input to Timer/Counter 0 or its toggle output. T1 T1 I/O External count input to Timer/Counter 1 or its toggle output. ML51/ML54/ML56 SERIES DATASHEET TK TK0 A Touch Key 0. TK1 A Touch Key 1. TK2 A Touch Key 2. TK3 A Touch Key 3. TK4 A Touch Key 4. TK5 A Touch Key 5. TK6 A Touch Key 6. TK7 A Touch Key 7. TK8 A Touch Key 8. TK9 A Touch Key 9. TK10 A Touch Key 10. TK11 A Touch Key 11. TK12 A Touch Key 12. TK13 A Touch Key 13. TK14 A Touch Key 14. UART0_RXD I UART0 data receiver input pin. UART0_TXD O UART0 data transmitter output pin. UART1_RXD I UART1 data receiver input pin. UART1_TXD O UART1 data transmitter output pin. UART2_RXD I UART2 data receiver input pin. UART0 UART1 UART2 Sep. 1, 2020 Page 76 of 164 Rev 2.00 ML51/ML54/ML56 Group Pin Name Type Description UART2_TXD O UART2 data transmitter output pin. UART3_RXD I UART3 data receiver input pin. UART3_TXD O UART3 data transmitter output pin. VREF A ADC reference voltage input. Note: This pin needs to be connected with a 1uF capacitor when use internal voltage reference output. X32_IN I External 32.768 kHz crystal input pin. X32_OUT O External 32.768 kHz crystal output pin. XT1_IN I External 4~24 MHz (high speed) crystal input pin. XT1_OUT O External 4~24 MHz (high speed) crystal output pin. UART3 VREF X32 XT1 ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 77 of 164 Rev 2.00 ML51/ML54/ML56 5 BLOCK DIAGRAM 5.1 ML51/ML54/ML56 Series Full Function Block 1T High Performance 8051 Core Memory Access POR / LVR / BOD Max. 64KB APROM Flash Timer 2 with Input Capture GPIO P2[7:0] P3[7:0] ML51/ML54/ML56 SERIES DATASHEET P4[7:0] P5[7:0] P6[7:0] Any Port 8 8 8 Watchdog Timer 4 Kbytes XRAM (Auxiliary RAM) Serial Ports (UART 0/1) PDMA with CRC Smart Card/ Series Ports (UART 2/3) P1 SPI0 P2 SPI1 P3 PWM0/1/2/3 P4 8 6 6 UART0_TXD UART0_RXD UART1_TXD UART1_RXD UART2_TXD UART2_RXD UART3_TXD UART3_RXD I2C0_SDA I2C0_SCL I2C1_SDA I2C1_SCL SPI0_MOSI SPI0_MISO SPI0_SS SPI0_SCK SPI1_MOSI SPI1_MISO SPI1_SS SPI1_SCK PWM0CH0~5 PWM1/2/3CH0~1 FB0 RTC P5 8 15 P6 8 ICAP0~2 Digital Peripheral I2C0/1 8 INT0 INT1 12-bit ADC AIN0~7, 9~15 STADC Internal VREF External VREF Analog Peripheral GPIO Interrupt External Interrupt ACMP0_P ACMP0_N ACMP1_P ACMP1_N ACMP 0/1 15 TK0~14 256 bytes Internal RAM P0 3 Self Wake-up Timer 8-bit Internal Bus P1[7:0] 8 T0 T1 Timer 3 Max. Bytes Data Flash (page: 128B) P0[7:0] VSS Timer 0/1 Max. 4KB LDROM Flash Power Management VDD 4/6/8 Touch key LCD 32/30/28 COM SEG System Clock XOUT 4-24 MHz Oscillator Circuit (HXT) X32IN X32OUT 32768 Hz Oscillator Circuit (LXT) XIN 24 MHz Internal RC Oscillator (HIRC) Clock Divider 38.4 kHz Internal RC Oscillator (LIRC) System Clock Source Figure 5.1-1 Functional Block Diagram Sep. 1, 2020 Page 78 of 164 Rev 2.00 ML51/ML54/ML56 6 FUNCTIONAL DESCRIPTION 6.1 Memory Organization A standard 80C51 based microcontroller divides the memory into two different sections, Program Memory and Data Memory. The Program Memory is used to store the instruction codes, whereas the Data Memory is used to store data or variations during the program execution. The Data Memory occupies a separate address space from Program Memory. In ML51/ML54/ML56 Series, there are 256 bytes of internal scratch-pad RAM. For many applications those need more internal RAM, the ML51/ML54/ML56 Series provides another on-chip 4 Kbytes of RAM, which is called XRAM, accessed by MOVX instruction. The whole embedded Flash, functioning as Program Memory, is divided into three blocks: Application ROM (APROM) normally for User Code, Loader ROM (LDROM) normally for Boot Code, and CONFIG bytes for hardware initialization. Actually, APROM and LDROM function in the same way but have different size. Each block is accumulated page by page and the page size is 128 bytes. The Flash control unit supports Erase, Program, and Read modes. The external writer tools though specific I/O pins, In-Application-Programming (IAP), or In-System-Programming (ISP) can both perform these modes. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 79 of 164 Rev 2.00 ML51/ML54/ML56 6.2 System Manager The ML51/ML54/ML56 Series has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. The ML51/ML54/ML56 Series provides five options of the system clock sources including internal oscillator, crystal/resonator, or external clock from X IN pin via software. The ML51/ML54/ML56 Series is embedded with two internal oscillators: one 38.4 kHz low-speed and one 24 MHz high-speed, which is factory trimmed to ±2% under all conditions. A clock divider CKDIV is also available on ML51/ML54/ML56 Series for adjustment of the flexibility between power consumption and operating performance. 32.768 kHz Oscillating Circuit X32OUT X32IN FLXT 111 4~24 MHz Oscillating Circuit XOUT XIN FHXT 10X FECLK 01X 24 MHz Internal Oscillator [1] 38.4 kHz Internal Oscillator Flash Memory 110 FHIRC Clock Filter FOSC Clock Divider FSYS CPU 00X CKDIV FLIRC OSC[2:0] (CKSWT[2:0]) Watchdog Timer ML51/ML54/ML56 SERIES DATASHEET 0 1 [1] Default system clock source after power-on WKTCK (WKCON.5) Self Wake-up Timer Peripherals CLOEN (CKCON.1) CLO Figure 6.2-1 Clock System Block Diagram Sep. 1, 2020 Page 80 of 164 Rev 2.00 ML51/ML54/ML56 6.3 6.3.1 Flash Memory Control In-application-programming (IAP) Unlike RAM’s real-time operation, to update Flash data often takes long time. Furthermore, it is a quite complex timing procedure to erase, program, or read Flash data. The ML51/ML54/ML56 Series carried out the Flash operation with convenient mechanism to help user re-programming the Flash content by In-Application-Programming (IAP). IAP is an in-circuit electrical erasure and programming method through software. After IAP enabling by setting IAPEN (CHPCON.0 with TA protected) and setting the enable bit in IAPUEN that allows the target block to be updated, user can easily fill the 16-bit target address in IAPAH and IAPAL, data in IAPFD, and command in IAPCN. Then the IAP is ready to begin by setting a triggering bit IAPGO (IAPTRG.0). Note that IAPTRG is also TA protected. At this moment, the CPU holds the Program Counter and the built-in IAP automation takes over to control the internal chargepump for high voltage and the detail signal timing. The erase and program time is internally controlled disregard of the operating voltage and frequency. Nominally, a page-erase time is 5 ms and a byteprogram time is 23.5 μs. After IAP action completed, the Program Counter continues to run the following instructions. The IAPGO bit will be automatically cleared. An IAP failure flag, IAPFF (CHPCON.6), can be check whether the previous IAP operation was successful or not. Through this progress, user can easily erase, program, and verify the Flash Memory by just taking care of pure software. 6.3.2 In-Circuit-Programming (ICP) There are three signal pins, ̅̅̅̅̅̅ RST, ICPDA, and ICPCK, involved in ICP function. ̅̅̅̅̅̅ RST is used to enter or exit ICP mode. ICPDA is the data input and output pin. ICPCK is the clock input pin, which synchronizes the data shifted in to or out from MCU under programming. User should leave these three pins plus VDD and GND pins on the circuit board to make ICP possible. Nuvoton provides ICP tool for ML51/ML54/ML56 Series, which enables user to easily perform ICP through Nuvoton ICP programmer. The ICP programmer developed by Nuvoton has been optimized according to the electric characteristics of MCU. It also satisfies the stability and efficiency during production progress. For more details, please visit Nuvoton 8-bit Microcontroller website: Nuvoton 80C51 Microcontroller Technical Support. 6.3.3 On-Chip-Debugger (ICE) The ML51/ML54/ML56 Series is embedded in an on-chip-debugger (OCD) providing developers with a low cost method for debugging user code, which is available on each package. The OCD gives debug capability of complete program flow control with eight hardware address breakpoints, single step, free running, and non-intrusive commands for memory access. The OCD system does not occupy any locations in the memory map and does not share any on-chip peripherals. Sep. 1, 2020 Page 81 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET The Flash Memory can be programmed by “In-Circuit-Programming” (ICP). If the product is just under development or the end product needs firmware updating in the hand of an end customer, the hardware programming mode will make repeated programming difficult and inconvenient. ICP method makes it easy and possible without removing the microcontroller from the system. ICP mode also allows customers to manufacture circuit boards with un-programmed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a customized firmware. ML51/ML54/ML56 6.4 GPIO Port Structure and Operation 6.4.1 GPIO Mode The ML51/ML54/ML56 Series has a maximum of 56 general purpose I/O pins which 40 bitaddressable general I/O pins grouped as 5 ports, P0 to P4, and 16 general I/O pins grouped as P5 and P6. Each port has its port control register (Px register). The writing and reading of a port control register have different meanings. A write to port control register sets the port output latch logic value, where as a read gets the port pin logic state. These four modes are quasi-bidirectional (standard 8051 port structure), push-pull, input-only, and open-drain modes. Each port spends two special function registers PxM1 and PxM2 to select the I/O mode of port Px. The list below illustrates how to select the I/O mode of Px.n. Note that the default configuration of is input-only (high-impedance) after any reset. PnM1.X[1] PnM2.X[1] 0 0 Quasi-bidirectional 0 1 Push-pull 1 0 Input-only (high-impedance) 1 1 Open-drain I/O Type Note: N = 0~5, x = 0~7 Table 6.4-1 Configuration for Different I/O Modes ML51/ML54/ML56 SERIES DATASHEET All I/O pins can be selected as TTL level inputs or Schmitt triggered inputs by selecting corresponding bit in PxS register. Schmitt triggered input has better glitch suppression capability. All I/O pins also have bit-controllable, slew rate select ability via software. The Register Description are PxSR. By default, the slew rate is slow. If user would like to increase the I/O output speed, setting the corresponding bit in PxSR, the slew rate is selected in a faster level. Sep. 1, 2020 Page 82 of 164 Rev 2.00 ML51/ML54/ML56 6.5 Timer 6.5.1 Overview ML51/ML54/ML56 Series provides following 16-bit Timer. Two 16-bit Timers/Counters 0 and 1 compatible with standard 8051. One 16-bit Timer 2 with three-channel input capture module and 9 input pin can be selected. One 16-bit auto-reload Timer 3, which can be the baud rate clock source of UARTs. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 83 of 164 Rev 2.00 ML51/ML54/ML56 6.6 Watchdog Timer (WDT) The ML51/ML54/ML56 Series provides one Watchdog Timer (WDT). It can be configured as a timeout reset timer to reset whole device. Once the device runs in an abnormal status or hangs up by outward interference, a WDT reset recover the system. It provides a system monitor, which improves the reliability of the system. Therefore, WDT is especially useful for system that is susceptible to noise, power glitches, or electrostatic discharge. The WDT also can be configured as a general purpose timer, of which the periodic interrupt serves as an event timer or a durational system supervisor in a monitoring system, which is able to operate during Idle or Power-down mode. WDTEN[3:0] (CONFIG4[7:4]) initialize the WDT to operate as a time-out reset timer or a general purpose timer. 1 × 64 , where FLIRC × clock dividerscalar FLIRC is the frequency of internal 38.4 kHz oscillator. The following table shows an example of the Watchdog time-out interval with different pre-scales. The Watchdog time-out interval is determined by the formula ML51/ML54/ML56 SERIES DATASHEET WDPS.3 WDPS.2 WDPS.1 WDPS.0 Clock Divider Scale WDT Time-Out Timing[1] 0 0 0 0 1/1 1.66 ms 0 0 0 1 1/4 6.64 ms 0 0 1 0 1/8 13.31 ms 0 0 1 1 1/16 26.62 ms 0 1 0 0 1/32 53.25 ms 0 1 0 1 1/64 106.66 ms 0 1 1 0 1/128 213.12 ms 0 1 1 1 1/256 426.64 ms 1 0 0 0 1/512 853.28ms 1 0 0 1 1/1024 1706.56ms 1 0 1 0 1/2048 3413.12ms 1/2048 3413.12ms Others Note: This is an approximate value since the deviation of LIRC. Table 6.6-1 Watchdog Timer-out Interval Under Different Pre-scalars Since the limitation of the maxima vaule of WDT timer delay. To wake up ML51/ML54/ML56 Series from idle mode or power down mode suggest use WKT function see Chapter 6.7 . The WDT is implemented with a set of divider that divides the low-speed internal oscillator clock nominal 38.4 kHz. The divider output is selectable and determines the time-out interval. When the time-out interval is fulfilled, it will wake the system up from Idle or Power-down mode and an interrupt event will occur if WDT interrupt is enabled. If WDT is initialized as a time-out reset timer, a system reset will occur after a period of delay if without any software action. Sep. 1, 2020 Page 84 of 164 Rev 2.00 ML51/ML54/ML56 6.7 Self Wake-up Timer (WKT) 6.7.1 Overview The ML51/ML54/ML56 Series has a dedicated Self Wake-up Timer (WKT), which serves for a periodic wake-up timer in low power mode or for general purpose timer. WKT remains counting in Idle or Power-down mode. When WKT is being used as a wake-up timer, a start of WKT can occur just prior to entering a power management mode. WKT has two clock source, internal LIRC 38.4 kHz or LXT 32.768 kHz. Note that the system clock frequency must be twice over WKT clock. If WKT starts counting, the selected clock source will remain active once the device enters Idle or Power-down mode. Note that the selected clock source of WKT will not automatically enabled along with WKT configuration. User should manually enable the selected clock source and waiting for stability to ensure a proper operation. The WKT is implemented simply as a 16-bit auto-reload, up-counting timer with pre-scale 1/1 to 1/2048 selected by WKPS[2:0] (WKCON[2:0]). User fills the reload value into RWK register to determine its overflow rate. The RWK can reloadable when counter is count to overflow. The CWK can read current count value. The WKTR (WKCON.3) can be set to start counting. When the counter rolls over FFH, WKTF (WKCON.4) is set as 1 and a reload is generated and causes the contents of the RWK register to be reloaded into the internal 8-bit counter. If EWKT (EIE1.2) is set as 1, WKT interrupt service routine will be served. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 85 of 164 Rev 2.00 ML51/ML54/ML56 6.8 Pulse Width Modulated (PWM) 6.8.1 Overview The PWM (Pulse Width Modulation) signal is a useful control solution in wide application field. It can used on motor driving, fan control, backlight brightness tuning, LED light dimming, or simulating as a simple digital to analog converter output through a low pass filter circuit. The ML51/ML54/ML56 Series PWM0 is especially designed for motor control by providing three pairs, maximum 16-bit resolution of PWM0 output with programmable period and duty. The architecture makes user easy to drive the one-phase or three-phase brushless DC motor (BLDC), or three-phase AC induction motor. Each of six PWM can be configured as one of independent mode, complementary mode, or synchronous mode. If the complementary mode is used, a programmable dead-time insertion is available to protect MOS turn-on simultaneously. The PWM waveform can be edge-aligned or center-aligned with variable interrupt points. The ML51/ML54/ML56 Series PWM1/2/3 provide individual configurable period and duty. maximum 16-bit resolution output. Each of two PWM1/2/3 can be configured as one of independent mode, complementary mode, or synchronous mode.The PWM1/2/3 waveform can be edge-aligned or centeraligned with variable interrupt points. 6.8.2 Features ML51/ML54/ML56 SERIES DATASHEET  Up To 12 output pins can be selected  Supports maximum clock source frequency up to 24 MHz  Supports up to Three PWM modules, each module provides 6 output channels.  Supports independent mode for PWM output  Supports complementary mode for 3 complementary paired PWM output channels  Dead-time insertion with 8-bit resolution  Supports 16-bit resolution PWM counter  Supports mask function and tri-state enable for each PWM pin  Supports brake function  Supports trigger ADC on the following events Sep. 1, 2020 Page 86 of 164 Rev 2.00 ML51/ML54/ML56 6.9 Serial Port (UART0 & UART1) 6.9.1 Overview The ML51/ML54/ML56 Series includes two enhanced full duplex serial ports enhanced with automatic address recognition and framing error detection. As control bits of these two serial ports are implemented the same. Generally speaking, in the following contents, there will not be any reference to serial port 1, but only to serial port 0. Each serial port supports one synchronous communication mode, Mode 0, and three modes of full duplex UART (Universal Asynchronous Receiver and Transmitter), Mode 1, 2, and 3. This means it can transmit and receive simultaneously. The serial port is also receiving-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. The receiving and transmitting registers are both accessed at SBUF. Writing to SBUF loads the transmitting register, and reading SBUF accesses a physically separate receiving register. There are four operation modes in serial port. In all four modes, transmission initiates by any instruction that uses SBUF as a destination register. 6.9.2 Features  Supports up to 2 UARTs: UART0, UART1  Supports 2 Smart Card configuration as UART function as UART2 and UART3.  UART baud rate clock from HIRC or HXT.  Full-duplex asynchronous communications  Programmable 9th bit.  TXD and RXD pins of UART0 exchangeable via software. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 87 of 164 Rev 2.00 ML51/ML54/ML56 6.10 Smart Card Interface (SC) 6.10.1 Overview The ML51/ML54/ML56 Series provides Smart Card Interface controller (SC controller) with asynchronous protocal based on ISO/IEC 7816-3 standard. Software controls GPIO pins as the smartcard reset function and card detection function. This controller also provides UART emulation for high precision baud rate communication. 6.10.2 Features  ISO 7816-3 T = 0, T = 1 compliant  Programmable transmission clock frequency  Programmable extra guard time selection  Supports auto inverse convention function  Supports UART mode  Full duplex, asynchronous communications  Supports programmable baud rate generator for each channel  Programmable transmitting data delay time between the last stop bit leaving the TX-FIFO and the de-assertion by setting SCnEGT register  Programmable even, odd or no parity bit generation and detection  Programmable stop bit, 1 or 2 stop bit generation ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 88 of 164 Rev 2.00 ML51/ML54/ML56 6.11 Serial Peripheral Interface (SPI) 6.11.1 Overview The ML51/ML54/ML56 Series provides two Serial Peripheral Interface (SPI) block to support highspeed serial communication. SPI is a full-duplex, high-speed, synchronous communication bus between microcontrollers or other peripheral devices such as serial EEPROM, LCD driver, or D/A converter. It provides either Master or Slave mode, high-speed rate up to FSYS/4, transfer complete and write collision flag. For a multi-master system, SPI supports Master Mode Fault to protect a multimaster conflict. 6.11.2 Features  2 sets of SPI devices  Supports Master or Slave mode operation  Supports MSB first or LSB first transfer sequence  Slave mode up to 12 Mhz ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 89 of 164 Rev 2.00 ML51/ML54/ML56 2 6.12 Inter-Integrated Circuit (I C) 6.12.1 Overview 2 The ML51/ML54/ML56 Series provides two Inter-Integrated Circuit (I C) bus to serves as an serial 2 interface between the microcontrollers and the I C devices such as EEPROM, LCD module, 2 temperature sensor, and so on. The I C bus used two wires design (a serial data line SDA and a serial clock line SCL) to transfer information between devices. 2 The I C bus uses bi-directional data transfer between masters and slaves. There is no central master and the multi-master system is allowed by arbitration between simultaneously transmitting masters. The serial clock synchronization allows devices with different bit rates to communicate via one serial 2 bus. The I C bus supports four transfer modes including master transmitter, master receiver, slave 2 receiver, and slave transmitter. The I C interface only supports 7-bit addressing mode. A special mode 2 General Call is also available. The I C can meet both standard (up to 100kbps) and fast (up to 400k bps) speeds. 6.12.2 Features 2 ML51/ML54/ML56 SERIES DATASHEET  2 sets of I C devices  Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  7-bit addressing mode  Standard mode (100 kbps) and Fast mode (400 kbps).  Supports 8-bit time-out counter requesting the I C interrupt if the I C bus hangs up and timer-out counter overflows  Multiple address recognition (four slave addresses with mask option)  Supports hold time programmable 2 Sep. 1, 2020 Page 90 of 164 2 Rev 2.00 ML51/ML54/ML56 6.13 12-bit Analog-to-digital Converter (ADC) 6.13.1 Overview The ML51/ML54/ML56 Series is embedded with a 12-bit SAR ADC. The ADC (analog-to-digital converter) allows conversion of an analog input signal to a 12-bit binary representation of that signal. The ML51/ML54/ML56 Series is selected as 8-channel inputs in single end mode. The internal bandgap voltage 0.814 V also can be the internal ADC input. The analog input, multiplexed into one sample and hold circuit, charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation and stores the result in the result registers. The ADC controller also supports DMA (direct memory access) function for ADC continuous conversion and storage result data into XRAM no need special enable PDMA module. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 91 of 164 Rev 2.00 ML51/ML54/ML56 6.14 Voltage Reference (VREF) The VREF pin is for analog multiplexer, such as ADC, ACMP. It default be used as an external source(set ENVRF = 0). It also could be configurable as on-chip reference voltage generator (VREF_IN) by setting ENVRF = 1. The output voltage is selectable by setting VRFSEL[2:0]. The maximum load of the VREF_IN must be less than 200 uA to AVSS. Set pre-load is to reduce stable time of VREF_IN. At first enable VREF_IN and turn on pre-load at the same time, the minimum stable time of pre-load on the VREF_IN must be greater than 3 ms. After the VREF_IN stable, user should be turn off pre-load to avoid any interference on analog multiplexer. Pre-load is only for internal VREF use. For detailed electrical characteristics ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 92 of 164 Rev 2.00 ML51/ML54/ML56 6.15 Analog Comparator Controller (ACMP) 6.15.1 Overview The ML51/ML54/ML56 Series contains two comparators. The comparator output is logic 1 when positive input is greater than negative input; otherwise, the output is 0. The comparator can be configured to generate an interrupt when the comparator output value changes. 6.15.2 Feature  Analog input voltage range: 0 ~ AVDD(voltage of AVDD pin)  Supports hysteresis function  Supports wake-up function  Selectable input sources of negative input  Comparator ACMP0 supports    P2.5 (ACMPn_P0)  P2.3 (ACMPn_P1)  P2.1 (ACMPn_P2)  P3.1 (ACMPn_P3) 4 negative sources  P2.4 (ACMP0_N0)  Comparator Reference Voltage (CRV)  VBG (BANDGAP voltage)  P2.0 (ACMP0_N1) ML51/ML54/ML56 SERIES DATASHEET  4 positive source Comparator ACMP1 supports   4 positive source  P2.5 (ACMPn_P0)  P2.3 (ACMPn_P1)  P2.1 (ACMPn_P2)  P3.1 (ACMPn_P3) 4 negative sources  P2.2 (ACMP1_N0)  Comparator Reference Voltage (CRV)  VBG (BANDGAP voltage)  P3.2 (ACMP1_N1) Sep. 1, 2020 Page 93 of 164 Rev 2.00 ML51/ML54/ML56 6.16 PDMA Controller (PDMA) 6.16.1 Overview The ML51/ML54/ML56 Series provides peripheral direct memory access (PDMA) controller. The PDMA controller is used to provide high-speed data transfer between memory and peripherals or between memory and memory. The PDMA controller can transfer data from one address to another without CPU intervention. This has the benefit of reducing the workload of CPU and keeps CPU resources free for other applications. 6.16.2 Feature  Supports transfer data width of 8 bits  Supports software and SPI and SMC/UART request  Supports source and destination address increment size can be byte  Supports transfer done and half done interrupt  Supports using PDMA to write data to perform CRC operation ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 94 of 164 Rev 2.00 ML51/ML54/ML56 6.17 LCD Driver 6.17.1 Overview The Liquid Crystal Displays (LCD) panel is widely used to meet the display need in applications. The ML54/ML56 series is equipped with LCD driver that can directly drive the LCD panel with 4 COM x 32 SEG , 6 COM x 30 SEG or 8 COM x 28 SEG. Use the corresponding COM and SEM according to the definition of multiple function pin. The LCD driver supports 1/4 duty, 1/6 duty, or 1/8 duty. The driving voltage supports 1/2 bias, 1/3 bias or 1/4 bias with waveform type A or Type B. The source of LCD clock is based on the choice of LIRC or LXT. The LCD display can keep display on or off during chip in power-down mode. The LCD power supply VLCD source is selectable from internal charge pump, external VLCD pin or analog power AVDD. 6.17.2 Features  1.8V to 5.5V LCD operating voltage.  Selectable LCD clock source from LIRC or LXT  1/2, 1/3, 1/4 bias selectable  Maximum 4 COM x 32 SEG, 6 COM x 30 SEG, 8 COM x 28 SEG  Supports buffer mode for high current driving  Support enhaced resistor mode for low power application  Support external VLCD source or AVDD as LCD voltage source.  Support programmable internal charge pump circuit for LCD voltage level is higher or lower than VDD application.  Support blink function.  Suppot display on or off during chip in power down mode ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 95 of 164 Rev 2.00 ML51/ML54/ML56 6.18 Real Time Clock (RTC) 6.18.1 Overview The Real Time Clock (RTC) controller provides the real time and calendar message. The RTC offers programmable time tick and alarm match interrupts. The data format of time and calendar messages are expressed in BCD format. A digital frequency compensation feature is available to compensate external crystal oscillator frequency accuracy. 6.18.2 Features  Supports real time counter and calendar counter for RTC time and calendar check.  Supports alarm time and calendar settings  Supports alarm time and calendar mask enable settings.  Selectable 12-hour or 24-hour time scale setting.  Supports Leap Year indication setting.  Supports Day of the Week counter setting.  Frequency of RTC clock source compensate by RTCFREQADJ0/1 register.  All time and calendar message expressed in BCD format.  Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second.  Supports RTC Time Tick and Alarm Match interrupt.  Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is generated. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 96 of 164 Rev 2.00 ML51/ML54/ML56 6.19 Touch Key (TK) 6.19.1 Overview The capacitive touch key sensing controller supports several programmable sensitivity levels for different applications to detect the finger touched or near the electrode covered by dielectric. It supports total 15 keys with single scan or programmable periodic key scans, and system can be waked up by any key for low power applications. 6.19.2 Features  Supports up to 14 touch keys + 1 reference  Supports any CLKO pin as shielding and any TK pin as reference.  Programmable sensitivity levels for each channel.  Programmable scanning speed for different applications.  Supports any touch key wake up for low power applications.  Supports single key scan and programmable periodic key scan.  Programmable interrupt options for key scan complete with/without threshold control. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 97 of 164 Rev 2.00 ML51/ML54/ML56 6.20 Auxiliary Features 6.20.1 Dual DPTRs The original 8051 contains one DPTR (data pointer) only. With single DPTR, it is difficult to move data form one address to another with wasting code size and low performance. The ML51/ML54/ML56 Series provides two data pointers. Thus, software can load both a source and a destination address when doing a block move. Once loading, the software simply switches between DPTR and DPTR1 by the active data pointer selection DPS (AUXR0.0) bit. An example of 64 bytes block move with dual DPTRs is illustrated below. By giving source and destination addresses in data pointers and activating cyclic makes block RAM data move more simple and efficient than only one DPTR. The INC AUXR0 instruction is the shortest (2 bytes) instruction to accomplish DPTR toggling rather than ORL or ANL. For AUXR0.1 contains a hard-wired 0, it allows toggling of the DPS bit by incrementing AUXR0 without interfering with other bits in the register. MOV MOV INC MOV LOOP: MOVX INC MOVX INC INC INC DJNZ INC R0,#64 DPTR,#D_Addr AUXR0 DPTR,#S_Addr ;number of bytes to move ;load destination address ;change active DPTR ;load source address A,@DPTR AUXR0 @DPTR,A DPTR AUXR0 DPTR R0,LOOP AUXR0 ;read source data byte ;change DPTR to destination ;write data to destination ;next destination address ;change DPTR to source ;next source address ;(optional) restore DPS ML51/ML54/ML56 SERIES DATASHEET AUXR0 also contains a general purpose flag GF2 in its bit 3 that can be set or cleared by the user via software. Sep. 1, 2020 Page 98 of 164 Rev 2.00 ML51/ML54/ML56 DPL – Data Pointer Low Byte Register SFR Address Reset Value DPL 82H, All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR[7:0] R/W Bit Name 7:0 DPTR[7:0] Description Data Pointer Low Byte This is the low byte of 16-bit data pointer. DPL combined with DPH serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory. DPS (AUXR0.0) bit decides which data pointer, DPTR or DPTR1, is activated. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 99 of 164 Rev 2.00 ML51/ML54/ML56 DPH – Data Pointer High Byte Register SFR Address Reset Value DPH 83H, All pages 0000_0000b 7 6 5 4 3 2 1 0 DPTR[15:8] R/W Bit Name 7:0 DPTR[15:8] Description Data Pointer High Byte This is the high byte of 16-bit data pointer. DPH combined with DPL serve as a 16-bit data pointer DPTR to access indirect addressed RAM or Program Memory. DPS (AUXR0.0) bit decides which data pointer, DPTR or DPTR1, is activated. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 100 of 164 Rev 2.00 ML51/ML54/ML56 AUXR0 – Auxiliary Register 0 Register SFR Address Reset Value POR: 0000 0000b, Software reset: 1U00 0000b, AUXR0 nRESET pin: U100 0000b, A2H , Page 0 Hard fault: UU10 0000b Others: UUU0 0000b 7 6 5 4 3 2 1 0 SWRF RSTPINF HardF HardFInt GF2 - 0 DPS R/W R/W R/W R/W R/W - R R/W Bit Name 3 GF2 Description General Purpose Flag 2 The general purpose flag that can be set or cleared by the user via software. 2 - Reserved 1 0 Reserved This bit is always read as 0. 0 DPS Data Pointer Select 0 = Data pointer 0 (DPTR) is active by default. After DPS switches the activated data pointer, the previous inactivated data pointer remains its original value unchanged. Sep. 1, 2020 Page 101 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 1 = Data pointer 1 (DPTR1) is active. ML51/ML54/ML56 6.20.2 96-Bit Unique Code (UID) Before shipping out, each ML51/ML54/ML56 Series chip was factory pre-programmed with a 96-bit width serial number, which is guaranteed to be unique for each piece of ML51/ML54/ML56 Series. The serial number is called Unique Code or UID. The user can read the Unique Code only by IAP command. More details please see Chapter 6.3 Flash Memory Control In-application-programming (IAP). IAPCN IAPA[15:0] IAP Mode 96-bit Unique Code read IAPB [1:0] FOEN FCEN FCTRL [3:0] XX 0 0 0100 {IAPAH, IAPAL} 0000H to 000BH IAPFD[7:0] Data out ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 102 of 164 Rev 2.00 ML51/ML54/ML56 6.21 Instruction Set 6.21.1 Instruction Set And Addressing Modes The ML51/ML54/ML56 Series executes all the instructions of the standard 80C51 family fully compatible with MCS-51. However, the timing of each instruction is different for it uses high performance 1T 8051 core. The architecture eliminates redundant bus states and implements parallel execution of fetching, decode, and execution phases. The ML51/ML54/ML56 Series uses one clock per machine-cycle. It leads to performance improvement of rate 8.1 (in terms of MIPS) with respect to traditional 12T 80C51 device working at the same clock frequency. However, the real speed improvement seen in any system will depend on the instruction mix. All instructions are coded within an 8-bit field called an OPCODE. This single byte should be fetched from Program Memory. The OPCODE is decoded by the CPU. It determines what action the CPU will take and whether more operation data is needed from memory. If no other data is needed, then only one byte was required. Thus the instruction is called a one byte instruction. In some cases, more data is needed, which is two or three byte instructions. Following lists all instructions for details. The note of the instruction set and addressing modes are shown below. Register R0 To R7 Of The Currently Selected Register Bank. Direct 8-bit internal data location’s address. It could be an internal data RAM location (00H to 7FH) or an SFR (80H to FFH). @RI (I = 0, 1) 8-bit internal data RAM location (00H to FFH) addressed indirectly through register R0 or R1. #data 8-bit constant included in the instruction. #data16 16-bit constant included in the instruction. Addr16 16-bit destination address. Used by LCALL and LJMP. A branch can be any-where within the Program Memory address space. Addr11 11-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K-Byte page of Program Memory as the first byte of the following instruction. Rel Signed (2’s complement) 8-bit offset Byte. Used by SJMP and all conditional branches. The range is -128 to +127 bytes relative to first byte of the following instruction. Bit Direct addressed bit in internal data RAM or SFR. Table 6.21-1 Instruction Set And Addressing Modes Sep. 1, 2020 Page 103 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET Rn (N = 0~7) ML51/ML54/ML56 Instruction CY OV AC Instruction CY ADD X[1] X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C, bit X MUL 0 X ANL C, /bit X DIV 0 X ORL C, bit X DA A X ORL C, /bit X RRC A X MOV C, bit X RLC A X CJNE X SETB C 1 OV AC Note: X indicates the modification depends on the result of the instruction. Table 6.21-2 Instructions Affect Flag Settings ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 104 of 164 Rev 2.00 ML51/ML54/ML56 6.21.2 Read-Modify-Write Instructions Instructions that read a byte from SFR or internal RAM, modify it, and rewrite it back, are called “ReadModify-Write” instructions. When the destination is an I/O port or a port bit, these instructions read the internal output latch rather than the external pin state. This kind of instructions read the port SFR value, modify it and write back to the port SFR. All “Read-Modify-Write” instructions are listed as follows. Instruction Description ANL Logical AND. (ANL direct, A and ANL direct, #data) ORL Logical OR. (ORL direct, A and ORL direct, #data) XRL #data) Logical exclusive OR. (XRL direct, A and XRL direct, JBC Jump if bit = 1 and clear it. (JBC bit, rel) CPL Complement bit. (CPL bit) INC Increment. (INC direct) DEC Decrement. (DEC direct) DJNZ Decrement and jump if not zero. (DJNZ direct, rel) MOV bit, C CLR bit Clear bit. (CLR bit) SETB bit Set bit. (SETB bit) Move carry to bit. (MOV bit, C) the entire port latch value, modify the changed bit, and then write the new value back to the port latch. 6.21.3 Instruction Set Instruction NOP OPCODE Bytes Clock Cycles ML51/ML54/ML56 Series V.S. Tradition 80C51 Speed Ratio 00 1 1 12 28~2F 1 2 6 ADD A, Rn ADD A, direct 25 2 3 4 ADD A, @Ri 26, 27 1 4 3 ADD A, #data 24 2 2 6 ADDC A, Rn 38~3F 1 2 6 ADDC A, direct 35 2 3 4 ADDC A, @Ri 36, 37 1 4 3 ADDC A, #data 34 2 2 6 SUBB A, Rn 98~9F 1 2 6 SUBB A, direct 95 2 3 4 SUBB A, @Ri 96, 97 1 4 3 SUBB A, #data 94 2 2 6 Sep. 1, 2020 Page 105 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET The last three seem not obviously “Read-Modify-Write” instructions but actually they are. They read ML51/ML54/ML56 Instruction INC A INC Rn INC OPCODE Bytes Clock Cycles ML51/ML54/ML56 Series V.S. Tradition 80C51 Speed Ratio ML51/ML54/ML56 SERIES DATASHEET 04 1 1 12 08~0F 1 3 4 direct 05 2 4 3 INC @Ri 06, 07 1 5 2.4 INC DPTR A3 1 1 24 DEC A 14 1 1 12 DEC Rn 18~1F 1 3 4 DEC direct 15 2 4 3 DEC @Ri 16, 17 1 5 2.4 MUL AB A4 1 4 12 DIV AB 84 1 4 12 DA A D4 1 1 12 ANL A, Rn 58~5F 1 2 6 ANL A, direct 55 2 3 4 ANL A, @Ri 56, 57 1 4 3 ANL A, #data 54 2 2 6 ANL direct, A 52 2 4 3 ANL direct, #data 53 3 4 6 ORL A, Rn 48~4F 1 2 6 ORL A, direct 45 2 3 4 ORL A, @Ri 46, 47 1 4 3 ORL A, #data 44 2 2 6 ORL direct, A 42 2 4 3 ORL direct, #data 43 3 4 6 XRL A, Rn 68~6F 1 2 6 XRL A, direct 65 2 3 4 XRL A, @Ri 66, 67 1 4 3 XRL A, #data 64 2 2 6 XRL direct, A 62 2 4 3 XRL direct, #data 63 3 4 6 CLR A E4 1 1 12 CPL A F4 1 1 12 RL A 23 1 1 12 RLC A 33 1 1 12 RR A 03 1 1 12 RRC A 13 1 1 12 SWAP A MOV A, Rn MOV MOV C4 1 1 12 E8~EF 1 1 12 A, direct E5 2 3 4 A, @Ri E6, E7 1 4 3 Sep. 1, 2020 Page 106 of 164 Rev 2.00 ML51/ML54/ML56 Instruction OPCODE Bytes Clock Cycles ML51/ML54/ML56 Series V.S. Tradition 80C51 Speed Ratio MOV A, #data 74 2 2 6 MOV Rn, A F8~FF 1 1 12 MOV Rn, direct A8~AF 2 4 6 MOV Rn, #data 78~7F 2 2 6 MOV direct, A MOV direct, Rn MOV F5 2 2 6 88~8F 2 3 8 direct, direct 85 3 4 6 MOV direct, @Ri 86, 87 2 5 4.8 MOV direct, #data 75 3 3 8 MOV @Ri, A F6, F7 1 3 4 MOV @Ri, direct A6, A7 2 4 6 MOV @Ri, #data 76, 77 2 3 6 MOV DPTR, #data16 90 3 3 8 MOVC A, @A+DPTR 93 1 4 6 MOVC A, @A+PC 83 1 4 6 MOVX A, @Ri[1] E2, E3 1 5 4.8 MOVX A, @DPTR[1] MOVX @Ri, A[1] MOVX 1 4 6 1 6 4 @DPTR, A[1] F0 1 5 4.8 PUSH direct C0 2 4 6 POP direct D0 2 3 8 XCH A, Rn C8~CF 1 2 6 XCH A, direct C5 2 3 4 XCH A, @Ri C6, C7 1 4 3 XCHD A, @Ri D6, D7 1 5 2.4 CLR C C3 1 1 12 CLR bit C2 2 4 3 SETB C D3 1 1 12 SETB bit D2 2 4 3 CPL C B3 1 1 12 CPL bit B2 2 4 3 ANL C, bit 82 2 3 8 ANL C, /bit B0 2 3 8 ORL C, bit 72 2 3 8 ORL C, /bit A0 2 3 8 MOV C, bit A2 2 3 4 MOV bit, C 92 2 4 6 2 4 6 ACALL addr11 11, 31, 51, 71, 91, B1, D1, F1[2] LCALL addr16 12 3 4 6 22 1 5 4.8 RET Sep. 1, 2020 Page 107 of 164 ML51/ML54/ML56 SERIES DATASHEET E0 F2, F3 Rev 2.00 ML51/ML54/ML56 Instruction RETI OPCODE Bytes Clock Cycles ML51/ML54/ML56 Series V.S. Tradition 80C51 Speed Ratio 32 1 5 4.8 AJMP addr11 01, 21, 41, 61, 81, A1, C1, E1[3] 2 3 8 LJMP addr16 02 3 4 6 SJMP rel 80 2 3 8 JMP @A+DPTR 73 1 3 8 JZ rel 60 2 3 8 JNZ rel 70 2 3 8 JC rel 40 2 3 8 JNC rel 50 2 3 8 JB bit, rel 20 3 5 4.8 JNB bit, rel 30 3 5 4.8 JBC bit, rel 10 3 5 4.8 CJNE A, direct, rel B5 3 5 4.8 CJNE A, #data, rel B4 3 4 6 CJNE Rn, #data, rel B8~BF 3 4 6 CJNE @Ri, #data, rel B6, B7 3 6 4 DJNZ Rn, rel D8~DF 2 4 6 DJNZ direct, rel D5 3 5 4.8 ML51/ML54/ML56 SERIES DATASHEET Note: 1. The ML51/ML54/ML56 Series does not have external memory bus. MOVX instructions are used to access internal XRAM. 2. The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be [A10, A9, A8, 1, 0, 0, 0, 1]. 3. The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be [A10, A9, A8, 0, 0, 0, 0, 1]. Table 6.21-3 Instruction Set Sep. 1, 2020 Page 108 of 164 Rev 2.00 ML51/ML54/ML56 7 APPLICATION CIRCUIT 7.1 Power Supply Scheme EXT_PWR For external VREF source from VDD only Way 1 as close to VREF as possible L=30S VREF Way 2 1uF 10uF+0.1uF For internal VREF only ML51 Series as close to the EXT_PWR as possible VDD VSS EXT_VSS 0.1uF*N as close to VDD as possible ® Figure 7.1-1 NuMicro ML51/ML54/ML56 Series Power supply circuit ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 109 of 164 Rev 2.00 ML51/ML54/ML56 7.2 Peripheral Application Scheme DVCC DVCC SPI_SS SPI_CLK SPI_MISO SPI_MOSI ICE / ICP Interface 100K 100K CS VDD CLK MISO MOSI VSS SPI Device VDD 100 100 ICE_CLK DVCC DVCC VSS 4.7K 4.7K XT1_IN 20pF 4~24 MHz crystal 20pF I2C_SCL CLK VDD I2C_SDA DIO VSS I2C Device XT1_OUT ML51 Series Crystal X32_IN 20pF RS 232 Transceiver 32.768 kHz crystal 20pF X32_OUT UART_RXD ROUT UART_TXD TIN RIN PC COM Port DVCC DH1 10K 0.1uF nRST ML51/ML54/ML56 SERIES DATASHEET Reset Circuit UART TOUT 10 uF VLCD Source DH2 VLCD 1uF LCD Note 1: It is recommended to use 100 kΩ pull-up resistor on both ICE_DAT and ICE_CLK pin. 2: It is recommended to use 10 kΩ pull-up resistor and 10 uF capacitor on nRESET pin. 3: It is suggest add 100ohm series resistor between ICE_DAT/ICE_CLK and writer pin to filter the disturb of noise on the circuit. ® Figure 7.2-1 NuMicro ML51/ML54/ML56 Series Peripheral interface circuit Sep. 1, 2020 Page 110 of 164 Rev 2.00 ML51/ML54/ML56 8 ELECTRICAL CHARACTERISTICS Please refer to the relative Datasheet for detailed information about the ML51/ML54/ML56 series electrical characteristics. 8.1 General Operating Conditions (VDD-VSS = 1.8 ~ 5.5V, TA = 25C, Fsys = 24 MHz unless otherwise specified.) 8.1.1 ML51 32KB/16KB Flash Series Symbol Parameter Min Typ Max Unit ℃ TA Temperature -40 - 105 VDD Operation voltage 1.8 - 5.5 AVDD[1] Test Conditions V Analog operation voltage VDD Note: 1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between V DD and AVDD can be tolerated during power-on and power-off operation . 2. Based on characterization, tested in production. Table 8.1-1 ML51 32KB/16KB Flash Series General Operating Conditions 8.1.2 ML51 64KB Flash/ML54/ML56 Series Symbol Parameter Min Typ Max Unit ℃ TA Temperature -40 - 105 VDD Operation voltage 1.8 - 3.6 V Analog operation voltage VDD Note: 1. It is recommended to power VDD and AVDD from the same source. A maximum difference of 0.3V between V DD and AVDD can be tolerated during power-on and power-off operation . 2. Based on characterization, tested in production. Table 8.1-2 ML56/ML54/ML51 64KB Flash Series General Operating Conditions Sep. 1, 2020 Page 111 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET AVDD[1] Test Conditions ML51/ML54/ML56 8.2 DC Electrical Characteristics 8.2.1 Supply Current Characteristics The current consumption is a combination of internal and external parameters and factors such as operating frequencies, device software configuration, I/O pin loading, I/O pin switching rate, program location in memory and so on. The current consumption is measured as described in below condition and table to inform test characterization result. 8.2.1.1 ML51 32KB/16KB Flash Series      All GPIO pins are in push pull mode and output high. The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient temperature (TA), and the typical values for T A= 25 °C and VDD = 3.3 V unless otherwise specified. VDD = AVDD When the peripherals clock base is the system clock Fsys. Program run “while (1);” in flash. Normal Run Mode Typ [6] Symbol Conditions Fsys Unit TA = 25 °C ML51/ML54/ML56 SERIES DATASHEET Normal run mode, executed from Flash, all peripherals disable Max[6][7] TA = 25 °C TA = 85 °C TA = 105 °C 24 MHz (HIRC)[1] 2.40 2.64 2.87 2.90 24 MHz (HXT) [2][5] 2.52 2.97 3.10 3.16 12 MHz (HXT) [2][5] 1.56 2.04 2.13 2.20 4 MHz (HXT) [2][5] 0.91 1.33 1.39 1.43 38.4 kHz (LIRC)[3] 0.22 0.29 0.32 0.35 32.768 kHz (LXT)[4] 0.24 0.30 0.32 0.35 24 MHz (HIRC)[1] 3.50 3.78 3.86 3.89 24 MHz (HXT) [2][5] 3.62 4.11 4.24 4.31 12 MHz (HXT) [2][5] 2.26 2.74 2.83 2.92 4 MHz (HXT) [2][5] 1.30 1.74 1.81 1.83 38.4 kHz (LIRC)[3] 0.37 0.57 0.59 0.61 32.768 kHz (LXT)[4] 0.40 0.58 0.60 0.62 IDD_RUN mA Normal run mode, executed from Flash, all peripherals enable Notes: 1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable 2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable 3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable Sep. 1, 2020 Page 112 of 164 Rev 2.00 ML51/ML54/ML56 Typ [6] Symbol Conditions Fsys Unit TA = 25 °C 4. 5. 6. 7. Max[6][7] TA = 25 °C TA = 85 °C TA = 105 °C This value base on HIRC disable, HXT disable, LIRC enable, LXT enable Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable. Based on characterization, not tested in production unless otherwise specified. Table 8.2-1 ML51 32KB / 16KB Series Current Consumption In Normal Run Mode Low Power Run Mode Typ [3] Symbol Conditions Unit TA = 25 °C Low power run mode, executed from Flash, all peripherals disable Max[3][4] Fsys TA = 25 °C TA = 85 °C TA = 105 °C 38.4 kHz (LIRC)[1] 15 21 42 66 32.768 kHz (LXT)[2] 19 23 44 67 38.4 kHz (LIRC)[1] 193 307 320 344 32.768 kHz (LXT)[2] 194 308 321 345 IDD_LPRUN µA Low power run mode, executed from Flash, all peripherals enable Notes: 1. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable 2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable 3. Based on characterization, not tested in production unless otherwise specified. 4. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD disable. Idle Mode Typ [6] Symbol Conditions Unit TA = 25 °C Idle mode, all peripherals disable Max[6][7] Fsys TA = 25 °C TA = 85 °C TA = 105 °C 24 MHz (HIRC)[1] 1.43 1.58 1.62 1.64 24 MHz (HXT) [2][5] 1.52 1.91 2.00 2.05 12 MHz (HXT) [2][5] 1.07 1.44 1.50 1.56 4 MHz (HXT) [2][5] 0.76 1.10 1.15 1.19 IDD_IDLE mA Idle mode, all peripherals enable Sep. 1, 2020 38.4 kHz (LIRC)[3] 0.20 0.30 0.32 0.35 32.768 kHz (LXT)[4] 0.22 0.32 0.34 0.36 24 MHz (HIRC)[1] 2.46 2.72 2.78 2.80 24 MHz (HXT) [2][5] 2.55 3.04 3.15 3.19 Page 113 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET Table 8.2-2 ML51 32KB/16KB Flash Series Current Consumption In Low Power Run Mode ML51/ML54/ML56 Typ [6] Symbol Conditions Max[6][7] Fsys Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C 12 MHz (HXT) [2][5] 1.67 2.14 2.22 2.26 4 MHz (HXT) [2][5] 1.08 1.51 1.57 1.60 38.4 kHz (LIRC)[3] 0.37 0.57 0.60 0.61 32.768 kHz (LXT)[4] 0.38 0.59 0.61 0.62 Notes: 1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable 2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable 3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable 4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable 5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values 6. Based on characterization, not tested in production unless otherwise specified. 7. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable. Table 8.2-3 ML51 32KB/16KB Flash Series Current Consumption In Idle Mode Low Power Idle Mode Typ [3] Symbol Conditions Fsys Unit TA = 25 °C ML51/ML54/ML56 SERIES DATASHEET Low power idle mode, executed from Flash, all peripherals disable Max[3][4] TA = 25 °C TA = 85 °C TA = 105 °C 38.4 kHz (LIRC)[1] 13 19 40 63 32.768 kHz (LXT)[2] 15 20 41 65 IDD_LPIDLE µA Low power idle mode, executed from Flash, all peripherals enable 38.4 kHz (LIRC)[1] 173 304 317 341 32.768 kHz (LXT)[2] 174 306 319 342 Notes: 1. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable 2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable 3. Based on characterization, not tested in production unless otherwise specified. 4. AVDD = VDD = 3.3V , LVR17 enabled, POR enable and BOD enable. Table 8.2-4 ML51 32KB/16KB Flash Series Current Consumption In Low Power Idle Mode Sep. 1, 2020 Page 114 of 164 Rev 2.00 ML51/ML54/ML56 Power Down Mode Typ[1] Symbol IDD_PD Max[2][3] Test Conditions Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Power down mode, all peripherals disable@3.3V 0.8 1.6[4] 18 34 Power down mode, all peripherals disable@5.5V 1.6 2.5 25 50 Power down mode, LVR enable all other peripherals disable 1.4 3.2 19 36 Power down mode, LVR enable BOD enable all other peripherals disable 60 80 70 100 Power down mode, WDT / WKT enable all use LIRC, BOD disable 2.87 5.2 21 37 Power down mode, WDT use LIRC, WKT use LXT, BOD disable 2.42 4.2 20 38 µA Notes: 1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 enabled, POR disabled and BOD disabled. 2. Based on characterization, not tested in production unless otherwise specified. 3. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be considered. 4. Based on characterization, tested in production. Table 8.2-5 ML51 32KB/16KB Flash Series Chip Current Consumption in Power down mode ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 115 of 164 Rev 2.00 ML51/ML54/ML56 8.2.1.2 ML51 64KB Flash/ML54/ML56 Series      All GPIO pins are in push pull mode and output high. The maximum values are obtained for VDD = 1. 8V ~ 3.6 V and maximum ambient temperature (TA), and the typical values for T A= 25 °C and VDD = 3.3 V unless otherwise specified. VDD = AVDD When the peripherals clock base is the system clock Fsys. Program run “while (1);” in flash. Normal Run Mode Typ [6] Symbol Conditions Unit TA = 25 °C Normal run mode, executed from Flash, all peripherals disable Max[6][7] Fsys TA = 25 °C TA = 85 °C TA = 105 °C ML51/ML54/ML56 SERIES DATASHEET 24 MHz (HIRC)[1] 2.86 3.67 3.92 4.15 12 MHz (HIRC)[1] 1.98 2.37 2.6 2.89 1 MHz (HIRC)[1] 0.91 1.14 1.2 1.32 24 MHz (HXT) [2][5] 2.94 3.76 4.02 4.23 12 MHz (HXT) [2][5] 2.08 2.47 2.7 2.98 1 MHz (HXT) [2][5] 0.96 1.2 1.3 1.48 38.4 kHz (LIRC)[3] 0.23 0.32 0.34 0.39 32.768 kHz (LXT)[4] 0.25 0.35 0.37 0.42 24 MHz (HIRC)[1] 4.50 4.78 4.86 4.89 12 MHz (HIRC)[1] 2.8 3.4 3.6 3.98 1 MHz (HIRC)[1] 1.17 1.45 1.6 1.75 24 MHz (HXT) [2][5] 4.9 5.21 5.46 5.89 12 MHz (HXT) [2][5] 2.67 3.12 3.33 3.69 1 MHz (HXT) [2][5] 1.21 1.49 1.75 1.83 38.4 kHz (LIRC)[3] 0.41 0.61 0.67 0.72 32.768 kHz (LXT)[4] 0.42 0.62 0.69 0.73 IDD_RUN mA Normal run mode, executed from Flash, all peripherals enable Notes: 1. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable Sep. 1, 2020 Page 116 of 164 Rev 2.00 ML51/ML54/ML56 Typ [6] Symbol Conditions Max[6][7] Fsys Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C 2. This value base on HIRC disable, HXT enable, LIRC enable, LXT disable 3. This value base on HIRC disable, HXT disable, LIRC enable, LXT disable 4. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable 5. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values 6. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable. 7. Based on characterization, not tested in production unless otherwise specified. Table 8.2-6 ML56/ML54/ML51 64KB Flash Series Current Consumption In Normal Run Mode Low Power Run Mode Typ [3] Symbol Conditions Fsys Unit TA = 25 °C Low power run mode, executed from Flash, all peripherals disable Max[3][4] TA = 25 °C TA = 85 °C TA = 105 °C 38.4 kHz (LIRC)[1] 19 29 52 83 32.768 kHz (LXT)[2] 21 32 55 85 IDD_LPRUN µA Low power run mode, executed from Flash, all peripherals enable 38.4 kHz (LIRC)[1] 223 314 327 351 32.768 kHz (LXT)[2] 230 326 339 362 Notes: This value base on HIRC disable, HXT disable, LIRC enable, LXT disable 2. This value base on HIRC disable, HXT disable, LIRC enable, LXT enable 3. Based on characterization, not tested in production unless otherwise specified. 4. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD disable. Table 8.2-7 ML56/ML54/ML51 64KB Flash Series Current Consumption In Low Power Run Mode Idle Mode Typ [6] Symbol Conditions Fsys Unit TA = 25 °C IDD_IDLE Idle mode, all peripherals disable Sep. 1, 2020 Max[6][7] TA = 25 °C TA = 85 °C TA = 105 °C 24 MHz (HIRC)[1] 1.8 2.25 2.43 2.46 24 MHz (HXT) [2][5] 1.74 1.91 2.00 2.05 12 MHz (HXT) [2][5] 1.07 1.44 1.50 1.56 mA 4 MHz (HXT) [2][5] 0.97 1.10 1.15 1.19 38.4 kHz (LIRC)[3] 0.20 0.30 0.32 0.35 32.768 kHz (LXT)[4] 0.22 0.32 0.34 0.36 Page 117 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET 1. ML51/ML54/ML56 Typ [6] Symbol Conditions Fsys Unit TA = 25 °C Idle mode, all peripherals enable Max[6][7] TA = 25 °C TA = 85 °C TA = 105 °C 24 MHz (HIRC)[1] 2.46 2.72 2.78 2.80 24 MHz (HXT) [2][5] 2.55 3.04 3.15 3.19 12 MHz (HXT) [2][5] 1.67 2.14 2.22 2.26 4 MHz (HXT) [2][5] 1.08 1.51 1.57 1.60 38.4 kHz (LIRC)[3] 0.37 0.57 0.60 0.61 32.768 kHz (LXT)[4] 0.38 0.59 0.61 0.62 Notes: 1. 2. 3. 4. 5. 6. 7. This value base on HIRC enable, HXT disable, LIRC enable, LXT enable This value base on HIRC disable, HXT enable, LIRC enable, LXT disable This value base on HIRC disable, HXT disable, LIRC enable, LXT disable This value base on HIRC disable, HXT disable, LIRC enable, LXT enable Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values Based on characterization, not tested in production unless otherwise specified. AVDD = VDD = 3.3V, LVR17 enabled, POR enable and BOD enable. Table 8.2-8 ML56/ML54/ML51 64KB Flash Series Current Consumption In Idle Mode Low Power Idle Mode Typ [3] ML51/ML54/ML56 SERIES DATASHEET Symbol Conditions Low power idle mode, executed from Flash, all peripherals disable IDD_LPIDLE TA = 25 °C Max[3][4] TA = 25 °C TA = 85 °C TA = 105 °C 38.4 kHz (LIRC)[1] 17 27 50 81 32.768 kHz (LXT)[2] 22 32 55 87 38.4 kHz (LIRC)[1] 213 302 317 340 32.768 kHz (LXT)[2] 220 312 320 342 Unit µA Low power idle mode, executed from Flash, all peripherals enable Notes: 5. 6. 7. 8. Fsys This value base on HIRC disable, HXT disable, LIRC enable, LXT disable This value base on HIRC disable, HXT disable, LIRC enable, LXT enable Based on characterization, not tested in production unless otherwise specified. AVDD = VDD = 3.3V , LVR17 enabled, POR enable and BOD enable. Table 8.2-9 ML56/ML54/ML51 64KB Flash Series Current consumption in Low Power Idle mode Power Down Mode Typ[1] Symbol Max[2][3] Test Conditions Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Power down mode, all peripherals disable@3.3V 1.2 1.6[4] 20 37 Power down mode, all peripherals disable@5.5V 1.7 2.6 27 47 IDD_PD µA Sep. 1, 2020 Page 118 of 164 Rev 2.00 ML51/ML54/ML56 Typ[1] Symbol Max[2][3] Test Conditions Unit TA = 25 °C TA = 25 °C TA = 85 °C TA = 105 °C Power down mode, LVR enable all other peripherals disable 1.7 3.2 25 42 Power down mode, LVR enable, Low power BOD enable all other peripherals disable 4.8 10 52 69 Power down mode, LVR enable BOD enable all other peripherals disable 61 82 98 110 Power down mode, WDT / WKT enable all use LIRC, BOD disable 3 6.4 44 52 Power down mode, WDT use LIRC, WKT use LXT, BOD disable 3.5 7.2 48 68 Power-down mode, RTC use LIRC, BOD disable, HIRC off / HXT off / LIRC on / LXT off 2.9 5.9 32 49 Power-down mode, RTC/TK use LIRC, BOD disable, HIRC off / HXT off / LIRC on / LXT off 3.4 6.8 42 56 Power-down mode, RTC use LXT, BOD disable, HIRC off / HXT off / LIRC off / LXT on 3.9 7.3 48 77 Notes: 1. AVDD = VDD = 3.3V unless otherwise specified, LVR17 enabled, POR disabled and BOD disabled. 2. Based on characterization, not tested in production unless otherwise specified. 3. When analog peripheral blocks such as ADC and ACMP are ON, an additional power consumption should be considered. 4. Based on characterization, tested in production. Table 8.2-10 ML56/ML54/ML51 64KB Flash Series Series Chip Current Consumption In Power Down Mode ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 119 of 164 Rev 2.00 ML51/ML54/ML56 8.2.2 On-Chip Peripheral Current Consumption  The typical values for TA= 25 °C and VDD = AVDD = 3.3 V unless otherwise specified.  All GPIO pins are set as output high of push pull mode without multi-function.  The system clock = 24 MHz.  The result value is calculated by measuring the difference of current consumption between all peripherals clocked off and only one peripheral clocked on Peripheral IDD[1] IDD Base ADC[2] Unit 309.2 [3] ACMP0 1.0 ACMP1[3] 1.1 PWM0 152.3 SPI0 40.2 SPI1 44.2 UART0 1 98.8 UART1 1 I2C0 1 118.7 I2C1 1 SC0 67.8 PIN Interrupt 0.2 TIMER 0 4.1 ML51/ML54/ML56 SERIES DATASHEET TIMER 1 3.9 145 TIMER 2 4.4 TIMER 3 10 INT0 0.3 INT1 0.3 WDT 0.4 WKT 0.7 PDMA0 µA 0.5 PDMA1 0.5 13.4 PDMA2 0.5 PDMA3 0.5 CAPTURE0 0.5 CAPTURE1 145 0.3 CAPTURE2 0.5 RTC 1 LCD 23 Sep. 1, 2020 Page 120 of 164 Rev 2.00 ML51/ML54/ML56 Peripheral IDD Base IDD[1] Unit Notes: 1. Guaranteed by characterization results, not tested in production. 2. When the ADC is turned on, add an additional power consumption per ADC for the analog part. 3. When the ACMP is turned on, add an additional power consumption per ACMP for the analog part. Table 8.2-11 Peripheral Current Consumption ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 121 of 164 Rev 2.00 ML51/ML54/ML56 8.2.3 Wakeup Time from Low-Power Modes The wakeup times given in Table 8.2-12 Low-Power Mode Wakeup Timings is measured on a wakeup phase with a 24 MHz HIRC oscillator. Symbol tWU_IDLE Parameter Typ Max Unit 5 6 cycles Fsys = HIRC @5.5V 7 20 µs Fsys = HIRC @3.6V 10 20 µs Wakeup from IDLE mode Fsys = HIRC @1.8V tWU_NPD[1][2] Wakeup from Power down mode 13 20 µs [3] 370 - µs Fsys = HXT@24MHz @3.6V[3] 440 - [3] 600 - µs 938 1500 µs 860 - µs Fsys = HXT@24MHz @5.5V Fsys = HXT@24MHz @1.8V Fsys = LIRC [4] Fsys = LXT@32.768KHz Notes: 1. Based on test during characterization, not tested in production. 2. The wakeup times are measured from the wakeup event to the point in which the application code reads the first 3. Value variable based on extnerl Crystal stable time. 4 Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values, LXT not disabled when ML51/ML54/ML56 Series into Power down mode. Table 8.2-12 Low-Power Mode Wakeup Timings ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 122 of 164 Rev 2.00 ML51/ML54/ML56 8.2.4 8.2.4.1 I/O DC Characteristics PIN Input Characteristics Symbol Parameter VIL Input low voltage VIL1 Input low voltage (I/O with TTL input) VIH Input high voltage Min Typ Max Unit 0 - 0.3*VDD V VSS-0.3 - 0.2VDD-0.1 V 0.2VDD+0.9 - VDD+0.3 V 0.7*VDD - VDD V - 0.2*VDD - V Test Conditions Input high voltage VIH1 (I/O with Schmitt trigger input and Xin) VHY[1] Hysteresis voltage of schmitt input ILK[2] VSS < VIN < VDD, Open-drain or input only mode -1 1 -1 1 VDD < VIN < 5.5 V, Open-drain or input only mode VDD = 5.5 V, Quasi mode and Input mode with pull up enable A Input leakage current 40 - 60 40 - 60 VDD = 3.3 V, Quasi mode and Input mode with pull up enable 40 - 70 VDD = 1.8 V, Quasi mode and Input mode pull up enable 40 - 60 40 - 60 VDD = 3.3 V, Quasi mode and Input mode with pull up enable 40 - 70 VDD = 1.8 V, Quasi mode and Input mode pull up enable kΩ RPU[1] [3] Pull up resistor VDD = 5.5 V, Quasi mode and Input mode with pull up enable Notes: 1. Guaranteed by characterization result, not tested in production. 2. Leakage could be higher than the maximum value, if abnormal injection happens. 3. To sustain a voltage higher than VDD +0.3 V, the internal pull-up resistors must be disabled. Leakage could be higher than the maximum value, if positive current is injected on adjacent pins 4. Test condition of VDD is base on the maximum value of VDD Table 8.2-13I/O Input Characteristics Sep. 1, 2020 Page 123 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET RPD[1] [3] Pull down resistor kΩ ML51/ML54/ML56 8.2.4.2 nRESET Input Characteristics Symbol Parameter Min Typ Max Unit Test Conditions VILR Negative going threshold, nRESET - - 0.3*VDD V VIHR Positive going threshold, nRESET 0.7*VDD - - V 45 - 60 VDD = 5.5 V 45 - 60 KΩ VDD = 3.6 V 50 - 65 VDD = 1.8 V - 1.5 - RRST[1] tFR[1] Internal nRESET pull up resistor nRESET input response time Normal run and Idle mode µs 10 - 25 Power down mode Notes: 1. Guaranteed by characterization result, not tested in production. 2. It is recommended to add a 10 kΩ and 10uF capacitor at nRESET pin to keep reset signal stable. Table 8.2-14 nRESET Input Characteristics ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 124 of 164 Rev 2.00 ML51/ML54/ML56 8.3 AC Electrical Characteristics The maximum values are obtained for VDD = 1.8 V ~ 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. VDD = AVDD. 8.3.1 24 MHz Internal High Speed RC Oscillator (HIRC) The 24 MHz RC oscillator is calibrated in production. Symbol. VDD Parameter Operating voltage Oscillator frequnecy Min Typ Max Unit 1.8 - 5.5 V 23.76 24 24.24 MHz -1[1] - 1[1] % -2[2] - 2[2] % 5[2] % Test Conditions TA = 25 °C, VDD = 5V TA = 25 °C, VDD = 3.3V FHRC Frequency drift over temperarure and volatge -5[2] IHRC[2] Operating current - 490 550 µA TS[3] Stable time - 3 5 µs TA = -20C ~ +105 °C, VDD = 1.8 ~ 5.5V TA = -40C ~ -20°C, VDD = 1.8 ~ 5.5V TA = -40C ~ +105 °C, VDD = 1.8 ~ 5.5V Notes: 1. Based on characterization, tested in production. 2. Guaranteed by characterization result, not tested in production. 3. Guaranteed by design. ML51/ML54/ML56 SERIES DATASHEET Table 8.3-1 24 MHz Internal High Speed RC Oscillator(HIRC) Characteristic Sep. 1, 2020 Page 125 of 164 Rev 2.00 ML51/ML54/ML56 8.3.2 38.4 kHz Internal Low Speed RC Oscillator (LIRC) Symbol VDD Parameter Min Typ Max Unit 1.8 - 5.5 V - 38.4 - kHz -2[1] - 2[1] % TA = 25 °C, VDD = 5V -10[2] - 10[2] % TA=-40~105°C VDD=1.8V~5.5V Without software calibration Operating current - 0.85 1 µA VDD = 3.3V Stable time - 500 - μs Operating voltage Oscillator frequnecy FLRC ILRC [2] TS Frequency drift over temperarure and volatge Test Conditions TA=-40~105°C VDD=1.8V~5.5V Notes: 1. Guaranteed by characterization, tested in production. 2. Guaranteed by characterization, not tested in production. 3. The 38.4 kHz low speed RC oscillator can be calibrated by user. 4. Guaranteed by design. Table 8.3-2 38.4 kHz Internal Low Speed RC Oscillator(LIRC) Characteristics ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 126 of 164 Rev 2.00 ML51/ML54/ML56 8.3.3 External 4~24 MHz High Speed Crystal/Ceramic Resonator (HXT) characteristics The high-speed external (HXT) clock can be supplied with a 4 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the XT1_IN and XT1_Out pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Min[1] Typ Max[1] Unit 1.8 - 5.5 V Internal feedback resister - 500 - kΩ Oscillator frequency 4 - 24 MHz - 80 180 4 MHz, Gain = L0 - 110 300 8 MHz, Gain = L1 - 180 500 - 230 650 16 Mhz, Gain = L3 - 360 975 24 MHz, Gain = L4 - 3500 - 4 MHz, Gain = L0 - 950 - 8 MHz, Gain = L1 - 700 - - 450 - 16 Mhz, Gain = L3 - 400 - 24 MHz, Gain = L4 40 - 60 Symbol VDD Rf fHXT IHXT TS Operating voltage Current consumption Stable time [3] Duty cycle µA µs Test Conditions[2] 12 MHz, Gain = L2 12 MHz, Gain = L2 % Notes: 1. Guaranteed by characterization, not tested in production. 2. L0 ~ L4 defined by SFR XLTCON[6:4] HXSG 3. Value variable based on extnerl Crystal stable time. Table 8.3-3 External 4~24 MHz High Speed Crystal (HXT) Oscillator Typical Crystal Application Circuits For C1 and C2, it is recommended to use high-quality external ceramic capacitors in 10 pF ~ 25 pF range, designed for high-frequency applications, and selected to match the requirements of the crystal or resonator. The crystal manufacturer typically specifies a load capacitance which is the series combination of C1 and C2. PCB and MCU pin capacitance must be included (8 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing C1 and C2. Sep. 1, 2020 CRYSTAL C1 C2 R1 4 MHz ~ 24 MHz 10 ~ 25 pF 10 ~ 25 pF without Page 127 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET DuHXT Parameter ML51/ML54/ML56 XT1_OUT C2 XT1_IN R1 C1 Table 8.3-4 Typical Crystal Application ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 128 of 164 Rev 2.00 ML51/ML54/ML56 8.3.4 External 4~24 MHz High Speed Clock Input Signal Characteristics For clock input mode the HXT oscillator is switched off and XT1_IN is a standard input pin to receive external clock. The external clock signal has to respect the below Table. The characteristics result from tests performed using a wavefrom generator. Symbol fHXT_ext Parameter External user clock source frequency Min [1] Typ Max [1] Unit 4 - 24 MHz Test Conditions tCHCX Clock high time 8 - - ns tCLCX Clock low time 8 - - ns tCLCH Clock rise time - - 10 ns Low (10%) to high level (90%) rise time tCHCL Clock fall time - - 10 ns High (90%) to low level (10%) fall time 40 - 60 % DuE_HXT Duty cycle VIH Input high voltage 0.7*VDD - VDD V VIL Input low voltage VSS - 0.3*VDD V External clock source XT1_IN tCLCL VIH VIL ML51/ML54/ML56 SERIES DATASHEET tCLCH 90% tCLCX 10% tCHCL tCHCX Notes: 1. Guaranteed by characterization, not tested in production. Table 8.3-5 External 4~24 MHz High Speed Clock Input Signal Sep. 1, 2020 Page 129 of 164 Rev 2.00 ML51/ML54/ML56 8.3.5 External 32.768 kHz Low Speed Crystal/Ceramic Resonator (LXT) characteristics The low-speed external (LXT) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this secion are based on characterization results obtained with typical external components. In the application, the external components have to be placed as close as possible to the X32_OUT and X32_IN pins and must not be connected to any other devices in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Symbol Parameter Min [1] Typ Max [1] Unit VDD Operation voltage 1.8 - 5.5 V TLXT Temperature range -40 - 105 C - 6 - MΩ Rf Internal feedback resistor FLXT Oscillator frequency ILXT Current consumption TsLXT Stable time DuLXT Duty cycle Rs 32.768 [3] Equivalnet Series Resisotr(ESR) Test Conditions[2] kHz - 1.3 3.7 - 1.6 6 - 2 - s 30 - 70 % - 35 70 kΩ A ESR=35 kΩ, Gain = L2 ESR=70 kΩ, Gain = L3 Crystal @32.768 kHz Notes: 1. Guaranteed by characterization, not tested in production. 2. L1 ~ L2 defined by SFR XLTCON[1:0] LXSG 3. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values, Value variable based on extnerl Crystal stable time. ML51/ML54/ML56 SERIES DATASHEET Table 8.3-6 External 32.768 kHz Low Speed Crystal (LXT) Oscillator Characteristics Typical Crystal Application Circuits CRYSTAL 32.768 kHz, ESR < 70 KΩ C1 C2 R1 20 pF 20 pF without X32_OUT C2 X32_IN R1 C1 Table 8.3-7 Typical 32.768 kHz Crystal Application Circuit Sep. 1, 2020 Page 130 of 164 Rev 2.00 ML51/ML54/ML56 8.3.6 I/O AC Characteristics Symbol tf(IO)out tf(IO)out tr(IO)out fmax(IO)out[3] Normal mode [4] output high (90%) to low level (10%) falling time High slew rate mode [5] output high (90%) to low level (10%) falling time Normal mode [4] output low (10%) to high level (90%) rising time High slew rate mode [5] output low (10%) to high level (90%) rising time Typ. Max[1]. 4.6 5.1 CL = 30 pF, VDD >= 5.5 V 2.9 3.3 CL = 10 pF, VDD >= 5.5 V 6.6 8 Unit Test Conditions[2] CL = 30 pF, VDD >= 3.3 V ns 4.3 5 CL = 10 pF, VDD >= 3.3 V 8.5 12.5 CL = 30 pF, VDD >= 1.8 V 8.0 10.7 CL = 10 pF, VDD >= 1.8 V 4.0 4.3 CL = 30 pF, VDD >= 5.5 V 2.1 2.5 CL = 10 pF, VDD >= 5.5 V 4.9 5.8 CL = 30 pF, VDD >= 3.3 V ns 3.0 3.7 CL = 10 pF, VDD >= 3.3 V 9.5 13.8 CL = 30 pF, VDD >= 1.8 V 5.4 7.4 CL = 10 pF, VDD >= 1.8 V 5.6 6.1 CL = 30 pF, VDD >= 5.5 V 3.4 3.7 CL = 10 pF, VDD >= 5.5 V 8.1 9.4 CL = 30 pF, VDD >= 3.3 V ns 5.1 5.8 CL = 10 pF, VDD >= 3.3 V 15.1 20.3 CL = 30 pF, VDD >= 1.8 V 9.6 12.4 CL = 10 pF, VDD >= 1.8 V 4.8 5.2 CL = 30 pF, VDD >= 5.5 V 2.1 2.5 CL = 10 pF, VDD >= 5.5 V 6.4 7.4 CL = 30 pF, VDD >= 3.3 V ns 3.0 3.7 CL = 10 pF, VDD >= 3.3 V 12.7 16.9 CL = 30 pF, VDD >= 1.8 V 5.4 7.4 CL = 10 pF, VDD >= 1.8 V 24 24 CL = 30 pF, VDD >= 1.8 V I/O maximum frequency MHz CL = 10 pF, VDD >= 1.8 V Notes: 1. Guaranteed by characterization result, not tested in production. 2. CL is a external capacitive load to simulate PCB and device loading. 3. The maximum frequency is defined by . 4. PxSR.n bit value = 0, Normal output slew rate 5. PxSR.n bit value = 1, high speed output slew rate Table 8.3-8 I/O AC characteristics Sep. 1, 2020 Page 131 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET tr(IO)out Parameter ML51/ML54/ML56 8.4 Analog Characteristics 8.4.1 Reset and Power Control Block Characteristics The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V.The parameters in below table are derived from tests performed under ambient temperature unless otherwise specified. Symbol Parameter Min Typ Max Unit Test Conditions µA AVDD = 5.5V IPOR[1] POR Operating Current - 60 100 ILVR[1] LVR Operating Current - 30 80 AVDD = 5.5V 0.5 1 AVDD = 5.5V - 0.5 2.9 AVDD = 5.5V LVR Low Power Run Mode Operating Current IBOD[1] BOD Operating Current VPOR POR Reset Voltage 1.45 1.55 1.65 VLVR LVR Reset Voltage 1.55 1.63 1.70 VBOD BOD Brown-Out Detect Voltage 1.7 1.8 2 1.9 2 2.2 2.3 2.4 2.5 2.55 2.7 2.8 2.85 3 3.2 3.55 3.7 3.9 4.2 4.4 4.5 V - ML51/ML54/ML56 SERIES DATASHEET TLVR_SU[1] LVR Startup Time - 1 2 TLVR_RE[1] LVR Respond Time - 15 20 LVR Low Power Run Mode Respond Time - 20 30 TBOD_SU[1] BOD Startup Time - 250 350 - TBOD_RE[1] BOD Respond Time - 19 30 - µs - Notes: 1. Guaranteed by characterization, not tested in production. 2. Design for specified applcaiton. Table 8.4-1 Reset And Power Control Unit Sep. 1, 2020 Page 132 of 164 Rev 2.00 ML51/ML54/ML56 8.4.2 12-bit SAR ADC The maximum values are obtained for VDD = 1. 8V ~ 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V.The parameters in below table are derived from tests performed under ambient temperature unless otherwise specified. Symbol Min Typ Max Unit Temperature -40 - 105 ℃ AVDD Analog Operating Voltage 1.8 - VDD V VDD = AVDD VREF Reference Voltage 1.8 - AVDD V AVDD − VREF < 1.2 V ADC Channel Input Voltage 0 - VREF V Operating Current (AVDD + VREF Current) - - 360 µA TA VIN IADC[1] NR Parameter Resolution FADC[1] 12 ADC Conversion Rate Test Conditions AVDD = VDD = VREF = 5 V FADC = 500kHz Bit - - 500 0.375 - 2.12 0.417 - 1.54 Conversion Time 1 - 128 1/FADC Enable To Ready Time 20 - - μs INL Integral Non-Linearity Error -4 - +4 LSB VREF = AVDD DNL[1] Differential Non-Linearity Error -2 - +4.5 LSB VREF = AVDD Sampling Time [2] TSMP TCONV TEN [1] FADC ADC conversion rate TSMP Sampling Time [2] Gain Error -3.5 - +0.4 LSB VREF = AVDD EO[1]T Offset Error -2 - +2.5 LSB VREF = AVDD EA[1] Absolute Error -7 +7 LSB VREF = AVDD Notes: 1. Guaranteed by characterization result, not tested in production. 2. ADC sampling time =. 4 * ADCAQT  6 , FADCAQT is defined in ADCDIV (ADCCON2[3:1]). As default FADCAQT = FSYS FADCAQT (ADCDIV=0), 3. Since the minima sampling time must over 370ns that means when FADCAQT = 24MHz, ADCAQT should be defined as 1 at least. This value is defined by software. Table 8.4-2 ADC Characteristics Sep. 1, 2020 Page 133 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET EG[1] ML51/ML54/ML56 EF (Full scale error) = EO + EG Gain Error EG Offset Error EO 4095 4094 4093 4092 Ideal transfer curve 7 6 ADC output code 5 Actual transfer curve 4 3 2 DNL 1 1 LSB Offset Error EO Analog input voltage (LSB) 4095 ML51/ML54/ML56 SERIES DATASHEET Note: The INL is the peak difference between the transition point of the steps of the calibrated transfer curve and the ideal transfer curve. A calibrated transfer curve means it has calibrated the offset and gain error from the actual transfer curve. Sep. 1, 2020 Page 134 of 164 Rev 2.00 ML51/ML54/ML56 8.4.3 Analog Comparator Controller (ACMP) The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Min Typ Max Unit Analog supply voltage 1.8 - 5.5 V TA Temperature -40 - 105 ℃ IDD Operating current - 2 5 A AVDD Parameter Test Conditions VDD = AVDD VCM[2] Input common mode voltage range 0.35 1/2 AVDD AVDD -0.3 VDI[2] Differential input voltage sensitivity 10 20 - mV Hysteresis disable Input offset voltage - 10 20 mV Hysteresis disable Hysteresis window - 10 20 mV 45 65 75 dB Propagation delay - - 5 S TStable[2] Stable time - - 5 S ACRV[2] CRV output voltage -5 - 5 % RCRV[2] Unit resistor value - 4.5 - kΩ Stable time - - 2 µS Operating current - 2 - A Voffset [2] Vhys[2] Av [1] Td[2] TSETUP_CRV[2] IDD_CRV[2] DC voltage Gain AVDD x (1/6+CRVCTL/24) CRV output voltage settle to ±5% Notes: ML51/ML54/ML56 SERIES DATASHEET 1. Guaranteed by design, not tested in production 2. Guaranteed by characteristic, not tested in production. unless otherwise specified. Table 8.4-3 ACMP Characteristics Sep. 1, 2020 Page 135 of 164 Rev 2.00 ML51/ML54/ML56 8.4.4 Internal Voltage Reference The maximum values are obtained for VDD = 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max VREF_EXT External Analog reference voltage 1.8 - AVDD 1.49 1.538 1.59 AVDD >= 2.0 V, TA = 25°C Internal analog reference voltage VRFSEL[2:0] = 000 [2] AVDD >= 2.4 V, TA = 25°C Internal Analog reference voltage VRFSEL[2:0] = 001[2] Test in product. VREF_INT VBG Ts IVREF_INT ML51/ML54/ML56 SERIES DATASHEET IVREF_LOAD Unit Test Conditions 2.018 2.048 2.078 2.48 2.560 2.64 3.042 3.072 3.102 AVDD >= 3.4 V, TA = 25°C Internal Analog reference voltage VRFSEL[2:0] = 011[2] Test in product. 3.97 4.096 4.22 AVDD >= 4.5 V, TA = 25°C Internal analog reference voltage VRFSEL[2:0] = 100 [2] 0.793 0.814 0.835 V - 24 180 mS CL =1 uF, VREF initial=0, Preload is enabled. - 2 2.6 mS CL =1 uF, VREF initial=5.5, Preload is enabled. VREF_INT operating current - - 1 mA VREF_INT output loading current - - 1 mA Internal reference voltage Band-gap voltage V Stable time AVDD >= 2.9 V, TA = 25°C Internal analog reference voltage VRFSEL[2:0] = 010 [2] TA = -40°C ~105 °C, Test in product. Note: 1. Guaranteed by characterization, not tested in production Table 8.4-4 Voltage Reference Character VREF 1uF Note: VREF_INT is only supported while package includes VREF pin with external capacitor. Figure 8.4-1 Typical Connection With Internal Voltage Reference Sep. 1, 2020 Page 136 of 164 Rev 2.00 ML51/ML54/ML56 8.4.5 Temperature Sensor The maximum values are obtained for VDD = 1.8 ~ 5.5 V and maximum ambient temperature (T A), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol VTEMP_OS[1] TC[1] ITEMP [1] Parameter Tempereture sensor offset voltage Temperature Coefficient Temperature sensor operating current Min Typ Max Unit 645 675 705 mV 1.74 1.83 1.9 mV/℃ - 16 30 A Test Conditions TJ = 25 ℃ Note: 1. Guaranteed by characterization, not tested in production 2. VTEMP (mV) = TC (mV/°C) x Temperature (°C) + VTEMP_OS (mV) Table 8.4-5 Temperature Sensor Character ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 137 of 164 Rev 2.00 ML51/ML54/ML56 8.4.6 LCD Controller The maximum values are obtained for VDD = 3.6 V and maximum ambient temperature (TA), and the typical values for TA= 25 °C and VDD = 3.3 V unless otherwise specified. Symbol Parameter Min Typ Max Unit VDD Supply voltage 1.8 - 3.6 V VLCD LCD external pin voltage 1.8 - 5.5 V 0 - 85 °C TA CLCD CDH1-DH2 CVX VLCDCP Temperature VLCD pin external pin capacitor[2] 0.1 µF Wihtout charge pump mode 0.1 1 External charge-pump capacitor[2] 1 10 µF V1/V2/V3 external capacitance - N/A - F - 5.4 - VCP_SEL[5:0]=000000 - 5.2 - VCP_SEL[5:0]=000101 - 5.0 - VCP_SEL[5:0]=001010 - 4.8 - VCP_SEL[5:0]=001110 - 4.6 - VCP_SEL[5:0]=010011 - 4.4 - VCP_SEL[5:0]=011000 - 4.2 - LCD internal Charge Pump Voltage Output Value With charge pump mode ML51/ML54/ML56 SERIES DATASHEET - 4.0 - VCP_SEL[5:0]=100010 - 3.8 - VCP_SEL[5:0]=100111 - 3.6 - VCP_SEL[5:0]=101100 - 3.4 - VCP_SEL[5:0]=110000 - 3.2 - VCP_SEL[5:0]=110101 - 3.0 - VCP_SEL[5:0]=111010 - 2.8 - VCP_SEL[5:0]=111111 COM/SEG 3/4 VLCD (1/4 Bias) - 3/4 VLCD - V V2/4 COM/SEG 2/4 VLCD (1/4 Bias) - 2/4 VLCD - V V1/4 COM/SEG 2/4 VLCD (1/4 Bias) - 1/4 VLCD - V V2/3 COM/SEG 2/3 VLCD (1/3 Bias) - 2/3 VLCD - V V1/3 COM/SEG 1/3 VLCD (1/3 Bias) - 1/3 VLCD - V RR_MODE Resistor Mode total internal Resistor Value - 240 - KΩ RRE_MODE Resistor Enhance Mode total internal Resistor Value 6 - 18 Supply current from VDD with builtin charge pump and buffer mode MΩ A 31 Sep. 1, 2020 The capacitor between DH1 and DH2 VCP_SEL[5:0]=011101 V V3/4 ILCD[3] Test Conditions Page 138 of 164 VDD=1.8, VLCD=VCP=3.2, Buffer Mode, all LCD display on VDD=1.8, VLCD=VCP=3.2, Resistor Mode, all LCD display on Rev 2.00 ML51/ML54/ML56 Symbol IVLCD[3] Parameter Min Typ Max Unit Test Conditions - 5.5 - VDD=1.8, VLCD=VCP=3.2, Resistor Enhance Mode, all LCD display on - 24 - VDD=3.3, VLCD=VCP=5.4, Buffer Mode, all LCD display on - 1.8 - VDD=1.8, VLCD=VCP=3.2, Buffer Mode, all LCD display off - 7 - VDD=1.8, VLCD=3.3, Buffer Mode, all LCD display on 14 VDD=1.8, VLCD=3.3, Resistor Mode, all LCD display on 0.8 VDD=1.8, VLCD=3.3, Resistor Enhance Mode, all LCD display on Supply current from VLCD without Bulit-In Charge Pump A - 9.2 - VDD=1.8, VLCD=5.4, Buffer Mode, all LCD display on - 7 - VDD=3.3, VLCD=3.3, Buffer Mode, all LCD display on - 9 - VDD=1.8, VLCD=5.4, Buffer Mode, all LCD display off Notes: 1. 1. All condition not special defined is guaranteed by design, not tested in production 2. 2. CDH1-DH2 value should be 1/10 CLCD 3．LCD COM/SEG is set to clock source is LIRC, 1/8 duty, 1/4 bias, type B 64 Hz frame rate, all pixels active, waveform, without LCD panel loading. Table 8.4-6 LCD Digital Characteristics Parameter LCD Status Symbol Typ. VDD 1.8V ILCDCPPD (LIRC) ILCDCPPD (LXT) VDD Supply Current in Power Down Mode with LIRC, VLCD source internal Charge Pump VDD Supply Current in Power Down Mode with LXT, VLCD Sep. 1, 2020 LCD On Resistor Enhance Mode 0 25 85 0 25 85 0 25 85 3.2V 17 18 24 30 31 36 5.1 5.5 10 3.2V 20 22 29 37 39 44 6 6.3 6 5.4V 22 24 31 49 52 58 7 7 6 3.2V 1.6 1.6 5 1.6 1.6 5 1.6 1.6 5 3.2V 1.8 2 5.7 1.8 2 5.7 1.8 2 5.7 5.4V 1.8 2 5.7 1.8 2 5.7 1.8 2 5.7 3.2V 17 18 25 30 32 37 5.5 6 11 3.2V 21 22 30 37 40 45 6 6.5 16 5.4V 22 24 32 50 52 59 7 7.5 17 Unit ℃ µA 3.3V 1.8V LCD On Resistor Mode 3.3V 1.8V LCD Off Buffer Mode VLCD 3.3V Page 139 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET LCD Voltage Source From Internal Charge Pump ML51/ML54/ML56 Parameter source internal Charge Pump LCD Status Symbol Typ. VDD 1.8V LCD Off Buffer Mode VLCD Resistor Mode Resistor Enhance Mode 0 25 85 0 25 85 0 25 85 3.2V 1.6 1.6 5 1.6 1.6 5 1.6 1.6 5 3.2V 1.8 2 5.7 1.8 2 5.7 1.8 2 5.7 5.4V 1.8 2 5.7 1.8 2 5.7 1.8 2 5.7 Unit ℃ 3.3V Notes: 3. 1. All condition not special defined is guaranteed by design, not tested in production 2. The values are obtained for TA= 25 °C and VDD = 3.3 V unless otherwise specified. 3. LCD COM/SEG is set as 1/8 duty, 1/4 bias, type B 64 Hz frame rate, all pixels active, without LCD panel loading. Table 8.4-7 Current Consumption In Power Down Mode With LCD Voltage Source From Internal Charge Pump LCD Voltage Source From AVDD Symbol Parameter LCD Status Typ. Buffer Mode VLCD Unit Resistor Mode Resistor Enhance Mode 0 25 85 0 25 85 0 25 85 1.8V 6.2 6.8 13 9 9.2 13 2.1 2.4 6 3.3V 9 9.5 15 16 16.4 21 2.6 3 7 1.8V 5.2 6 11 8 8.3 12 1.2 1.4 5 3.3V 8 8.5 13.5 14.2 14.6 19 1.6 1.8 6 1.8V 6.6 7.5 5.2 9.6 10 12.1 2.7 3 4.8 3.3V 9 10 6.2 16.8 14.5 19.2 3.2 3.5 5.8 1.8V 5.2 6 11 8 8.3 12 1.2 1.4 5 3.3V 8 8.5 13.5 14.2 14.6 19 1.6 1.8 6 ℃ (AVDD) ILCDAVDDP D(LIRC) ML51/ML54/ML56 SERIES DATASHEET VDD Supply Current in Power Down Mode with LIRC, VLCD source internal AVDD LCD On LCD Off µA ILCDAVDDP D(LXT) VDD Supply Current in Power Down Mode with LXT, VLCD source internal AVDD LCD On LCD Off Notes: 4. 1. All condition not special defined is guaranteed by design, not tested in production 2. The values are obtained for TA= 25 °C unless otherwise specified. 3. LCD COM/SEG is set to 1/8 duty, 1/4 bias, 128 Hz frame rate, all pixels active, type B waveform, no LCD panel loading. Table 8.4-8 Current Consumption In Power Down Mode With LCD Voltage Source From AVDD Sep. 1, 2020 Page 140 of 164 Rev 2.00 ML51/ML54/ML56 LCD Voltage Source From External VLCD Pin Symbol ILCDVLCDP D(LIRC) Parameter LCD Status Typ. VLCD Supply Current in Power Down Mode with LIRC, LCD On VLCD source External VLCD pin LCD Off Supply Current in Power Down Mode with LXT, LCD On Buffer Mode Unit Resistor Mode Resistor Enhance Mode VLCD 0 25 85 0 25 85 0 25 85 3.3 6.5 7 9 13.5 14 15 0.7 0.8 1.2 5.4V 8.6 9.2 11 22 23 24 1.2 1.2 2 3.3V 6.5 7 8.5 14 14 14.5 0.5 0.6 1 5.4V 8.3 9 11 22 23 23.5 0.9 1 2 3.3 6.5 7 9 13.5 14 15 0.7 0.8 1.2 5.4V 8.6 9.2 11 22 23 24 1.2 1.2 2 3.3V 6.5 7 8.5 14 14 14.5 0.5 0.6 1 5.4V 8.3 9 11 22 23 23.5 0.9 1 2 ℃ µA ILCDVLCDP D(LXT) VLCD source External VLCD pin LCD Off Notes: 5. 1. All condition not special defined is guaranteed by design, not tested in production 2. The values are obtained for TA= 25 °C and VDD = 3.3 V unless otherwise specified. 3. LCD COM/SEG is set to 1/8 duty, 1/4 bias, 128 Hz frame rate, all pixels active, type B waveform, no LCD panel loading Sep. 1, 2020 Page 141 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET Table 8.4-9 Current Consumption In Power Down Mode With LCD Voltage Source From External VLCD pin ML51/ML54/ML56 8.5 Flash DC Electrical Characteristics The devices are shipped to customers with the Flash memory erased. Symbol Parameter Min Typ Max Unit 1.62 1.8 1.98 V Page erase time - 5 - ms TPROG Program time - 10 - µs IDD1 Read current - 4 - mA IDD2 Program current - 4 - mA IDD3 Erase current - 12 - mA 100,000 - 50 - - year 100 kcycle[3] TA = 55℃ 25 - - year 100 kcycle[3] TA = 85℃ 10 - - year 100 kcycle[3] TA = 105℃ VFLA[1] Supply voltage TERASE NENDUR TRET Endurance Data retention cycles[2] Test Condition TA = 25℃ TJ = -40℃~125℃ Notes: 1. VFLA is source from chip internal LDO output voltage. 2. Number of program/erase cycles. 3. Guaranteed by design. Table 8.5-1 Flash Memory Characteristics ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 142 of 164 Rev 2.00 ML51/ML54/ML56 8.6 Absolute Maximum Ratings Volrage Stesses above the absolute maximum ratings may cause permanent damage to the device. The limiting values are stress ratings only and cannot be used to functional operation of the device. Exposure to the absolute maximum ratings may affect device reliability and proper operation is not guaranteed. 8.6.1 Voltage Characteristics 8.6.1.1 ML51 32KB/16KB Flash Series Symbol VDD-VSS[1] ΔVDD |VDD –AVDD| ΔVSS |VSS - AVSS| VIN Description Max Unit -0.3 6.5 V Variations between different power pins - 50 mV Allowed voltage difference for VDD and AVDD - 50 mV Variations between different ground pins - 50 mV Allowed voltage difference for VSS and AVSS - 50 mV VSS-0.3 6.5 V DC power supply Input voltage on I/O Min Notes: 1. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply. Table 8.6-1 ML51 32KB/16KB Flash Series Voltage Characteristics 8.6.1.2 ML51 64KB Flash/ML54/ML56 Series Symbol ΔVDD |VDD –AVDD| ΔVSS |VSS - AVSS| VIN Description Max Unit -0.3 4.0 V Variations between different power pins - 50 mV Allowed voltage difference for VDD and AVDD - 50 mV Variations between different ground pins - 50 mV Allowed voltage difference for VSS and AVSS - 50 mV VSS-0.3 3.6 V DC power supply Input voltage on I/O Min Notes: 2. All main power (VDD, AVDD) and ground (VSS, AVSS) pins must be connected to the external power supply. Table 8.6-2 ML51 64KB Flash/ML54/ML56 Series Voltage Characteristics Sep. 1, 2020 Page 143 of 164 Rev 2.00 ML51/ML54/ML56 SERIES DATASHEET VDD-VSS[1] ML51/ML54/ML56 8.6.2 Current Characteristics Symbol ΣIDD[1] ΣISS IIO IINJ(PIN) [3] ΣIINJ(PIN) [3] Description Min Max Maximum current into VDD - 150 Maximum current out of VSS - 150 Maximum current sunk by a I/O Pin - 22 Maximum current sourced by a I/O Pin - 10 Maximum current sunk by total I/O Pins[2] - 100 Maximum current sourced by total I/O Pins[2] - 100 Maximum injected current by a I/O Pin - ±5 Maximum injected current by total I/O Pins - ±25 Unit mA Note: 1. Maximum allowable current is a function of device maximum power dissipation. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins. 3. A positive injection is caused by VIN>AVDD and a negative injection is caused by VIN 30 sec. Time with 5℃ of actual peak temperature Peak temperature range 260℃ Ramp-down rate 6℃/sec ax. Time 25℃ to peak temperature 8 min. max Note: 1. Determined according to J-STD-020C Table 8.6-8 Soldering Profile Sep. 1, 2020 Page 149 of 164 Rev 2.00 ML51/ML54/ML56 9 PACKAGE DIMENSIONS 9.1 LQFP 64L-pin (7.0 x 7.0 x 1.4 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.1-1 LQFP 64L Package Dimension Sep. 1, 2020 Page 150 of 164 Rev 2.00 ML51/ML54/ML56 9.2 LQFP 48-pin (7.0 x 7.0 x 1.4 mm) H 36 25 37 24 48 13 H 12 1  ML51/ML54/ML56 SERIES DATASHEET Controlling dimension : Millimeters Symbol A A1 A2 b c D E e HD HE L L1 Y 0 Dimension in inch Dimension in mm Min Nom Max Min Nom Max 0.002 0.004 0.006 0.05 0.053 0.055 0.057 1.35 1.40 1.45 0.006 0.008 0.010 0.15 0.20 0.25 0.004 0.006 0.008 0.10 0.15 0.20 0.272 0.276 0.280 6.90 7.00 7.10 0.272 0.276 0.280 6.90 7.00 7.10 0.020 0.026 0.35 0.50 0.65 0.014 0.10 0.15 0.350 0.354 0.358 8.90 9.00 9.10 0.350 0.354 0.358 8.90 9.00 9.10 0.018 0.024 0.030 0.45 0.60 0.75 1.00 0.039 0.004 0 7 0.10 0 7 Figure 9.2-1 LQFP-48 Package Dimension Sep. 1, 2020 Page 151 of 164 Rev 2.00 ML51/ML54/ML56 9.3 LQFP 44-pin (10 x 10 x 1.4mm ML51/ML54/ML56 SERIES DATASHEET Figure 9.3-1 LFP44 Package Dimension Sep. 1, 2020 Page 152 of 164 Rev 2.00 ML51/ML54/ML56 9.4 QFN 33-pin (4.0 x 4.0 x 0.8 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.4-1 QFN-33 Package Dimension Sep. 1, 2020 Page 153 of 164 Rev 2.00 ML51/ML54/ML56 9.5 LQFP 32-pin (7.0 x 7.0 x 1.4 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.5-1 LQFP-32 Package Dimension Sep. 1, 2020 Page 154 of 164 Rev 2.00 ML51/ML54/ML56 9.6 TSSOP 28-pin (4.4 x 9.7 x 1.0 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.6-1 TSSOP-28 Package Dimension Sep. 1, 2020 Page 155 of 164 Rev 2.00 ML51/ML54/ML56 9.7 SOP 28-pin (300mil) 15 28 E 14 1 ML51/ML54/ML56 SERIES DATASHEET Control demensions are in milmeters . E  Figure 9.7-1 SOP-28 Package Dimension Sep. 1, 2020 Page 156 of 164 Rev 2.00 ML51/ML54/ML56 9.8 TSSOP 20-pin (4.4 x 6.5 x 0.9 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.8-1 TSSOP-20 Package Dimension Sep. 1, 2020 Page 157 of 164 Rev 2.00 ML51/ML54/ML56 9.9 SOP 20-pin (300 mil) 11 20 E 10 1 ML51/ML54/ML56 SERIES DATASHEET Control demensions are in milmeters . E  Figure 9.9-1 SOP-20 Package Dimension Sep. 1, 2020 Page 158 of 164 Rev 2.00 ML51/ML54/ML56 9.10 QFN 20-pin ( 3.0 x 3.0 x 0.8 mm ) ML51/ML54/ML56 SERIES DATASHEET Figure 9.10-1 QFN-20 Package Dimension Sep. 1, 2020 Page 159 of 164 Rev 2.00 ML51/ML54/ML56 9.11 TSSOP 14-pin (4.4 x 5.0 x 0.9 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.11-1 TSSOP-14 Package Dimension Sep. 1, 2020 Page 160 of 164 Rev 2.00 ML51/ML54/ML56 9.12 MSOP 10-pin (3.0 x 3.0 x 0.85 mm) ML51/ML54/ML56 SERIES DATASHEET Figure 9.12-1 MSOP-10 Package Dimension Sep. 1, 2020 Page 161 of 164 Rev 2.00 ML51/ML54/ML56 10 ABBREVIATIONS 10.1 Abbreviations ML51/ML54/ML56 SERIES DATASHEET Acronym Description ADC Analog-to-Digital Converter BOD Brown-out Detection GPIO General-Purpose Input/Output Fsys Frequency of system clock HIRC 12 MHz Internal High Speed RC Oscillator IAP In Application Programming ICP In Circuit Programming ISP In System Programming LCD Liquid Crystal Displays LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) LVR Low Voltage $eset PDMA Peripheral Direct Memory Access POR Power On Reset PWM Pulse Width Modulation RTC Real Time Clock SPI Serial Peripheral Interface TK Touch Key UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID WKT Wakeup Timer WDT Watchdog Timer Table 10.1-1 List of Abbreviations Sep. 1, 2020 Page 162 of 164 Rev 2.00 ML51/ML54/ML56 11 REVISION HISTORY Date Revision Description 2018.12.05 1.00 Initial release. Section 3.1 Added package type table. Section 4.2.2 Added Multi-function summary table. Section 6.2 Added ICP connect circuit. Section 7.2.4 Modified ISR value. 2019.09.03 1.01 Section 7.3 Removed 32.768kHz external clock input and deviation figure. Section 7.4.1 Modified POR/LVR/BOD operating current value. Section 7.6.1 Modified DC power supply item. Section 8.6 Modified TSSOP20 package dimension in title. Section 37.6 Modified TSSOP20 package value. Section 6.2 Added note in application circuit. Section 7.4.2 Added RS and CIN value in table. 2020.03.11 1.02 Section 7.4.4 Added section 7.4.4. Moved internal voltage character table to this section. Chapter 8.1 Modified QFN33 package L value to 0.3. Chapter 7.6.2 Modified Maximum current to 150mA 2020.06.29 1.03 Chapter 7.6.4 Modified Pin current for latch-up value to 150mA . Modified Fast transient voltage burst value to 4.4kV. Chapter 7.4.2 Modified ADC conversion rate and sampling timing description. 2020.09.01 2.00 Added ML51 64KB/ML54/ML56 Series description. ML51/ML54/ML56 SERIES DATASHEET Sep. 1, 2020 Page 163 of 164 Rev 2.00 ML51/ML54/ML56 ML51/ML54/ML56 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. Sep. 1, 2020 Page 164 of 164 Rev 2.00