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F1C200S

F1C200S

  • 厂商:

    ALLWINNER(全志科技)

  • 封装:

    MQFN-88_10X10MM-EP

  • 描述:

    F1C200S

  • 数据手册
  • 价格&库存
F1C200S 数据手册
s t s a F1C200s Datasheetusi h t n E h c e T r e n n i w l l A Revision 1.1 Dec.25,2017 r o F Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved. Declaration Declaration THIS DOCUMENTATION IS THE ORIGINAL WORK AND COPYRIGHTED PROPERTY OF ALLWINNER TECHNOLOGY (“ALLWINNER”). REPRODUCTION IN WHOLE OR IN PART MUST OBTAIN THE WRITTEN APPROVAL OF ALLWINNER AND GIVE CLEAR ACKNOWLEDGEMENT TO THE COPYRIGHT OWNER. THE INFORMATION FURNISHED BY ALLWINNER IS BELIEVED TO BE ACCURATE AND RELIABLE. ALLWINNER RESERVES THE RIGHT TO MAKE CHANGES IN CIRCUIT DESIGN AND/OR SPECIFICATIONS AT ANY TIME WITHOUT NOTICE. ALLWINNER DOES NOT ASSUME ANY RESPONSIBILITY AND LIABILITY FOR ITS USE. NOR FOR ANY INFRINGEMENTS OF PATENTS OR OTHER RIGHTS OF THE THIRD PARTIES WHICH MAY RESULT FROM ITS USE. NO LICENSE IS GRANTED BY IMPLICATION OR OTHERWISE UNDER ANY PATENT OR PATENT RIGHTS OF ALLWINNER. THIS DATASHEET NEITHER STATES NOR IMPLIES WARRANTY OF ANY KIND, INCLUDING FITNESS FOR ANY PARTICULAR APPLICATION. s t s a i s u th THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT. CUSTOMERS SHALL BE SOLELY RESPONSIBLE TO OBTAIN ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES. ALLWINNER SHALL NOT BE LIABLE FOR ANY LICENCE FEE OR ROYALTY DUE IN RESPECT OF ANY REQUIRED THIRD PARTY LICENCE. ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS COVERED UNDER ANY REQUIRED THIRD PARTY LICENCE. n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 2 Revision History Revision History Revision Date Description 1.0 Apr.18,2017 Initial Release Version 1.1 Dec.25,2017 Update video decoding features in Section 2.5 s t s a i s u th n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 3 Table of Contents Table of Contents 1. 2. 3. 4. 5. 6. Overview ............................................................................................................................................................ 5 Features ............................................................................................................................................................. 6 2.1. CPU Architecture.................................................................................................................................... 6 2.2. Memory Subsystem ............................................................................................................................... 6 2.3. System Peripheral .................................................................................................................................. 6 2.4. Display Subsystem.................................................................................................................................. 7 2.5. Video Engine .......................................................................................................................................... 8 2.6. Image Subsystem ................................................................................................................................... 8 2.7. Audio Subsystem.................................................................................................................................... 8 2.8. Interfaces ............................................................................................................................................... 8 2.9. Package ................................................................................................................................................ 10 Block Diagram .................................................................................................................................................. 11 Pin Description ................................................................................................................................................. 12 4.1. Pin Characteristics................................................................................................................................ 12 4.2. GPIO Multiplexing Functions ............................................................................................................... 14 4.3. Detailed Pin Description ...................................................................................................................... 15 Electrical Characteristics .................................................................................................................................. 18 5.1. Absolute Maximum Ratings ................................................................................................................. 18 5.2. Recommended Operating Conditions .................................................................................................. 18 5.3. DC Electrical Characteristics................................................................................................................. 18 5.4. Oscillator Electrical Characteristics ...................................................................................................... 19 5.5. Power Up/Down Sequence .................................................................................................................. 19 Pin Assignment ................................................................................................................................................ 20 6.1. Pin Map ................................................................................................................................................ 20 6.2. Package Dimension .............................................................................................................................. 21 s t s a i s u th n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 4 Overview 1. Overview The F1C200s processor represents Allwinner’s latest achievement in mobile applications processors. The processor targets the needs of video boombox markets. The F1C200s is based on the ARM9 CPU architecture with a high degree of functional integration, and supports Full HD video playback, including H.264,H.263,MPEG1/2/4 decoder. Integrated audio codec and I2S/PCM interface provide end users with a good audio experience. TV-IN interface enables video input by connecting to video devices such as camera, and TV-OUT interface enables video output by connecting to TV devices. s t s a i To reduce the BOM costs, the F1C200s built-in DDR1 memory , and it is packed with general-purpose peripherals such as USB OTG, UART, SPI, TWI, TP, SD/MMC, CSI, etc. The F1C200s outperforms competitors in terms of its powerful performance, low power consumption, and flexible scalability. s u th Applications: ● Video Playback ● Audio Playback ● FM n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 5 Features 2. Features 2.1. CPU Architecture The F1C200s platform is based on ARM9 CPU architecture. ● Five-stage pipeline architecture ● Support 16KByte D-Cache ● Support 32KByte I-Cache 2.2. Memory Subsystem This section consists of internal memory and external memory: ● Boot ROM ● SDRAM ● SD/MMC Interface Boot ROM ● Internal memory ● On-Chip ROM boot loader ● Support system boot from SPI Nor/Nand Flash, and SD/TF card ● Support system code download through USB OTG SDRAM ● SIP DDR1 r e n s t s a i s u th n E h c Te SD/MMC Interface ● External memory ● Support secure digital memory protocol commands (up to SD2.0) ● Support secure digital I/O protocol commands (up to SDIO2.0) ● Support multimedia card protocol commands (up to eMMC4.41) ● Support one SD (Verson1.0 to 2.0) or MMC (version 3.3 to eMMC4.41) ● Support hardware CRC generation and error detection ● Support host pull-up control ● Support SDIO interrupts in 1-bit and 4-bit modes ● Support SDIO suspend and resume operation ● Support SDIO read wait ● Support block size of 1 to 65535 bytes ● Support descriptor-based internal DMA controller ● Internal 128 bytes FIFO for data transfer ● Support 3.3V IO pad n i lw l A r Fo 2.3. System Peripheral This section includes: ● Timer ● INTC ● CCU ● DMA ● PWM Timer ● Three timers F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 6 Features ● Support watchdog reset ● Support audio and video synchronize counter INTC ● Support up to 64 interrupts ● Support 4-level priority ● Support interrupt mask ● Support interrupt fast forcing ● Support one external interrupt CCU ● Support 6 PLLs ● Control of clock generation, division, distribution and gating ● Control of device software reset DMA ● Support Normal DMA and Dedicated DMA ● Support two kinds of interrupt ● Support hardware continuous transfer mode PWM ● Support two PWM outputs ● Support cycle mode and pulse mode ● Support 24MHz maximum output frequency 2.4. Display Subsystem This section includes: ● Display Engine ● Display Output n i lw r e n s t s a i s u th n E h c Te Display Engine ● Support four layers overlay, each layer size up to 2048x2048 pixels ● Support Alpha blending / color key ● Support multi-format input formats  1/2/4/8/16/32 bpp color  YUV444/YUV422/YUV420/YUV411 ● Support hardware cursor ● Support scaling function for one layer  ARGB8888/YUV444/YUV420/YUV422/YUV411  Input and output size up to 1280x720 pixels  Resize ratio from 1/16X to 32X  4-tap 32-phase anti-aliasing filter in horizontal and vertical direction  Scaler supports write-back to memory function l A r Fo Display Output ● LCD RGB interface, TTL interface, up to 1280x720@60fps ● LCD Serial RGB interface, CCIR656 interface, up to 720x576@60fps ● LCD i8080 interface with 18/16/9/8 bit, up to 800x480@60fps ● LCD Dither function, support RGB666/RGB565 interface ● TV CVBS output, support NTSC/PAL, with auto plug detecting F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 7 Features 2.5. Video Engine ● ● ● ● ● ● Support H.264 BP/MP/HP up to 1920x1080@30fps decoding Support MPEG1 and MPEG2 up to 1920x1080@30fps decoding Support MPEG4 SP/ASP GMC and H.263 including Sorenson Spark up to 1920x1080@30fps decoding Support MJPEG encode up to 1280x720@30fps Support JPEG encode size up to 8192 x 8192 Support JPEG decode size up to 16384 x 16384 2.6. Image Subsystem s t s a i This section includes: ● CSI ● CVBS Input CSI ● Support 8-bit CMOS-sensor interface ● Support YUV camera up to 5Mega pixel ● Support CCIR656 protocol for NTSC and PAL CVBS Input ● Support NTSC/PAL ● Support 3D comb filter ● Support two TV CVBS channels:TVIN0,TVIN1 r e n 2.7. Audio Subsystem n i lw s u th n E h c Te Audio Codec ● Two audio digital-to-analog(DAC) channels ● Stereo capless headphone drivers:  Up to 100dB DR  Supports DAC Sample Rates from 8KHz to 192KHz ● Support analog/ digital volume control ● Analog low-power loop from FM/ line-in /microphone to headphone outputs ● Three audio inputs:  One microphone input  Stereo FM left/right input  One Line-in input ● One audio analog-to-digital(ADC) channel  96dB SNR@A-weight  Supports ADC Sample Rates from 8KHz to 48KHz  Support Auto Gain Control(AGC) l A r Fo 2.8. Interfaces This section includes: ● USB 2.0 OTG ● KEYADC ● TP ● Digital Audio Interface ● UART F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 8 Features ● ● ● ● ● SPI TWI IR RSBTM OWA USB 2.0 OTG ● Support AMBA AHB Slave mode ● Support the Host Negotiation Protocol (HNP) and the Session Request Protocol (SRP) ● Support the UTMI+ Level 3 interface . The 8-bit bidirectional data buses are used. ● 64-Byte Endpoint 0 for Control Transfer (Endpoint0) ● Support High-Bandwidth Isochronous & Interrupt transfers ● Automated splitting/combining of packets for Bulk transfers ● Support point-to-point and point-to-multipoint transfer in both Host and Peripheral mode ● Include automatic ping capabilities ● Soft connect/disconnect function ● Perform all transaction scheduling in hardware ● Power Optimization and Power Management capabilities ● Include interface to an external Dedicated Central DMA controller. Data is transferred through Special bus for saving AHB bus bandwidth ● Support industry-standard single port SRAM for USB Configurable Data FIFO. The size is 2048 byte with 32-bit word width. The RAM can be used by other modules when USB OTG disable KEYADC ● 6-bit resolution ● Support hold key and general key ● Support single key and continuous key ● Sample rate up to 250Hz TP ● ● ● ● ● ● ● ● ● ● r e n s t s a i s u th n E h c Te 12-bit SAR type analog-to-digital converter 4-wire I/F Dual Touch Detect Touch-pressure measurement Sampling frequency: 2MHz Single-Ended conversion of touch screen inputs and ratio metric conversion of touch screen inputs TACQ up to 262ms Median and averaging filter to reduce noise Pen down detection, with programmable sensitivity Support X, Y change function n i lw Fo l A r Digital Audio Interface ● I2S or PCM configured by software ● Master / Slave Mode operation configured by software ● I2S Audio data sample rate from 8KHz to 192KHz ● I2S Data format for standard I2S, Left Justified and Right Justified ● PCM supports linear sample (8-bits or 16-bits), 8-bits u-law and A-law commanded sample UART ● Three UART controllers ● Compatible with industry-standard 16550 UARTs ● Support IRDA version 1.0 SIR protocol with maximum baud rate to 115200bps for all UARTs ● Support for word length from 5 to 8 bits,an optional parity bit, and 1,1.5 or 2 stop bits ● Programmable parity(even,odd and no parity) ● 32-Bytes Transmit and receive data FIFOs ● Support DMA controller interface ● Software/ Hardware Flow Control ● Interrupt support for FIFOs, Status Change F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 9 Features SPI ● ● ● ● ● Two SPI controllers Full-duplex synchronous serial interface Master/Slave configurable 8-bit wide by 64-entry FIFO for both transmit and receive data Polarity and phase of the chip select (SPI_SS) and SPI Clock (SPI_SCLK) are configurable TWI ● ● ● ● ● ● ● ● ● ● Three TWI controllers Software-programmable for Slave or Master Support repeated START signal Multi-master systems supported Allow 10-bit addressing with TWI bus Performs arbitration and clock synchronization Own address and general call address detection Interrupt on address detection Support speeds up to 400Kbits/s (‘fast mode’) Allow operation from a wide range of input clock frequencies IR ● ● ● ● Full physical layer implementation Support CIR for remote control 64x8bits FIFO for data buffer Programmable FIFO thresholds s t s a i s u th n E h c Te RSBTM ● Support speed up to 20MHz with ultra low power ● Support push-pull bus ● Support host mode ● Support programmable output delay of CD signal ● Support parity check for address and data transmission ● Support multi-devices n i lw r e n l A r OWA ● EC-60958 transmitter functionality ● Support S/PDIF Interface ● Support channel status insertion for the transmitter ● Support Parity generation on the transmitter ● One 32×24bits FIFO (TX) for audio data transfer ● Programmable FIFO thresholds ● Interrupt and DMA support Fo 2.9. Package ● QFN88,10mm x 10mm F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 10 Block Diagram 3. Block Diagram The block diagram of F1C200s processor is as follows: Connectivity SDIO Video Engine (H.264,H.263,MPEG1,MPEG2,MPEG4, JPEG/MJPEG) Display Engine I2S/PCM Audio Codec USB OTG s t s a i 3 x TWI 2 x SPI CPU s u th RSB 32KB I-Cache 3 x UART 16KB D-Cache KEYADC System Memory SIP DDR1 JTAG r e n SD/eMMC IR n i lw SPI Nor/NAND Flash OWA out l A r h c Te Interrupt Controller RTP En Image and Display CSI Timer CVBS Input CCU CVBS Output DMA RGB LCD The typical application diagram of F1C200s is as follows: Fo Wi-Fi USB SDIO TV Display TV IN FM TV OUT FM IN MIC IN HP OUT F1C200s Audio Codec RGB LCD TWI DDR1 Class D AMP HP OUT SPI SPI Nand/ Nor Flash F1C200s Datasheet(Revision 1.1) LCD Display &Touch SD2.0 SD/TF card Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 11 Pin Description 4. Pin Description 4.1. Pin Characteristics Following table describes the F1C200s pin characteristics from seven aspects: BALL#, Pin Name, Default Function, Type, Reset State, Default Pull Up/Down and Buffer Strength. (1). Default function defines the default function of each pin, especially for pins with multiplexing functions; (2). Pin types : O for output, I for input, I/O for input/output, A for analog, AI for analog input, AO for analog output, AI/O for analog input/output, OD for Open-Drain, P for power and G for ground; (3). Reset state defines the state of the terminal at reset: Z for high-impedance. (4). Default Pull up/down defines the presence of an internal pull up or pull down resistor. Unless otherwise specified, the pin is default to be floating, and can be configured as pull up or pull down; (5). Buffer strength defines the driver strength of the associated output buffer. It is tested in the condition that VCC= 3.0V, strength=MAX; Pin Num(1) Pin PC0 PC1 PC2 PC3 GPIO GPIO GPIO GPIO I/O I/O I/O I/O Disabled Disabled Disabled Disabled Pull-up - - PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled - - PE0 PE1 PE2 PE3 PE4 PE5 PE6 GPIO GPIO GPIO GPIO GPIO GPIO GPIO I/O I/O I/O I/O I/O I/O I/O Disabled Disabled Disabled Disabled Disabled Disabled Disabled - - r e n n i lw l A r Fo n E h c Te Pin Name GPIOD 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23 24 25 26 27 28 29 s u th Buffer Default Pull Strength(5) Up/ Down(4) (mA) Default Function GPIOC 59 60 61 62 s t s a i Type(2) Reset State(3) GPIOE 49 48 47 46 45 44 43 F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 12 Pin Description 42 41 40 39 38 37 PE7 PE8 PE9 PE10 PE11 PE12 GPIO GPIO GPIO GPIO GPIO GPIO I/O I/O I/O I/O I/O I/O Disabled Disabled Disabled Disabled Disabled Disabled - - PF0 PF1 PF2 PF3 PF4 PF5 GPIO GPIO GPIO GPIO GPIO GPIO I/O I/O I/O I/O I/O I/O Disabled Disabled Disabled Disabled Disabled Disabled - - UVCC USB-DM USB-DP - P A A - - - VRA1 VRA2 AGND FMINR FMINL MICIN LINL HPR HPL HPCOM HPVCC HPCOMFB AVCC - A A P A A A A A A A P A P - - - - - GPIOF 58 57 56 55 54 53 USB 67 68 69 Audio Codec 81 83 82 85 84 87 86 88 1 3 4 2 80 Touch Panel 66 65 64 63 TV IN r o F 73 74 75 76 77 78 Al n i lw r e n A A A A s t s a i s u th n E h c Te - TPX1 TPX2 TPY1 TPY2 - TV_VCC TVGND TV_VRN TV_VRP TVIN1 TVIN0 - P P A A A A - - - LRADC0 - A - - - TVOUT - A - - - HOSCO HOSCI - A A - - - RESET - I - - - SVREF - P VCC-IO VCC-DRAM VDD-CORE - P P P - - - KEYADC 79 TV OUT 72 Clock 52 51 Miscellaneous Signal 70 SIP DDR1 33 Power 5,20,50 30,31,32,34,36 22,35,71 F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 13 Pin Description 4.2. GPIO Multiplexing Functions Following table provides a description of the GPIO multiplexing functions of F1C200s. Default IO Function Type Default Default Multiplexing Multiplexing Multiplexing Multiplexing Multiplexing Pull-up/ IO State Function 2 Function 3 Function 4 Function 5 Function 6 down PA0 GPIO A DIS Z TPX1 DA_BCLK UART1_RTS SPI1_CS PA1 GPIO A DIS Z TPX2 DA_LRCK UART1_CTS SPI1_MOSI PA2 GPIO A DIS Z TPY1 PWM0 DA_IN UART1_RX SPI1_CLK PA3 GPIO A DIS Z TPY2 IR_RX DA_OUT UART1_TX SPI1_MISO GPIO I/O DIS Z DDR_REF_D IR_RX PC0 GPIO I/O DIS Z SPI0_CLK SDC1_CLK PC1 GPIO I/O DIS Pull-up SPI0_CS SDC1_CMD PC2 GPIO I/O DIS Z SPI0_MISO SDC1_D0 PC3 GPIO I/O DIS Z SPI0_MOSI UART0_TX GPIOD PD0 GPIO GPIO PD1 I/O I/O DIS DIS Z Z LCD_D2 PD2 GPIO I/O DIS Z LCD_D4 PD3 GPIO I/O DIS Z LCD_D5 PD4 GPIO I/O DIS Z PD5 GPIO I/O DIS Z PD6 GPIO I/O DIS Z PD7 GPIO I/O DIS Z PD8 GPIO PD9 GPIO llw Port GPIOA s t s a i GPIOB PB3 s u th GPIOC LCD_D3 UART1_RTS UART1_CTS En RSB_SDA EINTD0 EINTD1 EINTD2 UART1_RX EINTD3 UART1_TX TWI1_SCK EINTD4 LCD_D10 TWI1_SDA EINTD6 LCD_D11 EINTD7 er LCD_D6 n in h c Te TWI0_SDA LCD_D7 EINTD5 I/O DIS Z I/O DIS Z A r LCD_D13 DA_MCLK DA_BCLK DA_LRCK I/O DIS Z LCD_D14 DA_IN EINTD10 I/O DIS Z LCD_D15 DA_OUT EINTD11 I/O DIS Z LCD_D18 I/O DIS Z LCD_D19 TWI0_SCK UART2_TX LCD_D12 EINTD8 EINTD9 PD10 GPIO PD11 GPIO PD12 GPIO PD13 GPIO PD14 GPIO I/O DIS Z LCD_D20 UART2_RX PD15 GPIO I/O DIS Z LCD_D21 UART2_RTS TWI2_SCK EINTD15 PD16 GPIO I/O DIS Z LCD_D22 UART2_CTS TWI2_SDA EINTD16 PD17 GPIO I/O DIS Z LCD_D23 OWA_OUT EINTD17 PD18 GPIO I/O DIS Z LCD_CLK SPI0_CS EINTD18 PD19 GPIO I/O DIS Z LCD_DE SPI0_MOSI EINTD19 PD20 GPIO I/O DIS Z LCD_HSYNC SPI0_CLK EINTD20 PD21 GPIO I/O DIS Z LCD_VSYNC SPI0_MISO EINTD21 PE0 GPIO I/O DIS Z CSI_HSYNC LCD_D0 TWI2_SCK UART0_RX EINTE0 PE1 GPIO I/O DIS Z CSI_VSYNC LCD_D1 TWI2_SDA UART0_TX EINTE1 PE2 GPIO I/O DIS Z CSI_PCLK LCD_D8 CLK_OUT PE3 GPIO I/O DIS Z CSI_D0 LCD_D9 DA_BCLK RSB_SCK EINTE3 PE4 GPIO I/O DIS Z CSI_D1 LCD_D16 DA_LRCK RSB_SDA EINTE4 PE5 GPIO I/O DIS Z CSI_D2 DA_IN PE6 GPIO I/O DIS Z CSI_D3 LCD_D17 PWM1 Fo RSB_SCK EINTD12 EINTD13 EINTD14 GPIOE F1C200s Datasheet(Revision 1.1) DA_OUT EINTE2 EINTE5 OWA_OUT Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved EINTE6 Page 14 Pin Description PE7 GPIO I/O DIS Z CSI_D4 UART2_TX SPI1_CS EINTE7 PE8 GPIO I/O DIS Z CSI_D5 UART2_RX SPI1_MOSI EINTE8 PE9 GPIO I/O DIS Z CSI_D6 UART2_RTS SPI1_CLK EINTE9 PE10 GPIO I/O DIS Z CSI_D7 UART2_CTS SPI1_MISO EINTE10 PE11 GPIO I/O DIS Z CLK_OUT TWI0_SCK IR_RX EINTE11 PE12 GPIO I/O DIS Z DA_MCLK TWI0_SDA PWM0 EINTE12 PF0 GPIO I/O DIS Z SDC0_D1 DBG_MS IR_RX EINTF0 PF1 GPIO I/O DIS Z SDC0_D0 DBG_DI EINTF1 PF2 GPIO I/O DIS Z SDC0_CLK UART0_RX EINTF2 PF3 GPIO I/O DIS Z SDC0_CMD DBG_DO EINTF3 PF4 GPIO I/O DIS Z SDC0_D3 UART0_TX EINTF4 PF5 GPIO I/O DIS Z SDC0_D2 DBG_CK GPIOF PWM1 s u th 4.3. Detailed Pin Description Pin Name Description GPIO PC[3:0] Port C Bit[3:0] PD[21:0] Port D Bit[21:0] PE[12:0] Port E Bit[12:0] PF[5:0] Port F Bit[5:0] er USB n in USB-DM USB DM Signal USB-DP UVCC USB DP Signal w l l A Type n E h c Te I/O I/O I/O I/O A I/O A I/O USB 3.3V power P Headphone Left Output AO Headphone Right Output AO Headphone Common Reference AO Headphone Common Reference Feedback Input AI HPVCC Headphone Amplifier Power P FMINL FM in Left Input AI FMINR FM in Right Input AI LINEIN Line in Input AI MICIN Microphone Input AI VRA1 Reference Voltage AO VRA2 Reference Voltage AO AVCC Analog Power P AGND Analog Ground G DA_MCLK Digital Audio Master Clock O DA_BCLK Digital Audio sample rate Clock I/O Audio Codec HPL r o F HPR HPCOM HPCOMFB s t s a i EINTF5 Digital Audio F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 15 Pin Description DA_LRCK Digital Audio Left & Right channel Clock I/O DA_IN Digital Audio Data Out I DA_OUT Digital Audio Data in O RSB_SCK RSB Clock I/O RSB_SDA RSB Data I/O TPX1 Touch Panel X1 Input AI TPX2 Touch Panel X2 Input AI TPY1 Touch Panel Y1 Input AI TPY2 Touch Panel Y1 Input AI TV CVBS Output AO TVIN0 TV CVBS Input 0 AI TVIN1 TV CVBS Input 1 TVAVCC TV Analog VCC for TVIN and TVOUT P TVAGND TV Analog GND for TVIN and TVOUT G TVIN_VRP TV Input Voltage Reference Positive AI TVIN_VRN TV Input Voltage Reference Negative AI RSB Touch Panel s t s a i TV-Out TVOUT s u th TV-IN er Clock n in HOSCI 24MHz Crystal Input HOSCO n E h c Te AI AI 24MHz Crystal Output AO Chip Reset Signal I Pulse Width Modulation Output O ADC Input for Key I LCD[7:2] LCD Data Bus Bit[7:2] O LCD[15:10] LCD Data Bus Bit[15:10] O LCD[23:18] LCD Data Bus Bit[23:18] O LCD_CLK LCD Clock O LCD_DE LCD Data Enable O LCD_HSYNC LCD Horizon Sync O LCD_VSYNC LCD Vertical Sync O SPIx_MOSI SPI Master Output Slave Input I/O SPIx_MISO SPI Master Input Slave Output I/O SPIx_CS SPI Chip Select Signal I/O SPIx_CLK SPI Clock I/O Miscellaneous Signal llw RESET# A r PWM[1:0] ADC Fo LRADC0 LCD SPI(x=[1:0]) F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 16 Pin Description UART(x=[2:0]) UARTx_TX UART Data Transmit O UARTx_RX UART Data Receive I UARTx_CTS UART Clear to Send I UARTx_RTS UART Request to Send O IR Receive Signal I CSI_PCLK CSI Pixel Clock signal I CSI_HSYNC CSI Horizontal Synchronization Signal I CSI_VSYNC CSI Vertical Synchronization Signal I CSI_D[7:0] CSI Data Bit[7:0] I SDC0_D[3:0] SD/MMC/SDIO Data Bit[3:0] I/O SDC0_CLK SD/MMC/SDIO Clock O SDC0_CMD SD/MMC/SDIO Command I/O SDC1_D0 SD/MMC/SDIO Data Bit0 I/O SDC1_CLK SD/MMC/SDIO Clock O SDC1_CMD SD/MMC/SDIO Command I/O IR IR_RX CSI TWI(x=[2:0])(Open-Drain) TWIx-SCK n in TWIx-SDA r o F er TWI Clock TWI Data w l l A F1C200s Datasheet(Revision 1.1) s t s a i s u th SDC n E h c Te I/O I/O Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 17 Electrical Characteristics 5. Electrical Characteristics 5.1. Absolute Maximum Ratings Functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Symbol Parameter Min Max Unit Tstg Storage Temperature -65 150 °C II/O In/Out current for input and output -40 40 mA VCC-IO Power Supply for I/O -0.3 3.6 V AVCC Power Supply for Codec -0.3 3.1 V TV_AVCC Power Supply for TV -0.3 3.6 V VDD-CORE Power Supply for Internal Digital Logic -0.3 1.3 V UVCC Power Supply for USB 3.6 V VCC-DRAM Power Supply for DDR1 2.7 V s t s a i s u th n E h c Te -0.3 -0.3 5.2. Recommended Operating Conditions Symbol Parameter Ta VCC-IO AVCC TV_AVCC VDD-CORE r o F UVCC VCC-DRAM er Min Typ Max Unit Ambient Operating Temperature[Commercial] -20 - 85 °C Power Supply for I/O 3.0 3.3 3.6 V 2.5 2.8 3.1 V Power Supply for TV 3.0 3.3 3.6 V Power Supply for Internal Digital Logic 1.0 1.1 1.2 V Power Supply for USB 3.0 3.3 3.6 V Power Supply for DDR1 2.3 2.5 2.7 V n in w l l A Power Supply for Codec 5.3. DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VIH High-Level Input Voltage 0.7 * VCC-IO - VCC-IO + 0.3 V VIL Low-Level Input Voltage -0.3 - 0.3 * VCC-IO V RPU Input pull-up resistance 50 100 150 KΩ RPD Input pull-down resistance 50 100 150 KΩ IIH High-Level Input Current - - 10 uA IIL Low-Level Input Current - - 10 uA VOH High-Level Output Voltage VCC-IO -0.2 - VCC-IO V VOL Low-Level Output Voltage 0 - 0.2 V IOZ Tri-State Output Leakage Current -10 - 10 uA F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 18 Electrical Characteristics CIN Input Capacitance - - 5 pF COUT Output Capacitance - - 5 pF 5.4. Oscillator Electrical Characteristics The 24.000MHz crystal is connected between the OSC24MI and OSC24MO.The following table lists the 24.000MHz crystal specifications. Symbol Parameter Min Typ Max Unit 1/(tCPMAIN) Crystal Oscillator Frequency Range - 24.000 - MHz tST Startup Time - - - ms Frequency Tolerance at 25°C -50 - 50 ppm Oscillation Mode Fundamental Maximum Change Over Temperature Range -50 - PON Drive Level - - CL Equivalent Load Capacitance 12 18 RS Series Resistance(ESR) Duty Cycle CM Motional Capacitance CSHUT Shunt Capacitance RBIAS Internal Bias Resistor r e n n i lw 5.5. Power Up/Down Sequence - 25 30 50 - - 5 0.4 us 50 ppm h t n E h c Te - s t s a i 300 22 - uW pF Ω 70 % - pF 6.5 7.5 pF 0.5 0.6 MΩ The external voltage regulator and other power-on devices must provide the processor with a specific sequence of power and resets to ensure proper operations. l A r Power Up Sequence Fo 1.1V VDD-CORE 2.5V VCC-DRAM 2.8V AVCC 3.3V TV_AVCC 3.3V VCC-IO No special restrictions for power down sequence. F1C200s Datasheet(Revision 1.1) Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 19 Pin Assignment 6. Pin Assignment 6.1. Pin Map s t s a i s u th n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 20 Pin Assignment 6.2. Package Dimension The following figure shows the top, bottom, and side views of F1C200s package dimension. s t s a i s u th n i lw l A r Fo r e n F1C200s Datasheet(Revision 1.1) n E h c Te Copyright © 2017 Allwinner Technology Co., Ltd. All Rights Reserved Page 21
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