MINI58-ZDE

MINI58DE ARM® Cortex® -M0 32-bit Microcontroller NuMicro® Family Mini58DE Series Datasheet Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com May. 09, 2018 Page 1 of 84 Rev.1.03 MINI58DE SERIES DATASHEET The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. MINI58DE Table of Contents 1 GENERAL DESCRIPTION ....................................................................... 7 2 FEATURES ......................................................................................... 8 3 ABBREVIATIONS ................................................................................ 11 4 PARTS INFORMATION LIST AND PIN CONFIGURATION .............................. 12 4.1 NuMicro® Mini58 Series Naming Rule .............................................................12 4.2 NuMicro® Mini58 Series Product Selection Guide ...............................................13 4.3 PIN CONFIGURATION ..............................................................................14 4.3.1 LQFP 48-pin ................................................................................................... 14 4.3.2 QFN 33-pin .................................................................................................... 16 4.3.3 TSSOP 20-pin ................................................................................................. 18 Pin Description ........................................................................................19 4.4 BLOCK DIAGRAM ............................................................................... 24 5 NuMicro® Mini58 Block Diagram ...................................................................24 5.1 Functional Description ........................................................................... 25 6 6.1 ARM® Cortex® -M0 Core..............................................................................25 6.1.1 Overview ....................................................................................................... 25 6.1.2 Features ........................................................................................................ 25 6.2 System Manager ......................................................................................27 MINI58DE SERIES DATASHEET 6.2.1 Overview ....................................................................................................... 27 6.2.2 System Reset.................................................................................................. 27 6.2.3 Power Modes and Wake-up Sources ...................................................................... 33 6.2.4 System Power Architecture ................................................................................. 35 6.2.5 System Memory Mapping ................................................................................... 37 6.2.6 Memory Organization ........................................................................................ 37 6.2.7 System Timer (SysTick) ..................................................................................... 39 6.2.8 Nested Vectored Interrupt Controller (NVIC) ............................................................. 40 6.2.9 System Control Registers (SCB) ........................................................................... 43 6.3 Clock Controller .......................................................................................44 6.3.1 Overview ....................................................................................................... 44 6.3.2 Auto-trim........................................................................................................ 46 6.3.3 System Clock and SysTick Clock .......................................................................... 46 6.3.4 Peripherals Clock Source Selection ....................................................................... 47 6.3.5 Power-down Mode Clock .................................................................................... 49 May. 09, 2018 Page 2 of 84 Rev.1.03 MINI58DE 6.3.6 Flash Memory Controller (FMC) ....................................................................51 6.4 6.4.1 Overview ....................................................................................................... 51 6.4.2 Features ........................................................................................................ 51 General Purpose I/O (GPIO) ........................................................................52 6.5 6.5.1 Overview ....................................................................................................... 52 6.5.2 Features ........................................................................................................ 52 Timer Controller (TMR) ..............................................................................53 6.6 6.6.1 Overview ....................................................................................................... 53 6.6.2 Features ........................................................................................................ 53 Enhanced PWM Generator .........................................................................54 6.7 6.7.1 Overview ....................................................................................................... 54 6.7.2 Features ........................................................................................................ 54 Watchdog Timer (WDT)..............................................................................57 6.8 6.8.1 Overview ....................................................................................................... 57 6.8.2 Features ........................................................................................................ 57 Window Watchdog Timer (WWDT) ................................................................58 6.9 6.9.1 Overview ....................................................................................................... 58 6.9.2 Features ........................................................................................................ 58 6.10 UART Controller (UART) ............................................................................59 Overview ....................................................................................................... 59 6.10.2 Features ........................................................................................................ 59 I2C Serial Interface Controller (I2C) ................................................................60 6.11.1 Overview ....................................................................................................... 60 6.11.2 Features ........................................................................................................ 60 6.12 Serial Peripheral Interface (SPI) ....................................................................61 6.12.1 Overview ....................................................................................................... 61 6.12.2 Features ........................................................................................................ 61 6.13 Analog-to-Digital Converter (ADC) .................................................................62 6.13.1 Overview ....................................................................................................... 62 6.13.2 Features ........................................................................................................ 62 6.14 Analog Comparator (ACMP) ........................................................................63 6.14.1 Overview ....................................................................................................... 63 6.14.2 Features ........................................................................................................ 63 APPLICATION CIRCUIT ........................................................................ 64 May. 09, 2018 Page 3 of 84 Rev.1.03 MINI58DE SERIES DATASHEET 6.10.1 6.11 7 Frequency Divider Output ................................................................................... 49 MINI58DE ELECTRICAL CHARACTERISTICS .......................................................... 65 8 8.1 Absolute Maximum Ratings .........................................................................65 8.2 DC Electrical Characteristics ........................................................................66 8.3 AC Electrical Characteristics ........................................................................71 8.3.1 External Input Clock .......................................................................................... 71 8.3.2 External 4~24 MHz High Speed Crystal (HXT) .......................................................... 71 8.3.3 External 32.768 kHz XTAL Oscillator (LXT) .............................................................. 71 8.3.4 Typical Crystal Application Circuits ........................................................................ 71 8.3.5 22.1184 MHz Internal High Speed RC Oscillator (HIRC) .............................................. 72 8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC) ....................................................... 73 Analog Characteristics ...............................................................................74 8.4 8.4.1 10-bit SARADC................................................................................................ 74 8.4.2 LDO & Power Management ................................................................................. 75 8.4.3 Low Voltage Reset ........................................................................................... 75 8.4.4 Brown-out Detector ........................................................................................... 76 8.4.5 Power-on Reset ............................................................................................... 76 8.4.6 Comparator .................................................................................................... 77 8.5 Flash DC Electrical Characteristics ................................................................78 PACKAGE DIMENSIONS ...................................................................... 79 9 MINI58DE SERIES DATASHEET 9.1 48-pin LQFP ...........................................................................................79 9.2 33-pin QFN (4 mm x 4 mm) .........................................................................80 9.3 33-pin QFN (5 mm x 5 mm) .........................................................................81 9.4 20-pin TSSOP .........................................................................................82 10 REVISION HISTORY ............................................................................ 83 May. 09, 2018 Page 4 of 84 Rev.1.03 MINI58DE List of Figures ® Figure 4.1-1 NuMicro Mini58 Series Naming Rule ....................................................................... 12 ® Figure 4.3-1 NuMicro Mini58 Series LQFP 48-pin Diagram......................................................... 14 ® Figure 4.3-2 NuMicro Mini58 Series LQFP 48-pin Multi-Function Diagram ................................. 15 ® Figure 4.3-3 NuMicro Mini58 Series QFN 33-pin Diagram .......................................................... 16 ® Figure 4.3-4 NuMicro Mini58 Series QFN 33-pin Multi-funciton Diagram .................................... 17 ® Figure 4.3-5 NuMicro Mini58 Series TSSOP 20-pin Diagram ...................................................... 18 ® Figure 4.3-6 NuMicro Mini58 Series TSSOP 20-pin Multi-function Diagram ............................... 18 ® Figure 5.1-1 NuMicro Mini58 Series Block Diagram .................................................................... 24 Figure 6.1-1 Functional Block Diagram .......................................................................................... 25 Figure 6.2-1 System Rese Resources ........................................................................................... 28 Figure 6.2-2 nRESET Reset Waveform ......................................................................................... 30 Figure 6.2-3 Power-on Reset (POR) Waveform ............................................................................ 30 Figure 6.2-4 Low Voltage Reset (LVR) Waveform ......................................................................... 31 Figure 6.2-5 Brown-out Detector (BOD) Waveform ....................................................................... 32 Figure 6.2-6 Power Mode State Machine ...................................................................................... 33 ® Figure 6.2-7 NuMicro Mini58 Series Power Architecture Diagram .............................................. 36 Figure 6.3-1 Clock Generator Block Diagram ................................................................................ 44 Figure 6.3-2 Clock Generator Global View Diagram ...................................................................... 45 Figure 6.3-3 System Clock Block Diagram .................................................................................... 46 Figure 6.3-4 SysTick Clock Control Block Diagram ....................................................................... 47 Figure 6.3-6 Clock Source of Frequency Divider ........................................................................... 50 Figure 6.3-7 Block Diagram of Frequency Divider ......................................................................... 50 Figure 6.7-1 Application Circuit Diagram ....................................................................................... 56 Figure 8.3-1 Mini58 Typical Crystal Application Circuit.................................................................. 72 Figure 8.4-1 Power-up Ramp Condition ........................................................................................ 77 May. 09, 2018 Page 5 of 84 Rev.1.03 MINI58DE SERIES DATASHEET Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK ................................................... 48 MINI58DE List of Tables Table 3-1 List of Abbreviations ....................................................................................................... 11 ® Table 4.2-1 NuMicro Mini58 Series Product Selection Guide ...................................................... 13 ® Table 4.4-1 NuMicro Mini58 Series Pin Description ..................................................................... 22 Table 6.2-1 Reset Value of Registers ............................................................................................ 29 Table 6.2-2 Power Mode Difference Table .................................................................................... 33 Table 6.2-3 Clocks in Power Modes .............................................................................................. 34 Table 6.2-4 Condition of Entering Power-down Mode Again ......................................................... 35 Table 6.2-5 Memory Mapping Table .............................................................................................. 37 Table 6.2-6 Address Space Assignments for On-Chip Modules ................................................... 38 Table 6.2-7 Exception Model ......................................................................................................... 41 Table 6.2-8 System Interrupt Map Vector Table ............................................................................ 42 Table 6.2-9 Vector Table Format ................................................................................................... 42 Table 6.3-1 Peripheral Clock Source Selection Table ................................................................... 49 MINI58DE SERIES DATASHEET May. 09, 2018 Page 6 of 84 Rev.1.03 MINI58DE 1 GENERAL DESCRIPTION ® ® The NuMicro Mini58 series is pin-to-pin and function compatible with the NuMicro Mini51 series, ® ® the 32-bit microcontroller (MCU) embedded with the ARM Cortex -M0 core. The Mini58 series can bridge the gap and replace the cost equivalent to traditional 8- and 16-bit microcontroller by 32-bit performance and rich functions. The Mini58 series supports a wide range of applications from low-end, price sensitive designs to computing-intensive ones and provides advanced highend features in economical products. The Mini58 series can run up to 50 MHz which is faster than 24 MHz in Mini51 series, and operate at a wide voltage range of 2.5V ~ 5.5V and temperature range of -40℃ ~ +105℃. For the Mini58 series, the embedded program flash size upgrades from 16 Kbytes to 32 Kbytes and SRAM upgrades from 2 Kbytes to 4 Kbytes. The Mini58 series also offers size configurable Data Flash (shared with program flash), and 2.5 Kbytes flash for the ISP. The Mini58 series has many high-performance peripheral functions, such as 22.1184 MHz internal RC oscillator (±1% accuracy), I/O port with up to 30 pins, four 32-bit timers, two UARTs 2 with the RS485 function and IrDA function interface, one SPI interface, two I C interfaces, up to three 16-bit PWM generators providing six channels, an 8-channel 10-bit ADC, Watchdog Timer, Window Watchdog Timer, two Analog Comparators and a Brown-out Detector. All these peripherals have been incorporated into the Mini58 series to reduce component count, board space and system cost. Compared to the Mini51 series, the Mini58 series supports additional one 2 UART and one I C interface for better and more flexible connectivity applications. Additionally, the Mini58 series is equipped with ISP (In-System Programming) and ICP (In-Circuit Programming) functions, which allow the user to update the program memory without removing the chip from the actual end product. The Mini58 series also supports In-Application-Programming (IAP) function, user switches the code executing without the chip reset after the embedded flash updated. MINI58DE SERIES DATASHEET May. 09, 2018 Page 7 of 84 Rev.1.03 MINI58DE 2 FEATURES  Core ® ®  ARM Cortex -M0 core running up to 50 MHz  One 24-bit system timer  Supports low power Idle mode  A single-cycle 32-bit hardware multiplier  NVIC for the 32 interrupt inputs, each with 4-level of priority  Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints  Built-in LDO for wide operating voltage: 2.5V to 5.5V  Memory   32 KB Flash memory for program memory (APROM)  Configurable Flash memory for data memory (Data Flash)  2.5 KB Flash for loader (LDROM)  4 KB SRAM for internal scratch-pad RAM (SRAM) Clock Control  Programmable system clock source  MINI58DE SERIES DATASHEET  Support 4 ~ 24 MHz external high speed crystal oscillator (HXT) for precise timing operation  Support 32.768 kHz external low speed crystal oscillator (LXT) for idle wake-up and system operation clock  Built-in 22.1184 MHz internal high speed RC oscillator (HIRC) for system 0 operation (1% accuracy at 25 C, 5V)   Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-up operation  PLL allowing CPU operation up to the maximum 50 MHz I/O Port  Up to 30 general-purpose I/O (GPIO) pins for LQFP-48 package  Four I/O modes:  Quasi-bidirectional input/output  Push-Pull output  Open-Drain output  Input only with high impendence Optional Schmitt trigger input Timer  May. 09, 2018 Dynamically calibrating the HIRC OSC to 22.1184 MHz ±1% from -40℃ to 105℃ by external 32.768K crystal oscillator (LXT)    Switch clock sources on-the-fly Provides two channel 32-bit Timers; one 8-bit pre-scaler counter with 24-bit uptimer for each timer Page 8 of 84 Rev.1.03 MINI58DE      May. 09, 2018 Supports Event Counter mode  Supports Toggle Output mode  Supports external trigger in Pulse Width Measurement mode  Supports external trigger in Pulse Width Capture mode WDT (Watchdog Timer)  Programmable clock source and time-out period  Supports wake-up function in Power-down mode and Idle mode  Interrupt or reset selectable on watchdog time-out WWDT (Window Watchdog Timer)  6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the WWDT time-out window period flexible  Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of WWDT counter PWM  Up to three built-in 16-bit PWM generators, providing six PWM outputs or three complementary paired PWM outputs  Individual clock source, clock divider, 8-bit pre-scalar and dead-time generator for each PWM generator  PWM interrupt synchronized to PWM period  Supports edge-alignment or center-alignment  Supports fault detection UART (Universal Asynchronous Receiver/Transmitters)  Two UART devices  Buffered receiver and transmitter, each with 16-byte FIFO  Optional flow control function (CTSn and RTSn)  Supports IrDA (SIR) function  Programmable baud-rate generator up to 1/16 system clock  Supports RS-485 function MINI58DE SERIES DATASHEET   SPI (Serial Peripheral Interface)  One SPI device  Master up to 25 MHz, and Slave up to 10 MHz  Supports Master/Slave mode  Full-duplex synchronous serial data transfer  Variable length of transfer data from 1 to 32 bits  MSB or LSB first data transfer  RX latching data can be either at rising edge or at falling edge of serial clock  TX sending data can be either at rising edge or at falling edge of serial clock  Supports Byte Suspend mode in 32-bit transmission 2 IC Page 9 of 84 Rev.1.03 MINI58DE   2  Two I C devices  Supports Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer  Programmable clocks allow for versatile rate control  Supports multiple address recognition (four slave addresses with mask option) ADC (Analog-to-Digital Converter)  10-bit SAR ADC with 250 kSPS  Up to 8-ch single-end input and one internal input from band-gap  Conversion started either by software trigger or external pin trigger Analog Comparator  Two analog comparators with programmable 16-level internal voltage reference  Built-in CRV (comparator reference voltage)  ISP (In-System Programming), ICP (In-Circuit Programming), and IAP (In-ApplicationProgramming) update  BOD (Brown-out Detector) MINI58DE SERIES DATASHEET  With 4 programmable threshold levels: 4.4V/3.7V/2.7V/2.2V  Supports Brown-out interrupt and reset option  96-bit unique ID  LVR (Low Voltage Reset)  Threshold voltage level: 2.0V  Operating Temperature: -40℃~105℃  Reliability: EFT > ± 4KV, ESD HBM pass 4KV  Packages: May. 09, 2018  Green package (RoHS)  48-pin LQFP (7x7), 33-pin QFN (5x5) , 33-pin QFN (4x4), 20-pin TSSOP Page 10 of 84 Rev.1.03 MINI58DE 3 ABBREVIATIONS Description ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AHB Advanced High-Performance Bus APB Advanced Peripheral Bus BOD Brown-out Detection DAP Debug Access Port FIFO First In, First Out FMC Flash Memory Controller GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 22.1184 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator ICP In Circuit Programming ISP In System Programming ISR Interrupt Service Routine LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) LXT 32.768 kHz External Low Speed Crystal Oscillator NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PLL Phase-Locked Loop PWM Pulse Width Modulation SPI Serial Peripheral Interface SPS Samples per Second TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID WDT Watchdog Timer WWDT Window Watchdog Timer MINI58DE SERIES DATASHEET Acronym Table 3-1 List of Abbreviations May. 09, 2018 Page 11 of 84 Rev.1.03 MINI58DE 4 4.1 PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro® Mini58 Series Naming Rule ARM–Based 32-bit Microcontroller Mini58-X X X CPU Core Corte® -M0 Temperature E: -40oC ~ +105oC Flash ROM 58 : 32 KB Flash ROM Reserved Package Type L: LQFP 48 7x7mm Z: QFN 33 5x5mm T: QFN 33 4x4mm F: TSSOP 20 ® Figure 4.1-1 NuMicro Mini58 Series Naming Rule MINI58DE SERIES DATASHEET May. 09, 2018 Page 12 of 84 Rev.1.03 MINI58DE 4.2 NuMicro® Mini58 Series Product Selection Guide ISP Part Number APROM RAM Data Flash Loader ROM Connectivity I/O Timer Comp. PWM UART SPI ADC 2 IC IRC ISP 22.1184 ICP MHz Package MINI58LDE 32 KB 4 KB Configurable 2.5 KB up to 30 2x32bit 2 1 2 2 6 8x10bit v v LQFP48 MINI58ZDE 32 KB 4 KB Configurable 2.5 KB up to 29 2x32bit 2 1 2 2 6 8x10bit v v QFN33(5x5) MINI58TDE 32 KB 4 KB Configurable 2.5 KB up to 29 2x32bit 2 1 2 2 6 8x10bit v v QFN33(4x4) MINI58FDE 32 KB 4 KB Configurable 2.5 KB up to 17 2x32bit 2 1 2 - 6 4x10bit v v TSSOP20 ® Table 4.2-1 NuMicro Mini58 Series Product Selection Guide MINI58DE SERIES DATASHEET May. 09, 2018 Page 13 of 84 Rev.1.03 MINI58DE NC P0.4 P0.5 P0.6 P0.7 NC P4.7 P4.6 NC NC P2.6 P2.5 36 35 34 33 32 31 30 29 28 27 26 25 LQFP 48-pin P0.1 37 24 P2.4 P0.0 38 23 P2.3 NC 39 22 P2.2 NC 40 21 NC P5.3 41 20 P5.2 19 P5.5 18 LDO_CAP VDD 42 AVDD 43 P1.0 44 17 VSS P1.2 45 16 P5.0 P1.3 46 15 P5.1 P1.4 47 14 P3.6 NC 48 13 NC 2 3 4 5 6 7 8 9 10 11 12 P1.5 P3.0 AVSS P5.4 P3.1 P3.2 P3.4 P3.5 NC NC MINI58DE SERIES DATASHEET nRESET LQFP 48-Pin 1 4.3.1 PIN CONFIGURATION NC 4.3 ® Figure 4.3-1 NuMicro Mini58 Series LQFP 48-pin Diagram May. 09, 2018 Page 14 of 84 Rev.1.03 NC P0.4 / SPI0_SS / PWM0_CH5 P0.5 / SPI0_MOSI / PWM0_CH4 P0.6 / SPI0_MISO / PWM0_CH1 P0.7 / SPI0_CLK / PWM0_CH0 NC P4.7 / ICE_DAT / UART1_TXD P4.6 / ICE_CLK / UART1_RXD NC NC P2.6 / PWM0_CH4 / ACMP1_O P2.5 / UART1_TXD / PWM0_CH3 36 35 34 33 32 31 30 29 28 27 26 25 MINI58DE UART0_RXD / UART0_nRTS / SPI0_SS / P0.1 37 24 P2.4 / UART1_RXD / PWM0_CH2 UART0_TXD / UART0_nCTS / P0.0 38 23 P2.3 / PWM0_CH1 / I2C1_SDA NC 39 22 P2.2 / PWM0_CH0 / I2C1_SCL NC 40 21 NC ADC_CH0 / P5.3 41 20 P5.2 / INT1 VDD 42 19 P5.5 AVDD 43 18 LDO_CAP ACMP0_P1 / ADC_CH1 / P1.0 44 17 VSS PWM0_CH0 / ACMP0_P2 / UART0_RXD / ADC_CH2 / P1.2 45 16 P5.0 / XT1_IN / I2C1_SDA / UART0_TXD PWM0_CH1 / ACMP0_P3 / UART0_TXD / ADC_CH3 / P1.3 46 15 P5.1 / XT1_OUT / I2C1_SCL / UART0_RXD PWM0_CH4 / ACMP0_N / UART1_RXD / ADC_CH4 / P1.4 47 14 P3.6 / TM1_EXT / CLKO / ACMP0_O NC 48 13 NC 1 2 3 4 5 6 7 8 9 10 11 12 NC nRESET ADC_CH6 / ACMP1_N / P3.0 AVSS P5.4 ADC_CH7 / ACMP1_P0 / P3.1 ACMP1_P1 / STADC / TM0_EXT / INT0 / P3.2 ACMP1_P2 / I2C0_SDA / TM0_CNT_OUT / P3.4 ACMP1_P3 / I2C0_SCL / TM1_CNT_OUT / P3.5 NC NC MINI58DE SERIES DATASHEET ACMP0_P0 / UART1_TXD / ADC_CH5 / P1.5 LQFP 48-Pin ® Figure 4.3-2 NuMicro Mini58 Series LQFP 48-pin Multi-Function Diagram May. 09, 2018 Page 15 of 84 Rev.1.03 MINI58DE P0.4 P0.5 P0.6 P0.7 P4.7 P4.6 P2.6 P2.5 23 22 21 20 19 18 17 Top Transparent View 24 QFN 33-pin P0.1 25 16 P2.4 P0.0 26 15 P2.3 P5.3 27 14 P2.2 VDD 28 13 P5.2 P1.0 29 12 VSS P1.2 30 11 P5.0 P1.3 31 10 P5.1 P1.4 32 9 P3.6 QFN 33-Pin 1 2 3 4 5 6 7 8 nRESET P3.0 P5.4 P3.1 P3.2 P3.4 P3.5 33 VSS P1.5 4.3.2 ® Figure 4.3-3 NuMicro Mini58 Series QFN 33-pin Diagram MINI58DE SERIES DATASHEET May. 09, 2018 Page 16 of 84 Rev.1.03 P0.4 / SPI0_SS / PWM0_CH5 P0.5 / SPI0_MOSI / PWM0_CH4 P0.6 / SPI0_MISO / PWM0_CH1 P0.7 / SPI0_CLK / PWM0_CH0 P4.7 / ICE_DAT / UART1_TXD P4.6 / ICE_CLK / UART1_RXD P2.6 / PWM0_CH4 / ACMP1_O P2.5 / UART1_TXD / PWM0_CH3 23 22 21 20 19 18 17 Top Transparent View 24 MINI58DE UART0_RXD / UART0_nRTS / SPI0_SS / P0.1 25 16 P2.4 / UART1_RXD / PWM0_CH2 UART0_TXD / UART0_nCTS / P0.0 26 15 P2.3 / PWM0_CH1 / I2C1_SDA ADC_CH0 / P5.3 27 14 P2.2 / PWM0_CH0 / I2C1_SCL 28 13 P5.2 / INT1 12 VSS VDD QFN 33-Pin ACMP0_P1 / ADC_CH1 / P1.0 29 PWM0_CH0 / ACMP0_P2 / UART0_RXD / ADC_CH2 / P1.2 30 11 P5.0 / XT1_IN / I2C1_SDA / UART0_TXD PWM0_CH1 / ACMP0_P3 / UART0_TXD / ADC_CH3 / P1.3 31 10 P5.1 / XT1_OUT / I2C1_SCL / UART0_RXD PWM0_CH4 / ACMP0_N / UART1_RXD / ADC_CH4 / P1.4 32 33 VSS 1 2 3 4 5 6 7 8 nRESET ADC_CH6 / ACMP1_N / P3.0 P5.4 ADC_CH7 / ACMP1_P0 / P3.1 ACMP1_P1 / STADC / TM0_EXT / INT0 / P3.2 ACMP1_P2 / I2C0_SDA / TM0_CNT_OUT / P3.4 ACMP1_P3 / I2C0_SCL / TM1_CNT_OUT / P3.5 P3.6 / TM1_EXT / CLKO / ACMP0_O ® Figure 4.3-4 NuMicro Mini58 Series QFN 33-pin Multi-funciton Diagram May. 09, 2018 Page 17 of 84 Rev.1.03 MINI58DE SERIES DATASHEET ACMP0_P0 / UART1_TXD / ADC_CH5 / P1.5 9 MINI58DE 4.3.3 TSSOP 20-pin 1 20 VDD P1.3 2 19 P0.4 P1.4 3 18 P0.5 P1.5 4 17 P0.6 nRESET 5 16 P0.7 P3.2 6 15 P4.7 P3.4 7 14 P4.6 P3.5 8 13 P2.5 P5.1 9 12 P2.4 P5.0 10 11 VSS TSSOP 20-Pin P1.2 ® Figure 4.3-5 NuMicro Mini58 Series TSSOP 20-pin Diagram 1 20 VDD PWM0_CH1 / UART0_TXD / ADC_CH3 / P1.3 2 19 P0.4 / SPI0_SS / PWM0_CH5 PWM0_CH4 / UART1_RXD / ADC_CH4 / P1.4 3 18 P0.5 / SPI0_MOSI / PWM0_CH4 UART1_TXD / ADC_CH5 / P1.5 4 17 P0.6 / SPI0_MISO / PWM0_CH1 nRESET 5 16 P0.7 / SPI0_CLK / PWM0_CH0 STADC / TM0_EXT / INT0 / P3.2 6 15 P4.7 / ICE_DAT / UART1_TXD I2C0_SDA / TM0_CNT_OUT / P3.4 7 14 P4.6 / ICE_CLK / UART1_RXD I2C0_SCL / TM1_CNT_OUT / P3.5 8 13 P2.5 / UART1_TXD / PWM0_CH3 UART0_RXD / I2C1_SCL / XT1_OUT / P5.1 9 12 P2.4 / UART1_RXD / PWM0_CH2 UART0_TXD / I2C1_SDA / XT1_IN / P5.0 10 11 VSS TSSOP 20-Pin MINI58DE SERIES DATASHEET PWM0_CH0 / UART0_RXD / ADC_CH2 / P1.2 ® Figure 4.3-6 NuMicro Mini58 Series TSSOP 20-pin Multi-function Diagram May. 09, 2018 Page 18 of 84 Rev.1.03 MINI58DE 4.4 Pin Description Pin Number LQFP 48-pin QFN 33-pin TSSOP 20-pin 1 --- --- 2 3 4 1 2 3 Pin Name Pin Type Description NC --- Not connected P1.5 I/O General purpose digital I/O pin ADC_CH5 AI ADC analog input pin UART1_TXD O UART1 transmitter output pin ACMP0_P0 AI Analog comparator positive input pin 4 5 --- nRESET I(ST) The Schmitt trigger input pin for hardware device reset. A “Low” on this pin for 768 clock counter of Internal RC 22.1184 MHz while the system clock is running will reset the device. nRESET pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to GND. P3.0 I/O General purpose digital I/O pin ADC_CH6 AI ADC analog input pin ACMP1_N AI Analog comparator negative input pin --- --- AVSS AP Ground pin for analog circuit 6 4 --- P5.4 I/O General purpose digital I/O pin P3.1 I/O General purpose digital I/O pin ADC_CH7 AI ADC analog input pin ACMP1_P0 AI Analog comparator positive input pin P3.2 I/O General purpose digital I/O pin INT0 I External interrupt 0 input pin STADC I ADC external trigger input pin 7 8 9 10 11 5 6 7 8 --- May. 09, 2018 --- 6 7 8 --- TM0_EXT I/O Timer 0 external capture / reset trigger input pin / toggle output pin ACMP1_P1 AI Analog comparator positive input pin (not support in TSSOP20 package) P3.4 I/O General purpose digital I/O pin TM0_CNT_OU T I/O Timer 0 external event counter input pin / toggle output pin I2C0_SDA I/O I2C0 data I/O pin ACMP1_P2 AI Analog comparator positive input pin P3.5 I/O General purpose digital I/O pin TM1_CNT_OU T I/O Timer 1 external event counter input pin / toggle output pin I2C0_SCL I/O I2C0 clock I/O pin ACMP1_P3 AI Analog comparator positive input pin NC --- Not connected Page 19 of 84 Rev.1.03 MINI58DE SERIES DATASHEET 5 MINI58DE Pin Number Pin Name Pin Type Description LQFP 48-pin QFN 33-pin TSSOP 20-pin 12 --- --- NC --- Not connected 13 --- -- NC --- Not connected P3.6 I/O General purpose digital I/O pin ACMP0_O O Analog comparator output pin CLKO O Frequency divider output pin TM1_EXT I/O Timer 1 external capture / reset trigger input pin / toggle output pin P5.1 I/O General purpose digital I/O pin XT1_OUT O The output pin from the internal inverting amplifier. It emits the inverted signal of XT1_IN. I2C1_SCL I/O I2C1 clock I/O pin 14 15 9 10 --- 9 UART0_RXD P5.0 XT1_IN 16 11 I UART0 data receiver input pin I/O General purpose digital I/O pin I 10 The input pin to the internal inverting amplifier. The system clock could be from external crystal or resonator. I2C1_SDA I/O I2C1 data I/O pin UART0_TXD O UART0 transmitter output pin 11 VSS P Ground pin for digital circuit P LDO output pin 12 17 33 MINI58DE SERIES DATASHEET 18 --- --- LDO_CAP 19 --- --- P5.5 I/O User program must enable pull-up resistor in the QFN-33 package. P5.2 I/O General purpose digital I/O pin 20 13 --INT1 I General purpose digital I/O pin 21 22 23 24 --- 14 15 16 May. 09, 2018 --- --- --- 12 External interrupt 1 input pin NC --- Not connected P2.2 I/O General purpose digital I/O pin PWM0_CH0 O PWM0 output of PWM unit I2C1_SCL I/O I2C1 clock I/O pin P2.3 I/O General purpose digital I/O pin PWM0_CH1 O PWM1 output of PWM unit I2C1_SDA I/O I2C1 data I/O pin P2.4 I/O General purpose input/output digital pin UART1_RXD I UART1 data receiver input pin PWM0_CH2 O PWM2 output of PWM unit Page 20 of 84 Rev.1.03 MINI58DE Pin Number LQFP 48-pin 25 26 QFN 33-pin 17 18 TSSOP 20-pin 13 --- Pin Name Pin Type Description P2.5 I/O General purpose digital I/O pin UART1_TXD O UART1 transmitter output pin PWM0_CH3 O PWM3 output of PWM unit P2.6 I/O General purpose digital I/O pin PWM0_CH4 O PWM4 output of PWM unit ACMP1_O O Analog comparator output pin --- --- NC --- Not connected 28 --- --- NC --- Not connected P4.6 I/O General purpose digital I/O pin ICE_CLK I Serial wired debugger clock pin UART1_RXD I UART1 data receiver input pin P4.7 I/O General purpose digital I/O pin ICE_DAT I/O Serial wired debugger data pin UART1_TXD O UART1 transmitter output pin NC --- Not connected P0.7 I/O General purpose digital I/O pin SPI0_CLK I/O SPI serial clock pin PWM0_CH0 O PWM0 output of PWM unit P0.6 I/O General purpose digital I/O pin SPI0_MISO I/O SPI MISO (master in/slave out) pin PWM0_CH1 O PWM1 output of PWM unit P0.5 I/O General purpose digital I/O pin SPI0_MOSI O SPI MOSI (master out/slave in) pin PWM0_CH4 O PWM4 output of PWM unit P0.4 I/O General purpose digital I/O pin SPI0_SS I/O SPI slave select pin PWM0_CH5 O PWM5 output of PWM unit NC --- Not connected P0.1 I/O General purpose digital I/O pin UART0_nRTS O UART0 RTS pin UART0_RXD I UART0 data receiver input pin 29 30 31 32 33 34 35 36 37 38 19 20 --- 21 22 23 24 --- 25 26 May. 09, 2018 14 15 --- 16 17 18 19 --- MINI58DE SERIES DATASHEET 27 --- --- SPI0_SS I/O SPI slave select pin P0.0 I/O General purpose digital I/O pin Page 21 of 84 Rev.1.03 MINI58DE Pin Number LQFP 48-pin QFN 33-pin TSSOP 20-pin Pin Name Pin Type Description UART0_nCTS I UART0 CTS pin UAR0_TXD O UART0 transmitter output pin 39 --- --- NC --- Not connected 40 --- --- NC --- Not connected P5.3 I/O General purpose digital I/O pin 41 27 --ADC_CH0 AI ADC analog input pin VDD P Power supply for digital circuit AVDD P Power supply for analog circuit P1.0 I/O General purpose digital I/O pin ADC_CH1 AI ADC analog input pin ACMP0_P1 AI Analog comparator positive input pin P1.2 I/O General purpose digital I/O pin ADC_CH2 AI ADC analog input pin 42 28 20 43 44 45 MINI58DE SERIES DATASHEET 46 47 48 29 30 31 32 --- --- 1 2 3 -- UART0_RXD I UART0 data receiver input pin ACMP0_P2 AI Analog comparator positive input pin (not support in TSSOP20 package) PWM0_CH0 O PWM0 output of PWM unit P1.3 I/O General purpose digital I/O pin ADC_CH3 AI ADC analog input pin UART0_TXD O UART0 transmitter output pin ACMP0_P3 AI Analog comparator positive input pin (not support in TSSOP20 package) PWM0_CH1 O PWM1 output of PWM unit P1.4 I/O General purpose digital I/O pin ADC_CH4 I/O ADC analog input pin UART1_RXD I UART1 data receiver input pin ACMP0_N AI Analog comparator negative input pin (not support in TSSOP20 package) PWM0_CH4 O PWM4 output of PWM unit NC --- Not connected ® Table 4.4-1 NuMicro Mini58 Series Pin Description [1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin, ST: Schmitt trigger, A: Analog input. May. 09, 2018 Page 22 of 84 Rev.1.03 MINI58DE MINI58DE SERIES DATASHEET May. 09, 2018 Page 23 of 84 Rev.1.03 MINI58DE 5 5.1 BLOCK DIAGRAM NuMicro® Mini58 Block Diagram ® Figure 5.1-1 NuMicro Mini58 Series Block Diagram MINI58DE SERIES DATASHEET May. 09, 2018 Page 24 of 84 Rev.1.03 MINI58DE 6 FUNCTIONAL DESCRIPTION ARM® Cortex® -M0 Core 6.1 6.1.1 Overview ® The Cortex -M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug ® functionality. The processor can execute Thumb code and is compatible with other Cortex -M profile processors. The profile supports two modes - Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset and can be entered as a result of an exception return. Figure 6.1-1 shows the functional controller of the processor. Cortex-M0 components Cortex-M0 processor Nested Vectored Interrupt Controller (NVIC) Interrupts Debug Cortex-M0 Processor core Breakpoint and Watchpoint unit Bus matrix Debugger interface Wakeup Interrupt Controller (WIC) AHB-Lite interface Debug Access Port (DAP) Serial Wire or JTAG debug port 6.1.2 MINI58DE SERIES DATASHEET Figure 6.1-1 Functional Block Diagram Features  A low gate count processor ®  ARMv6-M Thumb instruction set  Thumb-2 technology  ARMv6-M compliant 24-bit SysTick timer  A 32-bit hardware multiplier  System interface supported with little-endian data accesses  Ability to have deterministic, fixed-latency, interrupt handling  Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling  C Application Binary Interface compliant exception model: This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers  May. 09, 2018 Low power Idle mode entry using the Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature Page 25 of 84 Rev.1.03 MINI58DE    NVIC  32 external interrupt inputs, each with four levels of priority  Dedicated Non-maskable Interrupt (NMI) input  Supports for both level-sensitive and pulse-sensitive interrupt lines  Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Idle mode Debug support  Four hardware breakpoints  Two watch points  Program Counter Sampling Register (PCSR) for non-intrusive code profiling  Single step and vector catch capabilities Bus interfaces  Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory  Single 32-bit slave port that supports the DAP (Debug Access Port) MINI58DE SERIES DATASHEET May. 09, 2018 Page 26 of 84 Rev.1.03 MINI58DE 6.2 System Manager 6.2.1 Overview System management includes the following sections: 6.2.2  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers System Reset The system reset can be issued by one of the events listed below. These reset event flags can be read from SYS_RSTSTS register to determine the reset source. Hardware reset can reset chip through peripheral reset signals. Software reset can trigger reset through control registers.  May. 09, 2018  Power-on Reset (POR)  Low level on the nRESET pin  Watchdog Time-out Reset and Window Watchdog Reset (WDT/WWDT Reset)  Low Voltage Reset (LVR)  Brown-out Detector Reset (BOD Reset)  CPU Lockup Reset Software Reset Sources  CHIP Reset will reset whole chip by writing 1 to CHIPRST (SYS_IPRST0[0])  MCU Reset to reboot but keeping the booting setting from APROM or LDROM by writing 1 to SYSRESETREQ (SCS_AIRCR[2])  CPU Reset for Cortex -M0 core Only by writing 1 to CPURST (SYS_IPRST0[1]) ® Page 27 of 84 Rev.1.03 MINI58DE SERIES DATASHEET  Hardware Reset Sources MINI58DE Glitch Filter 36 us nRESET ~50k ohm @5v Power-on Reset VDD Reset Pulse Width 3.2ms Low Voltage Reset AVDD BODRSTEN(SYS_BODCTL[3]) Brown-out Reset WDT/WWDT Reset Reset Pulse Width 64 WDT clocks CPU Lockup Reset Reset Pulse Width 2 system clocks System Reset CHIP Reset CHIPRST(SYS_IPRST0[0]) MCU Reset SYSRSTREQ(SCS_AIRCR[2]) Reset Pulse Width 2 system clocks Software Reset CPU Reset CPURST(SYS_IPRST0[1]) Figure 6.2-1 System Rese Resources ® There are a total of 9 reset sources in the NuMicro family. In general, CPU reset is used to reset ® ® Cortex -M0 only; the other reset sources will reset Cortex -M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6.2-5. MINI58DE SERIES DATASHEET Reset Sources POR nRESET WDT LVR BOD Lockup CHIP MCU CPU Register SYS_RSTSTS 0x001 Bit 1 = 1 Bit 2 = 1 0x001 Bit 4 = 1 Bit 8 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 CHIPRST 0x0 - - - - - - - - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x1 - 0x1 - - - 0x1 - - 0x8 0x8 0x8 0x8 0x8 0x8 0x8 0x8 - (SYS_IPRST0[0]) BODEN (SYS_BODCTL[0]) BODVL (SYS_BODCTL[2:1]) BODRSTEN (SYS_BODCTL[3]) XTLEN (CLK_PWRCTL[1:0]) WDTCKEN (CLK_APBCLK0[0]) HCLKSEL (CLK_CLKSEL0[2:0]) May. 09, 2018 Page 28 of 84 Rev.1.03 MINI58DE WDTSEL 0x3 0x3 - - - - - - - 0x0 - - - - - - - - 0x0 - - - - - - - - 0x0 - - - - - - - - 0x0 0x0 - - - - - - - WDT_CTL 0x0700 0x0700 0x0700 0x0700 0x0700 - 0x0700 - - WDT_ALTCTL 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_RLDCNT 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CTL 0x3F0800 0x3F0800 0x3F0800 0x3F0800 0x3F0800 - 0x3F0800 - - WWDT_STATUS 0x0000 0x0000 0x0000 0x0000 0x0000 - 0x0000 - - WWDT_CNT 0x3F 0x3F 0x3F 0x3F 0x3F - 0x3F - - BS Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 - - FMC_DFBA Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 - Reload from CONFIG1 - - CBS Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 - - Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 - Reload base on CONFIG0 - - (CLK_CLKSEL1[1:0]) XLTSTB (CLK_STATUS[0]) PLLSTB (CLK_STATUS[2]) LIRCSTB 0x0 (CLK_STATUS[3]) HIRCSTB (CLK_STATUS[4]) CLKSFAIL (CLK_STATUS[7]) (FMC_ISPCTL[1]) ISPEN (FMC_ISPCTL[16]) VECMAP  (FMC_ISPSTS[20:9]) Other Peripheral Registers Reset Value FMC Registers Reset Value - Note: ‘-‘ means that the value of register keeps original setting. Table 6.2-1 Reset Value of Registers 6.2.2.1 nRESET Reset The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 VDD and the state keeps longer than 36 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps longer than 36 us (glitch filter). The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform. May. 09, 2018 Page 29 of 84 Rev.1.03 MINI58DE SERIES DATASHEET (FMC_ISPSTS[2:1)) MINI58DE nRESET 0.7 VDD 36 us 0.2 VDD 36 us nRESET Reset Figure 6.2-2 nRESET Reset Waveform 6.2.2.2 Power-On Reset (POR) The Power-on reset (POR) is used to generate a stable system reset signal and forces the system to be reset when power-on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the PORF (SYS_RSTSTS[0]) will be set to 1 to indicate there is a POR reset event. The PORF (SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows the waveform of Power-On reset. VPOR MINI58DE SERIES DATASHEET 0.1V VDD Power On Reset Figure 6.2-3 Power-on Reset (POR) Waveform 6.2.2.3 Low Voltage Reset (LVR) Low Voltage Reset detects AVDD during system operation. When the AVDD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR reset will control the chip in reset state until the AVDD voltage rises above VLVR and the state keeps longer than De-glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform. May. 09, 2018 Page 30 of 84 Rev.1.03 MINI58DE AVDD VLVR T1 T2 ( < de-glitch time) ( = de-glitch time) Low Voltage Reset T3 ( = de-glitch time) Figure 6.2-4 Low Voltage Reset (LVR) Waveform 6.2.2.4 Brown-out Detector Reset (BOD Reset) May. 09, 2018 Page 31 of 84 Rev.1.03 MINI58DE SERIES DATASHEET If the Brown-out Detector (BOD) function is enabled by setting the Brown-out Detector Enable Bit BODEN (SYS_BODCTL[0]), Brown-Out Detector function will detect AVDD during system operation. When the AVDD voltage is lower than VBOD which is decided by BODEN (SYS_BODCTL[0]) and BODVL (SYS_BODCTL[2:1]) and the state keeps longer than De-glitch time (Max(20*HCLK cycles, 1*LIRC cycle)), chip will be reset. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De-glitch time. The default value of BODEN, BODVL and BODRSTEN is set by flash controller user configuration register CBOVEXT (CONFIG0[23]), CBOV (CONFIG0[22:21]) and CBORST (CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector waveform. MINI58DE AVDD VBODH VBODL Hysteresis T1 T2 (< de-glitch time) (= de-glitch time) BODOUT T3 (= de-glitch time) BODRSTEN Brown-out Reset Figure 6.2-5 Brown-out Detector (BOD) Waveform 6.2.2.5 Watch Dog Timer Reset MINI58DE SERIES DATASHEET In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability. The watch dog timer (WDT) is widely used to check if the system works fine. If the MCU is crashed or out of control, it may cause the watch dog time-out. User may decide to enable system reset during watch dog time-out to recover the system and take action for the system crash/out-of-control after reset. Software can check if the reset is caused by watch dog time-out to indicate the previous reset is a watch dog reset and handle the failure of MCU after watch dog time-out reset by checking WDTRF (SYS_RSTSTS[2]). 6.2.2.6 CPU Lockup Reset CPU enters lockup status after CPU produces hardfault at hardfault handler and chip gives immediate indication of seriously errant kernel software. This is the result of the CPU being locked because of an unrecoverable exception following the activation of the processor’s built in system state protection hardware. When chip enters debug mode, the CPU lockup reset will be ignored. 6.2.2.7 CPU Reset, CHIP Reset and SYSTEM Reset ® The CPU Reset means only Cortex -M0 core is reset and all other peripherals remain the same status after CPU reset. User can set the CPURST (SYS_IPRST0[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power-On Reset. The CPU and all peripherals are reset and BS May. 09, 2018 Page 32 of 84 Rev.1.03 MINI58DE (FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG setting. User can set the CHIPRST (SYS_IPRST0[0]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS (FMC_ISPCTL[1]) will not be reloaded from CONFIG setting and keep its original software setting for booting from APROM or LDROM. User can set the SYSRESETREQ (SCS_AIRCR[2]) to 1 to assert the MCU Reset. 6.2.3 Power Modes and Wake-up Sources There are several wake-up sources in Idle mode and Power-down mode. Table 6.2-2 lists the available clocks for each power mode. Normal Mode Idle Mode Power-down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC. SRAM content retended. Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction. CPU sets sleep mode enable and power down enable and executes WFI instruction. Wake-up Sources N/A All interrupts WDT, I²C, Timer, UART, BOD and GPIO Available Clocks All All except CPU clock LXT and LIRC After Wake-up N/A CPU back to normal mode CPU back to normal mode Table 6.2-2 Power Mode Difference Table System reset released Normal Mode CPU Clock ON HXT, HIRC, LXT, LIRC, HCLK, PCLK ON Flash ON CPU executes WFI Interrupts occur 1. SLEEPDEEP (SCS_SCR[2]) = 1 2. PDEN (CLK_PWRCTL[7]) = 1 and PDWKIF (CLK_PWRCTL[8]) = 1 3. CPU executes WFI Idle Mode Wake-up events occur Power-down Mode CPU Clock OFF HXT, HIRC, LXT, LIRC, HCLK, PCLK ON Flash Halt CPU Clock OFF HXT, HIRC, HCLK, PCLK OFF LXT, LIRC ON Flash Halt Figure 6.2-6 Power Mode State Machine May. 09, 2018 Page 33 of 84 Rev.1.03 MINI58DE SERIES DATASHEET Power Mode MINI58DE 1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode. 2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode. 3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on. 4. If WDT clock source is selected as LIRC and LIRC is on. MINI58DE SERIES DATASHEET Normal Mode Idle Mode Power-down Mode HXT (4~20 MHz XTL) ON ON Halt HIRC (12/16 MHz OSC) ON ON Halt LXT (32768 Hz XTL) ON ON ON/OFF1 LIRC (10 kHz OSC) ON ON ON/OFF2 PLL ON ON Halt LDO ON ON ON CPU ON Halt Halt HCLK/PCLK ON ON Halt SRAM retention ON ON ON FLASH ON ON Halt GPIO ON ON Halt TIMER ON ON ON/OFF3 PWM ON ON Halt WDT ON ON ON/OFF4 WWDT ON ON Halt UART ON ON Halt IC ON ON Halt SPI ON ON Halt ADC ON ON Halt ACMP ON ON Halt 2 Table 6.2-3 Clocks in Power Modes Wake-up sources in Power-down mode: WDT, I²C, Timer, UART, BOD and GPIO After chip enters power down, the following wake-up sources can wake chip up to normal mode. Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral. *User needs to wait this condition before setting PDEN (CLK_PWRCTL[7]) and execute WFI to enter Power-down mode. Wake-up Source May. 09, 2018 Wake-up condition System can enter Power-down mode again condition* Page 34 of 84 Rev.1.03 MINI58DE BOD Brown-Out Detector Interrupt GPIO GPIO Interrupt After software write 1 to clear the Px_INTSRC[n] bit. Timer Interrupt After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]). WDT WDT Interrupt After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect). UART nCTS wake-up After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]). I2C Falling edge in the I2C_SDA or I2C_CLK TIMER After software writes 1 to clear SYS_BODCTL[BODIF]. After software writes 1 to clear WKIF ( I2C_STATUS1[0]). Table 6.2-4 Condition of Entering Power-down Mode Again 6.2.4 System Power Architecture In this chip, the power distribution is divided into three segments.  Analog power from AVDD and AVSS provides the power for analog components operation. AVDD must be equal to VDD to avoid leakage current.  Digital power from VDD and VSS supplies power to the I/O pins and internal regulator which provides a fixed 1.8V power for digital operation.  Built-in a capacitor for internal voltage regulator The output of internal voltage regulator, LDO_CAP, requires an external capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level as the digital power (VDD). Figure 6.2-7 shows the power distribution of the Mini58 series. MINI58DE SERIES DATASHEET May. 09, 2018 Page 35 of 84 Rev.1.03 MINI58DE AVDD AVSS Low Voltage Reset 10-bit SAR-ADC 22.1184 MHz HIRC Oscillator FLASH SRAM Brown Out Detector Analog Comparator 10 kHz LIRC Oscillator 1.8V POR18 XT1_OUT XT1_IN PLL LDO_CAP Digital Logic 4~24 MHz or 32.768 kHz crystal oscillator 2.5~5.5V to 1.8V LDO IO cell GPIO Pins VDD VSS Mini58 TM Series Power Distribution ® Figure 6.2-7 NuMicro Mini58 Series Power Architecture Diagram MINI58DE SERIES DATASHEET May. 09, 2018 Page 36 of 84 Rev.1.03 MINI58DE 6.2.5 System Memory Mapping Mini58 4 GB System Control 0xFFFF_FFFF Reserved | 0xE000_F000 System C ontrol System C ontrol 0xE000_ED00 SC S_BA External Interrupt C ontrol 0xE000_E100 SC S_BA System Timer C ontrol 0xE000_E010 SC S_BA 0xE000_EFFF 0xE000_E000 0xE000_E00F Reserved | 0x6002_0000 0x6001_FFFF Reserved 0x6000_0000 0x5FFF_FFFF Reserved | 0x5020_0000 AHB AHB peripherals 0x501F_FFFF FMC 0x5000_C 000 FMC _BA 0x5000_0000 GPIO C ontrol 0x5000_4000 GP_BA 0x4FFF_FFFF Interrupt Multiplexer C ontrol 0x5000_0300 INT_BA C lock C ontrol 0x5000_0200 C LK_BA System Global C ontrol 0x5000_0000 SYS_BA UART1 C ontrol 0x4015_0000 UART1_BA I 2C 1 C ontrol 0x4012_0000 I2C 1_BA ADC C ontrol 0x400E_0000 ADC _BA AC MP C ontrol 0x400D_0000 C MP_BA UART0 C ontrol 0x4005_0000 UART0_BA 0x2000_1000 PWM C ontrol 0x4004_0000 PWM_BA 0x2000_0FFF SPI C ontrol 0x4003_0000 SPI_BA 0x2000_0000 I 2C 0 C ontrol 0x4002_0000 I2C 0_BA 0x1FFF_FFFF Timer0/Timer1 C ontrol 0x4001_0000 TMR_BA WWDT C ontrol 0x4000_4100 WWDT_BA WDT C ontrol 0x4000_4000 WDT_BA Reserved | 0x4020_0000 0x401F_FFFF APB | 1 GB 0x4000_0000 0x3FFF_FFFF Reserved 4 KB SRAM Reserved | MINI58DE SERIES DATASHEET 0.5 GB | APB peripherals 0x0000_8000 0x0000_7FFF | 32 KB on-chip Flash (Mini58) 0 GB 0x0000_0000 Table 6.2-5 Memory Mapping Table 6.2.6 6.2.6.1 Memory Organization Overview ® The NuMicro Mini58 series provides 4G-byte addressing space. The addressing space assigned to each on-chip controllers is shown the following table. The detailed register definition, addressing space, and programming details will be described in the following sections for each on-chip peripheral. The Mini58 series only supports little-endian data format. May. 09, 2018 Page 37 of 84 Rev.1.03 MINI58DE 6.2.6.2 System Memory Map The memory locations assigned to each on-chip controllers are shown in the following table. Addressing Space Token Modules 0x0000_0000 – 0x0000_7FFF FLASH_BA Flash Memory Space (32 KB) 0x2000_0000 – 0x2000_0FFF SRAM_BA SRAM Memory Space (4 KB) Flash and SRAM Memory Space AHB Modules Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF SYS_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GP_BA GPIO (P0~P5) Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers APB Modules Space (0x4000_0000 – 0x401F_FFFF) MINI58DE SERIES DATASHEET 0x4000_4000 – 0x4000_00FF WDT_BA Watchdog Timer Control Registers 0x4000_4100 – 0x4000_47FF WWDT_BA Window Watchdog Timer Control Registers 0x4001_0000 – 0x4001_3FFF TMR_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I2C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI_BA SPI with Master/slave Function Control Registers 0x4004_0000 – 0x4004_3FFF PWM_BA PWM Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 – 0x400E_3FFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 0x4012_0000 – 0x4012_3FFF I2C1_BA I2C1 Interface Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers System Control Space (0xE000_E000 – 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA Nested Vectored Interrupt Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Block Registers Table 6.2-6 Address Space Assignments for On-Chip Modules May. 09, 2018 Page 38 of 84 Rev.1.03 MINI58DE 6.2.7 System Timer (SysTick) ® The Cortex -M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the feature. This ensures the timer to count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ARM ® Manual” and “ARM v6-M Architecture Reference Manual”. ® ® Cortex -M0 Technical Reference MINI58DE SERIES DATASHEET May. 09, 2018 Page 39 of 84 Rev.1.03 MINI58DE 6.2.8 6.2.8.1 Nested Vectored Interrupt Controller (NVIC) Overview ® The Cortex -M0 CPU provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the processor core and provides following features. 6.2.8.2 Features  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Dynamic priority change  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. MINI58DE SERIES DATASHEET When an interrupt is accepted, the starting address of the Interrupt Service Routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the “ARM ® Manual” and “ARM v6-M Architecture Reference Manual”. 6.2.8.3 ® ® Cortex -M0 Technical Reference Exception Model and System Interrupt Map ® The following table lists the exception model supported by NuMicro Mini58 series. Software can set four levels of priority on some of these exceptions as well as on all interrupts. The highest user-configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of all the user-configurable interrupts is 0. Note that the priority 0 is treated as the fourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”. May. 09, 2018 Page 40 of 84 Rev.1.03 MINI58DE Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6.2-7 Exception Model Exception Number Interrupt Number (Bit In Interrupt Interrupt Name Registers) Source Module 1 ~ 15 - - - 16 0 BODOUT Brown-out 17 1 WDT_INT 18 2 19 Interrupt Description System exceptions Power-Down Wake-Up Yes WDT Watchdog Timer interrupt Yes EINT0 GPIO External signal interrupt from P3.2 pin Yes 3 EINT1 GPIO External signal interrupt from P5.2 pin Yes 20 4 GP0/1_INT GPIO External signal interrupt from GPIO group P0~P1 Yes 21 5 GP2/3/4_INT GPIO External signal interrupt from GPIO group P2~P4 except P3.2 Yes 22 6 PWM_INT PWM PWM interrupt No 23 7 BRAKE_INT PWM PWM Brake interrupt No 24 8 TMR0_INT TMR0 Timer 0 interrupt Yes 25 9 TMR1_INT TMR1 Timer 1 interrupt Yes 26 ~ 27 10 ~ 11 - - 28 12 UART0_INT UART0 UART0 interrupt Yes 29 13 UART1_INT UART1 UART1 interrupt Yes 30 14 SPI_INT SPI SPI interrupt No 31 15 - - 32 16 GP5_INT GPIO External signal interrupt from GPIO group P5 except P5.2 Yes 33 17 HIRC_TRIM_IN T HIRC HIRC trim interrupt No 34 18 I2C0_INT I2C0 I C0 interrupt May. 09, 2018 - - 2 Page 41 of 84 Yes Rev.1.03 MINI58DE SERIES DATASHEET Brown-out low voltage detected interrupt MINI58DE Exception Number Interrupt Number (Bit In Interrupt Interrupt Name Registers) Source Module Interrupt Description I2C1 interrupt Power-Down Wake-Up 35 19 I2C1_INT I2C1 36 ~ 40 20 ~ 24 - - 41 25 ACMP_INT ACMP 42 ~ 43 26 ~ 27 - - 44 28 PWRWU_INT CLKC Clock controller interrupt for chip wakeup from Power-down state Yes 45 29 ADC_INT ADC ADC interrupt No 46 ~ 47 30 ~ 31 - - No Analog Comparator 0 or Comparator 1 interrupt Yes - - Table 6.2-8 System Interrupt Map Vector Table 6.2.8.4 Vector Table When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table based address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with the exception handler entry as illustrated in previous section. Vector Table Word Offset (Bytes) 0x00 MINI58DE SERIES DATASHEET Exception Number * 0x04 Description Initial Stack Pointer Value Exception Entry Pointer using that Exception Number Table 6.2-9 Vector Table Format 6.2.8.5 Operation Description NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear-Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section. May. 09, 2018 Page 42 of 84 Rev.1.03 MINI58DE 6.2.9 System Control Registers (SCB) ® The Cortex -M0 status and operating mode control are managed System Control Registers. Including ® ® CPUID, Cortex -M0 interrupt priority and Cortex -M0 power management can be controlled through these system control registers. ® ® For more detailed information, please refer to the “ARM Cortex -M0 Technical Reference Manual” ® and “ARM v6-M Architecture Reference Manual”. MINI58DE SERIES DATASHEET May. 09, 2018 Page 43 of 84 Rev.1.03 MINI58DE 6.3 Clock Controller 6.3.1 Overview The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters ® Power-down mode when Cortex -M0 core executes the WFI instruction only if the PDEN (CLK_PWRCTL[7]) bit is set to 1. After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit Power-down mode. In Power-down mode, the clock controller turns off the 4~24 MHz external high speed crystal (HXT) and 22.1184 MHz internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. The following figures show the clock generator and the overview of the clock source control. The clock generator consists of 3 sources as listed below:  4~24 MHz external high speed crystal oscillator (HXT) or 32.768 kHz (LXT) external low speed crystal oscillator  Programmable PLL output clock frequency (PLL source can be selected from external 4 ~ 24 MHz external high speed crystal (HXT) or 22.1184 MHz internal high speed oscillator (HIRC)) (PLL FOUT)  22.1184 MHz internal high speed RC oscillator (HIRC)  10 kHz internal low speed RC oscillator (LIRC) XTLEN (CLK_PWRCTL[1:0]) MINI58DE SERIES DATASHEET XT1_IN XT1_OUT 4~24 MHz HXT or 32.768 kHz LXT HXT or LXT PLLSRC (CLK_PLLCTL[19]) 0 HIRCEN (CLK_PWRCTL[2]) PLL PLL FOUT 1 22.1184 MHz HIRC HIRC LIRCEN (CLK_PWRCTL[3]) LIRC 10 kHz LIRC Legend: HXT = 4~24 MHz external high speed crystal oscillator LXT = 32.768 kHz external low speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Figure 6.3-1 Clock Generator Block Diagram May. 09, 2018 Page 44 of 84 Rev.1.03 MINI58DE 22.1184 MHz 22.1184 MHz 111 10 kHz 4~24 MHz PLLFOUT 010 Reserved 4~24 MHz 1/(HCLKDIV+1) 000 HCLK ISP PCLK I2C 0~1 ACMP 22.1184 MHz CLKSEL0[2:0] 111 External trigger 4~24 MHz CPU 001 10 kHz 22.1184 MHz CPUCLK 011 HCLK 10 kHz 001 0 4~24 MHz PLLCON[19] TMR 1 TMR 0 010 1 PLLFOUT 011 000 22.1184 MHz CLKSEL1[14:12] CLKSEL1[10:8] 22.1184 MHz HCLK 4~24 MHz CPUCLK 1/2 111 1/2 011 1/2 010 Reserved SysTick 0 001 000 Reserved PWMCH45 PWMCH23 PWMCH01 11 HCLK 10 CLKSEL0[5:3] CLKSEL2[5:4] CLKSEL1[31:30] CLKSEL1[29:28] CLKSEL2[17:16] 10 kHz HCLK 1/2048 HCLK 1/2048 PLLFOUT 01 HCLK 00 4~24 MHz WDT 00 CLKSEL1[1:0] 11 10 SPI 01 00 CLKSEL1[25:24] CLKSEL1[5:4] 22.1184 MHz HCLK PLLFOUT 4~24 MHz CLKSEL1[3:2] 1/(UARTDIV+1) UART 0~1 1/(ADC_DIV+1) ADC 11 10 01 22.1184 MHz 00 HCLK Reserved 4~24 MHz 10 kHz 11 BOD 10 FREQDIV 01 00 CLKSEL2[3:2] Note: Before clock switching, both the preselected and newly selected clock sources must be turned on and stable. Figure 6.3-2 Clock Generator Global View Diagram May. 09, 2018 Page 45 of 84 Rev.1.03 MINI58DE SERIES DATASHEET 4~24 MHz 10, 11 WWDT 11 10 4~24 MHz Reserved 11 10 10 kHz PLLFOUT 1 SYST_CSR[2] 4~24 MHz 22.1184 MHz FMC MINI58DE 6.3.2 Auto-trim This chip supports auto-trim function: the HIRC trim (22.1184 MHz internal RC oscillator), according to the accurate LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 1 % deviation within all temperature ranges. For instance, the system needs an accurate 22.1184 MHz clock. In such case, if users do not want to use 22.1184 MHz HXT as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL (SYS_IRCTCTL[0] trim frequency selection) to “1”, and the auto-trim function will be enabled. Interrupt status bit FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) high indicates the HIRC output frequency is accurate within 1% deviation. To get better results, it is recommended to set both LOOPSEL (SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT (SYS_IRCTCTL[7:6] trim value update limitation count) to “11”. 6.3.3 System Clock and SysTick Clock The system clock has 4 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 6.3-3. HCLKSEL (CLK_CLKSEL0[2:0]) 22.1184 MHz HIRC 10 kHz LIRC PLL FOUT Reserved 4~24 MHz HXT or 32.768 kHz LXT 111 011 CPUCLK 010 1/(HCLK_N+1) 001 HCLKDIV (CLK_CLKDIV[3:0]) HCLK PCLK CPU AHB APB 000 MINI58DE SERIES DATASHEET CPU in Power Down Mode Note: Before clock switching, both the preselected and newly selected clock sources must be turned on and stable. Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Figure 6.3-3 System Clock Block Diagram The source of PCLK is equal to HCLK in system clock architecture. ® The clock source of SysTick in Cortex -M0 core can use CPU clock or external clock CLKSRC(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure 6.3-4. May. 09, 2018 Page 46 of 84 Rev.1.03 MINI58DE STCLKSEL (CLK_CLKSEL0[5:3]) 22.1184 MHz HIRC HCLK 4~24 MHz HXT or 32.768 kHz LXT Reserved 4~24 MHz HXT or 32.768 kHz LXT 1/2 111 1/2 011 1/2 010 STCLK 001 000 Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Note: Before clock switching, both the preselected and newly selected clock sources must be turned on and stable. Figure 6.3-4 SysTick Clock Control Block Diagram 6.3.4 Peripherals Clock Source Selection The peripheral clock has different clock source switch settings depending on different peripherals. Please note that, while switching clock source from one to another, user must wait until both clock sources are running stabled. MINI58DE SERIES DATASHEET May. 09, 2018 Page 47 of 84 Rev.1.03 MINI58DE PCLK Watch Dog Timer WDTCKEN (CLK_APBCLK[0]) TMR0CKEN (CLK_APBCLK[2]) Timer0 TMR1CKEN (CLK_APBCLK[3]) Timer1 Frequency Divider CLKOCKEN (CLK_APBCLK[6]) I2C0 I2C0CKEN (CLK_APBCLK[8]) I2C1 I2C1CKEN (CLK_APBCLK[9]) SPIEN (CLK_APBCLK[12]) SPI UART0CKEN (CLK_APBCLK[16]) UART0 UART1CKEN (CLK_APBCLK[17]) UART1 PWM01 PWMCH01CKEN (CLK_APBCLK[20]) PWM23 PWMCH23CKEN (CLK_APBCLK[21]) PWM45 MINI58DE SERIES DATASHEET PWMCH45CKEN (CLK_APBCLK[22]) ADC ADCCKEN (CLK_APBCLK[28]) ACMP ACMPCKEN (CLK_APBCLK[30]) Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK May. 09, 2018 Page 48 of 84 Rev.1.03 MINI58DE Peripheral Clok Selectable Ext. CLK (HXT Or LXT) HIRC LIRC HCLK PLL WDT Yes Yes No Yes Yes No WWDT Yes Yes No Yes Yes No Timer0 Yes Yes Yes Yes Yes No Timer1 Yes Yes Yes Yes Yes No I2C0 No - - - - - I C1 No - - - - - SPI Yes Yes No No Yes Yes UART0 Yes Yes Yes No No Yes UART1 Yes Yes Yes No No Yes PWM No - - - - - ADC Yes Yes Yes No Yes Yes ACMP No - - - - - 2 Table 6.3-1 Peripheral Clock Source Selection Table Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to PCLK. 6.3.5 Power-down Mode Clock The clocks still kept active are listed below: 6.3.6  Clock Generator  10 kHz internal low speed oscillator (LIRC) clock  32.768 kHz external low speed crystal oscillator (LXT) clock (If PDLXT = 1 and XTLEN[1:0] = 10)  Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)  Watchdog Clock  Timer 0/1 Clock Frequency Divider Output This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to the CLKO pin. Therefore there are 16 options of power-of-2 divided 1 16 clocks with the frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock divider. May. 09, 2018 Page 49 of 84 Rev.1.03 MINI58DE SERIES DATASHEET When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripheral clocks are still active in Power-down mode. MINI58DE (N+1) The output formula is Fout = Fin/2 , where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]). When writing 1 to CLKOEN (CLK_CLKOCTL[4]), the chained counter starts to count. When writing 0 to CLKOEN (CLK_CLKOCTL[4]), the chained counter continuously runs till divided clock reaches low state and stay in low state. If DIV1EN (CLK_CLKOCTL[5]) set to 1, the frequency divider clock (FRQDIV_CLK) will bypass power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly. FREQSEL (CLK_CLKSEL2[3:2]) CLKOCKEN (CLK_APBCLK[6]) 22.1184 MHz HIRC 11 HCLK CLKO_CLK 10 LIRC 01 4~24 MHz HXT or 32.768 kHz LXT Legend: HXT = 4~24 MHz external high speed crystal oscillator LXT = 32.768 kHz external low speed crystal oscillator HIRC = 22.1184 MHz internal high speed RC oscillator 00 Note: Before clock switching, both the preselected and newly selected clock sources must be turned on and stable. Figure 6.3-6 Clock Source of Frequency Divider MINI58DE SERIES DATASHEET CLKOEN (CLK_CLKOCTL[4]) Enable divide-by-2 counter CLKO_CLK 1/2 1/22 FREQSEL (CLK_CLKOCTL[3:0]) 16 chained divide-by-2 counter 1/23 …... 1/215 DIV1EN (CLK_CLKOCTL[5]) 1/216 0000 0001 : : 1110 1111 16 to 1 MUX 0 CLKO 1 Figure 6.3-7 Block Diagram of Frequency Divider May. 09, 2018 Page 50 of 84 Rev.1.03 MINI58DE 6.4 Flash Memory Controller (FMC) 6.4.1 Overview ® The NuMicro Mini58 series is equipped with 32 Kbytes on-chip embedded flash for application and Data Flash to store some application dependent data. A User Configuration block provides for system initialization. A 2.5 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function. A 512 bytes security protection ROM (SPROM) can conceal user program. This chip also supports In-Application-Programming (IAP) function, user switches the code executing without the chip reset after the embedded flash updated. 6.4.2 Features  Supports 32 Kbytes application ROM (APROM).  Supports 2.5 Kbytes loader ROM (LDROM).  Supports configurable Data Flash size to share with APROM.  Supports 512 bytes security protection ROM (SPROM) to conceal user program.  Supports 12 bytes User Configuration block to control system initialization.  Supports 512 bytes page erase for all embedded flash.  Supports CRC-32 checksum calculation function.  Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update embedded flash memory. MINI58DE SERIES DATASHEET May. 09, 2018 Page 51 of 84 Rev.1.03 MINI58DE 6.5 General Purpose I/O (GPIO) 6.5.1 Overview ® The NuMicro Mini58 series has up to 30 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 30 pins are arranged in 6 ports named as P0, P1, P2, P3, P4 and P5. Each of the 30 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each pin can be configured by software individually as Input, Push-pull output, Open-drain output, or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins is stay in input mode and each port data register Px_DOUT[n] resets to 1. For Quasi-bidirectional mode, each I/O pin is equipped with a very weak individual pull-up resistor about 110 k ~ 300 k for VDD is from 5.0 V to 2.5 V. 6.5.2 Features  Four I/O modes:  Quasi-bidirectional mode  Push-pull output  Open-drain output  Input-only with high impendence  MINI58DE SERIES DATASHEET  Quasi-bidirectional TTL/Schmitt trigger input mode selected by SYS_Px_MFP[23:16] I/O pin configured as interrupt source with edge/level setting  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode  Enabling the pin interrupt function will also enable the pin wake-up function  High driver and high sink I/O mode support  Configurable default I/O mode of all pins after reset by CIOINI (Config0[10]) setting  CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset  CIOINI = 1, all GPIO pins in Input tri-state mode after chip reset May. 09, 2018 Page 52 of 84 Rev.1.03 MINI58DE 6.6 Timer Controller (TMR) 6.6.1 Overview The Timer Controller includes two 32-bit timers, TMR0 and TMR1, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, event counting by external input pins, and interval measurement by external capture pins. 6.6.2 Features  Two sets of 32-bit timer with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through CNT (TIMRTx_CNT[23:0])  Supports event counting function  24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])  Supports external capture pin event for interval measurement  Supports external capture pin event to reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated  Supports internal capture triggered while internal ACMP output signal transition MINI58DE SERIES DATASHEET May. 09, 2018 Page 53 of 84 Rev.1.03 MINI58DE 6.7 Enhanced PWM Generator 6.7.1 Overview ® The NuMicro Mini58 series has built in one PWM unit (PWM0) which is specially designed for motor driving control applications. The PWM0 supports six PWM generators which can be configured as six independent PWM outputs, PWM0_CH0~PWM0_CH5, or as three complementary PWM pairs, (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5) with three programmable dead-time generators. Every complementary PWM pairs share one 8-bit prescaler. There are six clock dividers providing five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. Each PWM output has independent 16-bit counter for PWM period control, and 16-bit comparators for PWM duty control. The six PWM generators provide twelve independent PWM interrupt flags which are set by hardware when the corresponding PWM period counter comparison matched period and duty. Each PWM interrupt source with its corresponding enable bit can request PWM interrupt. The PWM generators can be configured as One-shot mode to produce only one PWM cycle signal or Auto-reload mode to output PWM waveform continuously. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers, the updated value will be loaded into the 16-bit down counter/ comparator at the end of current period. The double buffering feature avoids glitch at PWM outputs. Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. In order to control motor more precisely, we provide some registers that not only configure PWM but also Timer, ADC and ACMP, by doing so, it can save more CPU time and control motor with ease especially in BLDC. 6.7.2 Features MINI58DE SERIES DATASHEET The PWM0 supports the following features:  Six independent 16-bit PWM duty control units with maximum six port pins:  Six independent PWM outputs – PWM0_CH0, PWM0_CH1, PWM0_CH2, PWM0_CH3, PWM0_CH4, and PWM0_CH5  Three complementary PWM pairs, with each pin in a pair mutually complement to each other and capable of programmable dead-time insertion – (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)  Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)  Group control bit – PWM0_CH2 and PWM0_CH4 are synchronized with PWM0_CH0, PWM0_CH3 and PWM0_CH5 are synchronized with PWM0_CH1  One-shot (only support edge-aligned type) or Auto-reload mode PWM  Up to 16-bit resolution  Supports edge-aligned, center-aligned and precise center-aligned mode  Supports asymmetric PWM generating in center-aligned and precise center-aligned mode  Supports center loading in center-aligned and precise center-aligned mode  Programmable dead-time insertion between complementary paired PWMs May. 09, 2018 Page 54 of 84 Rev.1.03 MINI58DE  Each pin of PWM0_CH0 to PWM0_CH5 has independent polarity setting control  Hardware fault brake protections  Supports software trigger  Two Interrupt source types:  Synchronously requested at PWM frequency when down counter comparison matched (edge- and center-aligned type) or underflow (edgealigned type)  Requested when external fault brake asserted  BKP0: EINT0 or CPO1  BKP1: EINT1 or CPO0  The PWM signals before polarity control stage are defined in the view of positive logic. The PWM ports is active high or active low are controlled by polarity control register  Supports mask aligned function  Supports independently rising CMP matching, PERIOD matching, falling CMP matching (in Center-aligned type), period matching to trigger ADC conversion  Timer comparing matching event trigger PWM to do phase change in BLDC application  Supports ACMP output event trigger PWM to force PWM output at most one period low, this feature is usually for step motor control  Provides interrupt accumulation function MINI58DE SERIES DATASHEET May. 09, 2018 Page 55 of 84 Rev.1.03 MINI58DE Trapezoidal Commutation System Architecture +VDC Bus Hyper Terminal DC Bus + BLDC Isolation circuit UART N UART Interface MINI58 +5V UART Timer nINT0 Push Button S +5V CPO0 PWM0 CH0 CH1 CH2 CH3 CH4 CH5 DC Bus - 3-Phase Inverter (IPM, MOSFET, IGBT) AIN[6] AIN[0] AIN[1] AIN[2] AIN[7] AIN[3] ADC +VDC Bus +5V Option 1 Option 2 Sensorless circuit MINI58DE SERIES DATASHEET Figure 6.7-1 Application Circuit Diagram May. 09, 2018 Page 56 of 84 Rev.1.03 MINI58DE 6.8 Watchdog Timer (WDT) 6.8.1 Overview The Watchdog Timer is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports the function to wake-up system from Idle/Power-down mode. 6.8.2 Features  18-bit free running up counter for WDT time-out interval  Selectable time-out interval (2 ~ 2 ) WDT_CLK cycles and the time-out interval is 1.6 ms ~ 26.214s if WDT_CLK = 10 kHz  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports selectable WDT reset delay period, including 1026、130、18 or 3 WDT_CLK reset delay period  Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in Config0 register  Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT 4 18 MINI58DE SERIES DATASHEET May. 09, 2018 Page 57 of 84 Rev.1.03 MINI58DE 6.9 Window Watchdog Timer (WWDT) 6.9.1 Overview The Window Watchdog Timer (WWDT) is used to perform a system reset within a specified window period to prevent software run to uncontrollable status by any unpredictable condition. 6.9.2 Features  6-bit down counter value (CNTDAT) and 6-bit compare value (CMPDAT) to make the WWDT time-out window period flexible  Supports 4-bit value (PSCSEL) to programmable maximum 11-bit prescale counter period of WWDT counter MINI58DE SERIES DATASHEET May. 09, 2018 Page 58 of 84 Rev.1.03 MINI58DE 6.10 UART Controller (UART) 6.10.1 Overview ® The NuMicro Mini58 series provides two channels of Universal Asynchronous Receiver/Transmitters (UART). The UART0 performs supports flow control function. The UART0 performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-toserial conversion on data transmitted from the CPU. The UART0 controller also supports IrDA SIR Function, and RS-485 function mode. The UART0 channel supports six types of interrupts. The UART1 channel supports five types of interrupts. The UART1 only performs a serial-toparallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART0 has 16 bytes Receiver/Transmitter FIFO. The UART1 only has one Receiver/Transmitter buffer. 6.10.2 Features Full duplex, asynchronous communications  Separates receive/transmit 16/16 bytes entry FIFO for data payloads (Only Available in UART0)  Separates receive/transmit 1/1 byte buffer for data payloads (Only Available in UART1)  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (Only Available in UART0)  Programmable receiver buffer trigger level (Only Available in UART0)  Supports programmable baud-rate generator for each channel individually  Supports CTS wake-up function (Only Available in UART0)  Supports 8-bit receiver buffer time-out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting UART_TOUT[15:8] register  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface characteristics   Programmable number of data bit, 5, 6, 7, 8 character  Programmable parity bit, even, odd, no parity or stick parity bit generation and detection  Programmable stop bit, 1, 1.5, or 2 stop bit generation Supports IrDA SIR function mode (Only Available in UART0)   Supports 3/16-bit duration for normal mode Supports RS-485 function mode (Only Available in UART0)  Supports RS-485 9-bit mode  Supports hardware or software enable to program RTS pin to control RS-485 transmission direction directly May. 09, 2018 Page 59 of 84 Rev.1.03 MINI58DE SERIES DATASHEET  MINI58DE 6.11 I2C Serial Interface Controller (I2C) 6.11.1 Overview 2 I C is a two-wire, bi-directional serial bus that provides a simple and efficient method for data 2 exchange between devices. The I C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus 2 2 simultaneously. There are two sets of I C controller and only I C0 supports Power-down wake-up function. 6.11.2 Features 2 The I C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include: 2 MINI58DE SERIES DATASHEET  Supports up to two I C ports  Master/Slave mode  Bi-directional data transfer between masters and slaves  Multi-master bus  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer  Built-in 14-bit time-out counter that requests the I C interrupt if the I C bus hangs up and timer-out counter overflows  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave address registers with mask option)  Supports Power-down wake-up function (Only I C0 channel support this function)  Supports two-level buffer function May. 09, 2018 2 2 2 Page 60 of 84 Rev.1.03 MINI58DE 6.12 Serial Peripheral Interface (SPI) 6.12.1 Overview The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction interface. The SPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. SPI controller can be configured as a master or a slave device. 6.12.2 Features  Supports Master or Slave mode operation  Configurable transfer bit length  Provides four 32-bit FIFO buffers  Supports MSB first or LSB first transfer  Supports byte reorder function  Supports byte or word suspend mode  Supports Slave 3-wire mode MINI58DE SERIES DATASHEET May. 09, 2018 Page 61 of 84 Rev.1.03 MINI58DE 6.13 Analog-to-Digital Converter (ADC) 6.13.1 Overview The Mini58 series contains one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with eight input channels. The A/D converters can be started by software, external pin (STADC/P3.2) or PWM trigger. 6.13.2 Features  Analog input voltage range: 0 ~ Analog Supply Voltage from AVDD  10-bit resolution and 8-bit accuracy is guaranteed  Up to eight single-end analog input channels  Maximum ADC clock frequency is 6 MHz, and 14 ADC clocks per sample  Two operating modes  Single mode: A/D conversion is performed one time on a specified channel  PWM sequence mode: When PWM trigger, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0,1] or channel[1,2] or channel[0,2] defined by MODESEL (ADC_SEQCTL[3:2])  An A/D conversion can be started by:  Software write 1 to SWTRG bit  External pin STADC  PWM trigger with optional start delay period MINI58DE SERIES DATASHEET  Each Conversion result is held in data register with valid and overrun indicators  Conversion results can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting  Channel 7 supports 2 input sources: External analog voltage and internal fixed bandgap voltage May. 09, 2018 Page 62 of 84 Rev.1.03 MINI58DE 6.14 Analog Comparator (ACMP) 6.14.1 Overview ® The NuMicro Mini58 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input is greater than negative input, otherwise the output is 0. Each comparator can be configured to generate interrupt when the comparator output value changes. 6.14.2 Features  Analog input voltage range: 0 ~ AVDD  Supports Hysteresis function  Optional internal reference voltage source for each comparator negative input  ACMP0 supports:  Four positive sources    Three negative sources  P1.4  Internal Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG) ACMP1 supports:  Four positive sources  P3.1, P3.2, P3.4, or P3.5 MINI58DE SERIES DATASHEET  May. 09, 2018 P1.5, P1.0, P1.2, or P1.3 Three negative sources  P3.0  Internal Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG) Page 63 of 84 Rev.1.03 MINI58DE 7 APPLICATION CIRCUIT DVCC [1] AVCC AVDD DVCC Power CS CLK MISO MOSI SPI_SS SPI_CLK SPI_MISO SPI_MOSI FB VDD VDD SPI Device VSS 0.1uF 0.1uF VSS FB AVSS VDD ICE_DAT ICE_CLK nRESET VSS SWD Interface DVCC 4.7K 20p XT1_IN Crystal 4~24 MHz or 32.768 kHz crystal 20p 4.7K [2] Mini58LDE LQFP48 DVCC CLK I2Cx_SCL I2Cx_SDA VDD DIO I2C Device VSS XT1_OUT DVCC Reset Circuit 10K RS232 Transceiver PC COM Port nRESET [2] 10uF/25V UARTx_RXD ROUT UARTx_TXD TIN RIN TOUT UART MINI58DE SERIES DATASHEET LDO_CAP 1uF Note 1: For the SPI device, the Mini58 chip supply voltage must be equal to SPI device working voltage. For example, when the SPI Flash working voltage is 3.3 V, the Mini58 chip supply voltage must also be 3.3V. LDO Note 2: x denotes 0 or 1. May. 09, 2018 Page 64 of 84 Rev.1.03 MINI58DE 8 ELECTRICAL CHARACTERISTICS 8.1 Absolute Maximum Ratings Symbol Parameter Min Max Unit VDD VSS DC Power Supply -0.3 +7.0 V VIN Input Voltage VSS -0.3 VDD +0.3 V 1/tCLCL Oscillator Frequency 4 24 MHz TA Operating Temperature -40 +105 ℃ TST Storage Temperature -55 +150 ℃ IDD Maximum Current into VDD - 120 mA ISS Maximum Current out of VSS - 120 mA Maximum Current sunk by an I/O pin - 35 mA Maximum Current sourced by an I/O pin - 35 mA Maximum Current sunk by total I/O pins - 100 mA Maximum Current sourced by total I/O pins - 100 mA IIO Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life and reliability of the device. MINI58DE SERIES DATASHEET May. 09, 2018 Page 65 of 84 Rev.1.03 MINI58DE 8.2 DC Electrical Characteristics (VDD - VSS = 2.5 ~ 5.5 V, TA = 25C) Symbol Parameter Min Typ Max Unit Test Conditions VDD Operation voltage 2.5 - 5.5 V VDD = 2.5V ~ 5.5V up to 50 MHz VSS / AVSS Power Ground -0.3 - - V VLDO LDO Output Voltage 1.62 1.8 1.98 V VDD ≥ 2.5 V 1.20 1.24 1.28 V VDD = 2.5V ~ 5.5V, TA = 25C 1.18 1.24 1.32 V -0.3 0 0.3 V VBG VDD-AVDD Band-gap Voltage Allowed Voltage Difference for VDD and AVDD IDD1 - 16.277 - VDD = 2.5V ~ 5.5V, TA = -40C~105C - HXT HIRC PLL 5.5V 24 MHz X V V mA Operating Current All Digital VDD Modules Normal Run Mode IDD2 HCLK = 50 MHz - 11.272 - mA 5.5V 24 MHz X V X - 14.651 - mA 3.3V 24 MHz X V V - 9.739 - mA 3.3V 24 MHz X V X VDD HXT HIRC PLL 5.5V X V X V while(1){} IDD3 Executed from Flash IDD4 MINI58DE SERIES DATASHEET IDD5 - 7.098 - mA Operating Current Normal Run Mode IDD6 HCLK =22.1184 MHz All Digital Modules - 4.050 - mA 5.5V X V X X - 6.997 - mA 3.3V X V X V - 4.001 - mA 3.3V X V X X VDD HXT HIRC PLL 5.5V 12 MHz X X V while(1){} IDD7 Executed from Flash IDD8 IDD9 - 5.514 - mA Operating Current All Digital Modules Normal Run Mode IDD10 HCLK = 12MHz - 4.038 - mA 5.5V 12 MHz X X X - 3.992 - mA 3.3V 12 MHz X X V - 2.809 - mA 3.3V 12 MHz X X X while(1){} IDD11 Executed from Flash IDD12 May. 09, 2018 Page 66 of 84 Rev.1.03 MINI58DE IDD13 - 3.151 - Normal Run Mode IDD14 HCLK = 4 MHz HXT HIRC PLL 5.5V 4 MHz X X V mA Operating Current All Digital VDD Modules - 2.747 - mA 5.5V 4 MHz X X X - 1.757 - mA 3.3V 4 MHz X X V - 1.360 - mA 3.3V 4 MHz X X X VDD LXT HIRC PLL 5.5V 32.76 8 kHz X X V while(1){} IDD15 Executed from Flash IDD16 IDD17 - 176 - μA Operating Current All Digital Modules Normal Run Mode IDD18 HCLK = 32.768 kHz - 173 - μA 5.5V 32.76 8 kHz X X X - 158 - μA 3.3V 32.76 8 kHz X X V - 155 - μA 3.3V 32.76 8 kHz X X X VDD HXT LIRC PLL 5.5V X V X V[4] while(1){} IDD19 Executed from Flash IDD20 IDD21 - 168 - μA Operating Current Normal Run Mode IDD22 HCLK = 10 kHz All Digital Modules - 167 - μA 5.5V X V X X - 150 - μA 3.3V X V X V[4] - 150 - μA 3.3V X V X X VDD HXT HIRC PLL 5.5V 24 MHz X V V while(1){} IDD23 Executed from Flash IIDLE1 - 12.386 - mA All Digital Modules Operating Current - 7.346 - mA 5.5V 24 MHz X V X IIDLE3 - 10.784 - mA 3.3V 24 MHz X V V IIDLE4 - 5.838 - mA 3.3V 24 MHz X V X VDD HXT HIRC PLL 5.5V X V X V IIDLE2 Idle Mode HCLK = 50MHz IIDLE5 - 5.378 - mA Operating Current All Digital Modules Idle Mode IIDLE6 HCLK=22.1184 MHz IIDLE7 May. 09, 2018 - 2.300 - mA 5.5V X V X X - 5.291 - mA 3.3V X V X V Page 67 of 84 Rev.1.03 MINI58DE SERIES DATASHEET IDD24 MINI58DE IIDLE8 - IIDLE9 - 2.265 4.577 - - mA Idle Mode X V X VDD HXT HIRC PLL 5.5V V X X V mA Operating Current IIDLE10 3.3V X All Digital Modules - 3.364 - mA 5.5V V X X X IIDLE11 - 3.062 - mA 3.3V V X X V IIDLE12 - 1.871 - mA 3.3V V X X X VDD HXT HIRC PLL 5.5V V X X V HCLK =12 MHz IIDLE13 - 2.838 - mA Operating Current IIDLE14 Idle Mode All Digital Modules - 2.433 - mA 5.5V V X X X IIDLE15 - 1.446 - mA 3.3V V X X V IIDLE16 - 1.048 - mA 3.3V V X X X VDD LXT HIRC PLL 5.5V V X X V HCLK = 4 MHz IIDLE17 - 167 - μA Operating Current Idle Mode All Digital Modules - 166 - μA 5.5V V X X X IIDLE19 - 150 - μA 3.3V V X X V IIDLE20 - 149 - μA 3.3V V X X X VDD HXT LIRC PLL 5.5V X V X V[4] IIDLE18 HCLK = 32.768 kHz MINI58DE SERIES DATASHEET IIDLE 21 - 167 - μA Operating Current Idle Mode All Digital Modules - 166 - μA 5.5V X V X X IIDLE 23 - 150 - μA 3.3V X V X V[4] IIDLE 24 - 149 - μA 3.3V X V X X - 6.2 - A VDD = 5.5 V, All oscillators and analog blocks turned off. IIDLE 22 HCLK = 10 kHz IPWD1 Standby Current Power-down Mode IPWD2 (Deep Sleep Mode) - 5.8 - A VDD = 3.3 V, All oscillators and analog blocks turned off. IIL Logic 0 Input Current P0/1/2/3/4/5 (Quasibidirectional Mode) - -70 -75 A VDD = 5.5 V, VIN = 0V May. 09, 2018 Page 68 of 84 Rev.1.03 MINI58DE ITL Logic 1 to 0 Transition Current P0/1/2/3/4/5 (Quasi-bidirectional Mode) [*3] - -595 -750 A ILK Input Leakage Current P0/1/2/3/4/5 -1 - +1 A Input Low Voltage P0/1/2/3/4/5 (TTL Input) -0.3 - 0.8 VIL1 VIH1 VIL3 VIH3 VILS VIHS RRST Input Low Voltage XTAL1[*2] Input High Voltage XTAL1[*2] Negative-going Threshold (Schmitt Input), nRESET Positive-going Threshold (Schmitt Input), nRESET Internal nRESETPin Pull-up Resistor Negative-going Threshold VDD = 5.5 V, 0 < VIN< VDD Open-drain or input only mode VDD = 4.5 V V -0.3 - 0.6 2.0 - VDD + 0.3 VDD = 2.5 V VDD = 5.5 V V 1.5 - VDD + 0.3 0 - 0.8 0 - 0.4 3.5 - VDD + 0.3 2.4 - VDD + 0.3 -0.3 - 0.2VDD V - 0.7 VDD - VDD + 0.3 V - 150 kΩ VDD = 2.5 V ~ 5.5V 40 VDD = 3.0 V V VDD = 4.5 V VDD = 2.5 V V VDD = 5.5 V VDD = 3.0 V -0.3 - 0.3VDD V - 0.7 VDD - VDD + 0.3 V - -300 -400 - A VDD = 4.5 V, VSS = 2.4 V -50 -80 - A VDD = 2.7 V, VSS = 2.2 V ISR13 -40 -73 - A VDD = 2.5 V, VSS = 2.0 V ISR21 -20 Source Current P0/1/2/3/4/5 (Push-pull -3 Mode) -2.5 -26 - mA VDD = 4.5 V, VSS = 2.4 V -5 - mA VDD = 2.7 V, VSS = 2.2 V -5 - mA VDD = 2.5 V, VSS = 2.0 V Sink Current P0/1/2/3/4/5 (Quasibidirectional, OpenDrain and Push-pull Mode) 10 15 - mA VDD = 4.5 V, VSS = 0.45 V 6 9 - mA VDD = 2.7 V, VSS = 0.45 V 5 8 - mA VDD = 2.5 V, VSS = 0.45 V VIHS (Schmitt input), P0/1/2/3/4/5 Positive-going Threshold (Schmitt input), P0/1/2/3/4/5 ISR11 ISR12 ISR22 ISR23 ISK11 ISK12 ISK13 Source Current P0/1/2/3/4/5 (Quasibidirectional Mode) MINI58DE SERIES DATASHEET VILS Input High Voltage P0/1/2/3/4/5 (TTL Input) VDD = 5.5 V, VIN = 2.0V Notes: 1. nRESET pin is a Schmitt trigger input. May. 09, 2018 Page 69 of 84 Rev.1.03 MINI58DE 2. XTAL1 is a CMOS input. 3. Pins of P0, P1, P2, P3, P4 and P5 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V. 4. Only enable modules which support 10 kHz LIRC clock source MINI58DE SERIES DATASHEET May. 09, 2018 Page 70 of 84 Rev.1.03 MINI58DE 8.3 AC Electrical Characteristics 8.3.1 External Input Clock tCLCL tCLCH 0.7 VDD 90% tCLCX 10% 0.3 VDD tCHCL tCHCX Note: Duty cycle is 50%. Symbol Parameter Min Typ Max Unit Test Conditions tCHCX Clock High Time 10 - - ns - tCLCX Clock Low Time 10 - - ns - tCLCH Clock Rise Time 2 - 15 ns - tCHCL Clock Fall Time 2 - 15 ns - 8.3.2 External 4~24 MHz High Speed Crystal (HXT) Parameter Min. Typ. Max Unit Test Conditions VHXT Operation Voltage 2.5 - 5.5 V - TA Temperature -40 - 105 ℃ - - 2.5 - mA 12 MHz, VDD = 5.5V IHXT Operating Current - 1.0 - mA 12 MHz, VDD = 3.3V 4 - 24 MHz - fHXT 8.3.3 Clock Frequency External 32.768 kHz XTAL Oscillator (LXT) Specifications Sym. Parameter Test Conditions Min. fLXTAL Oscillator frequency TLXTAL Temperature ILXTAL Operating current 8.3.4 Typ. Max. Unit 32.768 -40 kHz VDD = 2.5V ~ 5.5V o +105 C A 5 VDD = 2.5V Typical Crystal Application Circuits Crystal May. 09, 2018 C1 C2 Page 71 of 84 Rev.1.03 MINI58DE SERIES DATASHEET Symbol MINI58DE 4 MHz ~ 24 MHz 20 pF 20 pF 32.768 kHz 20 pF 20 pF XT1_IN XT1_OUT 4~24 MHz or 32.768 kHz Crystal C1 Vss C2 Vss Figure 8.3-1 Mini58 Typical Crystal Application Circuit 8.3.5 22.1184 MHz Internal High Speed RC Oscillator (HIRC) Symbol Parameter Min Typ Max Unit Test Conditions VHRC Supply Voltage 1.62 1.8 1.98 V - Center Frequency - 22.1184 MHz - -1 - +1 % -2 - +2 % - 700 - μA fHRC Calibrated Internal MINI58DE SERIES DATASHEET Oscillator Frequency IHRC Operating Current May. 09, 2018 Page 72 of 84 TA = 25 ℃ VDD = 5 V TA = -40℃~105℃ VDD=2.5 V~ 5.5 V TA = 25 ℃,VDD = 5 V Rev.1.03 MINI58DE HIRC oscillator accuracy vs. temperature 1.00 0.80 Deviation Percentage % 0.60 0.40 0.20 0.00 Max -0.20 Min -0.40 -0.60 -0.80 -1.00 -40 -30 -20 -10 0 10 20 25 30 40 50 60 70 80 85 90 100 110 TA ℃ 8.3.6 10 kHz Internal Low Speed RC Oscillator (LIRC) Parameter Min Typ Max Unit Test Conditions VLRC Supply Voltage 2.5 - 5.5 V - Center Frequency - 10 - kHz - -10 - +10 % -40 - +40 % fLRC MINI58DE SERIES DATASHEET Symbol VDD=2.5V~ 5.5V TA = 25℃ Oscillator Frequency May. 09, 2018 Page 73 of 84 VDD=2.5V~ 5.5V TA = -40℃~+105℃ Rev.1.03 MINI58DE 8.4 Analog Characteristics 8.4.1 10-bit SARADC Symbol Parameter Min Typ Max Unit Test Condition - Resolution - - 10 Bit - DNL Differential Nonlinearity Error - -1~1.5 -1~+2.5 LSB - INL Integral Nonlinearity Error - ±1 ±2 LSB - EO Offset Error - 1 2 LSB - EG Gain Error (Transfer Gain) - -1 -3 LSB - EA Absolute Error - 3 4 LSB - - Monotonic Guaranteed - - FADC ADC Clock Frequency - FS - 4.2 AVDD = 4.5~5.5 V MHz - - 2.8 AVDD =2.5~5.5 V - - 300 kSPS AVDD = 4.5~5.5 V - - 200 kSPS AVDD = 2.5~5.5 V Sample Rate (FADC/TCONV) MINI58DE SERIES DATASHEET TACQ Acquisition Time (Sample Stage) N+1 1/FADC TCONV Total Conversion Time N+14 1/FADC N is sampling counter, N=0,1,2, 4,8, 16,32, 4, 128, 256,1024 AVDD Supply Voltage 2.5 - 5.5 V - IDDA Supply Current (Avg.) - 600 - μA AVDD = 5.5 V VIN Analog Input Voltage 0 - AVDD V - CIN Input Capacitance - 3.2 - pF - RIN Input Load - 6 - kΩ - Note: ADC voltage reference is same with AVDD May. 09, 2018 Page 74 of 84 Rev.1.03 MINI58DE EF (Full scale error) = EO + EG Gain Error Offset Error EG EO 1023 1022 1021 1020 Ideal transfer curve 7 6 ADC output code 5 Actual transfer curve 4 3 2 DNL 1 1 LSB Offset Error EO LDO & Power Management Symbol Parameter Min Typ Max Unit Test Condition VDD DC Power Supply 2.5 - 5.5 V - VLDO Output Voltage 1.62 1.8 1.98 V - TA Temperature -40 25 105 ℃ Notes: 1. It is recommended a 0.1μF bypass capacitor is connected between V DD and the closest VSS pin of the device. 8.4.3 Low Voltage Reset Symbol Parameter Min Typ Max Unit Test Condition AVDD Supply Voltage 0 - 5.5 V - TA Temperature -40 25 105 ℃ - May. 09, 2018 Page 75 of 84 Rev.1.03 MINI58DE SERIES DATASHEET 8.4.2 1023 Analog input voltage (LSB) MINI58DE ILVR VLVR 8.4.4 Quiescent Current Threshold Voltage - 1 5 μA AVDD =5.5V 1.90 2.00 2.10 V TA=25℃ 1.70 1.90 2.05 V TA=-40℃ 2.00 2.20 2.45 V TA =105℃ Brown-out Detector Symbol Parameter Min Typ Max Unit Test Condition AVDD Supply Voltage 0 - 5.5 V - TA Temperature -40 25 105 ℃ - IBOD Quiescent Current - - 140 μA AVDD =5.5V 4.2 4.38 4.55 V 3.5 3.68 3.85 V 2.5 2.68 2.85 V 2.0 2.18 2.35 V 4.3 4.52 4.75 V 3.5 3.8 4.05 V 2.5 2.77 3.05 V 2.0 2.25 2.55 V VBOD MINI58DE SERIES DATASHEET VBOD 8.4.5 Brown-out Detector (Falling edge) Brown-out Detector (Rising edge) BODEN = 1, BOD_VL [1:0]=11 BODEN = 1, BOD_VL [1:0]=10 BODEN = 1, BOD_VL [1:0]=01 BODEN = 1, BOD_VL [1:0]=00 BODEN = 1, BOD_VL [1:0]=11 BODEN = 1, BOD_VL [1:0]=10 BODEN = 1, BOD_VL [1:0]=01 BODEN = 1, BOD_VL [1:0]=00 Power-on Reset Symbol Parameter Min Typ Max Unit Test Condition TA Temperature -40 25 105 ℃ - VPOR Reset Voltage 1.6 2 2.4 V - VPOR VDD Start Voltage to Ensure Power-on Reset - - 100 mV RRVDD VDD Raising Rate to Ensure Power-on Reset 0.025 - - V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset 0.5 - - ms May. 09, 2018 Page 76 of 84 Rev.1.03 MINI58DE VDD tPOR RRVDD VPOR Time Figure 8.4-1 Power-up Ramp Condition 8.4.6 Comparator Parameter Min Typ Max Unit VCMP Supply Voltage 2.5 - 5.5 V TA Temperature -40 25 105 ℃ - ICMP Operation Current - 40 80 μA AVDD=5V VOFF Input Offset Voltage 10 20 mV - VSW Output Swing 0.1 - AVDD – 0.1 V - VCOM Input Common Mode Range 0.1 - AVDD – 0.1 V - - DC Gain 40 70 - dB - TPGD Propagation Delay - 200 - ns VCOM=1.2 V, VDIFF=0.1 V VHYS Hysteresis - ±30 ±60 mV VCOM=1.2 V TSTB Stable time - - 1 μs May. 09, 2018 Page 77 of 84 Test Condition MINI58DE SERIES DATASHEET Symbol Rev.1.03 MINI58DE 8.5 Flash DC Electrical Characteristics Symbol Parameter Min Typ Max Unit VFLA[2] Supply Voltage 1.62 1.8 1.98 V NENDUR Endurance 20,000 - - cycles[1] TRET Data Retention 10 - - year TERASE Page Erase Time - 20 - ms TPROG Program Time - 40 - us IDD1 Read Current - 7 - mA IDD2 Program Current - 8 - mA IDD3 Erase Current - 12 - mA Test Condition TA =85℃ Notes: 1. 2. 3. Number of program/erase cycles. VFLA is source from chip LDO output voltage. Guaranteed by design, not test in production. MINI58DE SERIES DATASHEET May. 09, 2018 Page 78 of 84 Rev.1.03 MINI58DE 9 9.1 PACKAGE DIMENSIONS 48-pin LQFP MINI58DE SERIES DATASHEET May. 09, 2018 Page 79 of 84 Rev.1.03 MINI58DE 9.2 33-pin QFN (4 mm x 4 mm) MINI58DE SERIES DATASHEET May. 09, 2018 Page 80 of 84 Rev.1.03 MINI58DE 9.3 33-pin QFN (5 mm x 5 mm) MINI58DE SERIES DATASHEET May. 09, 2018 Page 81 of 84 Rev.1.03 MINI58DE 9.4 20-pin TSSOP MINI58DE SERIES DATASHEET May. 09, 2018 Page 82 of 84 Rev.1.03 MINI58DE 10 REVISION HISTORY Date Revision Description 2015.06.11 1.00 Preliminary version. 2015.10.12 1.01 Updated LDROM size from 2 Kbytes to 2.5 Kbytes. 2015.12.09 1.02 Fixed cross reference error. 2018.5.09 1.03 1. Rearranged pins of SWD interface in Chapter 7 APPLICATION CIRCUIT. 2. Modified Flash data retention time to 10 years in Sectoin 8.5. MINI58DE SERIES DATASHEET May. 09, 2018 Page 83 of 84 Rev.1.03 MINI58DE MINI58DE SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton. May. 09, 2018 Page 84 of 84 Rev.1.03