SLM27211CA-DG

SLM27211 SLM27211 120-V Boot, 4-A Peak, High-Frequency High-Side and Low-Side Driver GENERAL DESCRIPTION FEATURES The SLM27211 is a high-frequency N-channel MOSFET driver include a 120-V bootstrap diode and high-side and low-side drivers with independent inputs for maximum control flexibility. This allows for N-channel MOSFET control in half-bridge, fullbridge, two-switch forward, and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 2ns between the turnon and turnoff of each other. An on-chip bootstrap diode eliminates the external discrete diodes. Undervoltage lockout is provided for both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold. TYPICAL APPLICATIONS • • • • • • • • • • • • • • • • • Drives Two N-Channel MOSFETs in High-Side and Low-Side Configuration Input Pins are Independent of Supply Voltage Range Maximum Boot Voltage of 120 V 8-V to 17-V VDD Operation Range 4-A Sink and 3-A Source Output Currents 8-ns Rise and 5-ns Fall Time With1000-pF Load 20-ns(typical) Propagation Delay Time Undervoltage Lockout for High-Side and LowSide Driver 2-ns Delay Matching Specified from–40°C to 140°C Power Supplies for Telecom, Datacom, and Merchant Half-Bridge and Full-Bridge Converters Push-Pull Converters High Voltage Synchronous-Buck Converters Two-Switch Forward Converters Active-Clamp Forward Converters Class-D Audio Amplifiers TYPICAL APPLICATION CIRCUIT Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 1 SLM27211 PIN CONFIGURATION Package Pin Configuration (Top View) SOIC-8 DFN8 PIN DESCRIPTION No. Pin Description 1 VDD Positive supply to the lower-gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 4.7 µF. 2 HB High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependent on the gate charge of the high- side MOSFET and must also be selected based on speed and ripple criteria 3 HO High-side output. Connect to the gate of the high-side power MOSFET. 4 HS High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin. 5 HI High-side input.(1) 6 LI Low-side input.(1) 7 VSS Negative supply terminal for the device that is generally grounded. 8 LO Low-side output. Connect to the gate of the low-side power MOSFET. Thermal Pad(2) (1) (2) Utilized on the DFN package only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs. The thermal pad is not directly connected to any leads of the package; however, it is electrically and thermally connected to the substrate which is the ground of the device. Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 2 SLM27211 ORDERING INFORMATION Order Part No. Package QTY SLM27211CA-DG SOIC-8, Pb-Free 2500/Reel SLM27211EK-7G DFN-8, Pb-Free 1000/Reel FUNCTIONAL BLOCK DIAGRAM HB UVLO Level Shift HO VS HI VDD UVLO LO VSS LI Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 3 SLM27211 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted)(1) MIN –0.3 -0.3 –0.3 –2 VHS – 0.3 VHS – 2 –1 –(24 V – VDD) –0.3 –40 –65 Supply voltage range, VDD(2), VHB – VHS Input voltages on LI and HI, VLI, VHI Output voltage on LO, VLO DC Repetitive pulse < 100 ns(3) Output voltage on HO, VHO DC Repetitive pulse < 100 ns(3) Voltage on HS, VHS DC Repetitive pulse < 100 ns(3) Voltage on HB, VHB Operating virtual junction temperature range, TJ Storage temperature, TSTG MAX 20 20 VDD + 0.3 VDD + 0.3 VHB + 0.3 VHB + 0.3 120 120 120 150 150 UNIT V V V V V V °C °C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to VSS unless otherwise noted. Currents are positive into and negative out of the specified terminal. (3) Verified at bench characterization. VDD is the value used in an application design. (1) RECOMMENDED OPERATION CONDITIONS all voltages are with respect to VSS; currents are positive into and negative out of the specified terminal. –40°C < TJ = TA < 140°C (unless otherwise noted) Supply voltage range, VDD, VHB – VHS Voltage on HS, VHS Voltage on HS, VHS (repetitive pulse < 100 ns) Voltage on HB, VHB Voltage slew rate on HS Operating junction temperature Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 MIN NOM MAX UNIT 8 –1 –(24 V – VDD) VHS + 8, VDD – 1 12 17 105 110 VHS + 17, 115 50 140 V V V V –40 V/ns °C 4 SLM27211 STATIC ELECTRICAL CHARACTERISTICS VDD = VHB = 12 V, VHS = VSS = 0 V, no load on LO or HO, TA = TJ = –40°C to 140°C, (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENTS IDD VDD quiescent current V(LI) = V(HI) = 0 V 0.127 mA IDDO VDD operation current f = 500 kHz, CLOAD = 0 1.002 mA IHB Boot voltage quiescent current V(LI) = V(HI) = 0 V 0.102 mA IHBO Boot voltage operating current f = 500 kHz, CLOAD = 0 0.92 mA IHBS HB to VSS quiescent current V(HS) = V(HB) = 115 V 0.0005 µA IHBSO HB to VSS operating current f = 500 kHz, CLOAD = 0 0.12 mA INPUT VHIT Input voltage threshold 2.3 V VLIT Input voltage threshold 1.6 V VIHYS Input voltage hysteresis 700 mV RIN Input pulldown resistance 51 kΩ UNDER-VOLTAGE LOCKOUT (UVLO) VDDR VDD turnon threshold 7 V VDDHYS Hysteresis 0.5 V VHBR VHB turnon threshold 6.7 V VHBHYS Hysteresis 1.1 V BOOTSTRAP DIODE VF Low-current forward voltage IVDD-HB = 100 µA 0.4 V VFI High-current forward voltage IVDD-HB = 100 mA 0.82 V RD Dynamic resistance, ΔVF/ΔI IVDD-HB = 100 mA and 80 mA 0.9 Ω LO GATE DRIVER VLOL Low-level output voltage ILO = 100 mA 0.07 V VLOH High level output voltage ILO = –100 mA, VLOH = VDD – VLO 0.17 V Peak pull-up current(1) VLO = 0 V 3 A Peak pull-down current(1) VLO = 12 V 4.5 A HO GATE DRIVER VHOL Low-level output voltage IHO = 100 mA 0.07 V VHOH High-level output voltage IHO = –100 mA, VHOH = VHB – VHO 0.17 V Peak pull-up current(1) VHO = 0 V 3 A Peak pull-down current(1) VHO = 12 V 4.5 A (1) Ensured by design. Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 5 SLM27211 Switching Characteristics over operating free-air temperature range (unless otherwise noted) PARAMETER TDLFF VLI falling to VLO falling TDHFF VHI falling to VHO falling TDLRR VLI rising to VLO rising TDHRR VHI rising to VHO rising TMON From HO OFF to LO ON TMOFF From LO OFF to HO ON TEST CONDITIONS CLOAD = 0 TJ = 25°C TJ = –40°C to 140°C TJ = 25°C TJ = –40°C to 140°C CLOAD = 1000 pF, from 10% to 90% CLOAD = 1000 pF, from 90% to 10% CLOAD = 0.1 µF, (3 V to 9 V) CLOAD = 0.1 µF, (9 V to 3 V) MIN TYP 22 22 21 21 2 MAX UNIT ns ns ns ns 2 tR LO rise time 8 tR HO rise time 8 tF LO fall time 4 tF HO fall time 4 tR LO, HO 0.38 tF LO, HO 0.16 Minimum input pulse width that changes 50 the output Bootstrap diode turnoff time (1)(2) IF = 20 mA, IREV = 0.5 A(3) 20 （1） Ensured by design. （2） IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode. （3） Typical values for TA = 25°C. Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 ns ns ns ns ns ns µs µs ns ns 6 SLM27211 Typical Characteristics 100 180 140 Diode Current(mA) Quiescent Current(uA) 160 120 100 IDDQ IHBQ 80 60 10 40 20 0 0 2 4 6 8 10 12 14 16 18 1 450 20 VDD=VHB Supply Voltage(V) 10 10 IHBO Operation Current(mA) IDDO Operation Current(mA) 100 1 CL=0pF T=25℃ CL=0pF T=-40℃ CL=0pF T=140℃ CL=1000pF T=140℃ CL=1000pF T=25℃ CL=4700pF T=140℃ 10 600 650 700 750 800 850 Diode Current vs Diode Voltage 100 0.01 550 Diode Voltage (mV) Quiescent Current vs Supply Voltage 0.1 500 100 Frequency(KHz) IDD Operation Current vs Frequency Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 1000 1 CL=0pF T=25℃ CL=0pF T=-40℃ CL=0pF T=140℃ CL=1000pF T=140℃ CL=1000pF T=25℃ CL=4700pF T=140℃ 0.1 0.01 10 100 1000 Frequency(KHz) Boot Voltage Operation Current vs Frequency 7 SLM27211 6 T=25℃ 5 5 4 4 Input Threshold(V) HI, LI Thershold Voltage(V) 6 3 2 HI_Rising HI_Falling LI_Rising LI_Falling 1 0 -1 8 10 12 14 16 18 3 2 1 HI_Rising HI_Falling LI_Rising LI_Falling 0 -1 20 -40 -20 0 VDD Supply Voltage(V) 20 40 60 80 100 120 140 Temperature(℃) Input Threshold vs Supply Voltage Input Threshold vs Temperature 8.0 1.5 7.6 1.2 Hysteresis(V) Threshold(V) 7.2 6.8 6.4 0.9 0.6 6.0 VDD Rising VHB Rising 5.6 5.2 -40 -20 0 20 40 60 80 100 120 0.3 140 Temperature(℃) 0.0 VDD_Hysteresis VHB_Hysteresis -40 -20 0 20 40 60 80 100 120 140 Temperature(℃) Undervoltage Lockout Threshold vs Undervoltage Lockout Threshold Hysteresis vs Temperature Temperature Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 8 SLM27211 IHO=ILO=100mA 0.32 VOL-HO/LO Output Voltage(V) VOH-HO/LO Output Voltage(V) 0.36 0.28 0.24 0.20 0.16 0.12 VOH_HS VDD=VHB=8V VOH_LS VDD=VHB=8V VOH_HS VDD=VHB=12V VOH_LS VDD=VHB=12V VOH_HS VDD=VHB=16V VOH_LS VDD=VHB=16V 0.08 0.04 0.00 -40 -20 0 20 40 60 80 100 120 0.12 0.08 VOL_HS VDD=VHB=8V VOL_LS VDD=VHB=8V VOL_HS VDD=VHB=12V VOL_LS VDD=VHB=12V VOL_HS VDD=VHB=16V VOL_LS VDD=VHB=16V 0.04 0.00 140 IHO=ILO=100mA 0.16 -40 -20 0 20 Temperature(℃) 40 60 80 100 120 140 Temperature(℃) LO and HO Low Level Output Voltage vs Temperature Temperature 32 32 28 28 24 24 Propagation Delay(ns) Propagation Delay(ns) LO and HO High Level Output Voltage vs 20 16 12 TDLRR TDLFF TDHRR TDHFF 8 4 0 8 12 16 20 16 12 TDHRR TDHFF TDLRR TDLFF 8 4 20 VDD=VHB Supply Voltage(V) Propagation Delay vs Voltage Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 0 -40 -25 0 25 85 125 140 Temperature(℃) Propagation Delay vs Temperature 9 SLM27211 TMON TMOFF 10 Delay Matching(ns) 8 6 4 2 0 -2 -40 -25 0 25 85 125 140 Temperature(℃) Delay Matching Time Vs Temperature Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 10 SLM27211 Device Functional Modes The device operates in normal mode and UVLO mode. See the Undervoltage Lockout (UVLO) section for information on UVLO operation mode. In the normal mode the output state is dependent on states of the HI and LI pins. Table 2 lists the output states for different input pin combinations. Table 2. Device Logic Table HI PIN L L H H (1) (2) HO(1) LI PIN L H L H LO(2) L L H H L H L H HO is measured with respect to HS. LO is measured with respect to VSS. Application Information To affect fast switching of power devices and reduce associated switching power losses, a powerful gate driver is employed between the PWM output of controllers and the gates of the power semiconductor devices. Also, gate drivers are indispensable when it is impossible for the PWM controller to directly drive the gates of the switching devices. With the advent of digital power, this situation will be often encountered because the PWM signal from the digital controller is often a 3.3-V logic signal which cannot effectively turn on a power switch. Level shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter follower configurations, prove inadequate with digital power because they lack level-shifting capability. Gate drivers effectively combine both the level-shifting and buffer-drive functions. Gate drivers also find other needs such as minimizing the effect of high-frequency switching noise by locating the highcurrent driver physically close to the power switch, driving gate-drive transformers, and controlling floating powerdevice gates, reducing power dissipation and thermal stress in controllers by moving gate charge power losses from the controller into the driver. Power Dissipation Power dissipation of the gate driver has two portions as shown in Equation 1. PDISS = PDC + PSW (1) The DC portion of the power dissipation is PDC = IQ × VDD where IQ is the quiescent current for the driver. The quiescent current is the current consumed by the device to bias all internal circuits such as input stage, reference voltage, logic circuits, protections, and also any current associated with switching of internal devices when the driver output changes state (such as charging and discharging of parasitic capacitances, parasitic shoot-through, and so forth). The SLM27211 features very low quiescent currents (less than 0.17 mA, refer to the Electrical Characteristics table )and contain internal logic to eliminate any shoot-through in the output driver stage. Thus, the effect of the PDC on the total power dissipation within the gate driver can be safely assumed to be negligible. The power dissipated in the gate-driver package during switching (PSW) depends on the following factors: • Gate charge required of the power device (usually a function of the drive voltage VG, which is very close to input bias supply voltage VDD) • Switching frequency • Use of external gate resistors. When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given by Equation 2. 2 (2) ×V EG = ½C LOAD where • • DD CLOAD is load capacitor VDD is bias voltage feeding the driver Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 11 SLM27211 There is an equal amount of energy dissipated when the capacitor is charged and when it is discharged. This leads to a total power loss given by Equation 3. 2 PG = CLOAD × VDD × fSW where • fSW is the switching frequency (3) The switching load presented by a power MOSFET/IGBT is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications of typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, determine the power that must be dissipated when switching a capacitor which is calculated using the equation QG = CLOAD × VDD to provide Equation 4 for power. PG = CLOAD × VDD2 × fSW = QG × VDD × fSW (4) This power PG is dissipated in the resistive elements of the circuit when the MOSFET/IGBT is being turned on and off. Half of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external gate-drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor. Power Supply Recommendations The bias supply voltage range for which the SLM27211 device is recommended to operate is from 8 V to 17 V. The lower end of this range is governed by the internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. Whenever the driver is in UVLO condition when the VDD pin voltage is below the V(ON) supply start threshold, this feature holds the output low, regardless of the status of the inputs. The upper end of this range is driven by the 20-V absolute maximum voltage rating of the VDD pin of the device (which is a stress rating). Keeping a 3-V margin to allow for transient voltage spikes, the maximum recommended voltage for the VDD pin is 17 V. The UVLO protection feature also involves a hysteresis function, which means that when the VDD pin bias voltage has exceeded the threshold voltage and device begins to operate, and if the voltage drops, then the device continues to deliver normal functionality unless the voltage drop exceeds the hysteresis specification VDD(hys). Therefore, ensuring that, while operating at or near the 8-V range, the voltage ripple on the auxiliary power supply output is smaller than the hysteresis specification of the device is important to avoid triggering device shutdown. During system shutdown, the device operation continues until the VDD pin voltage has dropped below the V(OFF) threshold, which must be accounted for while evaluating system shutdown timing design requirements. Likewise, at system start-up the device does not begin operation until the VDD pin voltage has exceeded the V(ON) threshold. The quiescent current consumed by the internal circuit blocks of the device is supplied through the VDD pin. Although this fact is well known, it is important to recognize that the charge for source current pulses delivered by the HO pin is also supplied through the same VDD pin. As a result, every time a current is sourced out of the HO pin, a corresponding current pulse is delivered into the device through the VDD pin. Thus, ensure that a local bypass capacitor is provided between the VDD and GND pins and located as close to the device as possible for the purpose of decoupling is important. A low-ESR, ceramic surface-mount capacitor is required. Sillumin recommends using a capacitor in the range 0.22 µF to 4.7 µF between VDD and GND. In a similar manner, the current pulses delivered by the LO pin are sourced from the HB pin. Therefore a 0.022-µF to 0.1-µF local decoupling capacitor is recommended between the HB and HS pins. Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 12 SLM27211 Typical Application Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 13 SLM27211 Typical Application (continued) Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 14 SLM27211 Typical Application (continued) Profile Feature Pb-Free Assembly Preheat & Soak 150°C Temperature min (Tsmin) 200°C Temperature max (Tsmax) 60-120 seconds Time (Tsmin to Tsmax) (ts) 3°C/second max. Liquidous temperature (TL) 217°C Time at liquidous (tL) Peak package body temperature (Tp)* CONTROL Average ramp-up rate (Tsmax to Tp) Time (tp)** within 5°C of the specified classification temperature (Tc) 60-150 seconds Max 260°C Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Figure 7 Classification Profile Copyright© 2020, Sillumin® Semiconductor Co., Ltd. Rev0.4, Aug, 2020 15