XA-XTAG

xTAG v3.0 Hardware Manual IN THIS DOCUMENT · Introduction · XS1-U8 device · xSYS Connector (J2) · J3 and J4 connectors · 24MHz Crystal Oscillator · I/O Port-to-Pin Mapping · xTAG v3.0 Schematic 1 Introduction The xTAG v3.0 debug adapter converts between an XMOS XSYS connector and USB 2.0, providing pins for JTAG control, system reset, processor debug, one duplex UART link and one duplex serial XMOS Link. The xTAG v3.0 debug adapter can be used to connect XMOS development kits to most PCs, and provide a 5V power supply from a USB 2.0 port. The diagram below shows the layout of the components on the card. J3 J4 20-way IDC xSYS connector Figure 1: xTAG v3.0 features J1 Standard USB-B connector J2 LEDs To debug a board with the xTAG v3.0 you must use xTIMEcomposer 13.1 or later, available from the XMOS web site: http://xmos.com/downloads. The board requires an XMOS xSYS connector. Publication Date: 2015/6/1 XMOS © 2015, All Rights Reserved Document Number: XM006125A xTAG v3.0 Hardware Manual 2 2/8 XS1-U8 device The xTAG v3.0 is based on a single XS1-U8 device in a BGA package. The XS1-U8 consists of a single xCORE, which comprises a multicore microcontroller with tightly integrated general purpose I/O pins and 64 KBytes of on-chip RAM. The pins are brought out of the package and connected to the card’s components as follows: · USB Connector (J1) The xTAG v3.0 uses a Standard B-type micro USB connector to link to a PC. The USB connector is connected to the XS1-U8 device. · xSYS 20-way IDC header The processor has ports that are directly connected to the I/O pins. Six LEDs are driven by the debugger, their function (clockwise, starting from the power button on the bottom right): Power Green The xTAG is powered on Run Green Red Target is running Target is in debug mode and stopped Status Green Target stop reason is expected e.g. breakpoint, print message Target stop reason is unexpected e.g. exception Red Target Green Red 3 Target device is detected after a Run Configuration or Debug Configuration is used (xrun or xgdb command) Target device is not detected after a Run Configuration or Debug Configuration is used (xrun or xgdb command) xSCOPE Green Flashing Off xSCOPE is enabled No xSCOPE JTAG Green Off There is JTAG activity with the target happening No JTAG xSYS Connector (J2) The xTAG v3.0 includes an xSYS 20-way IDC header, which can be used to connect it to an XMOS development board for debugging programs on the hardware. The xSYS connector provides pins for JTAG control, system reset, processor debug, a duplex UART link and a 2-bit serial xCONNECT Link. XM006125A xTAG v3.0 Hardware Manual 3/8 Pin Signal Direction Description 1 5V Target to Host Power 2 NC N/A No connection 3 MSEL Host to Target Select boot from JTAG - Active Low 4 GND N/A Ground 5 TDSRC Host to Target JTAG Test Data 6 XL1_UP1 Target to Host xCONNECT Link 7 TMS Host to Target JTAG Test Mode Select 8 GND N/A Ground 9 TCK Host to Target JTAG Test Clock 10 XL1_UP0 Target to Host xCONNECT Link 11 DEBUG Bidirectional Debug 12 GND N/A Ground 13 TDSNK Target to Host JTAG Test Data 14 XL1_DN0 Host to Target xCONNECT Link 15 RST_N Host to Target System Reset - Active Low 16 GND N/A Ground 17 UART_RX Host to Target Serial Port 18 XL1_DN1 Host to Target xCONNECT Link 19 UART_TX Target to Host Serial Port 20 GND N/A Ground The routing of these I/O pins along with the power pins is shown below. 3.1 xCONNECT Link configuration Some of the I/O pins on the processor are configured as a duplex 2-bit serial xCONNECT Link. The mapping of xCONNECT Link to the pins is shown in the table below: XM006125A xTAG v3.0 Hardware Manual 1 Figure 2: xTAG v3.0 xSYS pinout 4/8 2 NC GND XL1_UP1 GND XL1-_UP0 GND XL1-DN0 GND XL1-DN1 GND 5V MSEL TDSCR TMS TCK DEBUG TDSNK RST_N UART_RX UART_TX 19 20 Pin xCONNECT Link X0D52 XL1_UP1 X0D53 XL1_UP0 X0D54 XL1_DN0 X0D55 XL1_DN1 3.2 JTAG Configuration Some of the I/O pins on the microcontroller are driven by the JTAG signals. The mapping of the signals to the pins is shown in the table below: XM006125A Pin Port Processor X0D11 P1D0 TDSRC X0D13 P1F0 TDSNK X0D22 P1G0 TMS X0D10 P1C0 TCK X0D70 P32A19 MSEL xTAG v3.0 Hardware Manual 3.3 5/8 System Reset The system reset signal is mapped to a 1-bit port on the processor as described below. It is used as an output to reset the target processor from the debugger 4 Pin Port Processor X0D50 P32A1 RST_N J3 and J4 connectors The xTAG v3.0 has two additional connectors. These are reserved for future use. 5 24MHz Crystal Oscillator The XS1-U8 is clocked at 24MHz by a crystal oscillator on the card. The processor is clocked at 500MHz and the I/O ports at 100MHz, by an on-chip phase locked loop (PLL). XM006125A xTAG v3.0 Hardware Manual 6 6/8 I/O Port-to-Pin Mapping The table below provides a full description of the port-to-pin mappings described throughout this document. Pin Processor 8b 32b X0D0 P1A0 UART_UP X0D10 P1C0 TCK X0D11 P1D0 TDSRC X0D12 P1E0 X0D13 P1F0 TDSNK X0D14 P8B0 LED X0D15 P8B1 LED X0D16 P8B2 LED X0D17 P8B3 LED X0D18 P8B4 LED X0D19 P8B5 LED X0D20 P8B6 LED X0D21 P8B7 LED X0D22 XM006125A Port 1b P1G0 TMS X0D50 P32A1 RST_N X0D51 P32A2 DBG X0D52 P32A3 XL1_UP1 X0D53 P32A4 XL1_UP0 X0D54 P32A5 XL1_DN0 X0D55 P32A6 XL1_DN1 X0D69 P32A19 UART_DN X0D70 P32A20 MSEL PIC130 PIC1302 1U PIC160 PIC1602 3 4U7 GND PIC10 PIC102 COC1 C1 100N GND PIC201 PIC20 COC2 C2 100N COC3 C3 GND PIC301 PIC302 GND M1 M2 H1 GND E5 E6 PIU10E6 E7 PIU10E7 E8 PIU10E8 F5 PIU10F5 F6 PIU10F6 F7 PIU10F7 F8 PIU10F8 G5 PIU10G5 G6 PIU10G6 G7 PIU10G7 G8 PIU10G8 H5 PIU10H5 H6 PIU10H6 H7 PIU10H7 H8 PIU10H8 PIU10E5 PIU10H1 PIU10M2 PIU10M1 XT3 DNF VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 4 1 100N 1U COC14 C14 100N M6 M7 L6 100N COC12 C12 GND PIC120 PIC120 5V COD6 D6 ADC_IN3 PIL201 4U7 L2 COL2 4U7 L1 COL1 100N COC9 C9 GND PIC901 PIC902 GND PIC401 PIC402 22U COC4 C4 1V8 6PIR606 ADC_IN3 22U COC5 C5 GND PIC501 PIC502 COR6D R6D 8PIR608 COR6A R6A 1V0 3V3 XT3 DNF XT3 DNF 3 4 PIR604 COR6C 10K R6C PIR603 1 2 PIR602 COR6B 10K R6B PIR601 COSW1 SW1 XT3 DNF GND COC10 C10 2P COC6 C6 3V3A NLUSB0DP USB_DP NLUSB0DN USB_DN A2 B2 A3 B3 ADC_IN0 ADC_IN1 ADC_IN2 ADC_IN3 AVDD H2 NC G2 NC L3 NC B4 NC A4 PIU10A4 NC L5 MODE0 L4 MODE1 B5 MODE2 B6 MODE3 F2 PIU10F2 OSC_EXT_N B1 TDO D2 TDI D1 PIU10D1 TMS C1 PIU10C1 TCK PIU10D2 PIU10B1 PIU10B6 PIU10B5 PIU10L4 PIU10L5 PIU10B4 PIU10L3 PIU10G2 PIU10H2 PIU10B3 PIU10A3 PIU10B2 PIU10A2 A1 PIU10A1 PIC701 PIC702 E1 F1 2P COC7 C7 PIU10F1 PIU10E1 GND PIX103 24M XRCGB COX1 X1 XI/CLK XO 470R GND PIR501 PID702 PID701 PIR502 3V3 COR5 COD7 D7 A5 USB_DP A6 USB_DN A7 PIU10A7 USB_VBUS B7 PIU10B7 USB_ID PIU10A6 PIU10A5 COU1B U1B E2 PIU10E2 DEBUG_N RST_N_LOCPIU10C2 C2 RST_N TDO_LOC TDI_LOC TMS_LOC TCK_LOC MSEL_LOC PIX101 GND PIC601 PIC602 LED7 GREEN PID801 100N LED6 LED5 LED4 COD1 D1 GREEN PID401 3 PID103 4 PID104 PIC1001 PID802 COD8 D8 PID402 COD4 D4 1 PID101 2 PID102 GND PIC1002 GND COR8A R8A COR8B R8B COR8C R8C COR8D R8D 470R 470R 470R 470R GND 5 10K PIR605 7 10K PIR607 2A 2B PISW102B 1 2 PIR802 3 PIR803 4 PIR804 PIR801 8PIR808 7PIR807 6PIR806 5PIR805 3V3 PISW102A XT3 DNF KSC421J XT3 DNF PISW101A 1A 1B PISW101B PIR70110K GND PIMTH101 COR7 R7 PIR702 ADC_IN2 NLADC0IN0 ADC_IN0 NLADC0IN1 ADC_IN1 BUT COMTH1 MTH1 PTH_M3 SMBJ5.0A XT3 DNF GND PIL202 PIL102 GND PID501 PID601 PID502 SMBJ5.0A PID602 PIL101 COD5 D5 GND PIU10L1 L1 L2 PIU10L2 M3 PIU10M3 PIU10M5 M5 M4 PIU10M4 J1 J2 PIU10J2 PIU10J1 K1 K2 PIU10K2 PIU10K1 PIU10L6 PIU10M7 3V3 100N COC18 C18 GND PIC180 PIC1802 3V3A GND PIC170 PIC1702 COC17 C17 3V3A GND PIC140 PIC1402 3V3 330R XXA PIFB102 PIU10M6 XS1_U8A_FB96 PGND PGND PGND SW2 VDD1V8 SW1 SW1 VDDCORE VDDCORE VDDIO VDDIO VDDIO ADC_IN1 COU1A U1A GND 1U COC15 C15 3V3A PIC150 PIC1502 COFB1 FB1 PIFB101 COC11 C11 GND PIC10 PIC102 ADC_IN0 3V3A GND PIU401 6 PIU406 GND 3V3A GND PIU403 3 1 PIU201 6 PIU206 3 2 PIU302 5 PIU305 PIU304 PIU203 VSUP VSUP VSUP REF 2 GND VP PIU402 IN_P OUT 5 IN_N 4 PIU405 ADC_IN1_N XT3 DNF INA214 COU4 U4 PIU404 ADC_IN1_P GND REF GND PIU202 2 OUT VP GND VOUT2 IN_N 5 ADC_IN0_N IN_P INA214 COU2 U2 MIC5321 BYP EN VOUT1 PIJ103 GND 1 2 USB_DN 3 USB_DP 4 PIJ104 5 PIJ105 PIJ101 PIJ102 PIU205 4 1 PIU204 10N COC16 C16 PIU301 6 VIN COU3 U3 PIU306 ADC_IN0_P 5V VBUS DD+ ID GND USB_MICROB PIU303 GND 1N COC13 C13 GND COC8 C8 GND PIC801 PIC802 5V UGND COJ1 J1 6 SH 7 SH 8 SH 9 PIJ109 SH 10 PIJ1010 SH 11 PIJ1011 SH PIJ108 XT3 DNF XT3 DNF ADC_IN2 PIJ107 XT3 DNF XM006125A XT3 DNF Figure 3: xTAG v3.0 schematic R5 X0D35 X0D24 X0D10 X0D11 X0D12 X0D13 X0D14 X0D15 X0D16 X0D17 X0D18 X0D19 X0D20 X0D21 X0D22 X0D0 X0D1 XS1_U8A_FB96 X0D61 X0D62 X0D63 X0D64 X0D65 X0D66 X0D67 X0D68 X0D69 X0D70 X0D49 X0D50 X0D51 X0D52 X0D53 X0D54 X0D55 X0D56 X0D57 X0D58 X0D43/WAKE GREEN A9 B9 XL_UP0 XL_UP1 SRST_N DBG NLBUT BUT DIG_IN0 TDSRC DIG_IN1 TDSNK LED0 LED1 NLLED4 LED4 NLLED5 LED5 NLLED6 LED6 NLLED7 LED7 LED2 LED3 TMS UART_UP F12 G11 G12 PIU10G12 H11 PIU10H11 H12 PIU10H12 J11 PIU10J11 J12 PIU10J12 K11 PIU10K11 K12 UART_DN PIU10K12 L12 MSEL PIU10L12 PIU10G11 PIU10F12 A12 B11 PIU10B11 B12 PIU10B12 C11 PIU10C11 C12 PIU10C12 D11 PIU10D11 D12 PIU10D12 E11 PIU10E11 E12 PIU10E12 F11 PIU10F11 G1 A8 PIU10A12 PIU10G1 PIU10A8 B8 PIU10B8 A10 PIU10A10 B10 PIU10B10 A11 PIU10A11 M12 PIU10M12 L11 PIU10L11 M11 PIU10M11 L10 PIU10L10 M10 PIU10M10 L9 PIU10L9 M9 PIU10M9 L8 PIU10L8 M8 PIU10M8 L7 PIU10L7 PIU10B9 PIU10A9 PIR401 PIR301 PIR201 NLADC0IN00P ADC_IN0_P NLADC0IN00N ADC_IN0_N NLADC0IN10P ADC_IN1_P NLADC0IN10N ADC_IN1_N NLADC0IN2 ADC_IN2 NLADC0IN3 ADC_IN3 NLDIG0IN0 DIG_IN0 NLDIG0IN1 DIG_IN1 1 3 5 PIJ305 7 PIJ307 9 PIJ309 11 PIJ3011 13 PIJ3013 15 PIJ3015 COJ3 J3 2 4 6 PIJ306 8 PIJ308 10 PIJ3010 12 PIJ3012 14 PIJ3014 16 PIJ3016 PIJ304 PIJ302 33R COR4 R4 33R COR3 R3 33R COR2 R2 PIR402 PIR302 PIR202 XL_DN0 XL_DN1 TCK 5V PIF102 1 PIJ201 COJ2 J2 PIJ2010 PIJ208 PIJ206 PIJ204 2 4 6 8 10 12 PIJ2012 14 PIJ2014 16 PIJ2016 18 PIJ2018 20 PIJ2020 3 4 PID303 PID304 3 4 PID203 PID204 PIJ202 COD3 D3 1PID301 2PID302 COD2 D2 1PID201 2PID202 1 2 3 4 PIJ404 5 PIJ405 6 PIJ406 7 PIJ407 PIJ403 PIJ402 PIJ401 NA COJ4 J4 NLXL0DN1 XL_DN1 NLXL0DN0 XL_DN0 NLXL0UP0 XL_UP0 NLXL0UP1 XL_UP1 NLLED3 LED3 NLLED2 LED2 NLLED1 LED1 NLLED0 LED0 Sheet 1 of 1 xTAG3 Sheet Name XTAG3.PrjPCB Project Name Copyright © XMOS Ltd 2012 GND NLTDO0LOC TDO_LOC NLTDI0LOC TDI_LOC NLTCK0LOC TCK_LOC NLTMS0LOC TMS_LOC NLMSEL0LOC MSEL_LOC NLRST0N0LOC RST_N_LOC GND FEM_HEADER_RA NLMSEL MSEL 3 PIJ203 NLTDSRC TDSRC PIJ205 5 NLTMS TMS 7 PIJ207 NLTCK TCK 9 PIJ209 NLDBG DBG 11 PIJ2011 NLTDSNK TDSNK PIJ2013 13 NLSRST0N SRST_N PIJ2015 15 NLUART0DN UART_DNPIJ2017 17 NLUART0UP UART_UPPIJ2019 19 Date 25/02/2014 Size A3 0.35A COF1 F1 COR1A R1A COR1B R1B COR1C R1C COR1D R1D 470R 470R 470R 470R PIF101 IDC_HEADER_MAL XT3 DNF GND PIJ303 PIJ301 PIR104 PIR103 PIR102 1 2 3 4 PIR101 8PIR108 7PIR107 6PIR106 5PIR105 3V3 Rev 1V2B 7 PIJ106 xTAG v3.0 Hardware Manual 7/8 xTAG v3.0 Schematic xTAG v3.0 Hardware Manual 8/8 Copyright © 2015, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XM006125A