JTAG-Booster for
AMD Alchemy Solutions Processors
P.O: Box 1103
Kueferstrasse 8
Tel. +49 (7667) 908-0
sales@fsforth.de
•
•
•
•
D-79200 Breisach, Germany
D-79206 Breisach, Germany
Fax +49 (7667) 908-200
http://www.fsforth.de
AMD Alchemy Solutions Processors
Copyright 1995..2004:
FS FORTH-SYSTEME GmbH
Postfach 1103, D-79200 Breisach, Germany
Release of Document:
Author:
Filename:
Program Version:
November 22, 2004
Dieter Fögele
JTAG_alchemyb.doc
4.xx
All rights reserved. No part of this document may be copied or reproduced in any
form or by any means without the prior written consent of FS FORTH-SYSTEME
GmbH.
2
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AMD Alchemy Solutions Processors
Table of Contents
1. General ............................................................................................................ 5
1.1. Ordering Information.............................................................................. 7
1.2. System Requirements ........................................................................... 7
1.3. Contents of Distribution Disk ................................................................. 8
1.4. Connecting your PC to the target system .............................................. 9
1.5. First Example with AMD Alchemy Solutions Au1000 Processor ......... 11
1.6. First Example with AMD Alchemy Solutions Au1100 Processor ......... 13
1.7. First Example with AMD Alchemy Solutions Au1500 Processor ......... 15
1.8. First Example with AMD Alchemy Solutions Au1550 Processor ......... 17
1.9. Trouble Shooting ................................................................................. 19
1.10.Error Messages ................................................................................... 20
1.11.Initialization file JTAuxxxx.INI.............................................................. 25
1.12.Supported flash devices ...................................................................... 60
2. JTAuxxxx Parameter Description................................................................... 61
2.1. Program a Flash Device ...................................................................... 64
2.2. Read a Flash Device to file.................................................................. 68
2.3. Verify a Flash Device with file.............................................................. 70
2.4. Dump target memory ........................................................................... 72
2.5. Program a Serial Device (I²C/SPI/MicroWire)...................................... 74
2.6. Read a Serial Device to file (I²C/SPI/MicroWire) ................................. 77
2.7. Verify a Serial Device with file (I²C/SPI/MicroWire) ............................. 79
2.8. Dump a Serial Device (I²C/SPI/MicroWire) .......................................... 81
2.9. Toggle CPU pins.................................................................................. 83
2.10.Polling CPU pins ................................................................................. 84
2.11.Polling CPU pins while the CPU is running ......................................... 85
2.12.Show status of all CPU pins while the CPU is running........................ 86
3. Implementation Information ........................................................................... 89
4. Converter Program HEX2BIN.EXE ................................................................ 90
5. Support for Windows NT, Windows 2000 and Windows XP.......................... 92
5.1. Installation on a clean system.............................................................. 92
5.2. Installation with already installed version 5.x/6.x of Kithara................. 92
5.3. Installation with already installed version 4.x of Kithara ...................... 92
JTAG_alchemyb.doc
3
AMD Alchemy Solutions Processors
5.4. De-Installation version 5.x/6.x: .............................................................93
4
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AMD Alchemy Solutions Processors
1. General
The programs JTAu1000.EXE, JTAu1100.EXE, JTAu1500.EXE and
JTAu1550.EXE use the IEEE 1149.1 JTAG port of the AMD Alchemy Solutions
Processors in conjunction with the small JTAG-Booster:
•
•
•
•
•
to program data into flash memory
to verify and read the contents of a flash memory
to make a memory dump
to access a serial device (I²C/SPI/MicroWire)
to test CPU signals
All functions are done without any piece of software running in the target. No
firmware or BIOS must be written. Bootstrap software may be downloaded to
initially unprogrammed memories.
As this tool uses boundary scan, it is extremely simple and very powerful. It
assists you in bringing-up new hardware. Even if there are essential bugs in the
hardware (i.e. RAM not reliable working, soldering problems with the BGA
package), in many cases you are able to load small test programs into flash,
which helps you to analyze hardware problems. Or if you have a flash memory,
which is not connected correctly to the CPU (i.e. CPU's A0 is connected to a 16
bit AMD flash), we can support you with a special adapted version of the JTAGBooster.
The JTAG-BOOSTER' s software is highly optimized to the JTAG chain of a
specific target CPU. To give support for all processors of the AMD Alchemy
Solutions Processors family, there are three different programs on the
distribution disk:
•
JTAu1000.EXE
: Tool for AMD Alchemy Solutions Au1000 Processor
•
JTAu1100.EXE
: Tool for AMD Alchemy Solutions Au1100 Processor
•
JTAu1500.EXE
: Tool for AMD Alchemy Solutions Au1500 Processor
•
JTAu1550.EXE
: Tool for AMD Alchemy Solutions Au1550 Processor
Please contact us, if you need support for other members of the AMD Alchemy
Solutions Processors family.
JTAG_alchemyb.doc
5
AMD Alchemy Solutions Processors
For latest documentation please refer to the file README.TXT on the distribution
disk.
6
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.1.
Ordering Information
The following related products are available
•
9019
1.2.
JTAG-Booster AMD Alchemy Solutions Processors, 3.3V,
AMD Au1000, Au1100, Au1500, Au1550
DOS/Win9x/WinNT/Win2000/WinXP
delivered with adapter type 285
and additional cable with single strands TK02206
System Requirements
To successfully run this tool the following requirements must be met:
•
MSDOS, WIN3.x, WIN9x, WinNT, Win2000 or WindowsXP
(WinNT/Win2000/WindowsXP is supported with an additional tool, see
chapter 5 “Support for Windows NT, Windows 2000 and Windows XP”)
•
Intel 80386 or higher
•
205 kByte of free DOS memory
•
Parallel Port
JTAG_alchemyb.doc
7
AMD Alchemy Solutions Processors
1.3.
Contents of Distribution Disk
•
JTAu1000.EXE
JTAu1000.OVL
Tool for AMD Alchemy Solutions Au1000 Processor
•
JTAu1000.INI
Template configuration file for AMD Alchemy Solutions
Au1000 Processor. See chapter 1.11 "Initialization file
JTAuxxxx.INI"
•
JTAu1100.EXE
JTAu1100.OVL
Tool for AMD Alchemy Solutions Au1100 Processor
•
JTAu1100.INI
Template configuration file for AMD Alchemy Solutions
Au1100 Processor. See chapter 1.11 "Initialization file
JTAuxxxx.INI"
•
JTAu1500.EXE
JTAu1500.OVL
Tool for AMD Alchemy Solutions Au1500 Processor
•
JTAu1500.INI
Template configuration file for AMD Alchemy Solutions
Au1500 Processor. See chapter 1.11 "Initialization file
JTAuxxxx.INI"
•
JTAu1550.EXE
JTAu1550.OVL
Tool for AMD Alchemy Solutions Au1550 Processor
•
JTAu1550.INI
Template configuration file for AMD Alchemy Solutions
Au1550 Processor. See chapter 1.11 "Initialization file
JTAuxxxx.INI"
•
WinNT
This subdirectory contains the support for Windows NT,
Windows 2000 and Windows XP. See chapter 5
"Support for Windows NT, Windows 2000 and
Windows XP"
•
JTAG_V4xx_FLAS
HES.pdf
List of all supported Flash devices
•
README.txt
Release notes, new features, known problems
8
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.4.
Connecting your PC to the target system
The JTAG-Booster can be plugged into standard parallel ports (LPT1-3) with a
DB25-Connector.
1
LPT1-3
1
Élan
SC400
Module Élan486
The target end of the cable has the following reference:
1
TCK
2*
GND
3
TMS
4
TRST#
5
NC
6
TDI
7
TDO
8
+3.3V
*PIN 2 can be detected by the thick cable.
To connect your design to the JTAG-BOOSTER you need a single row berg
connector with a spacing of 2.54mm on your PCB. The names refer to the target:
Pin 7 is the target’s TDO pin and is connected to the JTAG-Booster’s TDI pin.
The 3.3V version of the JTAG-Booster (FS part number 285) is delivered
together with this package. Don’t use the 5V version of the JTAG-Booster (FS
part number 227) with a 3.3V target. Don’t apply 5V to the 3.3V version of the
JTAG-Booster!
Your target must be able to power the JTAG-Booster, it draws about 100mA.
Before you start the program, the JTAG-BOOSTER must be plugged to a parallel
interface of your PC and to the 8 pin JTAG connector on the target.
JTAG_alchemyb.doc
9
AMD Alchemy Solutions Processors
The utility is started with the general command line format: JTAGxxx
JTAuxxxx /function [filename] [/option_1] ... [/option_n].
Note that the function must be the first argument followed (if needed) by the
filename.
If you want to cancel execution of JTAuxxxx, press CTRL-Break-Key.
On any error the program aborts with an MSDOS error level of one.
10
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.5.
First Example with AMD Alchemy Solutions Au1000 Processor
In the following simple example it is assumed that the JTAG-Booster is
connected to LPT1 of your PC and target power is on.
Typing
JTAu1000 /P MYAPP.BIN
at the DOS prompt results in the following output:
JTAu1000 --- JTAG utility for AMD Alchemy Solutions Au1000 Processor
Copyright FS FORTH-SYSTEME GmbH, Breisach
Version 4.xx of mm/dd/yyyy
(1)
(2)
(3)
(4)
Configuration loaded from file JTAu1000.INI
Target: Generic Target
Using LPT at I/O-address 0378h
JTAG Adapter detected
(5)
1 Device detected in JTAG chain
Device 0: IDCODE=003E828F AMD Alchemy Au1000, Revision 0
Sum of instruction register bits : 5
CPU position
:0
Instruction register offset
:0
Length of boundary scan reg : 569
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Looking for a known flash device. Please wait..
AMD 29LV160B, 3,3V, Boot Block Bottom detected
Bus size is 16 Bit
Erasing Flash-EPROM Block #:0 1 2 3
Unlock Bypass used
Programming File MYAPP.BIN
65536 Bytes programmed successfully
Erase Time
Programming Time
JTAG_alchemyb.doc
:
:
0.8 sec
xx.1 sec
11
AMD Alchemy Solutions Processors
(1)
The initialization file JTAu1000.INI was found in the current directory.
(2)
The target identification line of the initialization file is printed here.
(3)
The resulting I/O-address of the parallel port is printed here. With
WinNT/Win2000/WinXP you must specify the option /LPT2 to access to the
standard address 378h.
(4)
A JTAG-Booster is found on the parallel port
(5)
The JTAG chain is analyzed. There may be several parts in the JTAG
chain. The chain is analyzed and all parts except the AMD Alchemy
Solutions Au1000 Processor are switched to bypass mode.
(6)
The length of all instruction registers in the JTAG chain are added.
(7)
The position of the AMD Alchemy Solutions Au1000 Processor in the JTAG
chain is assumed to be zero, if not specified in the command line (see
option /CPUPOS=).
(8)
The position of the JTAG instruction register of the AMD Alchemy Solutions
Au1000 Processor is assumed to be zero, if not specified in the command
line (see option /IROFFS=).
(9)
The real length of the boundary scan register is displayed here and
compared with the boundary scan register length of a AMD Alchemy
Solutions Au1000 Processor.
(10) A Flash AMD 29LV160B selected with RCS0# was found.
(11) The resulting data bus size is printed here.
(12) In this example 4 blocks must be erased.
(13) If available, the "Unlock Bypass Mode" is activated. In boundary scan
mode, this increases the programming performance by 67..75%.
12
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.6.
First Example with AMD Alchemy Solutions Au1100 Processor
In the following simple example it is assumed that the JTAG-Booster is
connected to LPT1 of your PC and target power is on.
Typing
JTAu1100 /P MYAPP.BIN
at the DOS prompt results in the following output:
JTAu1100 --- JTAG utility for AMD Alchemy Solutions Au1100 Processor
Copyright FS FORTH-SYSTEME GmbH, Breisach
Version 4.xx of mm/dd/yyyy
(1)
(2)
(3)
(4)
Configuration loaded from file JTAu1100.INI
Target: Generic Target
Using LPT at I/O-address 0378h
JTAG Adapter detected
(5)
1 Device detected in JTAG chain
Device 0: IDCODE=0020228F AMD Alchemy Au1100, Revision 0
Sum of instruction register bits : 5
CPU position
:0
Instruction register offset
:0
Length of boundary scan reg : 672
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Looking for a known flash device. Please wait..
AMD 29LV160B, 3.3V, Boot Block Bottom detected
Bus size is 16 Bit
Erasing Flash-EPROM Block #:0 1 2 3
Unlock Bypass used
Programming File MYAPP.BIN
65536 Bytes programmed successfully
Erase Time
Programming Time
JTAG_alchemyb.doc
:
:
0.8 sec
xx.0 sec
13
AMD Alchemy Solutions Processors
(1)
The initialization file JTAu1100.INI was found in the current directory.
(2)
The target identification line of the initialization file is printed here.
(3)
The resulting I/O-address of the parallel port is printed here.
(4)
A JTAG-Booster is found on the parallel port
(5)
The JTAG chain is analyzed. There may be several parts in the JTAG
chain. The chain is analyzed and all parts except the AMD Alchemy
Solutions Au1100 Processor are switched to bypass mode.
(6)
The length of all instruction registers in the JTAG chain are added.
(7)
The position of the AMD Alchemy Solutions Au1100 Processor in the JTAG
chain is assumed to be zero, if not specified in the command line (see
option /CPUPOS=).
(8)
The position of the JTAG instruction register of the AMD Alchemy Solutions
Au1100 Processor is assumed to be zero, if not specified in the command
line (see option /IROFFS=).
(9)
The real length of the boundary scan register is displayed here and
compared with the boundary scan register length of a AMD Alchemy
Solutions Au1100 Processor.
(10) A Flash AMD 29LV160B selected with RCS0# was found.
(11) The resulting data bus size is printed here.
(12) In this example four block must be erased.
(13) If available, the "Unlock Bypass Mode" is activated. In boundary scan
mode, this increases the programming performance by 67..75%.
14
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.7.
First Example with AMD Alchemy Solutions Au1500 Processor
In the following simple example it is assumed that the JTAG-Booster is
connected to LPT1 of your PC and target power is on.
Typing
JTAu1500 /P MYAPP.BIN
at the DOS prompt results in the following output:
JTAu1500 --- JTAG utility for AMD Alchemy Solutions Au1500 Processor
Copyright FS FORTH-SYSTEME GmbH, Breisach
Version 4.xx of mm/dd/yyyy
(1)
(2)
(3)
(4)
Configuration loaded from file JTAu1500.INI
Target: Generic Target
Using LPT at I/O-address 0378h
JTAG Adapter detected
(5)
1 Device detected in JTAG chain
Device 0: IDCODE=0010228F AMD Alchemy Au1500, Revision 0
Sum of instruction register bits : 5
CPU position
:0
Instruction register offset
:0
Length of boundary scan reg : 744
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Looking for a known flash device. Please wait..
AMD 29LV160B, 3.3V, Boot Block Bottom detected
Bus size is 16 Bit
Erasing Flash-EPROM Block #:0 1 2 3
Unlock Bypass used
Programming File MYAPP.BIN
65536 Bytes programmed successfully
Erase Time
Programming Time
JTAG_alchemyb.doc
:
:
0.8 sec
xx.0 sec
15
AMD Alchemy Solutions Processors
(1)
The initialization file JTAu1500.INI was found in the current directory.
(2)
The target identification line of the initialization file is printed here.
(3)
The resulting I/O-address of the parallel port is printed here.
(4)
A JTAG-Booster is found on the parallel port
(5)
The JTAG chain is analyzed. There may be several parts in the JTAG
chain. The chain is analyzed and all parts except the AMD Alchemy
Solutions Au1500 Processor are switched to bypass mode.
(6)
The length of all instruction registers in the JTAG chain are added.
(7)
The position of the AMD Alchemy Solutions Au1500 Processor in the JTAG
chain is assumed to be zero, if not specified in the command line (see
option /CPUPOS=).
(8)
The position of the JTAG instruction register of the AMD Alchemy Solutions
Au1500 Processor is assumed to be zero, if not specified in the command
line (see option /IROFFS=).
(9)
The real length of the boundary scan register is displayed here and
compared with the boundary scan register length of a AMD Alchemy
Solutions Au1500 Processor.
(10) A Flash AMD 29LV160B selected with RCS0# was found.
(11) The resulting data bus size is printed here.
(12) In this example four block must be erased.
(13) If available, the "Unlock Bypass Mode" is activated. In boundary scan
mode, this increases the programming performance by 67..75%.
16
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.8.
First Example with AMD Alchemy Solutions Au1550 Processor
In the following simple example it is assumed that the JTAG-Booster is
connected to LPT1 of your PC and target power is on.
Typing
JTAu1550 /P MYAPP.BIN
at the DOS prompt results in the following output:
JTAu1550 --- JTAG utility for AMD Alchemy Solutions Au1550 Processor
Copyright FS FORTH-SYSTEME GmbH, Breisach
Version 4.xx of mm/dd/yyyy
(1)
(2)
(3)
(4)
Configuration loaded from file JTAu1550.INI
Target: Generic Target
Using LPT at I/O-address 0378h
JTAG Adapter detected
(5)
1 Device detected in JTAG chain
Device 0: IDCODE=0030228F AMD Alchemy Au1550, Revision 0
Sum of instruction register bits : 5
CPU position
:0
Instruction register offset
:0
Length of boundary scan reg : 773
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
Looking for a known flash device. Please wait..
AMD 29LV160B, 3.3V, Boot Block Bottom detected
Bus size is 16 Bit
Erasing Flash-EPROM Block #:0 1 2 3
Unlock Bypass used
Programming File MYAPP.BIN
65536 Bytes programmed successfully
Erase Time
Programming Time
JTAG_alchemyb.doc
:
:
0.8 sec
xx.0 sec
17
AMD Alchemy Solutions Processors
(1)
The initialization file JTAu1550.INI was found in the current directory.
(2)
The target identification line of the initialization file is printed here.
(3)
The resulting I/O-address of the parallel port is printed here.
(4)
A JTAG-Booster is found on the parallel port
(5)
The JTAG chain is analyzed. There may be several parts in the JTAG
chain. The chain is analyzed and all parts except the AMD Alchemy
Solutions Au1550 Processor are switched to bypass mode.
(6)
The length of all instruction registers in the JTAG chain are added.
(7)
The position of the AMD Alchemy Solutions Au1550 Processor in the JTAG
chain is assumed to be zero, if not specified in the command line (see
option /CPUPOS=).
(8)
The position of the JTAG instruction register of the AMD Alchemy Solutions
Au1550 Processor is assumed to be zero, if not specified in the command
line (see option /IROFFS=).
(9)
The real length of the boundary scan register is displayed here and
compared with the boundary scan register length of a AMD Alchemy
Solutions Au1550 Processor.
(10) A Flash AMD 29LV160B selected with RCS0# was found.
(11) The resulting data bus size is printed here.
(12) In this example four block must be erased.
(13) If available, the "Unlock Bypass Mode" is activated. In boundary scan
mode, this increases the programming performance by 67..75%.
18
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.9.
Trouble Shooting
Avoid long distances between your Host-PC and the target. If you are using
standard parallel extension cable, the JTAG-BOOSTER may not work. Don't use
Dongles between the parallel port and the JTAG-BOOSTER.
Switch off all special modes of your printer port (EPP, ECP, ...) in the BIOS
setup. Only standard parallel port (SPP) mode is allowed.
If there are problems with autodetection of the flash devices use the /DEVICE=
option. To speed up autodetection specify one of the options /8BIT /16BIT or
/32BIT.
Don't use hardware protected flash memories.
The used chip selects must be defined as output and inactive in the initialization
file (see chapter 1.11 “Initialization file JTAuxxxx.INI”). Also the address bits must
be defined as output.
Use the option /NOWRSETUP to speed up flash programming.
JTAG_alchemyb.doc
19
AMD Alchemy Solutions Processors
1.10.
Error Messages
•
80386 or greater required
The JTAG-BOOSTER does not work on a 8088/8086 or a 80286 platform.
•
Cable not connected or target power fail
The JTAG-Booster (or one of the simple Parallel Port JTAG adapters
selected with the options /LATTICE /WIGGLER /PLS) wasn't found. Please
check connection to parallel port and connection to target. Check target
power. Check the command line options. Check your BIOS-Setup. If you are
using this program with WinNT, Win2000 or WinXP you must specify /LPT2
or /LPT-BASE=378 to get access to the standard printer port.
•
Can't open x:\yyy\zzz\JTAuxxxx.OVL
The overlay file JTAuxxxx.OVL must be in the same directory as
JTAuxxxx.EXE.
•
Configuration file XYZ not found.
The file specified with the option /INI= wasn't found.
•
Device offset out of range
The value specified with the option /OFFSET= is greater than the size of the
detected flash device.
•
Disk full
Writing a output file was aborted as a result of missing disk space.
•
Do not specify option /NOCS with any other chip select
There is a conflict in the command line.
•
Do not specify option /BYTE-MODE. Flash device does not have a byte
mode pin.
The flash device specified with the option /DEVICE= does not support
switching between 16 (or 32) bit mode and 8 bit mode. In practice it does not
have a pin with the name BYTE#
•
Error creating file:
The output file could not be opened. Please check free disk space or write
protection.
20
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
•
Error: Pin-Name is an output only pin
The specified pin cannot be sampled. Check the command line. Check the
initialization file.
•
Error: Pin-Name is an input only pin
The specified pin cannot be activated. Check the command line. Check the
initialization file.
•
Error: Pin-Name may not be read back
The specified pin can be switched to tristate, but cannot be read back. Check
the command line.
•
illegal function:
The first parameter of the command line must be a valid function. See
chapter 2 “JTAuxxxx Parameter Description” for a list of supported functions.
•
illegal number:
The specified number couldn’t be interpret as a valid number. Check the
relevant number base.
•
illegal option:
See chapter 2 “JTAuxxxx Parameter Description” for a list of supported
options.
•
illegal Pin Type:
The name specified with the option /PIN= must be one of the list of chapter
1.11 ”Initialization file JTAuxxxx.INI”
•
illegal Flash Type:
The name specified with the option /DEVICE= must be one of the list of
chapter 1.12 “Supported flash devices”
•
Input file not found:
The specified file cannot be found
•
Input file is empty:
Files with zero length are not accepted
JTAG_alchemyb.doc
21
AMD Alchemy Solutions Processors
•
" " is undefined
Please check the syntax in your configuration file. (See chapter 1.11
“Initialization file JTAuxxxx.INI”).
•
LPTx not installed
The LPT port specified with /LPTx cannot be found. Please check the LPT
port or specify a installed LPT port. Check your BIOS setup. If you are using
this program with WinNT, Win2000 or WinXP you 1st must install the WinNT
support package as described in chapter 5"Support for Windows NT,
Windows 2000 and Windows XP
•
missing filename
Most functions need a filename as second parameter.
•
missing option /SERCLK=
Some functions need the option /SERCLK= to be defined.
•
missing option /SERDAT=
Some functions need the option /SERDAT= or the options /SERDATO=
and /SERDATI= to be defined.
•
missing option /SERCS=
Some functions need the option /SERCS= if the option /SPI or the option
/MWIRE is specified.
•
missing option /LENGTH=
Some functions need the option /LENGTH= to be defined.
•
missing option /PIN=
Some functions need the option /PIN= to be defined.
•
More than 9 devices in the JTAG chain or TDO pin stuck at low level
The JTAG chain is limited to 9 parts. Check target power. Check the target’s
TDO pin.
•
No devices found in JTAG chain or TDO pin stuck at high level
A stream of 32 high bits was detected on the pin TDO. TDO may stuck at
high level. Check the connection to your target. Check the target power.
Check the target’s TDO pin.
22
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
•
Option /CPUPOS= out of range
The number specified with the option /CPUPOS= must be less or equal to
the number of parts minus 1.
•
Option /IROFFS= out of range
Please specify a smaller value
•
Part at specified position is not a AMD Alchemy Solutions Processors
The option /CPUPOS= points to a part not a AMD Alchemy Solutions
Processors
•
Pins specified with /SERCLK= and /SERDAT= must have different
control cells
The pin specified with the option /SERDAT= must be able to be switched to
high impedance while the pin specified with option /SERCLK= is an active
output. See chapter 1.11 “Initialization file JTAuxxxx.INI”.
•
Pins specified with /SERCLK= and /SERDATI= must have different
control cells
The pin specified with the option /SERDATI= must be able to be switched to
high impedance while the pin specified with option /SERCLK= is an active
output. See chapter 1.11 “Initialization file JTAuxxxx.INI”.
•
Pins specified with /SERDATO= and /SERDATI= must have different
control cells
The pin specified with the option /SERDATI= must be able to be switched to
high impedance while the pin specified with option /SERDATO= is an active
output. See chapter 1.11 “Initialization file JTAuxxxx.INI”.
•
Specify only one of these options:
Some options are exclusive (i.e. /8BIT and /16BIT). Don't mix them.
•
Sum of instruction register bits to low. Should be at least 5 bits for a
AMD Alchemy Solutions Processors
The sum of all instruction register bits in the JTAG chain does not fit to the
AMD Alchemy Solutions Processors. Check the target connection. Check the
target CPU type. Check the settings for /IROFFS= and /CPUPOS= , if
there are several parts in the JTAG chain.
JTAG_alchemyb.doc
23
AMD Alchemy Solutions Processors
•
Target no longer connected
There is a cyclic check of the JTAG chain. Check target power. Check target
connection.
•
There are unknown parts in the JTAG chain. Please use the option
/IROFFS= to specify the instr. reg. offset of the CPU.
If there are unknown parts in the JTAG chain, the program isn’t able to
determine the logical position of the CPU’s instruction register.
•
There is no AMD Alchemy Solutions Processors in the JTAG chain
No AMD Alchemy Solutions Processors was found in the JTAG chain. Check
the target power. Try with option /DRIVER=4 again.
•
Value of option /FILE-OFFSET out of range
The value of the option /FILE-OFFSET= points behind end of file.
•
wrong driver #
The value specified with the option /DRIVER= is out of range.
•
Wrong Flash Identifier (xxxx)
No valid identifier found. Check the specified chip select signal and the bus
width. Try with the option /DEVICE= . Use the option /8BIT or /16BIT or
/32BIT to specify the correct data bus size.
•
Wrong length of boundary scan register. Should be 569 for a AMD
Alchemy Solutions Au1000 Processor. (Should be 672 for a AMD
Alchemy Solutions Au1100 Processor. Should be 744 for a AMD
Alchemy Solutions Au1500 Processor Should be 773 for a AMD
Alchemy Solutions Au1550 Processor.)
The length of the boundary scan register of the selected part (if there are
more than one in the chain) does not fit to the AMD Alchemy Solutions
Processors. Check the target connection. Check the target CPU type. Check
the settings for /IROFFS= and /CPUPOS= , if there are several parts in the
JTAG chain.
24
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
1.11.
Initialization file JTAuxxxx.INI
This file is used to define the default direction and level of all CPU signals. This
file must be carefully adapted to your design with the AMD Alchemy Solutions
Processors. The Target-Entry is used to identify your design which is displayed
with most commands.
When the program JTAuxxxx.EXE is started it scans the current directory for an
existing initialization file named JTAuxxxx.INI. If no entry is found the default
values are used. You may also specify the initialization file with the option /INI= .
If the specified file isn't found, the program aborts with an error message.
The CPU pins can also be used with the functions /BLINK (chapter 2.9), /PIN?
(chapter 2.10) and /SAMPLE (chapter 2.11) to test the signals on your design.
The sample file below represents the values which are used for default
initialization when no initialization file could be found in the current directory and
no initialization file is specified with the option /INI=.
Changes to the structure of the file could result in errors. Remarks can be added
by using //.
JTAG_alchemyb.doc
25
AMD Alchemy Solutions Processors
Sample File JTAu1000.INI:
// Description file for AMD Au1000
Target: Generic Target, 2003/10/02
// Adapt this file carefully to your design!!
// All chip select signals are set to output and inactive.
// All signals should be defined. Undefined signals are set to their defaults.
// Pin names are defined in upper case.
// Low active signals are signed with a trailing #.
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// During flash programming these pins are switched between
// input/inactive and output/active.
// For Flash programming and other memory accesses
// these pins should be set to Input
RD0
Inp
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Data Bus
RD1
Inp
//
RD2
Inp
//
RD3
Inp
//
RD4
Inp
//
RD5
Inp
//
RD6
Inp
//
RD7
Inp
//
RD8
Inp
//
RD9
Inp
//
RD10
Inp
//
RD11
Inp
//
RD12
Inp
//
RD13
Inp
//
RD14
Inp
//
RD15
Inp
//
RD16
Inp
//
RD17
Inp
//
RD18
Inp
//
RD19
Inp
//
RD20
Inp
//
RD21
Inp
//
26
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
RD22
RD23
RD24
RD25
RD26
RD27
RD28
RD29
RD30
RD31
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
//
//
//
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// For Flash Programming these pins must be set to output
RAD0
Out,Lo // SRAM/IO/PCMCIA/FLASH/ROM/LCD Address Bus
RAD1
Out,Lo //
RAD2
Out,Lo //
RAD3
Out,Lo //
RAD4
Out,Lo //
RAD5
Out,Lo //
RAD6
Out,Lo //
RAD7
Out,Lo //
RAD8
Out,Lo //
RAD9
Out,Lo //
RAD10
Out,Lo //
RAD11
Out,Lo //
RAD12
Out,Lo //
RAD13
Out,Lo //
RAD14
Out,Lo //
RAD15
Out,Lo //
RAD16
Out,Lo //
RAD17
Out,Lo //
RAD18
Out,Lo //
RAD19
Out,Lo //
RAD20
Out,Lo //
RAD21
Out,Lo //
RAD22
Out,Lo //
RAD23
Out,Lo //
JTAG_alchemyb.doc
27
AMD Alchemy Solutions Processors
RAD24
RAD25
RAD26
RAD27
RAD28
RAD29
RAD30
RAD31
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Lo
Out,Hi
//
//
//
//
//
//
//
//
// Group 552: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBH1P
Inp
//
USBH1M
Inp
//
// Group 546: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBDP
Inp
// USBH0P
USBDM
Inp
// USBH0M
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
GPIO10
Inp
// U3DSR#
GPIO11
Inp
// U3DCD#
GPIO12
Inp
// U3RI#
S0DOUT
Inp
// GPIO16
S0CLK
Inp
// GPIO17
S0DEN
Inp
// GPIO18
IRDATX
Inp
// GPIO19
I2SDIO
Inp
// GPIO29
ACRST#
Inp
// S1DEN
ACSYNC
Inp
// S1DOUT
ACDO
Inp
// S1CLK
I2SCLK
Inp
// GPIO30
I2SWORD
Inp
// GPIO31
U0TXD
Inp
// GPIO20
U1TXD
Inp
// GPIO21
U2TXD
Inp
// GPIO22
U3TXD
Inp
// GPIO23
28
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
GPIO13
GPIO14
GPIO15
N0TXEN
N0TXD0
N0TXD1
N0TXD2
N0TXD3
N0MDC
N0MDIO
N1TXEN
N1TXD0
N1TXD1
N1TXD2
N1TXD3
N1MDC
N1MDIO
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDD16
SDD17
SDD18
SDD19
SDD20
SDD21
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
// U3RTS#
// U3DTR#
// IRFIRSEL
//
//
//
//
//
//
//
// GPIO24
// GPIO25
// GPIO26
// GPIO27
// GPIO28
//
//
// SDRAM Data Bus
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
29
AMD Alchemy Solutions Processors
SDD22
SDD23
SDD24
SDD25
SDD26
SDD27
SDD28
SDD29
SDD30
SDD31
SDCLK0
SDCLK1
SDCLK2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
PIOW#
PIOR#
POE#
PREG#
PCE1#
PCE2#
PWE#
LRD0#
LRD1#
LWR0#
LWR1#
RBEN0#
RBEN1#
RBEN2#
RBEN3#
RWE#
30
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Lo
Out,Lo
Out,Lo
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Hi
Out,Hi
Out,Hi
Inp
Out,Hi
Out,Hi
Inp
Inp
Inp
Inp
Inp
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// EXTCLK0
// EXTCLK1
// DMA_REQ0
// DMA_REQ1
// SMROMCKE
//
// I2SDI
// U3CTS#
// PCMCIA Write Cycle Indication
// PCMCIA Read Cycle Indication
// PCMCIA Output Enable
// PCMCIA register-only access signal
// PCMCIA Card Enable
// PCMCIA Card Enable
// PCMCIA write enable
// LCD Controller Chip Interface read indicator
// LCD Controller Chip Interface read indicator
// LCD Controller Chip Interface write indicator
// LCD Controller Chip Interface write indicator
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Byte Enable
//
//
//
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Write Enable
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
ROE#
RCS0#
RCS1#
RCS2#
RCS3#
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Output Enable
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Chip Select
//
//
//
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
SDCS0#
Out,Hi // Programmable Chip Select
SDCS1#
Out,Hi //
SDCS2#
Out,Hi //
SDWE#
Out,Hi // SDRAM command Output
SDRAS#
Out,Hi // SDRAM command Output
SDCAS#
Out,Hi // SDRAM command Output
SDCKE
Out,Lo // SDRAM Clock enable
SDQM0#
Out,Hi // SDRAM Byte Mask
SDQM1#
Out,Hi // SDRAM Byte Mask
SDQM2#
Out,Hi // SDRAM Byte Mask
SDQM3#
Out,Hi // SDRAM Byte Mask
SDBA0
Out,Lo // SDRAM Bak Address
SDBA1
Out,Lo // SDRAM Bak Address
SDA0
Out,Lo // SDRAM Address Output
SDA1
Out,Lo //
SDA2
Out,Lo //
SDA3
Out,Lo //
SDA4
Out,Lo //
SDA5
Out,Lo //
SDA6
Out,Lo //
SDA7
Out,Lo //
SDA8
Out,Lo //
SDA9
Out,Lo //
SDA10
Out,Lo //
SDA11
Out,Lo //
SDA12
Out,Lo //
RESETOUT# Out,Hi // Buffered Output of CPU Reset Input
LCLK
Out,Lo // LCD Controller Chip Interface Clock
JTAG_alchemyb.doc
31
AMD Alchemy Solutions Processors
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
U0RXD
U1RXD
U2RXD
IRDARX
U3RXD
ACDI
ACBCLK
N0CRS
N0RXD0
N0RXD1
N0RXD2
N0RXD3
N0RXCLK
N0RXDV
N0COL
N0TXCLK
N1CRS
N1RXD0
N1RXD1
N1RXD2
N1RXD3
N1RXCLK
N1RXDV
N1COL
N1TXCLK
VDDXOK
TESTEN
ROMSEL
ROMSIZE
RESETIN#
TC0
TC1
TC2
TC3
PIOS16#
32
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
// UART0 receive
// UART1 receive
// UART2 receive
// Serial IrDA input
// UART3 receive
// AC-Link TDM input stream
// S1DIN
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// VDDX stable
// Test Enable, should be pulled low
// Boot from ROM or SMROM
// ROM width 16 or 32 bit
// CPU Reset input
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// PCMCIA I/O is 16 Bit
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
PWAIT#
LWAIT#
EWAIT#
Inp
Inp
Inp
JTAG_alchemyb.doc
// PCMCIA entend Cycle
// LCD Controller Chip Interface Extend Cycle
// SRAM/IO/PCMCIA/FLASH/ROM Extend Cycle
33
AMD Alchemy Solutions Processors
Sample File JTAu1100.INI:
// Description file for AMD Au1100
Target: Generic Target, 2003/10/02
// Adapt this file carefully to your design!!
// All chip select signals are set to output and inactive.
// All signals should be defined. Undefined signals are set to their defaults.
// Pin names are defined in upper case.
// Low active signals are signed with a trailing #.
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// During flash programming these pins are switched between
// input/inactive and output/active.
// For Flash programming and other memory accesses
// these pins should be set to Input
RD0
Inp
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Data Bus
RD1
Inp
//
RD2
Inp
//
RD3
Inp
//
RD4
Inp
//
RD5
Inp
//
RD6
Inp
//
RD7
Inp
//
RD8
Inp
//
RD9
Inp
//
RD10
Inp
//
RD11
Inp
//
RD12
Inp
//
RD13
Inp
//
RD14
Inp
//
RD15
Inp
//
RD16
Inp
//
RD17
Inp
//
RD18
Inp
//
RD19
Inp
//
RD20
Inp
//
RD21
Inp
//
34
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
RD22
RD23
RD24
RD25
RD26
RD27
RD28
RD29
RD30
RD31
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
//
//
//
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// For Flash Programming these pins must be set to output
RAD0
Out,Lo // SRAM/IO/PCMCIA/FLASH/ROM/LCD Address Bus
RAD1
Out,Lo //
RAD2
Out,Lo //
RAD3
Out,Lo //
RAD4
Out,Lo //
RAD5
Out,Lo //
RAD6
Out,Lo //
RAD7
Out,Lo //
RAD8
Out,Lo //
RAD9
Out,Lo //
RAD10
Out,Lo //
RAD11
Out,Lo //
RAD12
Out,Lo //
RAD13
Out,Lo //
RAD14
Out,Lo //
RAD15
Out,Lo //
RAD16
Out,Lo //
RAD17
Out,Lo //
RAD18
Out,Lo //
RAD19
Out,Lo //
RAD20
Out,Lo //
RAD21
Out,Lo //
RAD22
Out,Lo //
RAD23
Out,Lo //
JTAG_alchemyb.doc
35
AMD Alchemy Solutions Processors
RAD24
RAD25
RAD26
RAD27
RAD28
RAD29
RAD30
RAD31
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Lo
Out,Hi
//
//
//
//
//
//
//
//
// Group 666: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBH1P
Inp
//
USBH1M
Inp
//
// Group 659: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBDP
Inp
//
USBDM
Inp
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
GPIO10
Inp
// U3DSR#
GPIO11
Inp
// U3DCD#
GPIO12
Inp
// U3RI#
S0DOUT
Inp
// GPIO208
S0CLK
Inp
// GPIO209
S0DEN
Inp
// GPIO210
IRDATX
Inp
// GPIO211
I2SDIO
Inp
// GPIO29
ACRST#
Inp
// S1DEN#
ACSYNC
Inp
// S1DOUT
ACDO
Inp
// S1CLK
I2SCLK
Inp
// GPIO30
I2SWORD
Inp
// GPIO31
U0TXD
Inp
// GPIO212
U1TXD
Inp
// GPIO213
U3TXD
Inp
// GPIO214
GPIO13
Inp
// U3RTS#
36
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
GPIO14
GPIO15
N0TXEN
N0TXD0
N0TXD1
N0TXD2
N0TXD3
N0MDC
N0MDIO
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23
RESVD_3
LCD_PWM0
LCD_PWM1
SDMS0_CLK
SDMS0_CMD
SDMS0_DAT0
SDMS0_DAT1
SDMS0_DAT2
SDMS0_DAT3
SDMS1_CLK
SDMS1_CMD
SDMS1_DAT0
SDMS1_DAT1
SDMS1_DAT2
SDMS1_DAT3
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Lo
Inp
Inp
Inp
Inp
Inp
Out,Lo
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
// U3DTR#
// IRFIRSEL
// GPIO24
// GPIO25
// GPIO26
// GPIO27
// GPIO28
// GPIO215
//
//
//
//
//
//
//
//
//
// Reserved, should be left open
// Pulse Width Modulation Clock 0
// Pulse Width Modulation Clock 1
// SD Card 0 Interface Clock
// SD Card 0 Half Duplex Command and Response
// SD Card 0 Data Bus
// SD Card 0 Data Bus
// SD Card 0 Data Bus
// SD Card 0 Data Bus
// SD Card 1 Interface Clock
// SD Card 1 Half Duplex Command and Response
// SD Card 1 Data Bus
// SD Card 1 Data Bus
// SD Card 1 Data Bus
// SD Card 1 Data Bus
// SDRAM Data Bus
//
//
//
//
//
//
37
AMD Alchemy Solutions Processors
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
SDD16
SDD17
SDD18
SDD19
SDD20
SDD21
SDD22
SDD23
SDD24
SDD25
SDD26
SDD27
SDD28
SDD29
SDD30
SDD31
SDCLK0
SDCLK1
SDCLK2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
PIOW#
38
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Lo
Out,Lo
Out,Lo
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Hi
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// EXTCLK0
// EXTCLK1
// DMA_REQ0
// DMA_REQ1
// SMROMCKE
//
// I2SDI
// U3CTS#
// PCMCIA Write Cycle Indication
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
PIOR#
POE#
PREG#
PCE1#
PCE2#
PWE#
LRD0#
LRD1#
LWR0#
LWR1#
RBEN0#
RBEN1#
RBEN2#
RBEN3#
RWE#
ROE#
RCS0#
RCS1#
RCS2#
RCS3#
LCD_D0
LCD_D1
LCD_D2
LCD_D3
LCD_D4
LCD_D5
LCD_D6
LCD_D7
LCD_D8
LCD_D9
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_LCK
LCD_FCK
LCD_BIAS
Out,Hi
Out,Hi
Inp
Out,Hi
Out,Hi
Inp
Inp
Inp
Inp
Inp
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
JTAG_alchemyb.doc
// PCMCIA Read Cycle Indication
// PCMCIA Output Enable
// GPIO204
// GPIO205
// GPIO206
// GPIO207
// GPIO200
// GPIO201
// GPIO202
// GPIO203
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Byte Enable
//
//
//
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Write Enable
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Output Enable
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Chip Select
//
//
//
// LCD Data Output
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// LCD Line Clock
// LCD Frame Clock
// LCD Bias Clock
39
AMD Alchemy Solutions Processors
LCD_LEND
Out,Lo // LCD Line End
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
SDCS0#
Out,Hi // Programmable Chip Select
SDCS1#
Out,Hi //
SDCS2#
Out,Hi //
SDWE#
Out,Hi // SDRAM command Output
SDRAS#
Out,Hi // SDRAM command Output
SDCAS#
Out,Hi // SDRAM command Output
SDCKE
Out,Lo // SDRAM Clock enable
SDQM0#
Out,Hi // SDRAM Byte Mask
SDQM1#
Out,Hi // SDRAM Byte Mask
SDQM2#
Out,Hi // SDRAM Byte Mask
SDQM3#
Out,Hi // SDRAM Byte Mask
SDBA0
Out,Lo // SDRAM Bak Address
SDBA1
Out,Lo // SDRAM Bak Address
SDA0
Out,Lo // SDRAM Address Output
SDA1
Out,Lo //
SDA2
Out,Lo //
SDA3
Out,Lo //
SDA4
Out,Lo //
SDA5
Out,Lo //
SDA6
Out,Lo //
SDA7
Out,Lo //
SDA8
Out,Lo //
SDA9
Out,Lo //
SDA10
Out,Lo //
SDA11
Out,Lo //
SDA12
Out,Lo //
RESETOUT# Out,Hi // Buffered Output of CPU Reset Input
LCLK
Out,Lo // LCD Controller Chip Interface Clock
LCD_PCK
Out,Lo // LCD Pixel Clock
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
U0RXD
Inp
// UART0 receive
U1RXD
Inp
// UART1 receive
40
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
IRDARX
U3RXD
ACDI
ACBCLK
N0CRS
N0RXD0
N0RXD1
N0RXD2
N0RXD3
N0RXCLK
N0RXDV
N0COL
N0TXCLK
RESVD_0
RESVD_1
RESVD_2
RESVD_4
RESVD_5
VSEL
TESTEN
ROMSEL
ROMSIZE
RESETIN#
TC0
TC1
TC2
TC3
PIOS16#
PWAIT#
LWAIT#
EWAIT#
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
// Serial IrDA input
// UART3 receive
// AC-Link TDM input stream
// S1DIN
//
//
//
//
//
//
//
//
//
// Reserved, should be pulled low
// Reserved, should be pulled low
// Reserved, should be pulled low
// Reserved, should be pulled low
// Reserved, should be pulled low
// External SDRAM Voltage Type: 0=2.5V, 1=3.3V
// Test Enable, should be pulled low
// Boot from ROM or SMROM
// ROM width 16 or 32 bit
// CPU Reset input
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// PCMCIA I/O is 16 Bit
// PCMCIA entend Cycle
// LCD Controller Chip Interface Extend Cycle
// SRAM/IO/PCMCIA/FLASH/ROM Extend Cycle
41
AMD Alchemy Solutions Processors
Sample File JTAu1500.INI:
// Description file for AMD Alchemy Solutions Au1500 Processor
Target: Generic Target, 2003/10/02
// Adapt this file carefully to your design!!
// All chip select signals are set to output and inactive.
// All signals should be defined. Undefined signals are set to their defaults.
// Pin names are defined in upper case.
// Low active signals are signed with a trailing #.
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// During flash programming these pins are switched between
// input/inactive and output/active.
// For Flash programming and other memory accesses
// these pins should be set to Input
RD0
Inp
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Data Bus
RD1
Inp
//
RD2
Inp
//
RD3
Inp
//
RD4
Inp
//
RD5
Inp
//
RD6
Inp
//
RD7
Inp
//
RD8
Inp
//
RD9
Inp
//
RD10
Inp
//
RD11
Inp
//
RD12
Inp
//
RD13
Inp
//
RD14
Inp
//
RD15
Inp
//
RD16
Inp
//
RD17
Inp
//
RD18
Inp
//
RD19
Inp
//
RD20
Inp
//
RD21
Inp
//
42
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
RD22
RD23
RD24
RD25
RD26
RD27
RD28
RD29
RD30
RD31
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
//
//
//
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// For Flash Programming these pins must be set to output
RAD0
Out,Lo // SRAM/IO/PCMCIA/FLASH/ROM/LCD Address Bus
RAD1
Out,Lo //
RAD2
Out,Lo //
RAD3
Out,Lo //
RAD4
Out,Lo //
RAD5
Out,Lo //
RAD6
Out,Lo //
RAD7
Out,Lo //
RAD8
Out,Lo //
RAD9
Out,Lo //
RAD10
Out,Lo //
RAD11
Out,Lo //
RAD12
Out,Lo //
RAD13
Out,Lo //
RAD14
Out,Lo //
RAD15
Out,Lo //
RAD16
Out,Lo //
RAD17
Out,Lo //
RAD18
Out,Lo //
RAD19
Out,Lo //
RAD20
Out,Lo //
RAD21
Out,Lo //
RAD22
Out,Lo //
RAD23
Out,Lo //
JTAG_alchemyb.doc
43
AMD Alchemy Solutions Processors
RAD24
RAD25
RAD26
RAD27
RAD28
RAD29
RAD30
RAD31
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Lo
Out,Hi
//
//
//
//
//
//
//
//
// Group 151: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBH1P
Inp
//
USBH1M
Inp
//
// Group 146: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBDP
Inp
//
USBDM
Inp
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
GPIO10
Inp
// U3DSR#
GPIO11
Inp
// U3DCD#
GPIO12
Inp
// U3RI#
GPIO200
Inp
// PCI_RSTO#
GPIO201
Inp
//
GPIO202
Inp
//
GPIO203
Inp
//
GPIO204
Inp
//
GPIO205
Inp
//
GPIO206
Inp
//
GPIO207
Inp
//
GPIO208
Inp
// DMA_REQ2
GPIO209
Inp
// DMA_REQ3
GPIO210
Inp
//
GPIO211
Inp
//
GPIO212
Inp
//
GPIO213
Inp
//
44
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
GPIO214
GPIO215
ACRST#
ACSYNC
ACDO
U0TXD
U3TXD
GPIO13
GPIO14
GPIO15
N0TXEN
N0TXD0
N0TXD1
N0TXD2
N0TXD3
N0MDC
N0MDIO
N1TXEN
N1TXD0
N1TXD1
N1TXD2
N1TXD3
N1MDC
N1MDIO
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
//
//
// AC-Link CODEC reset
// AC-Link fixed rate sample sync
// AC-Link TDM output stream
// GPIO20
// GPIO23
// U3RTS#
// U3DTR#
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// SDRAM Data Bus
//
//
//
//
//
//
//
//
//
//
//
//
//
//
45
AMD Alchemy Solutions Processors
SDD15
SDD16
SDD17
SDD18
SDD19
SDD20
SDD21
SDD22
SDD23
SDD24
SDD25
SDD26
SDD27
SDD28
SDD29
SDD30
SDD31
SDCLK0
SDCLK1
SDCLK2
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
PIOW#
PIOR#
POE#
PREG#
PCE1#
PCE2#
PWE#
LRD0#
LRD1#
46
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Lo
Out,Lo
Out,Lo
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// EXTCLK0
// EXTCLK1
// DMA_REQ0
// DMA_REQ1
// SMROMCKE
//
//
// U3CTS#
// PCMCIA Write Cycle Indication
// PCMCIA Read Cycle Indication
// PCMCIA Output Enable
// PCMCIA register-only access signal
// PCMCIA card enable
// PCMCIA card enable
// PCMCIA write enable
// LCD controller chip interface read indicator
// LCD controller chip interface read indicator
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
LWR0#
LWR1#
RBEN0#
RBEN1#
RBEN2#
RBEN3#
RWE#
ROE#
RCS0#
RCS1#
RCS2#
RCS3#
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_PERR#
PCI_SERR#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
Out,Hi
Out,Hi
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
// LCD controller chip interface write indicator
// LCD controller chip interface write indicator
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Byte Enable
//
//
//
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Write Enable
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Output Enable
// SRAM/IO/PCMCIA/FLASH/ROM/LCD Chip Select
//
//
//
// PCI device select
// PCI target stop
// PCI frame
// PCI initiator ready
// PCI target ready
// PCI parity
// PCI arbiter bus grant output
// PCI arbiter bus grant output
// PCI arbiter bus grant output
// PCI arbiter bus grant output
// PCI parity error
// PCI system error
// PCI address/data
//
//
//
//
//
//
//
//
//
//
//
//
//
//
47
AMD Alchemy Solutions Processors
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// PCI bus command and byte enable
//
//
//
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
SDCS0#
Out,Hi // SDRAM Programmable Chip Select
SDCS1#
Out,Hi //
SDCS2#
Out,Hi //
SDWE#
Out,Hi // SDRAM command Output
SDRAS#
Out,Hi // SDRAM command Output
SDCAS#
Out,Hi // SDRAM command Output
SDCKE
Out,Lo // SDRAM Clock enable
SDQM0#
Out,Hi // SDRAM Byte Mask
SDQM1#
Out,Hi // SDRAM Byte Mask
SDQM2#
Out,Hi // SDRAM Byte Mask
SDQM3#
Out,Hi // SDRAM Byte Mask
SDBA0
Out,Lo // SDRAM Bank Address
SDBA1
Out,Lo // SDRAM Bank Address
SDA0
Out,Lo // SDRAM Address Output
SDA1
Out,Lo //
48
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
SDA2
SDA3
SDA4
SDA5
SDA6
SDA7
SDA8
SDA9
SDA10
SDA11
SDA12
RESETOUT#
LCLK
PCI_CLKO
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Lo
Out,Lo
//
//
//
//
//
//
//
//
//
//
//
// Buffered Output of CPU Reset Input
// LCD Controller Chip Interface Clock
// PCI clock output
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
U0RXD
Inp
// UART0 receive
U3RXD
Inp
// UART3 receive
PCI_LOCK#
Inp
// PCI lock fopr atomic operations
PCI_CLK
Inp
// PCI input clock
PCI_REQ0#
Inp
// PCI arbiter bus request input
PCI_REQ1#
Inp
// PCI arbiter bus request input
PCI_REQ2#
Inp
// PCI arbiter bus request input
PCI_REQ3#
Inp
// PCI arbiter bus request input
PCI_CFG
Inp
// PCI configuration, 0->sattelite mode, 1->host mode
PCI_IDSEL
Inp
// PCI initialization device select input
PCI_INTA#
Inp
// PCI interrupt input
PCI_INTB#
Inp
// PCI interrupt input
PCI_INTC#
Inp
// PCI interrupt input
PCI_INTD#
Inp
// PCI interrupt input
PCI_RST#
Inp
// PCI reset input
ACDI
Inp
// AC-Link TDM input stream
ACBCLK
Inp
// AC-Link serial data clock
N0CRS
Inp
//
N0RXD0
Inp
//
N0RXD1
Inp
//
N0RXD2
Inp
//
JTAG_alchemyb.doc
49
AMD Alchemy Solutions Processors
N0RXD3
N0RXCLK
N0RXDV
N0COL
N0TXCLK
N1CRS
N1RXD0
N1RXD1
N1RXD2
N1RXD3
N1RXCLK
N1RXDV
N1COL
N1TXCLK
VDDXOK
TESTEN
ROMSEL
ROMSIZE
RESETIN#
TC0
TC1
TC2
TC3
PIOS16#
PWAIT#
LWAIT#
EWAIT#
50
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// VDDX stable
// Test enable, should be pulled low
// Boot from ROM or SMROM
// ROM width 16 or 32 bit
// CPU Reset input
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// PCMCIA I/O is 16 Bit
// PCMCIA entend Cycle
// LCD Controller Chip Interface Extend Cycle
// SRAM/IO/Flash/ROM Extend Cycle
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
Sample File JTAu1550.INI:
// Description file for AMD Alchemy Solutions Au1550 Processor
Target: Generic Target, 2004/11/19
// Adapt this file carefully to your design!!
// All chip select signals are set to output and inactive.
// All signals should be defined. Undefined signals are set to their defaults.
// Pin names are defined in upper case.
// Low active signals are signed with a trailing #.
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// During flash programming these pins are switched between
// input/inactive and output/active.
// For Flash programming and other memory accesses
// these pins should be set to Input
RD0
Inp
// SRAM/IO/PCMCIA/FLASH/ROM/NAND Data Bus
RD1
Inp
//
RD2
Inp
//
RD3
Inp
//
RD4
Inp
//
RD5
Inp
//
RD6
Inp
//
RD7
Inp
//
RD8
Inp
//
RD9
Inp
//
RD10
Inp
//
RD11
Inp
//
RD12
Inp
//
RD13
Inp
//
RD14
Inp
//
RD15
Inp
//
RD16
Inp
//
RD17
Inp
//
RD18
Inp
//
RD19
Inp
//
RD20
Inp
//
RD21
Inp
//
RD22
Inp
//
RD23
Inp
//
RD24
Inp
//
RD25
Inp
//
JTAG_alchemyb.doc
51
AMD Alchemy Solutions Processors
RD26
RD27
RD28
RD29
RD30
RD31
Inp
Inp
Inp
Inp
Inp
Inp
//
//
//
//
//
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
// For Flash Programming these pins must be set to output
RAD0
Out,Lo // SRAM/IO/PCMCIA/FLASH/ROM/NAND Address Bus
RAD1
Out,Lo //
RAD2
Out,Lo //
RAD3
Out,Lo //
RAD4
Out,Lo //
RAD5
Out,Lo //
RAD6
Out,Lo //
RAD7
Out,Lo //
RAD8
Out,Lo //
RAD9
Out,Lo //
RAD10
Out,Lo //
RAD11
Out,Lo //
RAD12
Out,Lo //
RAD13
Out,Lo //
RAD14
Out,Lo //
RAD15
Out,Lo //
RAD16
Out,Lo //
RAD17
Out,Lo //
RAD18
Out,Lo //
RAD19
Out,Lo //
RAD20
Out,Lo //
RAD21
Out,Lo //
RAD22
Out,Lo //
RAD23
Out,Lo //
RAD24
Out,Lo //
RAD25
Out,Lo //
RAD26
Out,Lo //
RAD27
Out,Lo //
RAD28
Out,Lo //
// Group 765: All pins in this group must be set to the same direction
//
These pins are bidirectional
52
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
USBH0P
USBH0M
Inp
Inp
//
//
// Group 760: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBH1P
Inp
//
USBH1M
Inp
//
// Group 770: All pins in this group must be set to the same direction
//
These pins are bidirectional
USBDP
Inp
//
USBDM
Inp
//
// The following pins are complete bidirectional pins.
// The direction of each pin can be set independent of the other pins.
// Each pin can be used as an input.
GPIO200
Inp
// PCI_RSTO#
GPIO201
Inp
// PSC0_EXTCLK
GPIO202
Inp
// PSC1_EXTCLK
GPIO203
Inp
// PSC2_EXTCLK
GPIO204
Inp
// PSC3_EXTCLK
GPIO205
Inp
//
GPIO206
Inp
// PSC2_SYNC1
GPIO207
Inp
// PSC2_SYNC0
GPIO208
Inp
// PSC2_D1/DMA_REQ2
GPIO209
Inp
// PSC2_D0/DMA_REQ3
GPIO210
Inp
// PSC2_CLK
GPIO211
Inp
// PSC3_SYNC1
GPIO212
Inp
// PSC3_SYNC0
GPIO213
Inp
// PSC3_D1
GPIO214
Inp
// PSC3_D0
GPIO215
Inp
// PSC3_CLK
U0TXD
Inp
// GPIO20
U1TXD
Inp
// GPIO21
U1RTS#
Inp
// GPIO22
U3TXD
Inp
// GPIO23
N0TXEN
Inp
//
N0TXD0
Inp
//
N0TXD1
Inp
//
N0TXD2
Inp
//
N0TXD3
Inp
//
N0MDC
Inp
//
N0MDIO
Inp
//
JTAG_alchemyb.doc
53
AMD Alchemy Solutions Processors
N1TXEN
N1TXD0
N1TXD1
N1TXD2
N1TXD3
N1MDC
N1MDIO
DDQ0
DDQ1
DDQ2
DDQ3
DDQ4
DDQ5
DDQ6
DDQ7
DDQ8
DDQ9
DDQ10
DDQ11
DDQ12
DDQ13
DDQ14
DDQ15
DDQ16
DDQ17
DDQ18
DDQ19
DDQ20
DDQ21
DDQ22
DDQ23
DDQ24
DDQ25
DDQ26
DDQ27
DDQ28
DDQ29
DDQ30
DDQ31
DDQS0
DDQS1
DDQS2
DDQS3
54
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
// GPIO24
// GPIO25
// GPIO26
// GPIO27
// GPIO28
//
//
// SDRAM Data Bus
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// DDR SDRAM Strobe
//
//
//
JTAG_alchemyb.doc
AMD Alchemy Solutions Processors
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
PIOW#
PIOR#
POE#
PREG#
PCE1#
PCE2#
PWE#
RBEN0#
RBEN1#
RBEN2#
RBEN3#
RWE#
ROE#
RCS0#
RCS1#
RCS2#
RCS3#
RALE
RCLE
PCI_DEVSEL#
PCI_STOP#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_PAR
PCI_GNT0#
PCI_GNT1#
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Lo
Out,Lo
Out,Lo
Out,Lo
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Hi
Out,Lo
Out,Lo
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
//
//
// EXTCLK0
// EXTCLK1
// DMA_REQ0
// DMA_REQ1
// SMROMCKE
//
//
// U3CTS#
// U3DSR#
// U3DCD#
// U3RI#
// U3RTS#
// U3DTR#
//
// PCMCIA Write Cycle Indication
// PCMCIA Read Cycle Indication
// PCMCIA Output Enable
// PCMCIA register-only access signal
// PCMCIA card enable
// PCMCIA card enable
// PCMCIA write enable
// SRAM/IO/PCMCIA/FLASH/ROM/NAND Byte Enable
//
//
//
// SRAM/IO/PCMCIA/FLASH/ROM/NAND Write Enable
// SRAM/IO/PCMCIA/FLASH/ROM/NAND Output Enable
// SRAM/IO/PCMCIA/FLASH/ROM/NAND Chip Select
//
//
//
// NAND Address Latch Enable
// NAND Command Latch Enable
// PCI device select
// PCI target stop
// PCI frame
// PCI initiator ready
// PCI target ready
// PCI parity
// PCI arbiter bus grant output
// PCI arbiter bus grant output
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AMD Alchemy Solutions Processors
PCI_GNT2#
PCI_GNT3#
PCI_PERR#
PCI_SERR#
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#
PSC0_CLK
PSC0_SYNC0
PSC0_SYNC1
56
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
// PCI arbiter bus grant output
// PCI arbiter bus grant output
// PCI parity error
// PCI system error
// PCI address/data
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
// PCI bus command and byte enable
//
//
//
// PSC0 clock
//
// GPIO16
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AMD Alchemy Solutions Processors
PSC0_D0
PSC0_D1
PSC1_CLK
PSC1_SYNC0
PSC1_SYNC1
PSC1_D0
PSC1_D1
Inp
Inp
Inp
Inp
Inp
Inp
Inp
//
//
// PSC0 clock
//
// GPIO17
//
//
// The following pins are output only pins.
// Setting to input (tristate) one of these pins results in an error.
RESETOUT#
Out,Hi // Buffered Output of CPU Reset Input
DA0
Out,Lo // SDRAM Address Output
DA1
Out,Lo //
DA2
Out,Lo //
DA3
Out,Lo //
DA4
Out,Lo //
DA5
Out,Lo //
DA6
Out,Lo //
DA7
Out,Lo //
DA8
Out,Lo //
DA9
Out,Lo //
DA10
Out,Lo //
DA11
Out,Lo //
DA12
Out,Lo //
DA13
Out,Lo //
DBA0
Out,Lo // SDRAM Bank Address
DBA1
Out,Lo // SDRAM Bank Address
DCS0#
Out,Hi // SDRAM Programmable Chip Select
DCS1#
Out,Hi //
DCS2#
Out,Hi //
DCK0
Out,Lo //
DCK0#
Out,Lo //
DCK1
Out,Lo //
DCK1#
Out,Lo //
DCKE
Out,Lo // SDRAM Clock enable
DRAS#
Out,Hi // SDRAM command Output
DCAS#
Out,Hi // SDRAM command Output
DWE#
Out,Hi // SDRAM command Output
DDM0
Out,Hi // SDRAM Byte Mask
DDM1
Out,Hi // SDRAM Byte Mask
DDM2
Out,Hi // SDRAM Byte Mask
DDM3
Out,Hi // SDRAM Byte Mask
RCLK
Out,Lo // Bus clock output for synchrous mode
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AMD Alchemy Solutions Processors
PCI_CLKO
Out,Lo // PCI clock output
// The following pins are input only.
// Setting to output of one of these pins results in an error.
// Declaration of the direction of these pins is optional.
DRVSEL
Inp
// SDRAM drive strength select
U0RXD
Inp
// UART0 receive
U1RXD
Inp
// UART1 receive
U1CTS#
Inp
// UART1 CTS
U3RXD
Inp
// UART3 receive
PCI_LOCK#
Inp
// PCI lock fopr atomic operations
PCI_CLK
Inp
// PCI input clock
PCI_REQ0#
Inp
// PCI arbiter bus request input
PCI_REQ1#
Inp
// PCI arbiter bus request input
PCI_REQ2#
Inp
// PCI arbiter bus request input
PCI_REQ3#
Inp
// PCI arbiter bus request input
PCI_CFG
Inp
// PCI configuration, 0->sattelite mode, 1->host mode
PCI_IDSEL
Inp
// PCI initialization device select input
PCI_INTA#
Inp
// PCI interrupt input
PCI_INTB#
Inp
// PCI interrupt input
PCI_INTC#
Inp
// PCI interrupt input
PCI_INTD#
Inp
// PCI interrupt input
PCI_RST#
Inp
// PCI reset input
N0CRS
Inp
//
N0RXD0
Inp
//
N0RXD1
Inp
//
N0RXD2
Inp
//
N0RXD3
Inp
//
N0RXCLK
Inp
//
N0RXDV
Inp
//
N0COL
Inp
//
N0TXCLK
Inp
//
N1CRS
Inp
//
N1RXD0
Inp
//
N1RXD1
Inp
//
N1RXD2
Inp
//
N1RXD3
Inp
//
N1RXCLK
Inp
//
N1RXDV
Inp
//
N1COL
Inp
//
N1TXCLK
Inp
//
VDDXOK
Inp
// VDDX stable
WAKE#
Inp
// Wake from hibernate request
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FWTOY#
BOOT0
BOOT1
BOOT2
RESETIN#
TESTEN
TC0
TC1
TC2
TC3
PIOS16#
PWAIT#
EWAIT#
R/B#
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
Inp
JTAG_alchemyb.doc
// Firewall the TOY clock signal
// Boot Memory Select
//
//
// CPU Reset input
// Test enable, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// Test Clock Input, should be pulled low
// PCMCIA I/O is 16 Bit
// PCMCIA extend Cycle
// SRAM/IO/Flash/ROM Extend Cycle
// NAND Ready/not Busy
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AMD Alchemy Solutions Processors
1.12. Supported flash devices
Type JTAuxxxx /LIST [optionlist]
to get a online list of all flash types which could be used with the /DEVICE=
option.
See separate file JTAG_V4xx_FLASHES.pdf to get a complete list of supported
flash types.
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2. JTAuxxxx Parameter Description
When you start JTAuxxxx.EXE without any parameters the following help screen
with all possible functions and options is displayed:
JTAuxxxx --- JTAG utility for AMD Alchemy Solutions Processors
Copyright © FS FORTH-SYSTEME GmbH, Breisach
Version 4.xx of mm/dd/yyyy
Programming of Flash-EPROMs and hardware tests on targets with the
AMD Alchemy Solutions Processors.
The JTAG-Booster is needed to connect the parallel port of the PC
to the JTAG port of the AMD Alchemy Solutions Processors.
Usage: JTAuxxxx /function [filename] [/option_1] ... [/option_n]
Supported functions:
/P
: Program a Flash Device
/R
: Read a Flash Device to file
/V
: Verify a Flash Device with file
/DUMP
: Make a target dump
/PSER
: Program a I2C/SPI/MicroWire Device with file
/RSER
: Read a I2C/SPI/MicroWire Device to file
/VSER
: Verify a I2C/SPI/MicroWire Device with file
/DUMPSER : Make a dump of a I2C/SPI/MicroWire Device
/BLINK
: Toggle a CPU pin
/PIN?
: Test a CPU pin
/SAMPLE : Test a CPU pin while the CPU is running
/SNAP
: Test all CPU pins while CPU is running
/LIST
: Print a list of supported Flash devices
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Supported Options:
/CS0
/CS1
/CS2
/NOCS
/NOWRSETUP /TOP
/CFI
/CFIDEBUG
/PAUSE
/NOERASE /ERASEALL
/LATTICE
/LPT3
/LPT-BASE=
/32BIT
/NOMAN
/LENGTH=
/L=
/OFFSET=
/O=
/DELAY=
/DRIVER=
/IROFFS=
/CPUPOS=
/SERCS=
/SERCLK=
/SERDAT=
/SERBUFF= /SERBIG
/SPI
/SPIERA
/WATCH=
/OUT=
/CS3
/BYTE-MODE
/P
/LPT1
/16BIT
/FILE-OFFSET=
/DEVICE-BASE=
/DEVICE=
/SERDATI=
/MWIRE
/INI=
/BIG
/BM
/NODUMP
/LPT2
/8BIT
/FO=
/DB=
/PIN=
/SERDATO=
/LSB1ST
/REP
The following options are valid for most functions:
/BIG
This option switches the byte ordering to big endian mode. This option must fit to
the target's endianess
Default:
Little Endian
/DRIVER=x with x = 1,2,3,4
A driver for the interface to the JTAG-BOOSTER on the parallel port may be
specified. /DRIVER=1 selects the fastest available driver, /DRIVER=4 selects the
slowest one. Use a slower driver if there are problems with JTAG-BOOSTER.
Default:
/DRIVER=3
/INI=file
An initialization file may be specified. By default the current directory is searched
for the file JTAuxxxx.INI. If this file is not found and no initialization file is
specified in the command line, default initialization values are used (see also
chapter 1.11 “Initialization file JTAuxxxx.INI”).
Note: The initialization file is not loaded for the functions /SAMPLE (chapter
2.11) and /SNAP (chapter 2.12).
Default:
/INI=JTAuxxxx.INI
/LATTICE
For demonstration purposes this software works with the Lattice ispLSI-Adapter,
too. With the option /LATTICE you can simulate the speed achievable with the
simple ispLSI-Adapter.
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/LPT1 /LPT2 /LPT3
A printer port may be specified where the JTAG-Booster resides. If you are using
this program with WinNT, Win2000 or WinXP you must specify /LPT2 or /LPTBASE=378 to get access to the standard printer port.
Default:
/LPT1
/LPT-BASE
The physical I/O-Address of printer port may be specified instead of the logical
printer name. Useful option, if you work with WinNT, Win2000 or WinXP,
because the standard printer port is mapped as LPT2 here. Use the option
/LPT-BASE=378 to get a command line which works independent of the
operating system.
/OUT=file_or_device
All screen outputs are redirected to the specified file or device. Note that you
can't redirect to the same parallel port where the JTAG-Booster resides.
Default:
/OUT=CON
/PAUSE
With the option /PAUSE you can force the program to stop after each screen.
Please do not use this option if you redirect the output to a file.
Abbreviation:
/P
/WATCH=
With the option /WATCH= a pin can be specified, which is toggled twice per
second, while the program is active. This pin may be the trigger of a watchdog.
This pin must be specified as output in the initialization file.
/IROFFS=
Specifies the position of the AMD Alchemy Solutions Processors instruction
register within the JTAG chain. In most cases this option is not needed.
Default:
/IROFFS=0
/CPUPOS=
Specifies the position of the AMD Alchemy Solutions Processors within the JTAG
chain.
Default:
/CPUPOS=0
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AMD Alchemy Solutions Processors
2.1.
Program a Flash Device
Usage:
JTAuxxxx /P filename [optionlist]
The specified file is programmed into the flash memory. The flash status is polled
after programming of each cell (cell=8, 16 or 32 bit, depending on current data
bus width). In case of a programming error, the contents of the flash memory is
written to a file with the extension DMP.
If you want a complete verify after programming, please use an additional
command line with the verify function. See chapter 2.3 “Verify a Flash Device
with file”. In most cases this additional verify step is not needed.
The type of the flash device is normally detected by the software. When
autodetection fails you should use the /DEVICE= option together with /8BIT or
/16BIT or /32BIT to set the right flash device and configuration. The known flash
devices are shown in chapter 1.12 “Supported flash devices”. Use the option
/CFI if the flash is not in the list of know devices.
Options:
/DEVICE=devicename
The flash device is detected automatically by switching to autoselect mode. In
case of trouble you should select the flash device by using this parameter to
avoid autodetection. Combine this option with one of the following options which
specify the data bus width and the option /BYTE-MODE if applicable.
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/CFI
To be prepared for future flash chips, the JTAG-Booster integrates support for
flashes which contain the CFI (Common Flash Interface) information structure.
The CFI support is activated by simply adding the option /CFI to the command
line. The JTAG-Booster then automatically searches in all available bus widths
for all possible flash types and configurations instead of searching for the JEDEC
identification code.
In case of an error add the command line option /CFIDEBUG and redirect the
program output into a file. Sending us this file helps in solving problems.
/8BIT /16BIT /32BIT
Specifies the data bus width to the target flash device. You can speed up
autodetection, if you specify the correct data bus size. You need this option
together with the option /DEVICE= to explicit specify a specific flash
configuration.
/BYTE-MODE
If there is a flash device connected to the CPU which does have a byte mode pin
(8 bit and 16/32 bit bus mode), you can force it to be used as 8 bit mode with the
option /BYTE-MODE. In most cases this option will not be needed.
Abbreviation:
/BM
/NOMAN
If you use a flash device which is identical to one of the supported parts, but is
from a different manufacturer, with this option you can suppress the comparison
of the manufacturer identification code. We recommend to use this option
together with the /DEVICE= option to avoid failures in autodetection.
/DEVICE-BASE=hhhhhh1
Here you can specify a flash device starting address. In most cases, where the
flash device is selected with one of the CPUs chip select pins, this parameter is
not needed. But if there is any decoding logic in your hardware, this option will be
needed. Especially, if there are several flash banks connected to one chip select
and a sub decoding logic generates chip selects for these flash banks, this
option can be used to select a specific flash bank.
Default:
/DEVICE-BASE=0
Abbreviation:
/DB=
1
hhhhhh=number base is hex
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AMD Alchemy Solutions Processors
/OFFSET=hhhhhh
The programming starts at an offset of hhhhhh relative to the start address of the
flash device. If the offset is negative, the offset specifies an address relative to
the end of the flash device. See also option /TOP
Default:
/OFFSET=0
Abbreviation:
/O=
/TOP
If the option /TOP is used the option /OFFSET= specifies the address where the
programming ends (plus one) instead of the starting address. This option is very
important for Intel CPU architectures, because target execution always starts at
the top of the address space.
/FILE-OFFSET=hhhhhh
If FILE-OFFSET is specified, the first hhhhhh bytes of the file are skipped and
not programmed to target.
Default:
/FILE-OFFSET=0
Abbreviation:
/FO=
/LENGTH=hhhhhh
The number of programmed bytes may be limited to LENGTH. If no LENGTH is
specified the whole file is programmed.
Default:
/LENGTH=4000000 (64 MByte)
Abbreviation:
/L=
/NODUMP
In case of a verify error the contents of the flash memory is written to a file with
the extension .DMP. With /NODUMP you can suppress this feature.
/ERASEALL
Erase the whole flash device. If this option isn't set, only those blocks are erased
where new data should be written to.
/NOERASE
This option prevents the flash device from being erased.
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/CS0 /CS1 /CS2 /CS3
This options may be used to specify one or more chip select signals to the flash
memory. The used chip selects must be defined as output and inactive in the
initialization file. (See chapter 1.11 “Initialization file JTAuxxxx.INI”.)
Default:
/CS0
/NOCS
Use this option to switch off all chip select signals. This may be necessary if the
device's chip select is generated via a normal decoder instead of using the AMD
Alchemy Solutions Processors chip select unit.
/NOWRSETUP
By default write cycles to the Flash EPROM are realized with three steps: 1. set
address/data 2. write strobe active 3. write strobe inactive. In most cases it is
possible to set the write strobe coincident with setting of address and data by
specifying the option /NOWRSETUP. This increases the programming speed
by 50%.
Examples:
JTAuxxxx /P ROMDOS.ROM /L=20000 /TOP
This example programs up to 128 Kbytes of the file ROMDOS.ROM (with i.e. 512
Kbytes) to the top of the boot flash memory.
JTAuxxxx /P CE.ROM /32BIT /CS1
This example programs the file CE.ROM to the 32 Bit Flash-EPROM connected
to RCS1#.
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AMD Alchemy Solutions Processors
2.2.
Read a Flash Device to file
Usage:
JTAuxxxx /R filename [optionlist]
The contents of a flash device is read and written to a file.
The type of the flash device is normally detected by the software. When
autodetection fails you should use the /DEVICE= option together with /8BIT or
/16BIT or /32BIT to set the right flash device and configuration. The known
devices are shown in chapter 1.12 “Supported flash devices”. Use the option
/CFI if the flash is not in the list of know devices.
Options:
/DEVICE=devicename
See function /P (Chapter 2.1)
/CFI
See function /P (Chapter 2.1)
/8BIT /16BIT /32BIT
See function /P (Chapter 2.1)
/BYTE-MODE
See function /P (Chapter 2.1)
/NOMAN
See function /P (Chapter 2.1)
/DEVICE-BASE=hhhhhh2
See function /P (Chapter 2.1)
2
hhhhhh=number base is hex
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/OFFSET=hhhhhh
Reading of the flash memory starts at an offset of hhhhhh relative to the start
address of the flash device. If the offset is negative, the offset specifies a
address relative to the end of the flash device.
See also option /TOP.
Default:
/OFFSET=0
Abbreviation:
/O=
/TOP
If the option /TOP is used the option /OFFSET= specifies the address where
reading ends (plus one) instead of the starting address.
/LENGTH=hhhhhh
The number of read bytes may be limited to LENGTH. If no LENGTH is specified
the whole flash device is read (if no offset is specified).
/CS0 /CS1 /CS2 /CS3
See function /P (Chapter 2.1)
/NOWRSETUP
See function /P (Chapter 2.1)
Please note: In the function /R write cycles are needed to detect the type of the
flash memory.
Example:
JTAuxxxx /R BIOS.ABS /L=10000 /TOP
This example may be used to read the upper most 64 Kbyte of the flash memory
to the file BIOS.ABS.
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2.3.
Verify a Flash Device with file
Usage:
JTAuxxxx /V filename [optionlist]
The contents of a flash device is compared with the specified file. If there are
differences the memory is dumped to a file with the extension DMP.
The type of flash device is normally detected by the software. When autodetect
fails you should use the /DEVICE= option together with /8BIT or /16BIT or /32BIT
to set the right flash device and configuration. The known devices are shown in
chapter 1.12 “Supported flash devices”. Use the option /CFI if the flash is not in
the list of know devices.
Options:
/DEVICE=devicename
See function /P (Chapter 2.1)
/CFI
See function /P (Chapter 2.1)
/8BIT /16BIT /32BIT
See function /P (Chapter 2.1)
/BYTE-MODE
See function /P (Chapter 2.1)
/NOMAN
See function /P (Chapter 2.1)
/DEVICE-BASE=hhhhhh
See function /P (Chapter 2.1)
/OFFSET=hhhhhh
See function /P (Chapter 2.1)
/TOP
See function /P (Chapter 2.1)
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/FILE-OFFSET=hhhhhh
See function /P (Chapter 2.1)
/LENGTH=hhhhhh
See function /P (Chapter 2.1)
/NODUMP
See function /P (Chapter 2.1)
/CS0 /CS1 /CS2 /CS3
See function /P (Chapter 2.1)
/NOWRSETUP
See function /P (Chapter 2.1)
Please note: In the function /V write cycles are needed to detect the type of the
flash memory.
Example:
JTAuxxxx /V ROMDOS.ROM /L=20000 /TOP
This example may be used to verify the upper most 128 Kbytes of the flash
memory with the file ROMDOS.ROM (with i.e. 512 Kbytes).
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2.4.
Dump target memory
Usage:
JTAuxxxx /DUMP [optionlist]
A Hex-Dump of the target memory is printed on the screen, if not redirected to
file or device.
Options:
/8BIT /16BIT /32BIT
Default:
/32BIT
/OFFSET=hhhhhh
The memory dump starts at an offset of hhhhhh plus the device start address
(see option /DEVICE-BASE=).
Default:
/OFFSET=0
Abbreviation:
/O=
/DEVICE-BASE=hhhhhh3
The device start address is used as an additional offset. This gives the function
/DUMP the same behavior as function /P /V and /R.
Default:
/DEVICE-BASE=0
Abbreviation:
/DB=
/TOP
If the option /TOP is used the option /OFFSET= specifies the address where
the dump ends (plus one) instead of the starting address
/LENGTH=hhhhhh
Default:
/LENGTH=100
Abbreviation:
/L=
/CS0 /CS1 /CS2 /CS3
See function /P (Chapter 2.1)
Default:
/CS0
3
hhhhhh=number base is hex
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Example:
JTAuxxxx /DUMP
This example makes a memory dump of the first 256 bytes of the Boot-EPROM.
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2.5. Program a Serial Device (I²C/SPI/MicroWire)
Usage:
JTAuxxxx /PSER filename [/SERBIG] [optionlist]
The specified file is programmed to a serial device (i.e. EEPROM) connected to
pins of the CPU. Finally a complete verify is done. If the verify fails, the contents
of the serial device is written to a file with the extension DMP.
For an I²C device there are two different methods how to connect it to the CPU.
The first method uses two CPU pins, one pin for clock output (SERCLK) and one
pin for serial data input/output (SERDAT). The second method uses one pin for
clock output (SERCLK), one for serial data input (SERDATI) and one for serial
data output (SERDATO).
Connecting a SPI/MicroWire device needs four different CPU pins: SERCS is the
chip select output of the CPU, SERCLK is the clock output of the CPU,
SERDATO is the serial data output of the CPU and must be connected to the SI
input at the SPI/MicroWire device and SERDATI is the serial data input to the
CPU and must be connected to the SO output of the SPI/MicroWire device.
Options:
/SERBIG
Specify this option if there is a device which needs a three byte address instead
of a two byte address. For SPI devices this option is normally needed for devices
with more than or equal to 64 kBytes. For I²C devices this option is normally
needed for devices with more than 2 kByte.
This option must be the first option after the filename.
/SPI
Specify this option, if there is a SPI device connected instead of an I²C device.
/MWIRE
Specify this option, if there is a MicroWire device connected instead of an I²C
device.
Please Note: Actually only the M93C06 and the M93C46 and only in 16 Bit mode
are supported.
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/DEVICE-BASE=hhhhhh
This option specifies an I²C device starting address. The default values are
chosen to access a serial EEPROM. By changing the device starting address
different devices can be selected. As SPI/MicroWire devices are selected by the
chip select signal instead of an address, this option does not make sense for
SPI/MicroWire devices.
Default:
/DEVICE-BASE=5000
(if option /SERBIG omitted)
Default:
/DEVICE-BASE=500000
(if option /SERBIG specified)
Default:
/DEVICE-BASE=0
(for SPI/MicroWire devices)
/OFFSET=hhhhhh
The programming starts at an offset of hhhhhh relative to the start address of the
serial device.
Default:
/OFFSET=0
Abbreviation:
/O=
/FILE-OFFSET=hhhhhh
If FILE-OFFSET is specified, the first hhhhhh bytes of the file are skipped and
not programmed to target.
Default:
/FILE-OFFSET=0
Abbreviation:
/FO=
/LENGTH=hhhhhh
The number of programmed bytes may be limited to LENGTH. If no LENGTH is
specified the whole file is programmed.
Abbreviation:
/L=
/NODUMP
In case of a verify error the contents of the I²C-Device is written to a file with the
extension .DMP. With option /NODUMP you can suppress this feature.
/SERCS=pin_name (SPI/MicroWire mode only)
Specifies the CPU pin used to select the serial device.
In SPI mode SERCS is treated as low active.
In MicroWire mode SERCS is treated as high active.
/SERCLK=pin_name
Specifies the CPU pin used for serial clock output.
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/SERDAT=pin_name (I²C only)
Specifies the CPU pin used for serial data input and output for an I²C device.
Pin_name must specify a bidirectional pin otherwise an error message occurs.
Instead of one bidirectional pin one pin for serial data input and one for serial
data output may be used. See option /SERDATO= and /SERDATI= .
/SERDATO=pin_name
Specifies the CPU pin used for serial data output. Pin_name must specify a
output pin otherwise an error message occurs. This pin must be connected to the
serial data input of a SPI/MicroWire device.
/SERDATI=pin_name
Specifies the CPU pin used for serial data input. Pin_name must specify a input
pin otherwise an error message occurs. This pin must be connected to the serial
data output of a SPI/MicroWire device.
/SERBUFF= hhhhhh
For I²C and SPI devices the write page mode can be activated by specifying the
option /SERBUFF=. Using this feature increases the programming performance.
Please note: Some SPI devices do not support single byte write mode. For these
devices the option /SERBUFF= must be specified in the command line.
/LSB1ST
Some devices need the least significant data bit sent/received first (i.e. Altera
ECS1 configuration device for FPGAs). Addresses are still sent/received most
significant bit first. This option does not affect the behavior of accessing I²C
devices.
/SPIERA
Some SPI devices need to be erased before programming. Add option /SPIERA
to the command line to perform a chip erase procedure before programming.
Example:
JTAuxxxx /PSER EEPROM.CFG /SERCLK=GPIO0 /SERDAT=GPIO
This example loads the file EEPROM.CFG to a I²C EEPROM connected to the
pins GPIO0 and GPIO1 of the AMD Alchemy Solutions Processors
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2.6. Read a Serial Device to file (I²C/SPI/MicroWire)
Usage:
JTAuxxxx /RSER filename [/SERBIG] /L=hhhhhh [optionlist]
The contents of a serial device (i.e. EEPROM) is read and written to a file. The
option /LENGTH= must be specified.
Options:
/SERBIG
This option must be the first option after the filename.
See function /PSER (Chapter 2.5)
/SPI
Specify this option, if there is a SPI device connected instead of a I²C device.
/MWIRE
Specify this option, if there is a MicroWire device connected instead of an I²C
device.
/DEVICE-BASE=hhhhhh
See function /PSER (Chapter 2.5)
/OFFSET=hhhhhh
Reading of the serial device starts at an offset of hhhhhh relative to the start
address of the serial device.
Default:
/OFFSET=0
Abbreviation:
/O=
/LENGTH=hhhhhh
The number of read bytes must be specified otherwise an error message occurs.
Abbreviation:
/L=
/SERCS=pin_name
See function /PSER (Chapter 2.5)
/SERCLK=pin_name
See function /PSER (Chapter 2.5)
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/SERDAT=pin_name
See function /PSER (Chapter 2.5)
/SERDATO=pin_name
See function /PSER (Chapter 2.5)
/SERDATI=pin_name
See function /PSER (Chapter 2.5)
/LSB1ST
See function /PSER (Chapter 2.5)
Example:
JTAuxxxx /RSER EEPROM.CFG /SERCLK=GPIO0 /SERDAT=GPIO1 /L=100
This example reads 256 bytes from a I²C EEPROM to the file EEPROM.CFG.
The serial EEPROM is connected to the pins CPIO0 and GPIO1 of the AMD
Alchemy Solutions Processors.
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2.7. Verify a Serial Device with file (I²C/SPI/MicroWire)
Usage:
JTAuxxxx /VSER filename [/SERBIG] [optionlist]
The contents of a serial device (i.e. EEPROM) is compared with the specified
file. If there are differences the contents of the I²C -Device is written to a file with
the extension DMP.
Options:
/SERBIG
This option must be the first option after the filename.
See function /PSER (Chapter 2.5)
/SPI
Specify this option, if there is a SPI device connected instead of a I²C device.
/MWIRE
Specify this option, if there is a MicroWire device connected instead of an I²C
device.
/DEVICE-BASE=hhhhhh
See function /PSER (Chapter 2.5)
/OFFSET=hhhhhh
See function /PSER (Chapter 2.5)
/FILE-OFFSET=hhhhhh
See function /PSER (Chapter 2.5)
/LENGTH=hhhhhh
See function /PSER (Chapter 2.5)
/NODUMP
See function /PSER (Chapter 2.5)
/SERCS=pin_name
See function /PSER (Chapter 2.5)
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/SERCLK=pin_name
See function /PSER (Chapter 2.5)
/SERDAT=pin_name
See function /PSER (Chapter 2.5)
/SERDATO=pin_name
See function /PSER (Chapter 2.5)
/SERDATI=pin_name
See function /PSER (Chapter 2.5)
/LSB1ST
See function /PSER (Chapter 2.5)
Example:
JTAuxxxx /VSER EEPROM.CFG /SERCLK=GPIO0 /SERDAT=GPIO1
This example verifies 256 bytes from a serial EEPROM with the file
EEPROM.CFG. The serial EEPROM is connected to the pins GPIO0 and GPIO1
of the AMD Alchemy Solutions Processors.
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2.8. Dump a Serial Device (I²C/SPI/MicroWire)
Usage:
JTAuxxxx /DUMPSER [/SERBIG] [optionlist]
A Hex-Dump of serial device (i.e. EEPROM) is printed on the screen, if not
redirected to file or device.
Options:
/SERBIG
This option must be the first option.
See function /PSER (Chapter 2.5)
/SPI
Specify this option, if there is a SPI device connected instead of a I²C device.
/MWIRE
Specify this option, if there is a MicroWire device connected instead of an I²C
device.
/DEVICE-BASE=hhhhhh
See function /PSER (Chapter 2.5)
/OFFSET=hhhhhh4
The memory dump starts at an offset of hhhhhh.
Default:
/OFFSET=0
Abbreviation:
/O=
/LENGTH=hhhhhh
Default:
/LENGTH=100
Abbreviation:
/L=
/SERCS=pin_name
See function /PSER (Chapter 2.5)
/SERCLK=pin_name
See function /PSER (Chapter 2.5)
4
hhhhhh=number base is hex
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/SERDAT=pin_name
See function /PSER (Chapter 2.5)
/SERDATO=pin_name
See function /PSER (Chapter 2.5)
/SERDATI=pin_name
See function /PSER (Chapter 2.5)
/LSB1ST
See function /PSER (Chapter 2.5)
Example:
JTAuxxxx /DUMPSER /SERCLK=GPIO0 /SERDAT=GPIO1
This example makes a memory dump of the first 100h bytes of a I²C EEPROM
connected to the CPU.
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2.9.
Toggle CPU pins
Usage:
JTAuxxxx /BLINK /PIN=pinname [optionlist]
This command allows to test the hardware by blinking with LEDs or toggling CPU
signals. Faster signals can be generated by setting the delay option to zero. This
can be a very helpful feature to watch signals on an oscilloscope.
The signal on the defined pin has an duty cycle of 1/2: The level is 67% high and
33% low.
Please Note: Not every pin of the AMD Alchemy Solutions Processors may be
specified as an output pin.
Options:
/PIN=pin_name
CPU pin to toggle. If the option /PIN= is not specified an error message occurs.
Most pins of the list in chapter 1.11 “Initialization file JTAuxxxx.INI” can be used.
If you type /PIN= without any pin declaration a list of the CPU pins is displayed.
/DELAY=dddddd5
Time to wait to next change of signal. This option can be adjusted to get
optimum signals for measures with the oscilloscope.
Default:
/DELAY=10000
Example:
JTAuxxxx /BLINK /PIN=FLAG3 /DELAY=0
This example toggles the FLAG3 pin very fast which can be followed by the use
of an oscilloscope.
5
dddddd=number base is decimal
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2.10.
Polling CPU pins
Usage:
JTAuxxxx /PIN? /PIN=pinname [optionlist]
This command allows to test the hardware by polling CPU signals.
Please Note: Not every pin of the AMD Alchemy Solutions Processors may be
specified as an input pin.
Options:
/PIN=pin_name
CPU pin to poll. If the option /PIN= is not specified an error message occurs.
Most pins of the list in chapter 1.11 “Initialization file JTAuxxxx.INI” can be used.
If you type /PIN= without any pin declaration a list of the CPU pins is displayed.
Example:
JTAuxxxx /PIN? /PIN=RESET#
This example samples the reset pin of the AMD Alchemy Solutions Processors.
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2.11.
Polling CPU pins while the CPU is running
Usage:
JTAuxxxx /SAMPLE /PIN=pinname [optionlist]
This command is similar to the function /PIN?. But with this function any pin can
be observed, independent of the pin direction. Furthermore the CPU remains in
normal operation.
Options:
/PIN=pin_name
CPU pin to poll. If the option /PIN= is not specified an error message occurs. All
pins of the list in chapter 1.11 “Initialization file JTAuxxxx.INI” can be used. If you
type /PIN= without any pin declaration a list of the CPU pins is displayed.
Example:
JTAuxxxx /SAMPLE /PIN=FLAG3
This example samples the state of the port pin FLAG3 while the AMD Alchemy
Solutions Processors is running.
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2.12. Show status of all CPU pins while the CPU is running
Usage:
JTAuxxxx /SNAP [optionlist]
This function is similar to the function /SAMPLE, but displays the status of all
CPU pins on the screen. The CPU remains in normal operation.
The behavior of the function /SNAP depends on the option /REP: With this option
specified, the JTAG-Booster samples and displays the state of the CPU pins
repetitive. Without this option the status of the pins is displayed only once.
Options:
/PAUSE
Use this option to stop the output after each displayed screen. Don't use this
option together with the option /REP or if the output is redirected to a file.
Abbreviation
/P
/REP
If this option is specified the status of the pins is sampled and displayed
repetitive. In case of many signals the display is separated into several screens.
Therefor we recommend to use a video mode with 43 or 50 lines. Use the '+' and
the '-' key to switch between different screens. Any other key terminates the
program.
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Sample output:
This is a sample output for a AMD Alchemy Solutions Au1100 Processor
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0 GPIO10
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0 S0DIN
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0 GPIO12
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0 U1RXD
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0 U3RXD
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0 ACBCLK
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0 N0CRS
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0 U3TXD
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0 GPIO14
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0 N0TXEN
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0 N0TXD1
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0 N0MDIO
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0 GPIO16
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0 RESVD_2
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0 GPIO23
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0 RESVD_5
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0 SDMS0_CMD |
0 SDMS0_DAT3 |
0 SDMS1_DAT1 |
0 SDD1
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1 SDD5
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0 SDD9
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0 SDD13
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0 SDD17
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1 SDD21
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1 SDD25
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1 SDD29
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1 SDCLK1
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1 SDWE#
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1 SDCAS#
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1 SDQM3#
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1 SDA1
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1 SDA5
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1 SDA9
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1 RESETOUT# |
1 ROMSIZE
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0 GPIO1
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0 GPIO3
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0 TC3
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0 USBH1P
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0 USBDP
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0 S0DOUT
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0 IRDARX
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0 ACDI
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0 ACDO
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0 N0RXD0
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0 GPIO13
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0 GPIO15
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0 N0TXD0
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0 N0TXD2
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0 N0TXCLK
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0 GPIO17
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0 GPIO20
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0 RESVD_3
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0 LCD_PWM1 |
0 SDMS0_DAT0 |
0 SDMS1_CMD |
0 SDMS1_DAT2 |
0 SDD2
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1 SDD6
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1 SDD10
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1 SDD14
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1 SDD18
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1 SDD22
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1 SDD26
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1 SDCLK0
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1 SDCS0#
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1 SDCLK2
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1 SDQM0#
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1 SDBA0
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1 SDA2
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1 SDA6
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1 SDA10
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1 VSEL
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0 RESETIN#
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0 TC0
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0 GPIO4
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0 PIOW#
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JTAG_alchemyb.doc
0 USBH1M
0 USBDM
0 S0CLK
0 IRDATX
0 ACRST#
0 I2SCLK
0 U0TXD
0 N0RXD1
0 N0RXD3
0 N0RXDV
0 N0TXD3
0 RESVD_0
0 GPIO18
0 GPIO21
0 LCD_PWM0
0 SDMS_MS_EN
0 SDMS0_DAT1
0 SDMS1_CLK
0 SDMS1_DAT3
1 SDD3
1 SDD7
0 SDD11
0 SDD15
1 SDD19
1 SDD23
1 SDD27
1 SDD30
1 SDCS1#
1 SDRAS#
1 SDQM1#
1 SDBA1
1 SDA3
1 SDA7
1 SDA11
1 TESTEN
0 VDDXOK
0 TC1
0 GPIO5
0 GPIO6
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0 U0RXD
0 GPIO11
0 S0DEN
0 I2SDIO
0 ACSYNC
0 I2SWORD
0 U1TXD
0 N0RXD2
0 N0RXCLK
0 N0COL
0 N0MDC
0 RESVD_1
0 GPIO19
0 GPIO22
0 RESVD_4
0 SDMS0_CLK
0 SDMS0_DAT2
0 SDMS1_DAT0
0 SDD0
1 SDD4
1 SDD8
1 SDD12
1 SDD16
1 SDD20
1 SDD24
1 SDD28
1 SDD31
1 SDCS2#
1 SDCKE
1 SDQM2#
1 SDA0
1 SDA4
1 SDA8
1 SDA12
1 ROMSEL
0 GPIO0
0 GPIO2
0 TC2
0 GPIO7
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1 PIOR#
0 PREG#
0 LRD0#
0 EWAIT#
1 RD1
1 RD5
1 RD9
1 RD13
1 RD17
0 RD21
0 RD25
0 RD29
1 RAD1
1 RAD5
1 RAD9
1 RAD13
1 RAD17
1 RAD21
1 RAD25
1 RAD29
0 RBEN1#
1 ROE#
1 RCS3#
1 LCD_D2
1 LCD_D5
0 LCD_D8
0 LCD_D12
1 LCD_BIAS
88
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0 PIOS16#
0 PWAIT#
0 LRD1#
1 LCLK
0 RD2
1 RD6
1 RD10
1 RD14
0 RD18
0 RD22
0 RD26
1 RD30
1 RAD2
1 RAD6
1 RAD10
1 RAD14
1 RAD18
1 RAD22
1 RAD26
1 RAD30
0 RBEN2#
1 RCS0#
1 LCD_PCK
1 LCD_LCK
1 LCD_D6
1 LCD_D9
0 LCD_D13
1 LCD_LEND
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0 PWE#
0 PCE1#
1 LWR0#
0 LWR1#
1 RD3
1 RD7
1 RD11
1 RD15
0 RD19
0 RD23
0 RD27
1 RD31
1 RAD3
1 RAD7
1 RAD11
1 RAD15
1 RAD19
1 RAD23
1 RAD27
1 RAD31
0 RBEN3#
1 RCS1#
1 LCD_D0
1 LCD_D3
1 LCD_FCK
0 LCD_D10
1 LCD_D14
1 GPIO8
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1 POE#
0 PCE2#
0 LWAIT#
1 RD0
1 RD4
1 RD8
1 RD12
1 RD16
0 RD20
1 RD24
0 RD28
1 RAD0
1 RAD4
1 RAD8
1 RAD12
1 RAD16
1 RAD20
1 RAD24
1 RAD28
0 RBEN0#
1 RWE#
1 RCS2#
1 LCD_D1
1 LCD_D4
1 LCD_D7
1 LCD_D11
0 LCD_D15
1 GPIO9
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3. Implementation Information
This chapter summarizes some information about the implementation of the
JTAG-Booster and describes some restrictions.
•
The JTAG-Booster currently uses Boundary Scan to perform Flash
programming. EJTAG is not used.
•
The software assumes the following scheme for connecting the FlashEPROM to the AMD Alchemy Solutions Processors. Please contact us, if you
need support for a different method.
AMD Au1x00 signal
RCS0# RCS1#
RCS2# RCS3#
ROE#
RWE#
RAD0
RAD1
RAD2..28
RD0..7
RD0..15
RD0..31
8 Bit Flash
CS#
16 Bit Flash
CS#
32 Bit Flash
CS#
OE#
WE#
A0
A1
A2..28
D0..7
-
OE#
WE#
A1
A2..28
D0..15
-
OE#
WE#
A2..28
D0..31
1.) All other signals are hold static during flash programming. The state of
these signals is defined in the Initialization file.
•
Default endianess is "Little Endian". Use the option /BIG for big endian
support.
•
Physical address range for static memory and peripherals is limited to
512MByte (MIPS32 specific). For memory accesses with boundary scan, the
address lines RAD29, RAD30 and RAD31 are not modified.
•
Support for NAND flashes is not included as standard functionality, but can
be provided on customers request (AMD Alchemy Solutions Au1550
Processor only).
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4. Converter Program HEX2BIN.EXE
Since the JTAG-Booster software is not able to handle Intel-HEX or Motorola SRecord files, an separate converter tool is delivered with this product package.
Five types of HEX formats can be converted to BIN file:
•
I
•
D : Digital Research
•
M : MOTOROLA S HEX format (BYTE oriented)
•
T : TEKTRONICS HEX format (BYTE oriented)
•
H : Intel HEX-32
: INTEL HEX format (BYTE oriented)
Maximum conversion size is 256 kBytes. A 4th parameter for starting address can
be specified to skip out the leading garbage and you will maintain a small size of
output binary file.
If you start the HEX2BIN without any additional parameter all necessary
parameters will be asked for in a prompt mode:
HEX2BIN
Input HEX file name: MYAPP.H86
Output BIN file name[MYAPP.BIN]:
HEX file format
ntel /otorola /igital Research /ektronics /[H] Intel HEX-32[I] : H
Input CODE segment start address[0000000]: 10000
Input CODE segment end address[FFFFFFF]:
Unused bytes will be 00 FF [1] : 2
Instead of using the prompt mode, you can directly specify all necessary
parameters in the command line. This is essential for making batch files:
HEX2BIN MYAPP.H86 MYAPP.BIN H 0010000 FFFFFFF 2
It is very important to fill unused bytes with 0xFF, because this are simply
skipped by the JTAG-Boosters software and so it speeds up the programming
performance.
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Please Note: "CODE segment start address" is interpreted as a Intel x86
architecture segment address: You have to specify a start address of 10000 to
start the conversion at 1 MByte.
This converter is a relatively old DOS tool and therefor it has problems with non
DOS compliant file and directory names. Avoid names with spaces, limit names
to eight characters. Otherwise the converter does not convert the input file,
without any error message!!
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5. Support for Windows NT, Windows 2000 and Windows XP
A configured run time version of the "Kithara DOS Enabler, Version 6.x" is used
to give support for some of our DOS based tools (like the JTAG-Booster) for
Windows NT, Windows 2000 and Windows XP. After installation of the "DOS
Enabler" the accesses to the LPT ports are allowed for the all programs listed in
file Readme_WinNT.txt
Note: Accesses to the ports are only allowed for the programs listed in file
Readme_WinNT.txt. If you rename one of our tools, the DOS Enabler does not
work.
Important: You need administrator rights to install or de-install this program.
5.1.
Installation on a clean system
If you have a clean system without having installed a previous version of the
"Kithara Tool Center", this tool is really simple to install. Extract the ZIP file to a
new folder and start KSETUP.EXE. Everything is done within a few seconds. No
additional input is needed. Now reboot your PC.
5.2.
Installation with already installed version 5.x/6.x of Kithara
If you have already installed an older WinNT support (Kithara Version 5.x or 6.x),
you have to de-install it 1st as described in chapter 5.4.
After rebooting your PC you can install the Kithara 6.x as described above.
5.3.
Installation with already installed version 4.x of Kithara
Important!! If you have already installed an older WinNT support, you have to
deinstall it completely!!!
•
Start kcenter
•
Select Register "Einstellungen" (=Settings)
and deactivate "VDD benutzen"
and "speziellen seriellen Treiber benutzen".
•
Stop Kernel
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•
exit the kcenter program
•
Now you can deinstall the Kithara Package with:
Settings - Control Panel.
All unused parts must be removed.
•
Reboot your PC
•
Now you can install the Kithara 6.x as described above.
5.4.
De-Installation version 5.x/6.x:
For deinstallation of the runtime version of the "Kithara DOS-Enabler Version
5.x/6.x":
•
use: Settings - Control-Panel - Add/Remove Programs
and remove the
“FS FORTH-SYSTEME WinNT Support”
and/or
“WinNT Support for JTAG-Booster and FLASH166”
•
Reboot your PC
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