ISD-DMK_3800

ISD3800 ISD ChipCorder® ISD3800 Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of Audio Product Line based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com Jun 15, 2021 Page 1 of 25 Rev 1.5 ISD3800 TABLE OF CONTENTS 1 GENERAL DESCRIPTION .............................................................................................................. 3 2 FEATURES ...................................................................................................................................... 3 3 BLOCK DIAGRAM ........................................................................................................................... 5 4 PINOUT CONFIGURATION ............................................................................................................ 6 4.1 4.2 48L-LQFP ................................................................................................................................................ 6 32L-QFN.................................................................................................................................................. 7 5 PIN DESCRIPTION .......................................................................................................................... 8 6 ELECTRICAL CHARACTERISTICS .............................................................................................. 11 6.1 ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 11 6.2 OPERATING CONDITIONS ........................................................................................................................ 11 6.3 DC PARAMETERS ................................................................................................................................... 13 6.4 AC PARAMETER ..................................................................................................................................... 14 6.4.1 Internal Oscillator ......................................................................................................................... 14 6.4.2 Input ............................................................................................................................................... 14 6.4.3 Output ............................................................................................................................................ 15 6.4.4 SPI Timing ..................................................................................................................................... 17 6.4.5 I2S Timing ...................................................................................................................................... 18 7 APPLICATION DIAGRAM .............................................................................................................. 19 8 SPACKAGE SPECIFICATION ....................................................................................................... 21 8.1 8.2 9 10 48 LEAD LQFP(7X7X1.4MM FOOTPRINT 2.0MM).................................................................................... 21 32 LEAD QFN (5X5 MM^2, THICKNESS 0.8MM ,PITCH 0.5 MM) ......................................................... 22 ORDERING INFORMATION .......................................................................................................... 23 REVISION HISTORY.................................................................................................................. 24 IMPORTANT NOTICE........................................................................................................................... 25 Jun 15, 2021 Page 2 of 25 Rev 1.5 ISD3800 1 GENERAL DESCRIPTION The ISD3800 is a digital ChipCorder® featuring digital compression, comprehensive memory management, and integrated analog/digital audio signal paths. The ISD3800 utilizes serial flash memory to provide non-volatile audio playback for a two-chip solution. The ISD3800 provides an I2S digital audio interface, faster digital programming, higher sampling frequency, and a signal path with SNR 80dB. The ISD3800 can take digital audio data via I2S or SPI interface. When I2S input is selected, it will replace the analog audio inputs and will support sample rates of 32, 44.1 or 48 kHz depending upon clock configuration. When SPI interface is chosen, the sample rate of the audio data sent must be one of the ISD3800 supported sample rates. The ISD3800 has inbuilt analog audio inputs, analog audio line driver, and speaker driver output. The analog audio input, Aux-in, has a fixed gain configured by SPI command. Aux-in can directly feedthrough to the analog outputs; it can also mix with the DAC output and then feed-through to the analog outputs. The ISD3800 can deliver three kinds output: 1) Aux-out, an analog single-ended voltage output; 2) Class-AB BTL (bridge-tied-load) analog differential voltage output; 3) Class-D PWM. Both Class-AB BTL and Class-D PWM output can directly drive a speaker. 2 FEATURES • External Memory: o The ISD3800 supports the following flash: Manufacturer Family JEDEC ID Winbond 25X 25Q EF 30 1X EF 40 1X 25P 20 20 1X Numonyx 25PX 20 71 1X 25PE 20 80 1X MXIC 25L / 25V C2 20 1X The addressing ability of ISD3800 is up to 128Mbit, which is 64-minute playback time based on 8kHz/4bit ADPCM. o Inbuilt 3V voltage regulator to provide power source to the external flash memory Fast Digital Programming o Programming rate can go up to 1Mbits/second mainly limited by the flash memory write rate. Memory Management o Store pre-recorded audio (Voice Prompts) using high quality digital compression o Use a simple index-based command for playback o Execute pre-programmed macro scripts (Voice Macros) designed to control the configuration of the device and play back Voice Prompts sequences. Sample Rate o Seven sampling frequencies are available for a given master sample rate. For example, the sampling frequencies of 4, 5.3, 6.4, 8, 12.8, 16 and 32kHz are available when the device is clocked at a 32kHz master sample rate. o For I2S operation, 32, 44.1 and 48kHz master sample rates are available with playback sampling frequencies scaling accordingly. Compression Algorithm o For Pre-Recorded Voice Prompt  µ-Law: 6, 7 or 8 bits per sample  Differential µ-Law: 6, 7 or 8 bits per sample  PCM: 8, 10 or 12 bits per sample  Enhanced ADPCM: 2, 3, 4 or 5 bits per sample  Variable-bit-rate optimized compression. This allows best possible compression given a metric of SNR and background noise levels. o • • • • Jun 15, 2021 Page 3 of 25 Rev 1.5 ISD3800 • • • • • • • • • • 1 Oscillator o Internal oscillator with internal reference: 2.048 MHz with ±1% deviation o Internal oscillator with external resistor: 2.048 MHz with ±2% deviation 1 o External crystal or clock input  Crystals support standard audio sampling rates of 2.048, 4.096, 8.192, 12.288 and 11.2896MHz o I2S bit clock input Input o Aux-in: Analog input with 2-bit gain control configured by SPI command Output o Aux-out: an analog single-ended voltage output o Class-D PWM speaker driver, capable of delivering typical power:  4Ω load: 1W @5.5V; 335mW @3.3V.  8Ω load: 930mW @5.5V; 320mW @ 3.3V. o Class-AB BTL analog differential output, capable of delivering typical power:  4Ω load: 950mW @5.5V; 330mW @3.3V.  8Ω load: 930mW @5.5V; 320mW @ 3.3V. I/O o SPI interface: MISO, MOSI, SCLK, SSB for commands and digital audio data o I2S interface: I2S_CLK, I2S_WS, I2S_SDI, I2S_SDO for digital audio data o 8 GPIO pins:  4 GPIO pins share with I2S  4 GPIO pins share with SPI Interface  GPIO pins can trigger Voice Macro for a pushbutton application 8-bit Volume Control set by SPI command for flexible mixing Talarm temperature threshold: 125°C typical Operating Voltage: 2.7 ~ 5.5V Standby Current: 1uA typical Package: o Green 48L-LQFP o Green 32L-QFN Temperature Options: o Industrial: -40°C to 85°C With ±1% precision 80kohm external resistor. Jun 15, 2021 Page 4 of 25 Rev 1.5 ISD3800 3 BLOCK DIAGRAM Figure 3-1 ISD3800 Block Diagram Jun 15, 2021 Page 5 of 25 Rev 1.5 ISD3800 NC NC NC NC NC AUXOUT VCCA VSSA VMID NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 2 3 34 33 4 1 XTALIN XTALOUT VCCFS VCCF 32 VCCF 31 FCSB 30 FDI 8 29 FCLK 9 28 FDO 10 27 26 RESET 5 6 ISD3800 7 11 GPIO2 / RDY/BSYB GPIO3 / INTB NC NC NC VCCSPK SPK- VSSSPK SPK+ VCCSPK MOSI / GPIO0 SSB 12 25 13 14 15 16 17 18 19 20 21 22 23 24 MISO / GPIO1 NC NC NC I2S_SDI / GPIO7 I2S_SCK / GPIO6 I2S_WS / GPIO5 2 I S_SDO / GPIO4 NC NC VSSD VCCD VREG AUXIN 48L-LQFP NC 4.1 PINOUT CONFIGURATION SCLK 4 Figure 4-1 ISD3800 48-Lead LQFP Pin Configuration Jun 15, 2021 Page 6 of 25 Rev 1.5 ISD3800 4.2 32L-QFN Figure 4-2 ISD3800 32-Lead QFN Pin Configuration Jun 15, 2021 Page 7 of 25 Rev 1.5 ISD3800 5 PIN DESCRIPTION Pin # LQF P-48 QFN -32 Pin Name I/O Function 1 NC This pin should be left unconnected. 2 NC This pin should be left unconnected. 3 NC This pin should be left unconnected. 4 32 GPIO7 / I2S_SDI I/O A GPIO pin. By default this pin is a pull-high input. Can be configured as Serial Data Input of the I2S interface. 5 1 GPIO6 / I2S_SCK I/O A GPIO pin. By default this pin is a pull-high input. Can be configured as Clock input in slave mode or clock output in master mode. This pin can be configured as an external clock buffer if I2S is not used. 6 2 GPIO5 / I2S_WS I/O A GPIO pin. By default this pin is a pull-high input. Can be configured as Word Select (WS) input in slave mode or WS output in master mode. 7 3 GPIO4 / I2S_SDO I/O A GPIO pin. By default this pin is a pull-high input. Can be configured as Serial Data Output of the I2S Interface. 8 NC This pin should be left unconnected. 9 NC This pin should be left unconnected. 10 4 VSSD I Digital Ground. 11 5 VCCD I Digital power supply. 12 6 VREG O A 1.8V regulator to supply the internal logic. A minimum 1uF capacitor with low ESR