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A000069

A000069

  • 厂商:

    ARDUINO

  • 封装:

    -

  • 描述:

    ATmega2560 Arduino ADK AVR® ATmega MCU 8-Bit AVR Embedded Evaluation Board

  • 数据手册
  • 价格&库存
A000069 数据手册
ATmega640/V-1280/V-1281/V-2560/V-2561/V 8-bit Microcontroller with 16/32/64KB In-System Programmable Flash DATASHEET Features • • • High Performance, Low Power AVR® 8-Bit Microcontroller Advanced RISC Architecture – 135 Powerful Instructions – Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16MHz – On-Chip 2-cycle Multiplier High Endurance Non-volatile Memory Segments – 64K/128K/256KBytes of In-System Self-Programmable Flash – 4Kbytes EEPROM – 8Kbytes Internal SRAM – Write/Erase Cycles:10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85C/ 100 years at 25C – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – Programming Lock for Software Security • • • • Endurance: Up to 64Kbytes Optional External Memory Space QTouch® library support – Capacitive touch buttons, sliders and wheels – QTouch and QMatrix acquisition – Up to 64 sense channels JTAG (IEEE® std. 1149.1 compliant) Interface – Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface Peripheral Features – – – – – • – – – – – – – – Special Microcontroller Features – – – – • Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode Real Time Counter with Separate Oscillator Four 8-bit PWM Channels Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits (ATmega1281/2561, ATmega640/1280/2560) Output Compare Modulator 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560) Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560) Master/Slave SPI Serial Interface Byte Oriented 2-wire Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change Power-on Reset and Programmable Brown-out Detection Internal Calibrated Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby I/O and Packages – – – – 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560) 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561) 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560) RoHS/Fully Green • Temperature Range: • Ultra-Low Power Consumption • – -40C to 85C Industrial – Active Mode: 1MHz, 1.8V: 500µA – Power-down Mode: 0.1µA at 1.8V Speed Grade: – ATmega640V/ATmega1280V/ATmega1281V: • 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega2560V/ATmega2561V: • 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V – ATmega640/ATmega1280/ATmega1281: • 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V – ATmega2560/ATmega2561: • 0 - 16MHz @ 4.5V - 5.5V 2549Q–AVR–02/2014 1. Pin Configurations 81 80 PA1 (AD1) 82 PA2 (AD2) 83 PJ7 84 PA0 (AD0) 85 GND 86 VCC 87 PK7 (ADC15/PCINT23) 88 PK5 (ADC13/PCINT21) 89 PK6 (ADC14/PCINT22) 90 PK3 (ADC11/PCINT19) 91 PK4 (ADC12/PCINT20) 92 PK1 (ADC9/PCINT17) 93 PK2 (ADC10/PCINT18) PK0 (ADC8/PCINT16) 94 PF7 (ADC7/TDI) 95 PF6 (ADC6/TDO) 96 PF4 (ADC4/TCK) 97 PF5 (ADC5/TMS) PF1 (ADC1) 98 PF2 (ADC2) PF0 (ADC0) 100 99 PF3 (ADC3) GND AREF TQFP-pinout ATmega640/1280/2560 AVCC Figure 1-1. 79 78 77 76 (OC0B) PG5 1 75 PA3 (AD3) (RXD0/PCINT8) PE0 2 74 PA4 (AD4) INDEX CORNER (TXD0) PE1 3 73 PA5 (AD5) (XCK0/AIN0) PE2 4 72 PA6 (AD6) (OC3A/AIN1) PE3 5 71 PA7 (AD7) (OC3B/INT4) PE4 6 70 PG2 (ALE) (OC3C/INT5) PE5 7 69 PJ6 (PCINT15) (T3/INT6) PE6 8 68 PJ5 (PCINT14) (CLKO/ICP3/INT7) PE7 9 67 PJ4 (PCINT13) VCC 10 66 PJ3 (PCINT12) GND 11 65 PJ2 (XCK3/PCINT11) (RXD2) PH0 12 64 PJ1 (TXD3/PCINT10) (TXD2) PH1 13 63 PJ0 (RXD3/PCINT9) (XCK2) PH2 14 62 GND (OC4A) PH3 15 61 VCC (OC4B) PH4 16 60 PC7 (A15) (OC4C) PH5 17 59 PC6 (A14) (OC2B) PH6 18 58 PC5 (A13) 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 (T1) PD6 31 (T0) PD7 30 (ICP1) PD4 29 (XCK1) PD5 28 (TXD1/INT3) PD3 27 (RXD1/INT2) PD2 26 (SDA/INT1) PD1 PG0 (WR) PL7 51 (SCL/INT0) PD0 25 PL6 (OC1B/PCINT6) PB6 (OC5C) PL5 PG1 (RD) (OC5A) PL3 PC0 (A8) 52 (OC5B) PL4 53 24 (T5) PL2 23 (OC1A/PCINT5) PB5 (ICP5) PL1 (OC2A/PCINT4) PB4 (ICP4) PL0 PC1 (A9) XTAL2 PC2 (A10) 54 XTAL1 55 22 VCC 21 (MISO/PCINT3) PB3 GND (MOSI/PCINT2) PB2 RESET PC3 (A11) (TOSC1) PG4 PC4 (A12) 56 (T4) PH7 57 20 (TOSC2) PG3 19 (OC0A/OC1C/PCINT7) PB7 (SS/PCINT0) PB0 (SCK/PCINT1) PB1 ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 2 Figure 1-2. CBGA-pinout ATmega640/1280/2560 Top view 1 2 3 4 5 6 7 Bottom view 8 9 10 10 9 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K Table 1-1. CBGA-pinout ATmega640/1280/2560 1 2 3 4 5 6 7 8 9 10 A GND AREF PF0 PF2 PF5 PK0 PK3 PK6 GND VCC B AVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2 C PE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3 D PE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2 E PE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2 F VCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND G GND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC H PB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2 J PH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1 K PB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG0 Note: The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 3 (OC0B) PG5 1 (RXD0/PCINT8/PDI) PE0 2 AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2) 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 Pinout ATmega1281/2561 64 Figure 1-3. INDEX CORNER 48 PA3 (AD3) 47 PA4 (AD4) 46 PA5 (AD5) 38 PC3 (A11) (MOSI/ PCINT2) PB2 12 37 PC2 (A10) (MISO/ PCINT3) PB3 13 36 PC1 (A9) (OC2A/ PCINT4) PB4 14 35 PC0 (A8) (OC1A/PCINT5) PB5 15 34 PG1 (RD) (OC1B/PCINT6) PB6 16 33 PG0 (WR) Note: 32 11 (T0) PD7 (SCK/ PCINT1) PB1 31 PC4 (A12) (T1) PD6 39 30 10 (XCK1) PD5 (SS/PCINT0) PB0 29 PC5 (A13) (ICP1) PD4 40 28 9 (TXD1/INT3) PD3 (ICP3/CLKO/INT7) PE7 27 PC6 (A14) (RXD1/INT2) PD2 41 26 8 (SDA/INT1) PD1 (T3/INT6) PE6 25 PC7 (A15) (SCL/INT0) PD0 42 24 7 XTAL1 (OC3C/INT5) PE5 23 PG2 (ALE) XTAL2 43 22 6 GND (OC3B/INT4) PE4 21 PA7 (AD7) VCC 44 20 5 RESET (OC3A/AIN1) PE3 19 PA6 (AD6) (TOSC1) PG4 45 18 4 (TOSC2) PG3 (XCK0/AIN0) PE2 17 3 (OC0A/OC1C/PCINT7) PB7 (TXD0/PDO) PE1 The large center pad underneath the QFN/MLF package is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 4 2. Overview The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. Block Diagram PF7..0 PK7..0 PORT F (8) PORT K (8) PJ7..0 PE7..0 VCC Power Supervision POR/ BOD & RESET RESET PORT J (8) PORT E (8) Watchdog Timer GND Watchdog Oscillator Analog Comparator JTAG A/D Converter EEPROM Internal Bandgap reference USART 0 XTAL1 Oscillator Circuits / Clock Generation 16 bit T/C 3 USART 3 16 bit T/C 5 XTAL2 CPU PORT A (8) PA7..0 16 bit T/C 4 USART 1 PG5..0 PORT G (6) XRAM PC7..0 PORT C (8) TWI FLASH SPI SRAM 16 bit T/C 1 8 bit T/C 0 USART 2 8 bit T/C 2 NOTE: Shaded parts only available in the 100-pin version. Complete functionality for the ADC, T/C4, and T/C5 only available in the 100-pin version. PORT D (8) PORT B (8) PORT H (8) PORT L (8) PD7..0 PB7..0 PH7..0 PL7..0 ® The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 5 The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, four USARTs, a byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE® std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. Microchip offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your own touch applications. The device is manufactured using the Microchip high-density nonvolatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true ReadWhile-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 6 2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560 Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and number of pins. Table 2-1 summarizes the different configurations for the six devices. Table 2-1. 2.3 2.3.1 Configuration Summary Device Flash EEPROM RAM General Purpose I/O pins 16 bits resolution PWM channels Serial USARTs ADC Channels ATmega640 64KB 4KB 8KB 86 12 4 16 ATmega1280 128KB 4KB 8KB 86 12 4 16 ATmega1281 128KB 4KB 8KB 54 6 2 8 ATmega2560 256KB 4KB 8KB 86 12 4 16 ATmega2561 256KB 4KB 8KB 54 6 2 8 Pin Descriptions VCC Digital supply voltage. 2.3.2 GND Ground. 2.3.3 Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 75. 2.3.4 Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 76. 2.3.5 Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as listed on page 79. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 7 2.3.6 Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 80. 2.3.7 Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 82. 2.3.8 Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. 2.3.9 Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features of the ATmega640/1280/1281/2560/2561 as listed on page 86. 2.3.10 Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port H also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 88. 2.3.11 Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port J also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 90. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 8 2.3.12 Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port K output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up resistors are activated. The Port K pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port K also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 92. 2.3.13 Port L (PL7..PL0) Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port L output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up resistors are activated. The Port L pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port L also serves the functions of various special features of the ATmega640/1280/2560 as listed on page 94. 2.3.14 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in “System and Reset Characteristics” on page 360. Shorter pulses are not guaranteed to generate a reset. 2.3.15 XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit. 2.3.16 XTAL2 Output from the inverting Oscillator amplifier. 2.3.17 AVCC AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. 2.3.18 AREF This is the analog reference pin for the A/D Converter. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 9 3. Resources A comprehensive set of development tools and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Confirm with the C compiler documentation for more details. These code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 5. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 ppm over 20 years at 85°C or 100 years at 25°C. 6. Capacitive touch sensing The QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on most AVR® microcontrollers. The QTouch Library includes support for the QTouch and QMatrix acquisition methods. Touch sensing can be added to any application by linking the appropriate QTouch Library for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the touch sensing API’s to retrieve the channel information and determine the touch sensor states. The QTouch Library is FREE and downloadable from the Microchip website at the following location: www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch Library User Guide - also available for download from the Microchip website. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 10 7. AVR CPU Core 7.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Architectural Overview Figure 7-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control 32 x 8 General Purpose Registers Instruction Register Control Lines Indirect Addressing Instruction Decoder Direct Addressing 7.2 Interrupt Unit SPI Unit Watchdog Timer ALU Analog Comparator I/O Module1 Data SRAM I/O Module 2 I/O Module n EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two oper- ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 11 ands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16-bit or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega640/1280/1281/2560/2561 has Extended I/O space from 0x60 0x1FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 7.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bitfunctions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set Summary” on page 404 for a detailed description. 7.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the “Instruction Set Summary” on page 404. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 12 7.4.1 SREG – AVR Status Register The AVR Status Register – SREG – is defined as: Bit 7 6 5 4 3 2 1 0 0x3F (0x5F) I T H S V N Z C Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the “Instruction Set Summary” on page 404. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Summary” on page 404 for detailed information. • Bit 4 – S: Sign Bit, S = N V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Summary” on page 404 for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Summary” on page 404 for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 404 for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Summary” on page 404 for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Summary” on page 404 for detailed information. 7.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 13 • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-2 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr. R0 0x00 R1 0x01 R2 0x02 … R13 0x0D General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11 … R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 7.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3. The X-, Y-, and Z-registers 15 X-register XH 7 XL 0 R27 (0x1B) 15 Y-register YH 7 YL 0 0 7 0 R28 (0x1C) 15 ZH 7 0 R31 (0x1F) 0 R26 (0x1A) R29 (0x1D) Z-register 0 7 ZL 7 0 0 R30 (0x1E) In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the “Instruction Set Summary” on page 404 for details). ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 14 7.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0200. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two for ATmega640/1280/1281 and three for ATmega2560/2561 when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 14 13 12 11 10 9 8 0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Read/Write Initial Value ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 15 7.6.1 RAMPZ – Extended Z-pointer Register for ELPM/SPM Bit 7 6 5 4 3 2 1 0 0x3B (0x5B) RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 RAMPZ For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 7-4. Note that LPM is not affected by the RAMPZ setting. Figure 7-4. The Z-pointer used by ELPM and SPM Bit (Individually) 7 Bit (Z-pointer) 23 0 7 16 15 RAMPZ 0 7 8 7 0 ZH ZL 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 7.6.2 EIND – Extended Indirect Register Bit 7 6 5 4 3 2 1 0 EIND7 EIND6 EIND5 EIND4 EIND3 EIND2 EIND1 EIND0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 0x3C (0x5C) EIND For EICALL/EIJMP instructions, the Indirect-pointer to the subroutine/routine is a concatenation of EIND, ZH, and ZL, as shown in Figure 7-5. Note that ICALL and IJMP are not affected by the EIND setting. Figure 7-5. The Indirect-pointer used by EICALL and EIJMP Bit (Individually) 7 Bit (Indirectpointer) 23 0 7 16 15 EIND 0 7 8 7 ZH 0 ZL 0 The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero. 7.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-6 on page 17 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 16 Figure 7-6. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 7-7. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Programming” on page 325 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 101. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 101 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 325. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET] DS40002211A 17 flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1
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