DEV-13229

PSoC® 5LP: CY8C58LP Family Datasheet ® Programmable System-on-Chip (PSoC ) General Description PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:  32-bit ARM Cortex-M3 core plus DMA controller and digital filter processor, at up to 80 MHz  Ultra low power with industry's widest voltage range  Programmable digital and analog peripherals enable custom functions  Flexible routing of any analog or digital peripheral function to any pin PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality. Features  Operating characteristics  Analog peripherals Voltage range: 1.71 to 5.5 V, up to 6 power domains [1]  Temperature range (ambient): –40 to 85 °C Extended temperature parts: –40 to 105 °C  DC to 80-MHz operation  Power modes • Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz • 2-µA sleep mode • 300-nA hibernate mode with RAM retention  Boost regulator from 0.5-V input up to 5-V output  Performance  32-bit ARM Cortex-M3 CPU, 32 interrupt inputs  24-channel direct memory access (DMA) controller  24-bit 64-tap fixed-point digital filter processor (DFB)  Memories  Up to 256 KB program flash, with cache and security features  Up to 32 KB additional flash for error correcting code (ECC)  Up to 64 KB RAM  2 KB EEPROM  Digital peripherals  Four 16-bit timer, counter, and PWM (TCPWM) blocks 2  I C, 1 Mbps bus speed  USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral interface (TID#10840032) using internal oscillator[2]  Full CAN 2.0b, 16 Rx, 8 Tx buffers  20 to 24 universal digital blocks (UDB), programmable to create any number of functions: • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • I2C, UART, SPI, I2S, LIN 2.0 interfaces • Cyclic redundancy check (CRC) • Pseudo random sequence (PRS) generators • Quadrature decoders • Gate-level logic functions Configurable 8- to 20-bit delta-sigma ADC Up to two 12-bit SAR ADCs  Four 8-bit DACs  Four comparators  Four opamps  Four programmable analog blocks, to create: • Programmable gain amplifier (PGA) • Transimpedance amplifier (TIA) • Mixer • Sample and hold circuit ®  CapSense support, up to 62 sensors  1.024 V ±0.1% internal voltage reference     Versatile I/O system 46 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs) Up to eight performance I/O (SIO) pins • 25 mA current sink • Programmable input threshold and output high voltages • Can act as a general-purpose comparator • Hot swap capability and overvoltage tolerance  Two USBIO pins that can be used as GPIOs  Route any digital or analog peripheral to any GPIO  LCD direct drive from any GPIO, up to 46 × 16 segments  CapSense support from any GPIO  1.2-V to 5.5-V interface voltages, up to four power domains    Programming, debug, and trace JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire viewer (SWV), and Traceport (5-wire) interfaces  ARM debug and trace modules embedded in the CPU core 2  Bootloader programming through I C, SPI, UART, USB, and other interfaces   Package options: 68-pin QFN and 100-pin TQFP  Development support with free PSoC Creator™ tool  Programmable clocking 3- to 74-MHz internal oscillator, 1% accuracy at 3 MHz 4- to 25-MHz external crystal oscillator  Internal PLL clock generation up to 80 MHz  Low-power internal oscillator at 1, 33, and 100 kHz  32.768-kHz external watch crystal oscillator  12 clock dividers routable to any peripheral or I/O   Schematic and firmware design support Over 100 PSoC Components™ integrate multiple ICs and system interfaces into one PSoC. Components are free embedded ICs represented by icons. Drag and drop component icons to design systems in PSoC Creator.  Includes free GCC compiler, supports Keil/ARM MDK compiler  Supports device programming and debugging   Notes 1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. 2. This feature on select devices only. See Ordering Information on page 126 for details. Cypress Semiconductor Corporation Document Number: 001-84932 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 24, 2015 PSoC® 5LP: CY8C58LP Family Datasheet More Information Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 5LP:  Overview: PSoC Portfolio, PSoC Roadmap  Development Kits:  Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP CY8CKIT-001 provides a common development platform for any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP families of devices.  CY8CKIT-050 is designed for analog performance. It enables you to evaluate, develop and prototype high precision analog, low-power and low-voltage applications powered by PSoC 5LP. Both kits support the PSoC Expansion Board Kit ecosystem. Expansion kits are available for a number of applications including CapSense, precision temperature measurement, and power supervision. In addition, PSoC Creator includes a device selection tool.  Application notes: Cypress offers a large number of PSoC application notes covering a broad range of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 5LP are:  AN77759: Getting Started With PSoC 5LP  AN77835: PSoC 3 to PSoC 5LP Migration Guide  AN61290: Hardware Design Considerations  AN57821: Mixed Signal Circuit Board Layout  AN58304: Pin Selection for Analog Designs  AN81623: Digital Design Best Practices  AN73854: Introduction To Bootloaders  The MiniProg3 device provides an interface for flash programming and debug. PSoC Creator PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100 pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can: 1. Drag and drop component icons to build your hardware 3. Configure components using the configuration tools system design in the main design workspace 4. Explore the library of 100+ components 2. Codesign your application firmware with the PSoC hardware, 5. Review component datasheets using the PSoC Creator IDE C compiler Figure 1. Multiple-Sensor Example Project in PSoC Creator 1 2 3 4 5 Document Number: 001-84932 Rev. *H Page 2 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Contents 1. Architectural Overview ................................................. 4 2. Pinouts ........................................................................... 6 3. Pin Descriptions .......................................................... 11 4. CPU ............................................................................... 12 4.1 ARM Cortex-M3 CPU ...........................................12 4.2 Cache Controller ..................................................13 4.3 DMA and PHUB ...................................................13 4.4 Interrupt Controller ...............................................16 5. Memory ......................................................................... 18 5.1 Static RAM ...........................................................18 5.2 Flash Program Memory ........................................18 5.3 Flash Security .......................................................18 5.4 EEPROM ..............................................................18 5.5 Nonvolatile Latches (NVLs) ..................................19 5.6 External Memory Interface ...................................20 5.7 Memory Map ........................................................21 6. System Integration ...................................................... 22 6.1 Clocking System ...................................................22 6.2 Power System ......................................................25 6.3 Reset ....................................................................30 6.4 I/O System and Routing .......................................32 7. Digital Subsystem ....................................................... 39 7.1 Example Peripherals ............................................39 7.2 Universal Digital Block ..........................................41 7.3 UDB Array Description .........................................44 7.4 DSI Routing Interface Description ........................44 7.5 CAN ......................................................................46 7.6 USB ......................................................................47 7.7 Timers, Counters, and PWMs ..............................48 7.8 I2C ........................................................................48 7.9 Digital Filter Block .................................................50 8. Analog Subsystem ...................................................... 50 8.1 Analog Routing .....................................................51 8.2 Delta-sigma ADC ..................................................53 8.3 Successive Approximation ADC ...........................54 8.4 Comparators .........................................................54 8.5 Opamps ................................................................56 8.6 Programmable SC/CT Blocks ..............................56 8.7 LCD Direct Drive ..................................................57 8.8 CapSense .............................................................58 8.9 Temp Sensor ........................................................58 8.10 DAC ....................................................................58 8.11 Up/Down Mixer ...................................................59 8.12 Sample and Hold ................................................59 Document Number: 001-84932 Rev. *H 9. Programming, Debug Interfaces, Resources ............ 60 9.1 JTAG Interface .....................................................60 9.2 SWD Interface ......................................................62 9.3 Debug Features ....................................................63 9.4 Trace Features .....................................................63 9.5 SWV and TRACEPORT Interfaces ......................63 9.6 Programming Features .........................................63 9.7 Device Security ....................................................63 10. Development Support ............................................... 64 10.1 Documentation ...................................................64 10.2 Online .................................................................64 10.3 Tools ...................................................................64 11. Electrical Specifications ........................................... 65 11.1 Absolute Maximum Ratings ................................65 11.2 Device Level Specifications ................................66 11.3 Power Regulators ...............................................71 11.4 Inputs and Outputs .............................................75 11.5 Analog Peripherals .............................................84 11.6 Digital Peripherals ............................................110 11.7 Memory ............................................................115 11.8 PSoC System Resources .................................119 11.9 Clocking ............................................................122 12. Ordering Information ............................................... 126 12.1 Part Numbering Conventions ...........................127 13. Packaging ................................................................. 128 14. Acronyms ................................................................. 130 15. Reference Documents ............................................. 131 16. Document Conventions .......................................... 132 16.1 Units of Measure ..............................................132 Appendix: CSP Package Summary............................... 133 General Description................................................... 133 Electrical Specifications.............................................. 133 Pinout ........................................................................ 133 CSP Ordering Information .......................................... 134 Packaging.................................................................. 134 Document History Page ................................................. 136 Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 139 139 139 139 139 139 Page 3 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 1. Architectural Overview Introducing the CY8C58LP family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5LP platform. The CY8C58LP family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Clock Tree IMO Digital System Quadrature Decoder UDB UDB UDB UDB I 2C Slave Sequencer Universal Digital Block Array (24 x UDB) 8- Bit Timer 16- Bit PWM UDB 8- Bit SPI UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB 22  UDB 8- Bit Timer Logic UDB UDB UDB FS USB 2.0 4x Timer Counter PWM 12- Bit SPI UDB I2C Master/ Slave CAN 2.0 16- Bit PRS Logic UDB UDB UART UDB UDB USB PHY GPIOs 32.768 KHz ( Optional) GPIOs Xtal Osc SIO System Wide Resources Usage Example for UDB 4- 25 MHz ( Optional) GPIOs Digital Interconnect 12- Bit PWM RTC Timer WDT and Wake EEPROM SRAM CPU System Interrupt Controller Cortex M3CPU Program & Debug GPIOs System Bus Memory System Program GPIOs Debug & Trace EMIF FLASH ILO Cache Controller PHUB DMA Boundary Scan LCD Direct Drive Digital Filter Block POR and LVD 1.71 to 5.5 V Sleep Power 1.8 V LDO SMP 4 x SC / CT Blocks (TIA, PGA, Mixer etc) Temperature Sensor GPIOs Power Management System Analog System ADCs 2x SAR ADC + 4x Opamp - + 4x DAC CapSense 1x Del Sig ADC 4x CMP - 3 per Opamp GPIOs SIOs Clocking System 0. 5 to 5.5 V ( Optional) Figure 1-1 illustrates the major components of the CY8C58LP family. They are:  ARM Cortex-M3 CPU subsystem  Nonvolatile subsystem  Programming, debug, and test subsystem  Inputs and outputs  Clocking  Power  Digital subsystem PSoC’s digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also provides functional flexibility through an array of small, fast, low power UDBs. PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals.  Analog subsystem Document Number: 001-84932 Rev. *H Page 4 of 139 PSoC® 5LP: CY8C58LP Family Datasheet In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C58LP family, these blocks can include four 16-bit timers, counters, and PWM blocks; I2C slave, master, and multimaster; Full-Speed USB; and Full CAN 2.0. For more details on the peripherals see the Example Peripherals on page 39 of this datasheet. For information on UDBs, DSI, and other digital blocks, see the Digital Subsystem on page 39 of this datasheet. PSoC’s analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.1% error over temperature and voltage. The configurable analog subsystem includes:  Analog muxes  Comparators  Analog mixers  Voltage references  ADCs  DACs  Digital filter block (DFB) All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. One of the ADCs in the analog subsystem is a fast, accurate, configurable delta-sigma ADC with these features:  Less than 100-µV offset  A gain error of 0.2%  Integral non linearity (INL) less than ±2 LSB  Differential non linearity (DNL) less than ±1 LSB  SINAD better than 84 dB in 16-bit mode This converter addresses a wide variety of precision analog applications including some of the most demanding sensors. The CY8C58LP family also offers up to two SAR ADCs. Featuring 12-bit conversions at up to 1 M samples per second, they also offer low nonlinearity and offset errors and SNR better than 70 dB. They are well-suited for a variety of higher speed analog applications. The output of any of the ADCs can optionally feed the programmable DFB via DMA without CPU intervention. You can configure the DFB to perform IIR and FIR digital filters and several user defined custom functions. The DFB can implement filters with up to 64 taps. It can perform a 48-bit multiply-accumulate (MAC) operation in one clock cycle. Four high-speed voltage or current DACs support 8-bit output signals at an update rate of up to 8 Msps. They can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. Document Number: 001-84932 Rev. *H In addition to the ADCs, DACs, and DFB, the analog subsystem provides multiple:  Comparators  Uncommitted opamps  Configurable switched capacitor/continuous time (SC/CT) blocks. These support:  Transimpedance amplifiers  Programmable gain amplifiers  Mixers  Other similar analog components See the “Analog Subsystem” section on page 50 of this datasheet for more details. PSoC’s CPU subsystem is built around a 32-bit three-stage pipelined ARM Cortex-M3 processor running at up to 80 MHz. The Cortex-M3 includes a tightly integrated nested vectored interrupt controller (NVIC) and various debug and trace modules. The overall CPU subsystem includes a DMA controller, flash cache, and RAM. The NVIC provides low latency, nested interrupts, and tail-chaining of interrupts and other features to increase the efficiency of interrupt handling. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The flash cache also reduces system power consumption by allowing less frequent flash access. PSoC’s nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 256 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling boot loaders. You can enable an ECC for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Two KB of byte-writable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR. The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive, CapSense, flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of VDDIO when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with FS USB, the USB physical interface is also provided (USBIO). When not using USB, these pins may also be used for limited digital functionality and device programming. All the features of the PSoC I/Os are covered in detail in the I/O System and Routing on page 32 of this datasheet. Page 5 of 139 PSoC® 5LP: CY8C58LP Family Datasheet The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The internal main oscillator (IMO) is the master clock base for the system, and has one-percent accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 74 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate system clock frequencies up to 80 MHz from the IMO, external crystal, or external reference clock. It also contains a separate, very low-power internal low-speed oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in RTC applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C58LP family supports a wide supply operating range from 1.71 to 5.5 V. This allows operation from regulated supplies such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly from a wide range of battery types. In addition, it provides an integrated high efficiency synchronous boost converter that can power the device from supply voltages as low as 0.5 V. This enables the device to be powered directly from a single battery. In addition, you can use the boost converter to generate other voltages required by the device, such as a 3.3 V supply for LCD glass drive. The boost’s output is available on the VBOOST pin, allowing other devices in the application to be powered from the PSoC. PSoC supports a wide range of low power modes. These include a 300-nA hibernate mode with RAM retention and a 2-µA sleep mode with RTC. In the second mode, the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 3.1 mA when the CPU is running at 6 MHz. The details of the PSoC power modes are covered in the Power System on page 25 of this datasheet. PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for programming, debug, and test. Using these standard interfaces you can debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. The Cortex-M3 debug and trace modules include FPB, DWT, ETM, and ITM. These modules have many features to help solve difficult debug and trace problems. Details of the programming, test, and debugging interfaces are discussed in the Programming, Debug Interfaces, Resources on page 60 of this datasheet. Document Number: 001-84932 Rev. *H 2. Pinouts Each VDDIO pin powers a specific set of I/O pins. (The USBIOs are powered from VDDD.) Using the VDDIO pins, a single PSoC can support multiple voltage levels, reducing the need for off-chip level shifters. The black lines drawn on the pinout diagrams in Figure 2-3 and Figure 2-4 show the pins that are powered by each VDDIO. Each VDDIO may source up to 100 mA total to its associated I/O pins, as shown in Figure 2-1. Figure 2-1. VDDIO Current Limit IDDIO X = 100 mA VDDIO X I/O Pins PSoC Conversely, for the 100-pin and 68-pin devices, the set of I/O pins associated with any VDDIO may sink up to 100 mA total, as shown in Figure 2-2. Figure 2-2. I/O Pins Current Limit Ipins = 100 mA VDDIO X I/O Pins PSoC VSSD Page 6 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 P2[5] (GPIO, TRACEDATA[1]) VDDIO2 P2[4] (GPIO, TRACEDATA[0]) P2[3] (GPIO, TRACECLK) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPOI) P15[4] (GPIO) VDDD VSSD VCCD P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OPAMP2-) P0[4] (GPIO, OPAMP2+, SAR0 EXTREF) VDDIO0 Figure 2-3. 68-pin QFN Part Pinout [3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 51 50 Lines show VDDIO to I/O supply association QFN (TOP VIEW) 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 P0[3] (GPIO, OPAMP0-, EXTREF0) P0[2] (GPIO, OPAMP0+, SAR1 EXTREF) P0[1] (GPIO, OPAMP0OUT) P0[0] (GPIO, OPAMP2OUT) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, 12C1: SCL) P3[7] (GPIO, OPAMP3OUT) P3[6] (GPIO, OPAMP1OUT) VDDIO3 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] [4] (USBIO, D+, SWDIO) P15[6] [4] (USBIO, D-, SWDCK) P15[7] VDDD VSSD VCCD (MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1] (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (OPAMP3-, EXTREF1, GPIO) P3[2] (OPAMP3+, GPIO) P3[3] (OPAMP1-, GPIO) P3[4] (OPAMP1+, GPIO) P3[5] 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 (TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] VSSB IND VBOOST VBAT VSSD XRES (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (Configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (NTRST, GPIO) P1[5] VDDIO1 Notes 3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices. 4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-84932 Rev. *H Page 7 of 139 PSoC® 5LP: CY8C58LP Family Datasheet P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, OPAMP2-) P0[4] (GPIO, OPAMP2+, SAR0 EXTREF) P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO) VDDD VSSD VCCD P4[7] (GPIO) P4[6] (GPIO) 75 74 Lines show VDDIO to I/O supply association TQFP 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDIO0 P0[3] (GPIO, OPAMP0-, EXTREF0) P0[2] (GPIO, OPAMP0+, SAR1 EXTREF) P0[1] (GPIO, OPAMP0OUT) P0[0] (GPIO, OPAMP2OUT) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA (OPAMP1+, GPIO) P3[5] VDDIO3 VCCA NC NC NC NC NC NC P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO, OPAMP3OUT) P3[6] (GPIO, OPAMP1OUT) [5] [5] (USBIO, D-, SWDCK) P15[7] VDDD VSSD VCCD NC NC (MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1] (IDAC1, GPIO) P3[0] (IDAC3, GPIO) P3[1] (OPAMP3-, EXTREF1, GPIO) P3[2] (OPAMP3+, GPIO) P3[3] (OPAMP1-, GPIO) P3[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDIO1 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6] (GPIO) P5[7] (USBIO, D+, SWDIO) P15[6] (TRACEDATA[1], GPIO) P2[5] (TRACEDATA[2], GPIO) P2[6] (TRACEDATA[3], GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] VSSB IND VBOOST VBAT VSSD XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (Configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] (TDI, GPIO) P1[4] (NTRST, GPIO) P1[5] 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 VDDIO2 P2[4] (GPIO, TRACEDATA[0]) P2[3] (GPIO, TRACECLK) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO) Figure 2-4. 100-pin TQFP Part Pinout Figure 2-5 on page 9 and Figure 2-6 on page 10 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two-layer board.  The two pins labeled VDDD must be connected together.  The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 25. The trace between the two VCCD pins should be as short as possible.  The two pins labeled VSSD must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Note 5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-84932 Rev. *H Page 8 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections VDDD VDDD C1 1 UF VDDD C2 0.1 UF VSSD VDDIO0 OA0-, REF0, P0[3] OA0+, SAR1REF, P0[2] OA0OUT, P0[1] OA2OUT, P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] VSSD VDDA VSSA VCCA NC NC NC NC NC NC KHZXIN, P15[3] KHZXOUT, P15[2] SIO, P12[1] SIO, P12[0] OA3OUT, P3[7] VSSD VSSD VDDD C12 0.1 UF C15 1 UF C16 0.1 UF VDDA VDDD C8 0.1 UF C17 1 UF VSSD VSSD VDDA VSSA VCCA VSSD VSSA VDDA C9 1 UF C10 0.1 UF VSSA VDDIO3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDD C11 0.1 UF VCCD VDDD OA1OUT, P3[6] P3[5], OA1+ VDDIO1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] USB D+, P15[6] USB D-, P15[7] VDDD VSSD VCCD NC NC P15[0], MHZXOUT P15[1], MHZXIN P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1- P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] VSSB IND VBOOST VBAT VSSD XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWDIO, TMS P1[1], SWDCK, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], NTRST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSSD 1 2 3 4 5 6 7 8 9 10 11 12 13 VSSD 14 15 16 17 18 19 20 21 22 23 24 25 VSSD VDDIO2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] VDDD VSSD VCCD P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, SAR0REF, P0[4] VSSD VDDD 100 99 98 97 96 95 94 93 92 91 90 89 88 VDDD VSSD 87 86 85 84 83 82 81 80 79 78 77 76 VCCD C6 0.1 UF VSSD VSSD Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6. Document Number: 001-84932 Rev. *H Page 9 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance VSSA VDDD VSSD P lane Document Number: 001-84932 Rev. *H VSSD VDDA VSSA P la ne Page 10 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 3. Pin Descriptions TRACEDATA[3:0]. Cortex-M3 output data. IDAC0, IDAC1, IDAC2, IDAC3. Low-resistance output pin for high-current DACs (IDAC). SWV. SWV output. Opamp0out, Opamp1out, Opamp2out, Opamp3out. High current output of uncommitted opamp.[6] Extref0, Extref1. External reference input to the analog system. SAR0 EXTREF, SAR1 EXTREF. External references for SAR ADCs Opamp0-, Opamp1-, Opamp2-, Opamp3-. Inverting input to uncommitted opamp. Opamp0+, Opamp1+, Opamp2+, Opamp3+. Noninverting input to uncommitted opamp. GPIO. Provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense.[6] I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. Ind. Inductor connection to boost pump. kHz XTAL: Xo, kHz XTAL: Xi. 32.768-kHz crystal oscillator pin. MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25-MHz crystal oscillator pin. nTRST. Optional JTAG Test Reset programming and debug port connection to reset the JTAG connection. SIO. Provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. TRACEPORT connections, USBIO, D+. Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. USBIO, D-. Provides D- connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. VBOOST. Power sense connection to boost pump. VBAT. Battery supply to boost pump. VCCA. Output of the analog core regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 25. VCCD. Output of the digital core regulator or the input to the digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1uF capacitor to VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 25. SWDCK. SWD Clock programming and debug port connection. VDDA. Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. SWDIO. SWD Input and Output programming and debug port connection. VDDD. Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. TCK. JTAG Test Clock programming and debug port connection. VSSA. Ground for all analog peripherals. TDI. JTAG Test Data In programming and debug port connection. VSSB. Ground connection for boost pump. TDO. JTAG Test Data Out programming and debug port connection. VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA. TMS. JTAG Test Mode Select programming and debug port connection. TRACECLK. Cortex-M3 TRACEDATA pins. TRACEPORT connection, clocks VSSD. Ground for all digital logic and I/O pins. XRES (and configurable XRES). External reset pin. Active low with internal pull-up. Pin P1[2] may be configured to be a XRES pin; see “Nonvolatile Latches (NVLs)” on page 19. Note 6. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-84932 Rev. *H Page 11 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 4. CPU 4.1 ARM Cortex-M3 CPU The CY8C58LP family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low-power 32-bit three-stage pipelined Harvard-architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling features. Figure 4-1. ARM Cortex-M3 Block Diagram Interrupt Inputs Nested Vectored Interrupt Controller (NVIC) I- Bus JTAG/SWD D-Bus Embedded Trace Module (ETM) Instrumentation Trace Module (ITM) S-Bus Trace Pins: Debug Block (Serial and JTAG) Flash Patch and Breakpoint (FPB) Trace Port 5 for TRACEPORT or Interface Unit 1 for SWV mode (TPIU) Cortex M3 Wrapper C-Bus AHB 32 KB SRAM Data Watchpoint and Trace (DWT) Cortex M3 CPU Core AHB Bus Matrix Bus Matrix 1 KB Cache 256 KB ECC Flash AHB 32 KB SRAM Bus Matrix AHB Bridge & Bus Matrix DMA PHUB AHB Spokes GPIO & EMIF Prog. Digital Prog. Analog Special Functions Peripherals The Cortex-M3 CPU subsystem includes these features: 4.1.1 Cortex-M3 Features  ARM Cortex-M3 CPU The Cortex-M3 CPU features include:  Programmable nested vectored interrupt controller (NVIC), tightly integrated with the CPU core  Full featured debug and trace modules, tightly integrated with the CPU core  Up to 256 KB of flash memory, 2 KB of EEPROM, and 64 KB of SRAM  Cache controller  Peripheral HUB (PHUB)  DMA controller  External memory interface (EMIF) Document Number: 001-84932 Rev. *H  4 GB address space. Predefined address regions for code, data, and peripherals. Multiple buses for efficient and simultaneous accesses of instructions, data, and peripherals.  The Thumb®-2 instruction set, which offers ARM-level performance at Thumb-level code density. This includes 16-bit and 32-bit instructions. Advanced instructions include:  Bit-field control  Hardware multiply and divide  Saturation  If-Then  Wait for events and interrupts  Exclusive access and barrier  Special register access Page 12 of 139 PSoC® 5LP: CY8C58LP Family Datasheet The Cortex-M3 does not support ARM instructions for SRAM addresses.  Bit-band support for the SRAM region. Atomic bit-level write and read operations for SRAM addresses.  Unaligned data storage and access. Contiguous storage of Table 4-2. Cortex M3 CPU Registers (continued) Register R14 R15 data of different byte lengths.  Operation at two privilege levels (privileged and user) and in xPSR two modes (thread and handler). Some instructions can only be executed at the privileged level. There are also two stack pointers: Main (MSP) and Process (PSP). These features support a multitasking operating system running one or more user-level processes. Description R14 is the link register (LR). The LR stores the return address when a subroutine is called. R15 is the program counter (PC). Bit 0 of the PC is ignored and considered to be 0, so instructions are always aligned to a half word (2 byte) boundary. The program status registers are divided into three status registers, which are accessed either together or separately:  Application program status register (APSR) holds program execution status bits such as zero, carry, negative, in bits[27:31].  Extensive interrupt and system exception support.  Interrupt program status register (IPSR) holds the 4.1.2 Cortex-M3 Operating Modes  Execution program status register (EPSR) holds current exception number in bits[0:8]. 4.1.3 CPU Registers control bits for interrupt continuable and IF-THEN instructions in bits[10:15] and [25:26]. Bit 24 is always set to 1 to indicate Thumb mode. Trying to clear it causes a fault exception. PRIMASK A 1-bit interrupt mask register. When set, it allows only the nonmaskable interrupt (NMI) and hard fault exception. All other exceptions and interrupts are masked. FAULTMASK A 1-bit interrupt mask register. When set, it allows only the NMI. All other exceptions and interrupts are masked. BASEPRI A register of up to nine bits that define the masking priority level. When set, it disables all interrupts of the same or higher priority value. If set to 0 then the masking function is disabled. CONTROL A 2-bit register for controlling the operating mode. Bit 0: 0 = privileged level in thread mode, 1 = user level in thread mode. Bit 1: 0 = default stack (MSP) is used, 1 = alternate stack is used. If in thread mode or user level then the alternate stack is the PSP. There is no alternate stack for handler mode; the bit must be 0 while in handler mode. The Cortex-M3 CPU registers are listed in Table 4-2. Registers R0-R15 are all 32 bits wide. 4.2 Cache Controller The Cortex-M3 operates at either the privileged level or the user level, and in either the thread mode or the handler mode. Because the handler mode is only enabled at the privileged level, there are actually only three states, as shown in Table 4-1. Table 4-1. Operational Level Condition Privileged User Running an exception Handler mode Not used Running main program Thread mode Thread mode At the user level, access to certain instructions, special registers, configuration registers, and debugging components is blocked. Attempts to access them cause a fault exception. At the privileged level, access to all instructions and registers is allowed. The processor runs in the handler mode (always at the privileged level) when handling an exception, and in the thread mode when not. Table 4-2. Cortex M3 CPU Registers Register R0-R12 Description General purpose registers R0-R12 have no special architecturally defined uses. Most instructions that specify a general purpose register specify R0-R12.  Low registers: Registers R0-R7 are accessible by all instructions that specify a general purpose register.  High registers: Registers R8-R12 are accessible R13 by all 32-bit instructions that specify a general purpose register; they are not accessible by all 16-bit instructions. R13 is the stack pointer register. It is a banked register that switches between two 32-bit stack pointers: the main stack pointer (MSP) and the process stack pointer (PSP). The PSP is used only when the CPU operates at the user level in thread mode. The MSP is used in all other privilege levels and modes. Bits[0:1] of the SP are ignored and considered to be 0, so the SP is always aligned to a word (4 byte) boundary. Document Number: 001-84932 Rev. *H The CY8C58LP family has a 1 KB, 4-way set-associative instruction cache between the CPU and the flash memory. This improves instruction execution rate and reduces system power consumption by requiring less frequent flash access. 4.3 DMA and PHUB The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of:  A central hub that includes the DMA controller, arbiter, and router  Multiple spokes that radiate outward from the hub to most peripherals There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests. Page 13 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 4.3.1 PHUB Features 4.3.3 Priority Levels  CPU and DMA controller are both bus masters to the PHUB The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100% of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-4 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements.  Eight multi-layer AHB bus parallel access paths (spokes) for peripheral access  Simultaneous CPU and DMA access to peripherals located on different spokes  Simultaneous DMA source and destination burst transactions on different spokes  Supports 8-, 16-, 24-, and 32-bit addressing and data Table 4-3. PHUB Spokes and Peripherals PHUB Spokes 0 Peripherals SRAM 1 IOs, PICU, EMIF 2 PHUB local configuration, Power manager, Clocks, IC, SWV, EEPROM, Flash programming interface 3 Analog interface and trim, Decimator 4 USB, CAN, I2C, Timers, Counters, and PWMs 5 DFB 6 UDBs group 1 7 UDBs group 2 Table 4-4. Priority Levels Priority Level % Bus Bandwidth 0 100.0 1 100.0 2 50.0 3 25.0 4.3.2 DMA Features 4 12.5  24 DMA channels 5 6.2 6 3.1 7 1.5  Each channel has one or more transaction descriptors (TDs) to configure channel behavior. Up to 128 total TDs can be defined  Eight levels of priority per channel When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made.  Any digitally routable signal, the CPU, or another DMA channel, 4.3.4 Transaction Modes Supported  TDs can be dynamically updated can trigger a transaction  Each channel can generate up to two interrupts per transfer  Transactions can be stalled or canceled  Supports transaction size of infinite or 1 to 64k bytes  Large transactions may be broken into smaller bursts of 1 to 127 bytes  TDs may be nested and/or chained for complex transactions Document Number: 001-84932 Rev. *H The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: 4.3.4.1 Simple DMA In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing diagrams of DMA read and write cycles are shown in Figure 4-2. For more description on other transfer modes, refer to the Technical Reference Manual. Page 14 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 4-2. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase CLK ADDR 16/32 DATA Phase CLK A B A ADDR 16/32 WRITE B WRITE DATA (A) DATA READY DATA (A) DATA READY Basic DMA Read Transfer without wait states 4.3.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.3.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. 4.3.4.4 Circular DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. 4.3.4.5 Indexed DMA In an indexed DMA case, an external master requires access to locations on the system bus as if those locations were shared memory. As an example, a peripheral may be configured as an SPI or I2C slave where an address is received by the external master. That address becomes an index or offset into the internal system bus memory space. This is accomplished with an initial “address fetch” TD that reads the target address location from the peripheral and writes that value into a subsequent TD in the chain. This modifies the TD chain on the fly. When the “address fetch” TD completes it moves on to the next TD, which has the new address information embedded in it. This TD then carries out the data transfer with the address location required by the external master. 4.3.4.6 Scatter Gather DMA In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist Document Number: 001-84932 Rev. *H Basic DMA Write Transfer without wait states in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. 4.3.4.7 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase “subchains” can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. 4.3.4.8 Nested DMA One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD’s configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD’s configuration. This process repeats as often as necessary. Page 15 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 4.4 Interrupt Controller The Cortex-M3 NVIC supports 16 system exceptions and 32 interrupts from peripherals, as shown in Table 4-5. Table 4-5. Cortex-M3 Exceptions and Interrupts Exception Number Exception Type Priority Exception Table Address Offset Function 0x00 Starting value of R13 / MSP 1 Reset -3 (highest) 0x04 Reset 2 NMI -2 0x08 Non maskable interrupt 3 Hard fault -1 0x0C All classes of fault, when the corresponding fault handler cannot be activated because it is currently disabled or masked 4 MemManage Programmable 0x10 Memory management fault, for example, instruction fetch from a nonexecutable region 5 Bus fault Programmable 0x14 Error response received from the bus system; caused by an instruction prefetch abort or data access error 6 Usage fault Programmable 0x18 Typically caused by invalid instructions or trying to switch to ARM mode 7–10 - - 0x1C–0x28 Reserved 11 SVC Programmable 0x2C System service call via SVC instruction 12 Debug monitor Programmable 0x30 Debug monitor 13 - - 0x34 Reserved 14 PendSV Programmable 0x38 Deferred request for system service 15 SYSTICK Programmable 0x3C System tick timer 16–47 IRQ Programmable 0x40–0x3FC Peripheral interrupt request #0 - #31 Bit 0 of each exception vector indicates whether the exception is executed using ARM or Thumb instructions. Because the Cortex-M3 only supports Thumb instructions, this bit must always be 1. The Cortex-M3 non maskable interrupt (NMI) input can be routed to any pin, via the DSI, or disconnected from all pins. See DSI Routing Interface Description on page 44. The Nested Vectored Interrupt Controller (NVIC) handles interrupts from the peripherals, and passes the interrupt vectors to the CPU. It is closely integrated with the CPU for low latency interrupt handling. Features include:  32 interrupts. Multiple sources for each interrupt.  Eight priority levels, with dynamic priority control.  Priority grouping. This allows selection of preempting and non preempting interrupt levels. Document Number: 001-84932 Rev. *H  Support for tail-chaining, and late arrival, of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.  Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. All interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Page 16 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 4-6. Interrupt Vector Table Interrupt # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Cortex-M3 Exception # 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Document Number: 001-84932 Rev. *H Fixed Function Low voltage detect (LVD) Cache/ECC Reserved Sleep (Pwr Mgr) PICU[0] PICU[1] PICU[2] PICU[3] PICU[4] PICU[5] PICU[6] PICU[12] PICU[15] Comparators Combined Switched Caps Combined I2C CAN Timer/Counter0 Timer/Counter1 Timer/Counter2 Timer/Counter3 USB SOF Int USB Arb Int USB Bus Int USB Endpoint[0] USB Endpoint Data Reserved LCD DFB Int Decimator Int phub_err_int eeprom_fault_int DMA phub_termout0[0] phub_termout0[1] phub_termout0[2] phub_termout0[3] phub_termout0[4] phub_termout0[5] phub_termout0[6] phub_termout0[7] phub_termout0[8] phub_termout0[9] phub_termout0[10] phub_termout0[11] phub_termout0[12] phub_termout0[13] phub_termout0[14] phub_termout0[15] phub_termout1[0] phub_termout1[1] phub_termout1[2] phub_termout1[3] phub_termout1[4] phub_termout1[5] phub_termout1[6] phub_termout1[7] phub_termout1[8] phub_termout1[9] phub_termout1[10] phub_termout1[11] phub_termout1[12] phub_termout1[13] phub_termout1[14] phub_termout1[15] UDB udb_intr[0] udb_intr[1] udb_intr[2] udb_intr[3] udb_intr[4] udb_intr[5] udb_intr[6] udb_intr[7] udb_intr[8] udb_intr[9] udb_intr[10] udb_intr[11] udb_intr[12] udb_intr[13] udb_intr[14] udb_intr[15] udb_intr[16] udb_intr[17] udb_intr[18] udb_intr[19] udb_intr[20] udb_intr[21] udb_intr[22] udb_intr[23] udb_intr[24] udb_intr[25] udb_intr[26] udb_intr[27] udb_intr[28] udb_intr[29] udb_intr[30] udb_intr[31] Page 17 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 5. Memory 5.1 Static RAM CY8C58LP static RAM (SRAM) is used for temporary data storage. Code can be executed at full speed from the portion of SRAM that is located in the code space. This process is slower from SRAM above 0x20000000. The device provides up to 64 KB of SRAM. The CPU or the DMA controller can access all of SRAM. The SRAM can be accessed simultaneously by the Cortex-M3 CPU and the DMA controller if accessing different 32-KB blocks. “Device Security” section on page 63). For more information on how to take full advantage of the security features in PSoC, see the PSoC 5 TRM. Table 5-1. Flash Protection Protection Setting Allowed Not Allowed Unprotected External read and write – + internal read and write Factory Upgrade External write + internal read and write External read 5.2 Flash Program Memory Field Upgrade Internal read and write Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 256 KB of user program space. External read and write Full Protection Internal read External read and write + internal write Up to an additional 32 KB of flash space is available for Error Correcting Codes (ECC). If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. The flash output is 9 bytes wide with 8 bytes of data and 1 byte of ECC data. The CPU or DMA controller read both user code and bulk data located in flash through the cache controller. This provides higher CPU performance. If ECC is enabled, the cache controller also performs error checking and correction. Flash programming is performed through a special interface and preempts code execution out of flash. Code execution may be done out of SRAM during flash programming. The flash 24programming interface performs flash erasing, programming and setting code protection levels. Flash in-system serial programming (ISSP), typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol. 5.3 Flash Security All PSoC devices include a flexible flash protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a boot loader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, protecting your application from external access (see the Document Number: 001-84932 Rev. *H Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress datasheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 5.4 EEPROM PSoC EEPROM memory is a byte addressable nonvolatile memory. The CY8C58LP has 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into 128 rows of 16 bytes each. The factory default values of all EEPROM bytes are 0. Because the EEPROM is mapped to the Cortex-M3 Peripheral region, the CPU cannot execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware. It can take as much as 20 milliseconds to write to EEPROM or flash. During this time the device should not be reset, or unexpected changes may be made to portions of EEPROM or flash. Reset sources (see Reset Sources on page 31) include XRES pin, software reset, and watchdog; care should be taken to make sure that these are not inadvertently activated. In addition, the low voltage detect circuits should be configured to generate an interrupt instead of a reset. Page 18 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-3. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN 0x03 DBGEN DIG_PHS_DLY[3:0] PRT15RDM[1:0] ECCEN DPS[1:0] CFGSPEED The details for individual fields and their factory default settings are shown in Table 5-3:. Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog See “Reset Configuration” on page 38. All pins of the port 01b - high impedance digital are set to the same mode. 10b - resistive pull up 11b - resistive pull down XRESMEN 0 (default) - GPIO Controls whether pin P1[2] is used as a GPIO or as an external reset. See “Pin Descriptions” on page 11, XRES 1 - external reset description. DBGEN Debug Enable allows access to the debug system, for third-party programmers. 0 - access disabled 1 (default) - access enabled CFGSPEED Controls the speed of the IMO-based clock during the device boot process, for faster boot or low-power operation 0 (default) - 12 MHz IMO 1 - 48 MHz IMO DPS[1:0] Controls the usage of various P1 pins as a debug port. See “Programming, Debug Interfaces, Resources” on page 60. 00b - 5-wire JTAG 01b (default) - 4-wire JTAG 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general 0 - ECC disabled configuration and data storage. See “Flash Program 1 (default) - ECC enabled Memory” on page 18. DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited – see “Nonvolatile Latches (NVL)” on page 116. Document Number: 001-84932 Rev. *H Page 19 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 5.6 External Memory Interface CY8C58LP provides an external memory interface (EMIF) for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles. External memory is located in the Cortex-M3 external RAM space; it can use up to 24 address bits. See Memory Map on page 21. The memory can be 8 or 16 bits wide. Cortex-M3 instructions can be fetched/executed from external memory, although at a slower rate than from flash. There is no provision for code security in external memory. If code must be kept secure, then it should be placed in internal flash. See Flash Security on page 18 and Device Security on page 63. Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C58LP only supports one type of external memory device at a time. Figure 5-1. EMIF Block Diagram Address Signals External_ MEM_ ADDR[23:0] I/O PORTs Data Signals External_ MEM_ DATA[15:0] I/O PORTs Control Signals I/O PORTs Data, Address, and Control Signals IO IF PHUB Data, Address, and Control Signals Control DSI Dynamic Output Control UDB DSI to Port Data, Address, and Control Signals EM Control Signals Other Control Signals EMIF Document Number: 001-84932 Rev. *H Page 20 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 5-5. Peripheral Data Address Map (continued) 5.7 Memory Map The Cortex-M3 has a fixed address map, which allows peripherals to be accessed by simple memory access instructions. 5.7.1 Address Map The 4-GB address space is divided into the ranges shown in Table 5-4: Table 5-4. Address Map Address Range 0x00000000– 0x1FFFFFFF 0x20000000– 0x3FFFFFFF 0.5 GB 0x40004F00–0x40004FFF Fixed timer/counter/PWMs 0x40005000–0x400051FF I/O ports control 0x40005400–0x400054FF External Memory Interface (EMIF) control registers 0x40005800–0x40005FFF Analog Subsystem Interface 0x40006000–0x400060FF USB Controller UDB Working Registers Program code. This includes the exception vector table at power up, which starts at address 0. 0x40007000–0x40007FFF PHUB Configuration Use 0x40008000–0x400087FF EEPROM 0x4000A000–0x4000A400 CAN Static RAM. This includes a 1 MByte bit-band region starting at 0x20000000 and a 32 Mbyte bit-band alias region starting at 0x22000000. 0x4000C000–0x4000C800 Digital Filter Block 0x40010000–0x4001FFFF Digital Interconnect Configuration 0x48000000–0x48007FFF Flash ECC Bytes 0x60000000–0x60FFFFFF External Memory Interface (EMIF) 0xE0000000–0xE00FFFFF Cortex-M3 PPB Registers, including NVIC, debug, and trace 0x40000000– 0x5FFFFFFF 0.5 GB Peripherals. 0x60000000– 0x9FFFFFFF 1 GB External RAM. 0xA0000000– 0xDFFFFFFF 1 GB External peripherals. 0xE0000000– 0xFFFFFFFF 0.5 GB Internal peripherals, including the NVIC and debug and trace modules. Table 5-5. Peripheral Data Address Map Address Range 0x00000000–0x0003FFFF Purpose 0x40006400–0x40006FFF Size 0.5 GB Address Range Purpose 256 KB flash The bit-band feature allows individual bits in SRAM to be read or written as atomic operations. This is done by reading or writing bit 0 of corresponding words in the bit-band alias region. For example, to set bit 3 in the word at address 0x20000000, write a 1 to address 0x2200000C. To test the value of that bit, read address 0x2200000C and the result is either 0 or 1 depending on the value of the bit. Most memory accesses done by the Cortex-M3 are aligned, that is, done on word (4-byte) boundary addresses. Unaligned accesses of words and 16-bit half-words on nonword boundary addresses can also be done, although they are less efficient. 0x1FFF8000–0x1FFFFFFF 32 KB SRAM in Code region 5.7.2 Address Map and Cortex-M3 Buses 0x20000000–0x20007FFF 32 KB SRAM in SRAM region 0x40004000–0x400042FF Clocking, PLLs, and oscillators The ICode and DCode buses are used only for accesses within the Code address range, 0–0x1FFFFFFF. 0x40004300–0x400043FF Power management 0x40004500–0x400045FF Ports interrupt control 0x40004700–0x400047FF Flash programming interface 0x40004800–0x400048FF Cache controller 0x40004900–0x400049FF I2C controller 0x40004E00–0x40004EFF Decimator Document Number: 001-84932 Rev. *H The System bus is used for data accesses and debug accesses within the ranges 0x20000000–0xDFFFFFFF and 0xE0100000–0xFFFFFFFF. Instruction fetches can also be done within the range 0x20000000–0x3FFFFFFF, although these can be slower than instruction fetches via the ICode bus. The private peripheral bus (PPB) is used within the Cortex-M3 to access system control registers and debug and trace module registers. Page 21 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 6. System Integration DSI signal from an external I/O pin or other logic 24- to 80-MHz fractional phase-locked loop (PLL) sourced from IMO, MHzECO, or DSI  1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and Sleep Timer  32.768-kHz external crystal oscillator (ECO) for RTC   6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 80 MHz clock, accurate to ±1% over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. All of the system clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything you want, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system’s requirements. It greatly speeds the design process. PSoC Creator allows designers to build clocking systems with minimal input. The designer can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent in PSoC.  IMO has a USB mode that auto-locks to the USB bus clock requiring no external crystal for USB. (USB equipped parts only)  Independently sourced clock in all clock dividers  Eight 16-bit clock dividers for the digital system  Four 16-bit clock dividers for the analog system  Dedicated 16-bit divider for the CPU bus and CPU clock  Automatic clock configuration in PSoC Creator Key features of the clocking system include:  Seven general purpose clock sources 3- to 74-MHz IMO, ±1% at 3 MHz 4- to 25-MHz external crystal oscillator (MHzECO)  Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 25.   Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and temperature 74 MHz ±7% 13 µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 66 MHz Input dependent Input dependent PLL 24 MHz Input dependent 80 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz Crystal dependent 500 ms typ, max is crystal dependent Document Number: 001-84932 Rev. *H Page 22 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-1. Clocking Subsystem 3-74 MHz IMO 4-25 MHz ECO External IO or DSI 0-66 MHz 32 kHz ECO 1,33,100 kHz ILO CPU Clock 48 MHz Doubler for USB 24-80 MHz PLL System Clock Mux Bus Clock Bus Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Document Number: 001-84932 Rev. *H Page 23 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 6.1.1 Internal Oscillators Figure 6-1 shows that there are two internal oscillators. They can be routed directly or divided. The direct routes may not have a 50% duty cycle. Divided clocks have a 50% duty cycle. 6.1.1.1 Internal Main Oscillator In most designs the IMO is the only clock source required, due to its ±1% accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from ±1% at 3 MHz, up to ±7% at 74 MHz. The IMO, in conjunction with the PLL, allows generation of CPU and system clocks up to the device's maximum frequency (see USB Clock Domain on page 25). The IMO provides clock outputs at 3, 6, 12, 24, 48, and 74 MHz. 6.1.1.2 Clock Doubler The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works at input frequency of 24 MHz, providing 48 MHz for the USB. It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin). 6.1.1.3 Phase-Locked Loop The PLL allows low frequency, high accuracy clocks to be multiplied to higher frequencies. This is a tradeoff between higher clock frequency and accuracy and, higher power consumption and increased startup time. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 80 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired system clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, to generate the CPU and system clocks up to the device’s maximum frequency. The central timewheel can be programmed to wake the system periodically and optionally issue an interrupt. This enables flexible, periodic wakeups from low power modes or coarse timing applications. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100-kHz clock (CLK100K) can be used as a low power system clock to run the CPU. It can also generate time intervals using the fast timewheel. The fast timewheel is a 5-bit counter, clocked by the 100-kHz clock. It features programmable settings and automatically resets when the terminal count is reached. An optional interrupt can be generated each time the terminal count is reached. This enables flexible, periodic interrupts of the CPU at a higher rate than is allowed using the central timewheel. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768-kHz ECO clock with no need for a crystal. 6.1.2 External Oscillators Figure 6-1 shows that there are two external oscillators. They can be routed directly or divided. The direct routes may not have a 50% duty cycle. Divided clocks have a 50% duty cycle. 6.1.2.1 MHz External Crystal Oscillator The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate CPU and system clocks up to the device's maximum frequency (see Phase-Locked Loop on page 24). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO, or DSI (external pin). The PLL clock source can be used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low power modes. 4 - 25 MHz Crystal Osc XCLK_MHZ 6.1.1.4 Internal Low-Speed Oscillator The ILO provides clock frequencies for low power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1-kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to low power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The central timewheel is a 1 kHz, free running, 13-bit counter clocked by the ILO. The central timewheel is always enabled except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low power mode. Firmware can reset the central timewheel. Document Number: 001-84932 Rev. *H Xi (Pin P15[1]) External Components Xo (Pin P15[0]) 4 – 25 MHz crystal Capacitors Page 24 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 6.1.2.2 32.768 kHz ECO  The system clock is used to select and supply the fastest clock The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the RTC. The RTC uses a 1 second interrupt to implement the RTC functionality in firmware.  Bus clock 16-bit divider uses the system clock to generate the The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram XCLK32K 32 kHz Crystal Osc in the system for general system clock requirements and clock synchronization of the PSoC device. system’s bus clock used for data transfers and the CPU. The CPU clock is directly derived from the bus clock.  Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the UDBs and fixed function timer/counter/PWMs can also generate clocks.  Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADCs and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Xi (Pin P15[3]) External Components Xo (Pin P15[2]) 32 kHz crystal Capacitors Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50% duty cycle clocks, system clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain It is recommended that the external 32.768-kHz watch crystal have a load capacitance (CL) of 6 pF or 12.5 pF. Check the crystal manufacturer's datasheet. The two external capacitors, CL1 and CL2, are typically of the same value, and their total capacitance, CL1CL2 / (CL1 + CL2), including pin and trace capacitance, should equal the crystal CL value. For more information, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. See also pin capacitance specifications in the “GPIO” section on page 75. 6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and UDBs. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources. The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48-MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crystal oscillator. 6.2 Power System The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator. 6.1.3 Clock Distribution All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees. Document Number: 001-84932 Rev. *H Page 25 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 6-4. PSoC Power System VDDD 1 µF VDDIO2 VDDD I/O Supply VSSD VCCD VDDIO 2 VDDIO0 0.1 µF 0.1 µF I/O Supply VDDIO0 0.1 µF I2C Regulator Sleep Regulator Digital Domain VDDA VDDA Analog Regulator Digital Regulators VSSB VCCA 0.1 µF 1 µF . VSSA Analog Domain 0.1 µF I/O Supply VDDIO3 VDDD VSSD I/O Supply VCCD VDDIO1 Hibernate Regulator 0.1 µF 0.1 µF VDDIO1 VDDD VDDIO3 Notes  The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6.  You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx pins.  You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption.  It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications. With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a significant percentage of the rated working voltage. Document Number: 001-84932 Rev. *H Page 26 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and RTC functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 illustrates the allowable transitions between power modes. Sleep and hibernate modes should not be entered until all VDDIO supplies are at valid voltage levels. 6.2.1 Power Modes PSoC 5LP devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low power and portable devices. PSoC 5LP power modes, in order of decreasing power consumption are:  Active  Alternate active  Sleep  Hibernate Table 6-2. Power Modes Power Modes Description Entry Condition Wakeup Source Active Clocks Regulator Active Primary mode of operation, all Wakeup, reset, peripherals available (program- manual register mable) entry Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Alternate Active Manual register Similar to Active mode, and is entry typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off Any interrupt Any (programmable) All regulators available. Digital and analog regulators can be disabled if external regulation used. Sleep All subsystems automatically disabled Comparator, ILO/kHzECO PICU, I2C, RTC, CTW, LVD Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Hibernate Manual register All subsystems automatically entry disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained PICU Only hibernate regulator active. Manual register entry Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Wakeup Time Current (Typ) Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources Active – 3.1 mA[7] Yes All All All – All Alternate Active – – User defined All All All – All Vddsio 25 °C, Vddsio = 0 V, VIH = 3.0 V – – 10 µA – – 9 pF Single ended mode (GPIO mode) – 115 – mV Differential mode – 50 – mV – – 100 µA CIN Input Capacitance[36] VH Input voltage hysteresis (Schmitt-Trigger)[36] Idiode Current through protection diode to VSSIO Notes 35. See Figure 6-9 on page 34 and Figure 6-12 on page 37 for more information on SIO reference. 36. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 77 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-10. SIO Output High Voltage and Current, Unregulated Mode Figure 11-11. SIO Output Low Voltage and Current, Unregulated Mode Figure 11-12. SIO Output High Voltage and Current, Regulated Mode Document Number: 001-84932 Rev. *H Page 78 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-12 SIO AC Specifications[37] Parameter Description Conditions Min Typ Max Units TriseF Rise time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V – – 12 ns TfallF Fall time in fast strong mode (90/10%) Cload = 25 pF, VDDIO = 3.3 V – – 12 ns TriseS Rise time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.0 V – – 75 ns TfallS Fall time in slow strong mode (90/10%) Cload = 25 pF, VDDIO = 3.0 V – – 60 ns 2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast strong drive mode 90/10% VDDIO into 25 pF – – 33 MHz 1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast strong drive mode 90/10% VDDIO into 25 pF – – 16 MHz 3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow strong drive mode 90/10% VDDIO into 25 pF – – 5 MHz 1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow strong drive mode 90/10% VDDIO into 25 pF – – 4 MHz 2.7 V < VDDIO < 5.5 V, Regulated Output continuously switching into 25 pF output mode, fast strong drive mode – – 20 MHz 1.71 V < VDDIO < 2.7 V, Regulated Output continuously switching into output mode, fast strong drive 25 pF mode – – 10 MHz 1.71 V < VDDIO < 5.5 V, Regulated Output continuously switching into 25 pF output mode, slow strong drive mode – – 2.5 MHz – – 66 MHz SIO output operating frequency Fsioout Fsioin SIO input operating frequency 1.71 V < VDDIO < 5.5 V 90/10% VDDIO Note 37. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 79 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-13. SIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load Figure 11-14. SIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load Table 11-13. SIO Comparator Specifications[38] Parameter Vos Description Offset voltage Conditions Min Typ Max Units VDDIO = 2 V – – 68 mV VDDIO = 2.7 V – – 72 VDDIO = 5.5 V TCVos Offset voltage drift with temp CMRR Common mode rejection ratio Tresp Response time Document Number: 001-84932 Rev. *H – – 82 – – 250 μV/°C VDDIO = 2 V 30 – – dB VDDIO = 2.7 V 35 – – VDDIO = 5.5 V 40 – – – – 30 ns Page 80 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.4.3 USBIO For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 66. Table 11-14. USBIO DC Specifications Min Typ Max Units Rusbi Parameter USB D+ pull-up resistance[38] With idle bus 0.900 – 1.575 k Rusba USB D+ pull-up resistance[38] While receiving traffic 1.425 – 3.090 k Vohusb Static output high[38] 15 k ±5% to Vss, internal pull-up enabled 2.8 – 3.6 V Volusb Static output low[38] 15 k ±5% to Vss, internal pull-up enabled – – 0.3 V Vihgpio Input voltage high, GPIO mode[38] VDDD = 1.8 V 1.5 – – V VDDD = 3.3 V 2 – – V Vilgpio Vohgpio Volgpio Vdi Description Input voltage low, GPIO mode[38] Output voltage high, GPIO mode[38] Output voltage low, GPIO mode[38] Differential input sensitivity Conditions VDDD = 5.0 V 2 – – V VDDD = 1.8 V – – 0.8 V VDDD = 3.3 V – – 0.8 V VDDD = 5.0 V – – 0.8 V IOH = 4 mA, VDDD = 1.8 V 1.6 – – V IOH = 4 mA, VDDD = 3.3 V 3.1 – – V IOH = 4 mA, VDDD = 5.0 V 4.2 – – V IOL = 4 mA, VDDD = 1.8 V – – 0.3 V IOL = 4 mA, VDDD = 3.3 V – – 0.3 V IOL = 4 mA, VDDD = 5.0 V – – 0.3 V |(D+)–(D–)| – – 0.2 V V Vcm Differential input common mode range 0.8 – 2.5 Vse Single ended receiver threshold 0.8 – 2 V Rps2 PS/2 pull-up resistance[38] In PS/2 mode, with PS/2 pull-up enabled 3 – 7 k Rext External USB series resistor[38] In series with each USB pin 21.78 (–1%) 22 22.22 (+1%)  Zo USB driver output impedance[38] Including Rext 28 – 44  CIN USB transceiver input capacitance – – 20 pF 25 °C, VDDD = 3.0 V – – 2 nA IIL[38] Input leakage current (absolute value)[38] Note 38. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 81 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-15. USBIO Output High Voltage and Current, GPIO Mode Figure 11-16. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load Table 11-15. USBIO AC Specifications[39] Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 – 0.25% 12 12 + 0.25% MHz Tjr1 Receiver data jitter tolerance to next transition –8 – 8 ns Tjr2 Receiver data jitter tolerance to pair transition –5 – 5 ns Tdj1 Driver differential jitter to next transition –3.5 – 3.5 ns Tdj2 Driver differential jitter to pair transition –4 – 4 ns Tfdeop Source jitter for differential transition to SE0 transition –2 – 5 ns Tfeopt Source SE0 interval of EOP 160 – 175 ns Tfeopr Receiver SE0 interval of EOP 82 – – ns Tfst Width of SE0 interval during differential transition – – 14 ns Fgpio_out GPIO mode output operating frequency 3 V  VDDD  5.5 V – – 20 MHz – – 6 MHz VDDD = 1.71 V Tr_gpio Rise time, GPIO mode, 10%/90% VDDD VDDD > 3 V, 25 pF load VDDD = 1.71 V, 25 pF load Tf_gpio Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load VDDD = 1.71 V, 25 pF load – – 12 ns – – 40 ns – – 12 ns – – 40 ns Note 39. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 82 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-17. USBIO Output Low Voltage and Current, GPIO Mode Table 11-16. USB Driver AC Specifications[40] Parameter Description Conditions Min Typ Max Units Tr Transition rise time – – 20 ns Tf Transition fall time – – 20 ns TR Rise/fall time matching 90% – 111% Vcrs Output signal crossover voltage 1.3 – 2 V Min Typ Max Units VUSB_5, VUSB_3.3, see USB DC Specifications on page 113 11.4.4 XRES Table 11-17. XRES DC Specifications Parameter Description Conditions VIH Input voltage high threshold 0.7  VDDIO – – V VIL Input voltage low threshold – – 0.3 VDDIO V 8.5 k Rpullup Pull-up resistor 3.5 5.6 CIN Input capacitance[40] – 3 VH Input voltage hysteresis (Schmitt-Trigger)[40] – 100 – mV Idiode Current through protection diode to VDDIO and VSSIO – – 100 µA Min Typ Max Units 1 – – µs pF Table 11-18. XRES AC Specifications[40] Parameter TRESET Description Reset pulse width Conditions Note 40. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 83 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5 Analog Peripherals Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.5.1 Opamp Table 11-19. Opamp DC Specifications Parameter Description VI Input voltage range Vos Input offset voltage Conditions Operating temperature –40 °C to 70 °C TCVos Input offset voltage drift with temperature Power mode = high Min Typ Max Units VSSA – VDDA V – – 2.5 mV – – 2 mV – – ±30 µV / °C Ge1 Gain error, unity gain buffer mode Rload = 1 k – – ±0.1 % Cin Input capacitance Routing from pin – – 18 pF Vo Output voltage range 1 mA, source or sink, power mode VSSA + 0.05 = high Iout Output current capability, source or sink VSSA + 500 mV VOUT  VDDA –500 mV, VDDA > 2.7 V 25 – – mA VSSA + 500 mV  VOUT  VDDA –500 mV, 1.7 V = VDDA  2.7 V 16 – – mA Idd Quiescent current[41] CMRR Common mode rejection ratio[41] PSRR Power supply rejection ratio[41] IIB Input bias current[41] – VDDA – 0.05 V Power mode = min – 250 400 uA Power mode = low – 250 400 uA Power mode = med – 330 950 uA Power mode = high – 1000 2500 uA 80 – – dB VDDA  2.7 V 85 – – dB VDDA < 2.7 V 70 – – dB 25 °C – 10 – pA Note 41. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 84 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-18. Opamp Vos Histogram, 7020 samples/1755 parts, 30 °C, VDDA = 3.3 V Figure 11-19. Opamp Vos vs Temperature, VDDA = 5 V 0.2 20 18 0.1 16 Vos, mV 14 % 12 10 8 0 -0.1 6 -0.2 4 2 -0.3 -40 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 -20 0 20 40 60 80 100 Temperature, °C Vos, mV Figure 11-20. Opamp Vos vs Vcommon and VDDA, 25 °C Figure 11-21. Opamp Output Voltage vs Load Current and Temperature, High Power Mode, 25 °C, Vdda = 2.7 V 3 0.3 2.5 0.25 2 Vdda = 5 5.5 5V 0 15 0.15 Vdda = 2.7 V 0.1 Vdda = 1.7 V 0.05 Vo out, V Vos, mV 0.2 Vin = 2.7 V 1.5 Vin = 0 V 1 0.5 0 0 1 2 3 4 5 6 Vcommon, V 0 0 5 10 15 Iload, Source / Sink, mA 20 25 Figure 11-22. Opamp Operating Current vs Vdda and Power Mode 1 Current, mA 0.8 0.6 0.4 0.2 0 1 2 High Power Mode 3 VDDA, V Medium Document Number: 001-84932 Rev. *H 4 5 Low, Minimum Page 85 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-20. Opamp AC Specifications[42] Parameter Description GBW Gain-bandwidth product SR Slew rate, 20% - 80% en Input noise density Conditions Power mode = minimum, 15 pF load Power mode = low, 15 pF load Power mode = medium, 200 pF load Power mode = high, 200 pF load Power mode = minimum, 15 pF load Power mode = low, 15 pF load Power mode = medium, 200 pF load Power mode = high, 200 pF load Power mode = high, Vdda = 5 V, at 100 kHz Figure 11-23. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5V Typ – – – – – – – – 45 Max – – – – – – – – – Units MHz MHz MHz MHz V/µs V/µs V/µs V/µs nV/sqrtHz Figure 11-24. Opamp Step Response, Rising 1.2 Input and Outp put Signals, V 1000 nV/sq qrtHz Min 1 2 1 3 1.1 1.1 0.9 3 – 100 1 0.8 06 0.6 Input 0.4 Output 0.2 0 10 0.01 0.1 1 10 100 1000 Frequency, kHz -1 -0.5 0 Time, μs 0.5 1 Figure 11-25. Opamp Step Response, Falling Input and Outpu ut Signals, V 1.2 1 0.8 Input p 06 0.6 Output 0.4 0.2 0 -1 -0.5 0 Time, μs 0.5 1 Note 42. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 86 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.2 Delta-Sigma ADC Unless otherwise specified, operating conditions are:  Operation in continuous sample mode  fclk = 3.072 MHz for resolution = 16 to 20 bits; fclk = 6.144 MHz for resolution = 8 to 15 bits  Reference = 1.024 V internal reference bypassed on P3.2 or P0.3  Unless otherwise specified, all charts and graphs show typical values Table 11-21. 20-bit Delta-sigma ADC DC Specifications Parameter Min Typ Max Units Resolution Description Conditions 8 – 20 bits Number of channels, single ended – – No. of GPIO – Number of channels, differential Differential pair is formed using a pair of GPIOs. – – No. of GPIO/2 – Monotonic Yes – – – – Ge Gain error Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode, 25 °C – – ±0.4 % Gd Gain drift Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode – – 50 ppm/°C Buffered, 16-bit mode, full voltage range – – ±0.2 mV Buffered, 16-bit mode, VDDA = 1.8 V ±5%, 25 °C – – ±0.1 mV Buffer gain = 1, 16-bit, Range = ±1.024 V – – 1 µV/°C Input voltage range, single ended[43] VSSA – VDDA V Input voltage range, differential unbuffered[43] VSSA – VDDA V Input voltage range, differential, buffered[43] VSSA – VDDA – 1 V 90 – – dB 85 – – 80 – – Range = ±1.024 V, unbuffered – – ±32 LSB Vos TCVos Input offset voltage Temperature coefficient, input offset voltage Buffer gain = 1, 16-bit, Range = ±1.024 V PSRRb Power supply rejection ratio, buffered[43] CMRRb Buffer gain = 1, 16 bit, Common mode rejection ratio, buffered[43] Range = ±1.024 V TA ≤ 105 °C INL20 Integral non linearity[43] [43] dB DNL20 Differential non linearity Range = ±1.024 V, unbuffered – – ±1 LSB INL16 Integral non linearity[43] Range = ±1.024 V, unbuffered – – ±2 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB linearity[43] DNL16 Differential non INL12 Integral non linearity[43] linearity[43] DNL12 Differential non INL8 Integral non linearity[43] DNL8 [43] Differential non linearity Note 43. Based on device characterization (not production tested). Document Number: 001-84932 Rev. *H Page 87 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-21. 20-bit Delta-sigma ADC DC Specifications (continued) Parameter Min Typ Max Units Input buffer used 10 – – M Rin_ADC16 ADC input resistance Input buffer bypassed, 16-bit, Range = ±1.024 V – 74[44] – k Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range = ±1.024 V – 148[44] – k 0.9 – 1.3 V – – 1.5 mA – – 1.5 mA – – 1.95 mA – – 1.95 mA – – 2.5 mA Min Typ Max Units – – 4 Samples – – 0.0032 % Range = ±1.024 V, unbuffered 7.8 – 187 sps Range = ±1.024 V, unbuffered – 40 – Hz Rin_Buff Vextref Description Conditions ADC input resistance ADC external reference input voltage, see also internal reference in Voltage Pins P0[3], P3[2] Reference on page 92 Current Consumption IDD_20 IDDA + IDDD Current consumption, 20 bit[45] 187 sps, unbuffered [45] IDD_16 IDDA + IDDD Current consumption, 16 bit IDD_12 IDDA + IDDD Current consumption, 12 bit[45] 192 ksps, unbuffered IDD_8 IDDA + IDDD Current consumption, 8 IBUFF Buffer current consumption[45] bit[45] 48 ksps, unbuffered 384 ksps, unbuffered Table 11-22. Delta-sigma ADC AC Specifications Parameter Description Conditions Startup time THD Total harmonic distortion[45] Buffer gain = 1, 16 bit, Range = ±1.024 V 20-Bit Resolution Mode SR20 BW20 Sample rate[45] Input bandwidth at max sample rate[45] 16-Bit Resolution Mode SR16 Sample rate[45] Range = ±1.024 V, unbuffered 2 – 48 ksps BW16 Input bandwidth at max sample rate[45] Range = ±1.024 V, unbuffered – 11 – kHz SINAD16int Signal to noise ratio, 16-bit, internal reference[45] Range = ±1.024V, unbuffered 81 – – dB TA ≤ 105 °C 77 – – SINAD16ext Signal to noise ratio, 16-bit, external reference[45] Range = ±1.024 V, unbuffered 84 – – dB Range = ±1.024 V, unbuffered 4 – 192 ksps Range = ±1.024 V, unbuffered – 44 – kHz Range = ±1.024 V, unbuffered 66 – – dB 12-Bit Resolution Mode SR12 BW12 Sample rate, continuous, high power[45] Input bandwidth at max sample rate[45] SINAD12int Signal to noise ratio, 12-bit, internal reference[45] 8-Bit Resolution Mode SR8 Sample rate, continuous, high power[45] Range = ±1.024 V, unbuffered 8 – 384 ksps BW8 Input bandwidth at max sample rate[45] Range = ±1.024 V, unbuffered – 88 – kHz SINAD8int Signal to noise ratio, 8-bit, internal reference[45] Range = ±1.024 V, unbuffered 43 – – dB Notes 44. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. 45. Based on device characterization (not production tested). Document Number: 001-84932 Rev. *H Page 88 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-23. Delta-sigma ADC Sample Rates, Range = ±1.024 V Continuous Resolution, Bits 8 Multi-Sample Min Max Min Max Min Max 8000 384000 1911 91701 1829 87771 9 6400 307200 1543 74024 1489 71441 10 5566 267130 1348 64673 1307 62693 11 4741 227555 1154 55351 1123 53894 12 4000 192000 978 46900 956 45850 13 3283 157538 806 38641 791 37925 14 2783 133565 685 32855 674 32336 15 2371 113777 585 28054 577 27675 16 2000 48000 495 11861 489 11725 17 500 12000 124 2965 282 6766 18 125 3000 31 741 105 2513 19 16 375 4 93 15 357 20 8 187.5 2 46 8 183 Figure 11-26. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed Figure 11-27. Delta-sigma ADC Noise Histogram, 1000 Samples, 20-Bit, 187 sps, Ext Ref, VIN = VREF/2, Range = ±1.024 V 15 2 10 % 1 5 16 bit 1 10 100 Sample Rate, Ksps 1000 Figure 11-28. Delta-sigma ADC Noise Histogram, 1000 Samples, 16-bit, 48 ksps, Ext Ref, VIN = VREF/2, Range = ±1.024 V 264614 264612 264610 264608 264606 264604 264602 264600 264598 264596 264588 0 264594 0 12 bit 264592 0.5 264590 Curren nt, mA 1.5 Code, 20bit Figure 11-29. Delta-sigma ADC Noise Histogram, 1000 Samples, 16-bit, 48 ksps, Int Ref, VIN = VREF/2, Range = ±1.024 V 30 25 25 20 20 15 % % Multi-Sample Turbo 15 10 10 5 5 Document Number: 001-84932 Rev. *H 16172 16171 16170 16169 16168 16167 16166 16165 16164 16163 16162 16161 16160 16159 16158 16169 16168 16167 16166 16165 16164 16163 16162 16161 16160 16159 16158 16157 16156 Counts, 16 bit 16157 0 0 Counts, 16 bit Page 89 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-24. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Single Ended Sample Rate SPS Input Voltage Range 0 to VREF 0 to 2xVREF 0 to VDDA 0 to 6xVREF 2000 1.52 0.80 1.57 1.38 3000 1.63 0.87 1.64 1.43 6000 1.59 0.88 1.65 1.42 12000 1.59 0.85 1.62 1.40 24000 1.60 0.84 1.60 1.39 48000 1.57 0.83 1.57 1.36 Table 11-25. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 16-bit, Internal Reference, Differential Sample Rate SPS Input Voltage Range ± VREF ± VREF/2 ± VREF/4 ± VREF/8 ± VREF/16 2000 0.81 1.01 1.15 1.38 2.55 4000 0.84 1.05 1.17 1.42 2.76 8000 0.83 1.04 1.18 1.48 2.83 15625 0.85 1.08 1.18 1.50 2.87 32000 0.84 1.05 43750 0.83 1.06 48000 0.82 Table 11-26. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Single Ended Sample Rate Input Voltage Range VSSA_to_VREF VSSA_to_2*VREF VSSA_to_VDDA VSSA_to_6*VREF 8 1.53 1.00 1.63 1.62 23 1.84 0.99 2.14 1.52 45 1.82 0.96 1.91 1.57 90 1.83 0.99 1.98 1.76 187 1.87 0.98 1.92 1.61 Document Number: 001-84932 Rev. *H Page 90 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-27. Delta-sigma ADC RMS Noise in Counts vs. Input Range and Sample Rate, 20-bit, External Reference, Differential[46] Sample Rate, SPS Input Voltage Range ± VREF ± VREF/2 ± VREF/4 ± VREF/8 ± VREF/16 8 1.01 1.03 1.31 1.78 3.57 12 0.99 1.21 1.45 1.80 3.61 23 0.94 1.26 1.69 2.91 3.92 45 1.06 1.35 1.70 2.07 3.83 61 1.08 1.35 0.95 2.20 3.96 170 1.02 1.36 187 0.96 Figure 11-31. Delta-sigma ADC INL vs Output Code, 16-bit, 48 ksps, 25 °C VDDA = 3.3 V 1 0.25 0.5 -0.5 -1 Code, 16 bit 32768 -0.5 0 -0.25 Code, 16 bit 32768 0 0 0 -32768 INL, LSB 0.5 -32768 DNL, LSB Figure 11-30. Delta-sigma ADC DNL vs Output Code, 16-bit, 48 ksps, 25 °C VDDA = 3.3 V Note 46. The RMS noise (in volts) is the range (in volts) times noise in counts divided by 2^number of bits. RMS Noise = (Range × Counts) / 2^bits Document Number: 001-84932 Rev. *H Page 91 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.3 Voltage Reference Table 11-28. Voltage Reference Specifications See ADC external reference specifications in Delta-Sigma ADC on page 87. Parameter VREF[47] Description Conditions Precision reference voltage Initial trimming, 25 °C After typical PCB assembly, post reflow –40 °C Typical (non-optimized) board layout and 250 °C solder reflow. 25 °C Device may be calibrated after assembly to improve performance. 85 °C 105 °C Min Typ 1.023 1.024 (–0.1%) Max Units 1.025 (+0.1%) V – ±0.5 – % – ±0.2 – % – ±0.2 – % – ±0.3 – % Temperature drift[48] – – 30 ppm/°C Long term drift[48] – 100 – ppm/Khr Thermal cycling drift (stability)[48] – 100 – ppm Figure 11-32. Vref vs Temperature Figure 11-33. Vref Long-term Drift 1025 Vref, m mV 1024.5 1024 1.95V 1023.5 1.8V 1.71V 1023 -40 -20 0 20 40 60 80 100 Temperature, °C Notes 47. VREF is measured after packaging, and thus accounts for substrate and die attach stresses. 48. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 92 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.4 SAR ADC Table 11-29. SAR ADC DC Specifications Parameter Description Conditions Units bits – – 12 – – No of GPIO – – No of GPIO/2 Yes – – error[50] Ge Gain VOS Input offset voltage IDD Current consumption[49] Differential pair is formed using a pair of neighboring GPIO. External reference Input voltage range – single-ended[49] Input voltage range – differential[49] Power supply rejection ratio[49] CMRR Common mode rejection ratio INL Integral non linearity[49] RIN Max Number of channels – single-ended Monotonicity[49] DNL Typ Resolution Number of channels – differential PSRR Min Differential non linearity[49] Input resistance[49] – – ±0.1 % – – ±2 mV – – 1 mA VSSA – VDDA V VSSA – VDDA V 70 – – dB 70 – – dB VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V, bypassed at ExtRef pin – – +2/–1.5 LSB VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA, bypassed at ExtRef pin – – ±1.2 LSB VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V, bypassed at ExtRef pin – – ±1.3 LSB VDDA 1.71 to 5.5 V, 1 Msps, VREF 1 to 5.5 V, bypassed at ExtRef pin – – +2/–1 LSB VDDA 2.0 to 3.6 V, 1 Msps, VREF 2 to VDDA, bypassed at ExtRef pin No missing codes – – 1.7/–0.99 LSB VDDA 1.71 to 5.5 V, 500 ksps, VREF 1 to 5.5 V, bypassed at ExtRef pin No missing codes – – +2/–0.99 LSB – 180 – kΩ Notes 49. Based on device characterization (Not production tested). 50. For total analog system Idd < 5 mA, depending on package used. With higher total analog system currents it is recommended that the SAR ADC be used in differential mode. Document Number: 001-84932 Rev. *H Page 93 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-35. SAR ADC INL vs Output Code, Bypassed Internal Reference Mode 1 1 0.5 0.5 INL, L LSB DNL, LSB Figure 11-34. SAR ADC DNL vs Output Code, Bypassed Internal Reference Mode 0 -0.5 0 -0.5 -1 -2048 0 2048 Code (12 bit) -1 -2048 0 2048 Code (12 bit) Figure 11-36. SAR ADC IDD vs sps, VDDA = 5 V, Continuous Sample Mode, External Reference Mode 0.5 Current, mA 0.4 0.3 0.2 0.1 0 0 250 500 750 1000 Sample Rate, ksps Document Number: 001-84932 Rev. *H Page 94 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-30. SAR ADC AC Specifications[51] Parameter Description Conditions Min Typ Max Units A_SAMP_1 Sample rate with external reference bypass cap – – 1 Msps A_SAMP_2 Sample rate with no bypass cap. Reference = VDD – – 500 Ksps A_SAMP_3 Sample rate with no bypass cap. Internal reference – – 100 Ksps Startup time – – 10 µs SINAD Signal-to-noise ratio 68 – – dB THD Total harmonic distortion – – 0.02 % Figure 11-37. SAR ADC Noise Histogram, 100 ksps, Internal Reference No Bypass Figure 11-38. SAR ADC Noise Histogram, 1 msps, Internal Reference Bypassed 100 100 80 80 60 % % 60 40 40 20 20 1026 1025 1024 1023 1025 1024 1023 1022 1021 Counts, 12 bit 1022 0 0 Counts, 12 bit Figure 11-39. SAR ADC Noise Histogram, 1 msps, External Reference 100 80 % 60 40 20 1024 1023 1022 1021 1020 0 Counts, 12 bit Note 51. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 95 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.5 Analog Globals Table 11-31. Analog Globals DC Specifications Parameter Rppag Rppmuxbus Description Conditions Min Typ Max Units Resistance pin-to-pin through P2[4], AGL0, DSM INP, AGL1, P2[5][52, 54] VDDA = 3.0 V – 1500 2200  VDDA = 1.71 V – 1200 1700  Resistance pin-to-pin through P2[3], amuxbusL, P2[4][52, 54] VDDA = 3.0 V – 700 1100  VDDA = 1.71 V – 600 900  Min Typ Max Units 106 – – dB – 26 – MHz Table 11-32. Analog Globals AC Specifications Parameter Description Conditions Inter-pair crosstalk for analog routes[53] BWag Analog globals 3 db bandwidth[53] VDDA = 3.0 V, 25 °C Notes 52. Based on device characterization (Not production tested). 53. Pin P6[4] to del-sig ADC input; calculated, not measured. 54. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended. Document Number: 001-84932 Rev. *H Page 96 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.6 Comparator Table 11-33. Comparator DC Specifications[55] Parameter Description Conditions Input offset voltage in fast mode Factory trim, Vdda > 2.7 V, Vin  0.5 V Input offset voltage in slow mode Factory trim, Vin  0.5 V VOS Min – Max Units 10 mV – 9 mV – 4 mV – – 4 mV – ±12 – mV – 63 85 µV/°C – 15 20 – 10 32 mV High current / fast mode VSSA – VDDA V Low current / slow mode VSSA – VDDA V Ultra low power mode Input offset voltage in fast mode[56] Custom trim – Input offset voltage in slow mode[56] Custom trim VOS Input offset voltage in ultra low power mode TCVos Temperature coefficient, input offset VCM = VDDA / 2, fast mode voltage VCM = VDDA / 2, slow mode VHYST Hysteresis Hysteresis enable mode VICM Input common mode voltage VOS Typ VSSA – VDDA – 1.15 V CMRR Common mode rejection ratio – 50 – dB ICMP High current mode/fast mode – – 400 µA Low current mode/slow mode – – 100 µA Ultra low power mode – 6 – µA Min Typ Max Units Table 11-34. Comparator AC Specifications[55] Parameter TRESP Description Conditions Response time, high current mode[56] 50 mV overdrive, measured pin-to-pin – 75 110 ns Response time, low current mode[56] 50 mV overdrive, measured pin-to-pin – 155 200 ns Response time, ultra low power mode[56] 50 mV overdrive, measured pin-to-pin – 55 – µs Notes 55. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 56. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 97 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.7 Current Digital-to-analog Converter (IDAC) All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 11 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-35. IDAC DC Specifications Parameter Description Conditions Min Typ Max Units – – 8 bits Range = 2.04 mA, code = 255, VDDA  2.7 V, Rload = 600  – 2.04 – mA Range = 2.04 mA, High mode, code = 255, VDDA  2.7 V, Rload = 300  – 2.04 – mA Range = 255 µA, code = 255, Rload = 600  – 255 – µA Range = 31.875 µA, code = 255, Rload = 600  – 31.875 – µA – – Yes Resolution IOUT Output current at code = 255 Monotonicity Ezs Zero scale error Eg Gain error TC_Eg INL Range = 2.04 mA – 0 ±1 LSB – – ±2.5 % Range = 255 µA – – ±2.5 % Range = 31.875 µA – – ±3.5 % Temperature coefficient of gain error Range = 2.04 mA – – 0.045 % / °C Range = 255 µA – – 0.045 % / °C Range = 31.875 µA – – 0.05 % / °C Integral nonlinearity Sink mode, range = 255 µA, Codes 8–255, Rload = 2.4 k, Cload = 15 pF – ±0.9 ±1 LSB Source mode, range = 255 µA, Codes 8–255, Rload = 2.4 k, Cload = 15 pF – ±1.2 ±1.6 LSB Source mode, range = 31.875 µA, Codes 8–255, Rload = 20 kΩ, Cload = 15 pF[57] – ±0.9 ±2 LSB Sink mode, range = 31.875 µA, Codes 8–255, Rload = 20 kΩ, Cload = 15 pF[57] – ±0.9 ±2 LSB Source mode, range = 2.04 mA, Codes 8–255, Rload = 600 Ω, Cload = 15 pF[57] – ±0.9 ±2 LSB Sink mode, range = 2.04 mA, Codes 8–255, Rload = 600 Ω, Cload = 15 pF[57] – ±0.6 ±1 LSB Notes 57. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 98 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-35. IDAC DC Specifications (continued) Parameter DNL Description Differential nonlinearity Conditions Min Typ Max Units Sink mode, range = 255 µA, Rload = 2.4 k, Cload = 15 pF – ±0.3 ±1 LSB Source mode, range = 255 µA, Rload = 2.4 k, Cload = 15 pF – ±0.3 ±1 LSB Source mode, range = 31.875 µA, Rload = 20 kΩ, Cload = 15 pF[58] – ±0.2 ±1 LSB Sink mode, range = 31.875 µA, Rload = 20 kΩ, Cload = 15 pF[58] – ±0.2 ±1 LSB Source mode, range = 2.0 4 mA, Rload = 600 Ω, Cload = 15 pF[58] – ±0.2 ±1 LSB Sink mode, range = 2.0 4 mA, Rload = 600 Ω, Cload = 15 pF[58] – ±0.2 ±1 LSB Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current, Rload to VDDA or Rload to VSSA, VDIFF from VDDA 1 – – V IDD Operating current, code = 0 Slow mode, source mode, range = 31.875 µA – 44 100 µA Slow mode, source mode, range = 255 µA, – 33 100 µA Slow mode, source mode, range = 2.04 mA – 33 100 µA Slow mode, sink mode, range = 31.875 µA – 36 100 µA Slow mode, sink mode, range = 255 µA – 33 100 µA Slow mode, sink mode, range = 2.04 mA – 33 100 µA Fast mode, source mode, range = 31.875 µA – 310 500 µA Fast mode, source mode, range = 255 µA – 305 500 µA Fast mode, source mode, range = 2.04 mA – 305 500 µA Fast mode, sink mode, range = 31.875 µA – 310 500 µA Fast mode, sink mode, range = 255 µA – 300 500 µA Fast mode, sink mode, range = 2.04 mA – 300 500 µA Note 58. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 99 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-43. IDAC INL vs Input Code, Range = 255 µA, Sink Mode 1 1 0.5 0.5 INL, L LSB INL, L LSB Figure 11-42. IDAC INL vs Input Code, Range = 255 µA, Source Mode 0 0 -0.5 -0.5 -1 -1 0 32 64 96 128 160 192 224 256 0 32 64 96 Code, 8-bit Figure 11-44. IDAC DNL vs Input Code, Range = 255 µA, Source Mode 0.25 DNL, LSB 0.25 DNL, LSB 0.5 0 -0.25 -0.5 -0.5 64 96 128 160 192 224 0 256 32 64 224 256 96 128 160 192 224 256 Code, 8-bit Code, 8-bit Figure 11-46. IDAC INL vs Temperature, Range = 255 µA, Fast Mode Figure 11-47. IDAC DNL vs Temperature, Range = 255 µA, Fast Mode 1 0.5 Source mode 0.75 Source mode 0.4 Sink mode Sink mode DNL, LSB INL, L LSB 192 0 -0.25 32 160 Figure 11-45. IDAC DNL vs Input Code, Range = 255 µA, Sink Mode 0.5 0 128 Code, 8-bit 05 0.5 0.3 0.2 0.25 0.1 0 0 -40 -20 0 20 40 Temperature, °C Document Number: 001-84932 Rev. *H 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Page 100 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-49. IDAC Full Scale Error vs Temperature, Range = 255 µA, Sink Mode 1.5 1.5 1 1 Full Scale Error, % Full Scale Error, % Figure 11-48. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode 0.5 0 -0.5 0.5 0 -0.5 -1 -1 -1.5 -1.5 -40 -20 0 20 40 60 80 -40 100 -20 0 Figure 11-50. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode 40 60 80 100 Figure 11-51. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Sink Mode 350 350 300 300 Operating C Current, μA Operating C Current, μA 20 Temperature, °C Temperature, °C 250 Fast Mode 200 Slow Mode 150 100 50 250 Fast Mode 200 Slow Mode 150 100 50 0 0 -40 -20 0 20 40 Temperature, °C Document Number: 001-84932 Rev. *H 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Page 101 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-36. IDAC AC Specifications[59] Parameter FDAC TSETTLE Description Update rate Settling time to 0.5 LSB Conditions Range = 31.875 µA, full scale transition, fast mode, 600  15-pF load Range = 255 µA, full scale transition, fast mode, 600  15-pF load Range = 255 µA, source mode, fast mode, Vdda = 5 V, 10 kHz Current noise Figure 11-52. IDAC Step Response, Codes 0x40 - 0xC0, 255-µA Mode, Source Mode, Fast Mode, VDDAa = 5 V Min – – Typ – – Max 8 125 Units Msps ns – – 125 ns – 340 – pA/sqrtHz Figure 11-53. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, Fast Mode, VDDA = 5 V 134 250 132 200 Iout, μA Iout, μA 130 150 100 128 126 124 50 122 120 0 0 0.5 1 1.5 0 2 0.5 1 1.5 2 Time, μs Time, μs Figure 11-54. IDAC PSRR vs Frequency Figure 11-55. IDAC Current Noise, 255 µA Mode, Source Mode, Fast Mode, VDDA = 5 V 60 10000 40 1000 30 pA / sq qrtHz PSRR, dB P 50 20 10 100 10 0 0.1 1 10 100 1000 10000 Frequency, kHz 255 ȝA, code 0x7F 1 255 ȝA, code 0xFF 0.01 0.1 1 Frequency, kHz 10 100 Note 59. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 102 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.8 Voltage Digital to Analog Converter (VDAC) See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-37. VDAC DC Specifications Parameter Description Conditions Min Resolution 1 V scale 8 – bits ±2.1 ±2.5 LSB – ±2.1 ±2.5 LSB – ±0.3 ±1 LSB – ±0.3 ±1 LSB – 4 – k 16 – k 1.02 – V 4.08 – V – Yes – INL4 Integral nonlinearity[60] 4 V scale DNL1 Differential nonlinearity 1 V scale DNL4 Differential nonlinearity[60] 4 V scale Rout Output resistance 1 V scale 4 V scale – VOUT Output voltage range, code = 255 1 V scale – – – VOS Zero scale error Eg Gain error TC_Eg IDD Operating current[60] – 0 ±0.9 LSB 1 V scale – – ±2.5 % 4 V scale – – ±2.5 % Temperature coefficient, gain error 1 V scale – – 0.03 %FSR / °C 4 V scale – – 0.03 %FSR / °C Slow mode – – 100 µA Fast mode – – 500 µA Figure 11-56. VDAC INL vs Input Code, 1 V Mode Figure 11-57. VDAC DNL vs Input Code, 1 V Mode 1 0.5 0.5 0.25 DNL, LSB INL, L LSB Units – Integral nonlinearity 4 V scale, Vdda = 5 V Max – INL1 Monotonicity Typ 0 -0.5 0 -0.25 -1 -0.5 0 32 64 96 128 160 192 Code, 8-bit 224 256 0 32 64 96 128 160 192 224 256 Code, 8-bit Note 60. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 103 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-58. VDAC INL vs Temperature, 1 V Mode Figure 11-59. VDAC DNL vs Temperature, 1 V Mode 1 0.5 0.4 DNL, LSB INL, L LSB 0.75 05 0.5 0.3 0.2 0.25 0.1 0 0 -40 -20 0 20 40 60 80 100 -40 -20 0 20 Temperature, °C 60 80 100 Figure 11-61. VDAC Full Scale Error vs Temperature, 4 V Mode 1 2 0.75 1.5 Full Scale Error, % Full Scale Error, % Figure 11-60. VDAC Full Scale Error vs Temperature, 1 V Mode 05 0.5 0.25 1 0.5 0 0 -40 -20 0 20 40 60 80 -40 100 -20 0 20 40 60 80 100 Temperature, °C Temperature, °C Figure 11-62. VDAC Operating Current vs Temperature, 1V Mode, Slow Mode Figure 11-63. VDAC Operating Current vs Temperature, 1 V Mode, Fast Mode 50 400 40 Operating C Current, μA Operating C Current, μA 40 Temperature, °C 30 20 10 0 300 200 100 0 -40 -20 0 20 40 Temperature, °C Document Number: 001-84932 Rev. *H 60 80 100 -40 -20 0 20 40 60 80 100 Temperature, °C Page 104 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-38. VDAC AC Specifications[61] Parameter FDAC Description Conditions Update rate Min Typ Max Units 1 V scale – – 1000 ksps 4 V scale – – 250 ksps – 0.45 1 µs TsettleP Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF 75% 4 V scale, Cload = 15 pF – 0.8 3.2 µs TsettleN Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF 25% – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.7 3 µs Range = 1 V, fast mode, Vdda = 5 V, 10 kHz – 750 – nV/sqrtHz Voltage noise Figure 11-64. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, Fast Mode, Vdda = 5 V Figure 11-65. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, Fast Mode, Vdda = 5 V 0.54 1 0.75 Voutt, V Voutt, V 0.52 05 0.5 0.5 0.25 0.48 0 0 0.5 1 1.5 0 2 0.5 1 1.5 2 Time, μs Time, μs Figure 11-66. VDAC PSRR vs Frequency Figure 11-67. VDAC Voltage Noise, 1 V Mode, Fast Mode, Vdda = 5 V 50 100000 10000 30 nV/sq qrtHz PSRR, dB P 40 20 10 0 1000 100 0.1 1 10 Frequency, kHz 4 V, code 0x7F 100 4 V, code 0xFF 1000 10 0.01 0.1 1 10 100 Frequency, kHz Note 61. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 105 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.9 Mixer The mixer is created using a SC/CT analog block; see the Mixer component datasheet in PSoC Creator for full electrical specifications and APIs. Table 11-39. Mixer DC Specifications Parameter VOS G Description Min Typ Max Units – – 15 mV Quiescent current – 0.9 2 mA Gain – 0 – dB Min Typ Max Units – – 4 MHz Input offset voltage Conditions High power mode, VIN = 1.024 V, VREF = 1.024 V Table 11-40. Mixer AC Specifications[62] Parameter Description fLO Local oscillator frequency Conditions Down mixer mode fin Input signal frequency Down mixer mode – – 14 MHz fLO Local oscillator frequency Up mixer mode – – 1 MHz fin Input signal frequency Up mixer mode – – 1 MHz SR Slew rate 3 – – V/µs 11.5.10 Transimpedance Amplifier The TIA is created using a SC/CT analog block; see the TIA component datasheet in PSoC Creator for full electrical specifications and APIs. Table 11-41. Transimpedance Amplifier (TIA) DC Specifications Parameter VIOFF Rconv Description Conditions Min Typ Max Units – – 10 mV R = 20K; 40 pF load –25 – +35 % R = 30K; 40 pF load –25 – +35 % R = 40K; 40 pF load –25 – +35 % R = 80K; 40 pF load –25 – +35 % R = 120K; 40 pF load –25 – +35 % R = 250K; 40 pF load –25 – +35 % R= 500K; 40 pF load –25 – +35 % R = 1M; 40 pF load –25 – +35 % – 1.1 2 mA Min Typ Max Units R = 20K; –40 pF load 1200 – – kHz R = 120K; –40 pF load 240 – – kHz R = 1M; –40 pF load 25 – – kHz Input offset voltage Conversion Quiescent resistance[63] current[62] Table 11-42. Transimpedance Amplifier (TIA) AC Specifications[62] Parameter BW Description Input bandwidth (–3 dB) Conditions Notes 62. Based on device characterization (Not production tested). 63. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component datasheets. External precision resistors can also be used. Document Number: 001-84932 Rev. *H Page 106 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.11 Programmable Gain Amplifier The PGA is created using a SC/CT analog block; see the PGA component datasheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, operating conditions are:  Operating temperature = 25 °C for typical values  Unless otherwise specified, all charts and graphs show typical values. Table 11-43. PGA DC Specifications Parameter Description Conditions Min Typ Max Units Vssa – Vdda V Power mode = high, gain = 1 – – 10 mV Input offset voltage drift with Power mode = high, temperature gain = 1 – – ±30 µV/°C Ge1 Gain error, gain = 1 – – ±0.15 % Ge16 Gain error, gain = 16 – – ±2.5 % Vin Input voltage range Power mode = minimum Vos Input offset voltage TCVos Ge50 Gain error, gain = 50 Vonl DC output nonlinearity – – ±5 % – – ±0.01 % of FSR Cin Input capacitance Voh Output voltage swing Power mode = high, gain = 1, Rload = 100 k to VDDA / 2 – – 7 pF VDDA – 0.15 – – V Vol Output voltage swing Power mode = high, gain = 1, Rload = 100 k to VDDA / 2 – – VSSA + 0.15 V Vsrc Output voltage under load Iload = 250 µA, Vdda  2.7V, power mode = high – – 300 mV Idd Operating current[64] Power mode = high – 1.5 1.65 mA PSRR Power supply rejection ratio 48 – – dB Gain = 1 Figure 11-68. PGA Voffset Histogram, 4096 samples/ 1024 parts Note 64. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 107 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-44. PGA AC Specifications[65] Parameter BW1 Description Conditions –3 dB bandwidth Min Typ Max Units 6.7 8 – MHz TA ≤ 105 °C 6 8 – Power mode = high, gain = 1, input = 100 mV peak-to-peak SR1 Slew rate Power mode = high, gain = 1, 20% to 80% 3 – – V/µs en Input noise density Power mode = high, Vdda = 5 V, at 100 kHz – 43 – nV/sqrtHz Figure 11-69. Bandwidth vs. Temperature, at Different Gain Settings, Power Mode = High Figure 11-70. Noise vs. Frequency, Vdda = 5 V, Power Mode = High 1000 nV/sq qrtHz BW,, MHz 10 1 100 0.1 -40 -20 0 20 40 60 80 100 Temperature, °C Gain = 1 Gain = 24 10 0.01 Gain = 48 0.1 1 10 Frequency, kHz 100 1000 Note 65. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 108 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.5.12 Temperature Sensor Table 11-45. Temperature Sensor Specifications Parameter Description Temp sensor accuracy Conditions Min Typ Max Units – ±5 – °C Conditions Min Typ Max Units Range: –40 °C to +105 °C 11.5.13 LCD Direct Drive Table 11-46. LCD Direct Drive DC Specifications[66] Parameter Description ICC LCD Block (no glass) Device sleep mode with wakeup at 400Hz rate to refresh LCD, bus, clock = 3MHz, Vddio = Vdda = 3V, 8 commons, 16 segments, 1/5 duty cycle, 40 Hz frame rate, no glass connected – 81 – A ICC_SEG Current per segment driver Strong drive mode – 260 – µA VBIAS LCD bias range (VBIAS refers to the VDDA  3 V and VDDA  VBIAS main output voltage(V0) of LCD DAC) 2 – 5 V IOUT LCD bias step size VDDA  3 V and VDDA  VBIAS – 9.1 × VDDA – mV LCD capacitance per segment/ common driver Drivers may be combined – 500 5000 pF Maximum segment DC offset VDDA 3 V and VDDA  VBIAS – – 20 mV Output drive current per segment driver) VDDIO = 5.5 V, strong drive mode 355 – 710 µA Table 11-47. LCD Direct Drive AC Specifications[66] Parameter Description fLCD LCD frame rate Conditions Min 10 Typ 50 Max 150 Units Hz Note 66. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 109 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.6 Digital Peripherals Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.6.1 Timer The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for more information, see the Timer component datasheet in PSoC Creator. Table 11-48. Timer DC Specifications[67] Parameter Description Block current consumption Conditions 16-bit timer, at listed input clock frequency 3 MHz 12 MHz 48 MHz 80 MHz Min – Typ – Max – Units µA – – – – 15 60 260 360 – – – – µA µA µA µA Min DC 15 30 15 15 30 15 30 Typ – – – – – – – – Max 80.01 – – – – – – – Units MHz ns ns ns ns ns ns ns Table 11-49. Timer AC Specifications[67] Parameter Description Operating frequency Capture pulse width (Internal)[68] Capture pulse width (external) Timer resolution[68] Enable pulse width[68] Enable pulse width (external) Reset pulse width[68] Reset pulse width (external) Conditions Notes 67. Based on device characterization (Not production tested). 68. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. Document Number: 001-84932 Rev. *H Page 110 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.6.2 Counter The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in UDBs; for more information, see the Counter component datasheet in PSoC Creator. Table 11-50. Counter DC Specifications[69] Parameter Description Block current consumption Conditions Min Typ Max Units 16-bit counter, at listed input clock frequency – – – µA 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 80 MHz – 360 – µA Min DC 15 15 15 30 15 30 15 30 Typ – – – – Max 80.01 – – – – – – – – – – – Units MHz ns ns ns ns ns ns ns ns Table 11-51. Counter AC Specifications[69] Parameter Description Operating frequency Capture pulse[70] Resolution[70] Pulse width[70] Pulse width (external) Enable pulse width[70] Enable pulse width (external) Reset pulse width[70] Reset pulse width (external) Conditions Notes 69. Based on device characterization (Not production tested). 70. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. Document Number: 001-84932 Rev. *H Page 111 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.6.3 Pulse Width Modulation The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented in UDBs; for more information, see the PWM component datasheet in PSoC Creator. Table 11-52. PWM DC Specifications[71] Parameter Description Block current consumption Conditions Min 16-bit PWM, at listed input clock frequency Typ Max Units – – – µA 3 MHz – 15 – µA 12 MHz – 60 – µA 48 MHz – 260 – µA 80 MHz – 360 – µA Table 11-53. PWM AC Specifications[71] Parameter Description Conditions Min Typ Max Units Operating frequency DC – 80.01 MHz Pulse width[72] 15 – – ns Pulse width (external) 30 – – ns Kill pulse width[72] 15 – – ns Kill pulse width (external) 30 – – ns Enable pulse width[72] 15 – – ns Enable pulse width (external) 30 – – ns Reset pulse width[72] 15 – – ns Reset pulse width (external) 30 – – ns Conditions Enabled, configured for 100 kbps Enabled, configured for 400 kbps Min – – Typ – – Max 250 260 Units µA µA Conditions Min – Typ – Max 1 Units Mbps Conditions Min Typ Max Units – – 200 µA 11.6.4 I2C Table 11-54. Fixed I2C DC Specifications[71] Parameter Description Block current consumption Table 11-55. Fixed I2C AC Specifications[73] Parameter Description Bit rate 11.6.5 Controller Area Network Table 11-56. CAN DC Specifications[71, 74] Parameter IDD Description Block current consumption Table 11-57. CAN AC Specifications[71, 74] Parameter Description Bit rate Conditions Minimum 8 MHz clock Min – Typ – Max 1 Units Mbit Notes 71. Based on device characterization (Not production tested). 72. For correct operation, the minimum Timer/Counter/PWM input pulse width is the period of bus clock. 73. Rise/fall time matching (TR) not guaranteed, see Table 11-16 on page 83. 74. Refer to ISO 11898 specification for details. Document Number: 001-84932 Rev. *H Page 112 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.6.6 Digital Filter Block Table 11-58. DFB DC Specifications[75] Parameter Description DFB operating current Conditions Min Typ Max Units – 0.16 0.27 mA 1 MHz (13.4 ksps) – 0.33 0.53 mA 10 MHz (134 ksps) – 3.3 5.3 mA 48 MHz (644 ksps) – 15.7 25.5 mA 80 MHz (1.07 Msps) – 26.0 42.5 mA Min Typ Max Units DC – 80.01 MHz 64-tap FIR at FDFB 500 kHz (6.7 ksps) Table 11-59. DFB AC Specifications[75] Parameter FDFB Description Conditions DFB operating frequency 11.6.7 USB Table 11-60. USB DC Specifications Parameter Min Typ Max Units USB configured, USB regulator enabled 4.35 – 5.25 V VUSB_3.3 USB configured, USB regulator bypassed 3.15 – 3.6 V VUSB_3 USB configured, USB regulator bypassed[76] 2.85 – 3.6 V – 10 – mA – 8 – mA – 0.5 – mA VDDD = 5 V, disconnected from USB host – 0.3 – mA VDDD = 3.3 V, connected to USB host, PICU configured to wake on USB resume signal – 0.5 – mA VDDD = 3.3 V, disconnected from USB host – 0.3 – mA VUSB_5 Description Device supply for USB operation Conditions IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz mode, bus clock and IMO = 24 MHz V DDD = 3.3 V, FCPU = 1.5 MHz IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB mode host, PICU configured to wake on USB resume signal Note 75. Rise/fall time matching (TR) not guaranteed, see Table 11-16 on page 83. Document Number: 001-84932 Rev. *H Page 113 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.6.8 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-61. UDB AC Specifications[76] Parameter Description Conditions Min Typ Max Units FMAX_TIMER Maximum frequency of 16-bit timer in a UDB pair – – 67.01 MHz FMAX_ADDER Maximum frequency of 16-bit adder in a UDB pair – – 67.01 MHz – – 67.01 MHz – – 67.01 MHz Datapath Performance FMAX_CRC Maximum frequency of 16-bit CRC/PRS in a UDB pair PLD Performance FMAX_PLD Maximum frequency of a two-pass PLD function in a UDB pair Clock to Output Performance tCLK_OUT Propagation delay for clock in to data 25 °C, VDDD  2.7 V out, see Figure 11-71. – 20 25 ns tCLK_OUT Propagation delay for clock in to data Worst-case placement, routing, out, see Figure 11-71. and pin selection – – 55 ns Figure 11-71. Clock to Output Performance Note 76. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 114 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.7 Memory Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.7.1 Flash Table 11-62. Flash DC Specifications Parameter Description Erase and program voltage Conditions VDDD pin Min Typ Max Units 1.71 – 5.5 V Min Typ Max Units Table 11-63. Flash AC Specifications Parameter Description Conditions TWRITE Row write time (erase + program) – 15 20 ms TERASE Row erase time – 10 13 ms Row program time – 5 7 ms Bulk erase time (256 KB) – – 140 ms – – 15 ms – 5 7.5 seconds 20 – – years Ambient temp. TA  85 °C, 10 K erase/program cycles 10 – – Ambient temp. TA ≤ 105 °C, 10 K erase/program cycles, ≤ one year at TA ≥ 75 °C [78] 10 – – Min Typ Max Units 1.71 – 5.5 V Min Typ Max Units Single row erase/write cycle time – 10 20 ms EEPROM data retention time, retention Ambient temp, TA  25 °C, period measured from last erase cycle 1M erase/program cycles 20 – – years Ambient temp, TA  55 °C, 100K erase/program cycles 20 – – Ambient temp. TA 85 °C, 10K erase/program cycles 10 – – Ambient temp. TA ≤ 105 °C, 10K erase/program cycles, ≤ one year at TA ≥75 °C [78] 10 – – TBULK Sector erase time (16 KB) TPROG Total device programming time No overhead[77] Flash data retention time, retention Ambient temp. TA  55 °C, period measured from last erase cycle 100 K erase/program cycles 11.7.2 EEPROM Table 11-64. EEPROM DC Specifications Parameter Description Conditions Erase and program voltage Table 11-65. EEPROM AC Specifications Parameter TWRITE Description Conditions Notes 77. See PSoC 5 Device Programming Specifications for a description of a low-overhead method of programming PSoC 5 flash. 78. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C ambient temperature range. Contact customercare@cypress.com. Document Number: 001-84932 Rev. *H Page 115 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.7.3 Nonvolatile Latches (NVL) Table 11-66. NVL DC Specifications Parameter Description Erase and program voltage Conditions Min Typ Max Units 1.71 – 5.5 V Min Typ Max Units Programmed at 25 °C 1K – – program/ erase cycles Programmed at 0 °C to 70 °C 100 – – program/ erase cycles Ambient temp. TA ≤ 55 °C 20 – – years Ambient temp. TA ≤ 85 °C 10 – – Ambient temp. TA ≤ 105 °C, ≤ one year at TA ≥ 75 °C [79] 10 – – Min Typ Max Units 1.2 – – V Min Typ Max Units DC – 80.01 MHz VDDD pin Table 11-67. NVL AC Specifications Parameter Description NVL endurance NVL data retention time Conditions 11.7.4 SRAM Table 11-68. SRAM DC Specifications Parameter VSRAM Description Conditions SRAM retention voltage[80] Table 11-69. SRAM AC Specifications Parameter FSRAM Description SRAM operating frequency Conditions Notes 79. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +105 °C ambient temperature range. Contact customercare@cypress.com. 80. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 116 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.7.5 External Memory Interface Figure 11-72. Asynchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Addr EM_CE EM_WE EM_OE Twr_setup Trd_hold Trd_setup EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-70. Asynchronous Write and Read Timing Specifications[81] Parameter Description Fbus_clock Bus clock frequency[82] Tbus_clock Bus clock period[83] Conditions Min Typ Max Units – – 33 MHz 30.3 – – ns Tbus_clock – 10 – – ns Time that EM_data must be valid before rising edge of EM_OE 5 – – ns Time that EM_data must be valid after rising edge of EM_OE 5 – – ns Twr_Setup Time from EM_data valid to rising edge of EM_WE and EM_CE Trd_setup Trd_hold Notes 81. Based on device characterization (Not production tested). 82. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 75. 83. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-84932 Rev. *H Page 117 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 11-73. Synchronous Write and Read Cycle Timing, No Wait States Tbus_clock Bus Clock EM_Clock EM_Addr EM_CE EM_ADSC EM_WE EM_OE Twr_setup Trd_hold Trd_setup EM_Data Write Cycle Read Cycle Minimum of 4 bus clock cycles between successive EMIF accesses Table 11-71. Synchronous Write and Read Timing Specifications[84] Parameter Description Fbus_clock Bus clock frequency[85] Tbus_clock Bus clock period [86] Conditions Min Typ Max Units – – 33 MHz 30.3 – – ns Tbus_clock – 10 – – ns Time that EM_data must be valid before rising edge of EM_OE 5 – – ns Time that EM_data must be valid after rising edge of EM_OE 5 – – ns Twr_Setup Time from EM_data valid to rising edge of EM_Clock Trd_setup Trd_hold Notes 84. Based on device characterization (Not production tested). 85. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 75. 86. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency. Document Number: 001-84932 Rev. *H Page 118 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.8 PSoC System Resources Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, VDDD and VDDA must be  2.0 V. Brown out detect is not available in externally regulated mode. Table 11-72. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications Parameter Description Min Typ Max Units 1.64 – 1.68 V 1.62 – 1.66 V Min Typ Max Units – – 0.5 µs – 5 – V/sec Min Typ Max Units LVI_A/D_SEL[3:0] = 0000b 1.68 1.73 1.77 V LVI_A/D_SEL[3:0] = 0001b 1.89 1.95 2.01 V LVI_A/D_SEL[3:0] = 0010b 2.14 2.20 2.27 V PRESR Rising trip voltage PRESF Falling trip voltage Conditions Factory trim Table 11-73. Power-On-Reset (POR) with Brown Out AC Specifications[87] Parameter Description Conditions PRES_TR[88] Response time VDDD/VDDA droop rate Sleep mode 11.8.2 Voltage Monitors Table 11-74. Voltage Monitors DC Specifications Parameter LVI Description Conditions Trip voltage LVI_A/D_SEL[3:0] = 0011b 2.38 2.45 2.53 V LVI_A/D_SEL[3:0] = 0100b 2.62 2.71 2.79 V LVI_A/D_SEL[3:0] = 0101b 2.87 2.95 3.04 V LVI_A/D_SEL[3:0] = 0110b 3.11 3.21 3.31 V LVI_A/D_SEL[3:0] = 0111b 3.35 3.46 3.56 V LVI_A/D_SEL[3:0] = 1000b 3.59 3.70 3.81 V LVI_A/D_SEL[3:0] = 1001b 3.84 3.95 4.07 V LVI_A/D_SEL[3:0] = 1010b 4.08 4.20 4.33 V LVI_A/D_SEL[3:0] = 1011b 4.32 4.45 4.59 V LVI_A/D_SEL[3:0] = 1100b 4.56 4.70 4.84 V LVI_A/D_SEL[3:0] = 1101b 4.83 4.98 5.13 V LVI_A/D_SEL[3:0] = 1110b 5.05 5.21 5.37 V LVI_A/D_SEL[3:0] = 1111b HVI Trip voltage 5.30 5.47 5.63 V 5.57 5.75 5.92 V Min Typ Max Units – – 1 µs Table 11-75. Voltage Monitors AC Specifications Parameter LVI_tr[88] Description Response time Conditions Notes 87. Based on device characterization (Not production tested). 88. This value is calculated, not measured. Document Number: 001-84932 Rev. *H Page 119 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.8.3 Interrupt Controller Table 11-76. Interrupt Controller AC Specifications Parameter Description Conditions Min Typ Max Units Delay from interrupt signal input to ISR code execution from main line code[89] – – 12 Tcy CPU Delay from interrupt signal input to ISR code execution from ISR code (tail-chaining)[89] – – 6 Tcy CPU 11.8.4 JTAG Interface Figure 11-74. JTAG Interface Timing (1/f_TCK) TCK T_TDI_setup T_TDI_hold TDI T_TDO_valid T_TDO_hold TDO T_TMS_setup T_TMS_hold TMS Table 11-77. JTAG Interface AC Specifications[90] Parameter f_TCK Description TCK frequency Conditions 3.3 V  VDDD  5 V 1.71 V  VDDD < 3.3 V T_TDI_setup TDI setup before TCK high T_TMS_setup TMS setup before TCK high T_TDI_hold TDI, TMS hold after TCK high T = 1/f_TCK max Min Typ Max Units – – 12[91] MHz MHz ns – – 7[91] (T/10) – 5 – – T/4 – – T/4 – – T_TDO_valid TCK low to TDO valid T = 1/f_TCK max – – 2T/5 T_TDO_hold TDO hold after TCK high T = 1/f_TCK max T/4 – – T_nTRST Minimum nTRST pulse width f_TCK = 2 MHz 8 – – ns Notes 89. ARM Cortex-M3 NVIC spec. Visit www.arm.com for detailed documentation about the Cortex-M3 CPU. 90. Based on device characterization (Not production tested). 91. f_TCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-84932 Rev. *H Page 120 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.8.5 SWD Interface Figure 11-75. SWD Interface Timing (1/f_S W D C K ) SW DCK T _SW D I_setup T_S W D I_hold S W D IO (P S oC input) T _S W D O _valid T_SW D O _hold S W D IO (P S oC output) Table 11-78. SWD Interface AC Specifications[92] Parameter f_SWDCK Description SWDCLK frequency Conditions 3.3 V  VDDD  5 V Min Typ Max Units – – 12[93] MHz MHz MHz 1.71 V  VDDD < 3.3 V – – 7[93] 1.71 V  VDDD < 3.3 V, SWD over USBIO pins – – 5.5[93] T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T/4 – – T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T/4 – – T = 1/f_SWDCK max – – T/2 T_SWDO_hold SWDIO output hold after SWDCK high T = 1/f_SWDCK max 1 – – ns Min Typ Max Units T_SWDO_valid SWDCK high to SWDIO output 11.8.6 TPIU Interface Table 11-79. TPIU Interface AC Specifications[92] Parameter Description Conditions [94] TRACEPORT (TRACECLK) frequency – – 33 MHz SWV bit rate – – 33[94] Mbit Notes 92. Based on device characterization (Not production tested). 93. f_SWDCK must also be no more than 1/3 CPU clock frequency. 94. TRACEPORT signal frequency and bit rate are limited by GPIO output frequency, see Table 11-10 on page 76. Document Number: 001-84932 Rev. *H Page 121 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.9 Clocking Specifications are valid for –40 °C  TA  105 °C and TJ  120 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Unless otherwise specified, all charts and graphs show typical values 11.9.1 Internal Main Oscillator Table 11-80. IMO DC Specifications[95] Parameter Description Conditions Min Typ Max Units 74.7 MHz – – 730 µA 62.6 MHz – – 600 µA Supply current 48 MHz Icc_imo – – 500 µA – – 500 µA 24 MHz – non-USB mode – – 300 µA 12 MHz – – 200 µA 6 MHz – – 180 µA 3 MHz – – 150 µA 24 MHz – USB mode With oscillator locking to USB bus Figure 11-76. IMO Current vs. Frequency 700 600 Curren nt, μA 500 400 300 200 100 0 0 10 20 30 40 50 Frequency, MHz 60 70 80 Note 95. Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 122 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 11-81. IMO AC Specifications Parameter Description Conditions Min IMO frequency stability (with factory trim) 74.7 MHz –7 62.6 MHz –7 48 MHz –5 24 MHz – non-USB mode –4 24 MHz – USB mode With oscillator locking to USB bus –0.25 FIMO[96] 12 MHz –3 6 MHz –2 3 MHz 0 °C to 70 °C –1 –40 °C to 105 °C –1.5 3-MHz frequency stability after typical Typical (non-optimized) board layout and – PCB assembly post-reflow 250 °C solder reflow. Device may be calibrated after assembly to improve performance. From enable (during normal system operation) – Tstart_imo Startup time[97] Jitter (peak to peak)[97] Jp-p F = 24 MHz – F = 3 MHz – Jitter (long term)[98] F = 24 MHz – Jperiod F = 3 MHz – Figure 11-77. IMO Frequency Variation vs. Temperature Typ Max Units – – – – – – – – – ±2% 7 7 5 4 0.25 3 2 1 1.5 – % % % % % % % % % % – 13 µs 0.9 1.6 – – ns ns 0.9 12 – – ns ns Figure 11-78. IMO Frequency Variation vs. VCC 0.5 62.6 MHz 24 MHz 3 MHz % Variation 0.25 0 -0.25 -0.5 -40 -20 0 20 40 60 Temperature, °C 80 100 Notes 96. FIMO is measured after packaging, and thus accounts for substrate and die attach stresses. 97. Based on device characterization (Not production tested). 98. Based on device characterization (Not production tested). USBIO pins tied to ground (VSSD). Document Number: 001-84932 Rev. *H Page 123 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.9.2 Internal Low-Speed Oscillator Table 11-82. ILO DC Specifications Parameter Description Operating current Conditions [99] Min Typ Max Units FOUT = 1 kHz – – 1.7 µA FOUT = 33 kHz – – 2.6 µA FOUT = 100 kHz – – 2.6 µA Power down mode – – 15 nA Min Typ Max Units – – 2 ms 100 kHz 45 100 200 kHz 1 kHz 0.5 1 2 kHz ICC Leakage current[99] Table 11-83. ILO AC Specifications[100] Parameter Tstart_ilo Description Conditions Startup time, all frequencies Turbo mode ILO frequencies FILO Figure 11-79. ILO Frequency Variation vs. Temperature Figure 11-80. ILO Frequency Variation vs. VDD 20 50 10 % Variiation % Variation 25 0 100 kHz -25 0 100 kHz -10 1 kHz 1 kHz -20 -50 -40 -20 0 20 40 60 80 Temperature, °C 100 1.5 2.5 3.5 4.5 5.5 VDDD, V Notes 99. This value is calculated, not measured. 100.Based on device characterization (Not production tested). Document Number: 001-84932 Rev. *H Page 124 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 11.9.3 MHz External Crystal Oscillator For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. Table 11-84. MHzECO AC Specifications Parameter F Description Conditions Crystal frequency range Min Typ Max Units 4 – 25 MHz Min Typ Max Units – 0.25 1.0 µA – – 1 µW Min Typ Max Units – 32.768 – kHz – 1 – s Min Typ Max Units 11.9.4 kHz External Crystal Oscillator Table 11-85. kHzECO DC Specifications[101] Parameter Description ICC Operating current DL Drive level Conditions Low power mode; CL = 6 pF Table 11-86. kHzECO AC Specifications[101] Parameter Description F Frequency TON Startup time Conditions High power mode 11.9.5 External Clock Reference Table 11-87. External Clock Reference AC Specifications[101] Parameter Description Conditions External frequency range 0 – 33 MHz Input duty cycle range Measured at VDDIO/2 30 50 70 % Input edge rate VIL to VIH 0.5 – – V/ns 11.9.6 Phase-Locked Loop Table 11-88. PLL DC Specifications Parameter IDD Description PLL operating current Min Typ Max Units In = 3 MHz, Out = 80 MHz Conditions – 650 – µA In = 3 MHz, Out = 67 MHz – 400 – µA In = 3 MHz, Out = 24 MHz – 200 – µA Min Typ Max Units 1 – 48 MHz 1 – 3 MHz 24 – 80 MHz Table 11-89. PLL AC Specifications Parameter Fpllin Description PLL intermediate Fpllout Conditions PLL input frequency[102] frequency[103] PLL output frequency[102] Lock time at startup Jperiod-rms Jitter (rms)[101] Output of prescaler – – 250 µs – – 250 ps Notes 101.Based on device characterization (Not production tested). 102.This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 103.PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-84932 Rev. *H Page 125 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 12. Ordering Information In addition to the features listed in Table 12-1, every CY8C58LP device includes: up to 256 KB flash, 64 KB SRAM, 2 KB EEPROM, a precision on-chip voltage reference, precision oscillators, flash, ECC, DMA, a fixed function I2C, JTAG/SWD programming and debug, external memory interface, boost, and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C58LP derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details. Table 12-1. CY8C58LP Family with ARM Cortex-M3 CPU I/O[106] Digital CAN 2.0B SIO USBIO 0 100-TQFP 0x2E11F069 CY8C5868AXI-LP032 67 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E120069 CY8C5868AXI-LP035 67 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E123069 CY8C5868LTI-LP036 67 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 – – 46 38 8 0 68-QFN 0x2E124069 CY8C5868LTI-LP038 67 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E126069 CY8C5868LTI-LP039 67 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E127069 CY8C5867AXI-LP023 67 128 32 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 24 4 – – 70 62 8 0 100-TQFP 0x2E117069 CY8C5867AXI-LP024 67 128 32 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ – 72 62 8 2 100-TQFP 0x2E118069 CY8C5867LTI-LP025 67 128 32 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 24 4 – – 46 38 8 0 68-QFN 0x2E119069 CY8C5867LTI-LP028 67 128 32 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ – 48 38 8 2 68-QFN 0x2E11C069 CY8C5866AXI-LP020 67 64 16 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 20 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E114069 CY8C5866AXI-LP021 67 64 16 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 20 4 ✔ – 72 62 8 2 100-TQFP 0x2E115069 CY8C5866LTI-LP022 67 64 16 2 ✔ 1x20-bit Del-Sig 4 1x12-bit SAR 4 4 4 ✔ ✔ 20 4 ✔ – 48 38 8 2 68-QFN 0x2E116069 CY8C5888AXI-LP096 80 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E160069 CY8C5888AXQ-LP096 80 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 72 62 8 2 100-TQFP 0x2E160069 80 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E161069 CY8C5888LTQ-LP097 80 256 64 2 ✔ 1x20-bit Del-Sig 4 2x12-bit SAR 4 4 4 ✔ ✔ 24 4 ✔ ✔ 48 38 8 2 68-QFN 0x2E161069 CY8C5888LTI-LP097 GPIO FS USB – 70 62 8 TOTAL I/O 16-BIT TIMER/PWM – UDBS[105] 4 ✔ ✔ 24 4 CAPSENSE 4 DFB 4 COMPARATORS ✔ 1x20-bit Del-Sig 4 2x12-bit SAR DAC 2 ADCS EEPROM (KB) 67 256 64 FLASH (KB) CY8C5868AXI-LP031 Part Number CPU SPEED (MHZ) SRAM (KB) SC/CT ANALOG BLOCKS[104] OPAMPS Analog LCD SEGMENT DRIVE MCU Core Package JTAG ID[107] Notes 104.Analog blocks support a wide variety of functionality including TIA, PGA, and mixers. See Example Peripherals on page 39 for more information on how analog blocks can be used. 105.UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See Example Peripherals on page 39 for more information on how UDBs can be used. 106.The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See “I/O System and Routing” section on page 32 for details on the functionality of each of these types of I/O. 107.The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-84932 Rev. *H Page 126 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 12.1 Part Numbering Conventions PSoC 5LP devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-LPxxx  a: Architecture 3: PSoC 3  5: PSoC 5   b: Family group within architecture 2: CY8C52LP family 4: CY8C54LP family  6: CY8C56LP family  8: CY8C58LP family    c: Speed grade   6: 67 MHz 8: 80 MHz  d: Flash capacity 5: 32 KB  6: 64 KB  7: 128 KB  8: 256 KB   ef: Package code Two character alphanumeric AX: TQFP  LT: QFN  PV: SSOP  FN: CSP    g: Temperature Range C: Commercial I: Industrial  Q: Extended  A: Automotive    xxx: Peripheral set   Three character numeric No meaning is associated with these three characters Examples CY8C 5 8 8 8 AX/PV I - LPx x x Cypress Prefix 5: PSoC 5 8: CY8C58LP Family Architecture Family Group within Architecture 8: 80 MHz Speed Grade 8: 256 KB Flash Capacity AX: TQFP, PV: SSOP Package Code I: Industrial Temperature Range Peripheral Set Tape and reel versions of these devices are available and are marked with a “T” at the end of the part number. All devices in the PSoC 5LP CY8C58LP family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of life” requirements. Document Number: 001-84932 Rev. *H Page 127 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 13. Packaging Table 13-1. Package Characteristics Min Typ Max Units TA Parameter Operating ambient temperature Description Conditions –40 25 105 °C TJ Operating junction temperature –40 – 120 °C TJA Package JA (68-pin QFN) – 15 – °C/Watt TJA Package JA (100-pin TQFP) – 34 – °C/Watt TJC Package JC (68-pin QFN) – 13 – °C/Watt TJC Package JC (100-pin TQFP) – 10 – °C/Watt Table 13-2. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 68-pin QFN 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 68-pin QFN MSL 3 100-pin TQFP MSL 3 Document Number: 001-84932 Rev. *H Page 128 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 13-1. 68-pin QFN 8x8 with 0.4 mm Pitch Package Outline (Sawn Version) 001-09618 *E Figure 13-2. 100-pin TQFP (14 x 14 x 1.4 mm) Package Outline 51-85048 *I Document Number: 001-84932 Rev. *H Page 129 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 14-1. Acronyms Used in this Document (continued) 14. Acronyms Acronym Table 14-1. Acronyms Used in this Document Acronym Description Description FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin HVI high-voltage interrupt, see also LVI, LVD abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus IC integrated circuit ALU arithmetic logic unit IDAC current DAC, see also DAC, VDAC AMUXBUS analog multiplexer bus IDE integrated development environment API application programming interface APSR application program status register ARM® advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR 2C, I or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO common-mode rejection ratio IPOR initial power-on reset CPU central processing unit IPSR interrupt program status register CRC cyclic redundancy check, an error-checking protocol IRQ interrupt request DAC digital-to-analog converter, see also IDAC, VDAC ITM instrumentation trace macrocell DFB digital filter block LCD liquid crystal display DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LIN Local Interconnect Network, a communications protocol. DMA direct memory access, see also TD LR link register DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell Document Number: 001-84932 Rev. *H LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier Page 130 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Table 14-1. Acronyms Used in this Document (continued) Acronym Description Table 14-1. Acronyms Used in this Document (continued) Acronym Description PHUB peripheral hub SOF start of frame PHY physical layer SPI PICU port interrupt control unit Serial Peripheral Interface, a communications protocol PLA programmable logic array SR slew rate PLD programmable logic device, see also PAL SRAM static random access memory PLL phase-locked loop SRES software reset PMDD package material declaration datasheet SWD serial wire debug, a test protocol POR power-on reset SWV single-wire viewer PRES precise low-voltage reset TD transaction descriptor, see also DMA PRS pseudo random sequence THD total harmonic distortion PS port read data register TIA transimpedance amplifier PSoC® Programmable System-on-Chip™ TRM technical reference manual PSRR power supply rejection ratio TTL transistor-transistor logic PWM pulse-width modulator TX transmit RAM random-access memory UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request VDAC voltage DAC, see also DAC, IDAC RX receive WDT watchdog timer SAR successive approximation register WOL write once latch, see also NVL SC/CT switched capacitor/continuous time WRES watchdog timer reset 2C serial clock SCL I SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion Document Number: 001-84932 Rev. *H XRES external reset I/O pin XTAL crystal 15. Reference Documents PSoC® 3, PSoC® 5 Architecture TRM PSoC® 5 Registers TRM Page 131 of 139 PSoC® 5LP: CY8C58LP Family Datasheet 16. Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts  ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz V volts Document Number: 001-84932 Rev. *H Page 132 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Appendix: CSP Package Summary General Description This section contains preliminary data on the CY8C58 device in a 99-pin CSP package. Electrical Specifications The following specifications show differences in electrical specifications for CSP package devices. Table 1. Electrical Specifications Parameter TBD Description Conditions Min Typ Max Units Pinout Table 2 shows the pinout for the 99-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO may sink up to 100 mA total, same as for the 100-pin and 68-pin devices. Table 2. CSP Pinout Ball Name Ball Name Ball Name Ball Name E5 P2[5] L2 VIO1 B2 P3[6] C8 VIO0 G6 P2[6] K2 P1[6] B3 P3[7] D7 P0[4] G5 P2[7] C9 P4[2] C3 P12[0] E7 P0[5] H6 P12[4] E8 P4[3] C4 P12[1] B9 P0[6] K7 P12[5] K1 P1[7] E3 P15[2] D8 P0[7] L8 P6[4] H2 P12[6] E4 P15[3] D9 P4[4] J6 P6[5] F4 P12[7] A1 NC F8 P4[5] H5 P6[6] J1 P5[4] A9 NC F7 P4[6] J5 P6[7] H1 P5[5] L1 NC E6 P4[7] L7 VSSB F3 P5[6] L9 NC E9 VCCD K6 Ind G1 P5[7] A3 VCCA F9 VSSD L6 VBOOST G2 P15[6] A4 VSSA G9 VDDD K5 VBAT F2 P15[7] B7 VSSA H9 P6[0] L5 VSSD E2 VDDD B8 VSSA G8 P6[1] L4 XRES_N F1 VSSD C7 VSSA H8 P6[2] J4 P5[0] E1 VCCD A5 VDDA J9 P6[3] K4 P5[1] D1 P15[0] A6 VSSD G7 P15[4] K3 P5[2] D2 P15[1] B5 P12[2] F6 P15[5] L3 P5[3] C1 P3[0] A7 P12[3] F5 P2[0] H4 P1[0] C2 P3[1] C5 P4[0] J7 P2[1] J3 P1[1] D3 P3[2] D5 P4[1] J8 P2[2] H3 P1[2] D4 P3[3] B6 P0[0] K9 P2[3] J2 P1[3] B4 P3[4] C6 P0[1] H7 P2[4] G4 P1[4] A2 P3[5] A8 P0[2] K8 VIO2 G3 P1[5] B1 VIO3 D6 P0[3] Document Number: 001-84932 Rev. *H Page 133 of 139 PSoC® 5LP: CY8C58LP Family Datasheet CSP Ordering Information DAC Comparators SC/CT Analog Blocks Opamps DFB CapSense UDBs(96) 16-bit Timer/PWM FS USB CAN 2.0b Total I/O GPIO SIO USB I/O 256 64 2 4 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 4 4 24 4 4 4 72 62 8 2 99 WLCSP 0x2E1D2069 CY8C5888FNI-LP214 80 256 64 2 4 1x20-bit Del-Sig 2x12-bit SAR 4 4 4 4 4 4 24 4 4 – 72 62 8 2 99 WLCSP 0x2E1D6069 Package JTAG ID[101] ADC I/O Digital Analog EEPROM (KB) LCD Segment Drive 80 Flash (KB) CY8C5888FNI-LP210 CPU Speed (MHz) SRAM (KB) Part Number MCU Core Table 3. CSP Packaging Table 4. Package Characteristics Parameter TA TJ TJA TJC Description Operating ambient temperature Operating junction temperature Package JA (99-pin CSP) Package JC (99-pin CSP) Conditions Min –40 –40 – – Typ 25 – 16.5 0.1 Max 85 100 – – Units °C °C °C/Watt °C/Watt Table 5. Solder Reflow Peak Temperature Package 99-pin CSP Maximum Peak Temperature 255 Maximum Time at Peak Temperature 30 s Table 6. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package 99-pin CSP Document Number: 001-84932 Rev. *H MSL MSL1 Page 134 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Figure 2. WLCSP Package (5.192 × 5.940 × 0.6 mm) Package Outline 001-88034 *A Document Number: 001-84932 Rev. *H Page 135 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Document History Page Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Orig. of Change Submission Date ** 3825653 MKEA 12/07/2012 Datasheet for new CY8C58LP family *A 3897878 MKEA 02/07/2013 Updated characterization footnotes in Electrical Specifications. Updated conditions for SAR ADC INL and DNL specifications in Table 11-29 Changed number of opamps in Ordering Information Removed Preliminary status Removed references to CAN. Updated INL VIDAC spec. *B 3902085 MKEA 02/12/2013 Changed Hibernate wakeup time from 125 µs to 200 µs in Table 6-3 and Table 11-3. *C 3917994 MKEA 01/03/2013 Added Controller Area Network (CAN) content. *D 4114902 MKEA 09/30/2013 Added information about 1 KB cache in Features. Added warning on reset devices in the EEPROM section. Added DBGEN field in Table 5-3. Deleted statement about repeat start from the I2C section. Removed TSTG spec from Table 11-1 and added a note clarifying the maximum storage temperature range. Updated chip Idd, regulator, opamp, delta-sigma ADC, SAR ADC, IDAC, and VDAC graphs. Added min and max values for the Regulator Output Capacitor parameter. Updated CIN specs in GPIO DC Specifications and SIO DC Specifications. Updated rise and fall time specs in Fast Strong mode in Table 11-10, and deleted related graphs. Added IIB parameter in Opamp DC Specifications Updated Vos spec conditions and changed TCVos max value from 0.55 to 1 in Table 11-21. Updated Voltage Reference Specifications and IMO AC Specifications. Updated FIMO spec (3 MHz). Updated 100-TQFP package diagram. Added Appendix for CSP package (preliminary). *E 4225729 MKEA 12/20/2013 Added SIO Comparator Specifications. Changed THIBERNATE wakeup spec from 200 to 150 µs. Updated CSP package details and ordering information. Added 80 MHz parts in Table 12-1. *F 4386988 MKEA 05/22/2014 Updated General Description and Features. Added More Information and PSoC Creator sections. Updated JTAG IDs in Ordering Information. Updated 100-TQFP package diagram. *G 4587100 MKEA 12/08/2014 Added link to AN72845 in Note 3. Updated interrupt priority numbers in Section 4.4. Updated Section 5.4 to clarify the factory default values of EEPROM. Corrected ECCEN settings in Table 5-3. Updated Section 6.1.1 and Section 6.1.2. Added a note below Figure 6-4. Updated Figure 6-11. Changed ‘Control Store RAM’ to ‘Dynamic Configuration RAM’ in Figure 7-4 and changed Section 7.2.2.2 heading to ‘Dynamic Configuration RAM’. Updated Section 7.8. Document Number: 001-84932 Rev. *H Description of Change Page 136 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Document History Page (continued) Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Orig. of Change Submission Date *H 4698847 AVER / MKEA / GJV 03/24/2015 Description of Change Updated Features: Added “Extended temperature parts: –40 to 105 °C” as indented under “Temperature range (ambient)” under “Operating characteristics”. Updated System Integration: Updated Power System: Updated Boost Converter: Updated entire section. Updated Electrical Specifications: Replaced “Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted.” with “Specifications are valid for –40 °C ≤ TA ≤ 105 °C and TJ ≤ 120 °C, except where noted.” in all instances. Updated Device Level Specifications: Updated Table 11-2: Added details of IDD parameter corresponding to “T = 105 °C”. Updated Figure 11-3 and Figure 11-4. Updated Power Regulators: Updated Inductive Boost Regulator: Updated Table 11-6: Updated details of VBAT, IOUT, VOUT, RegLOAD, RegLINE parameters. Removed VOUT: VBAT parameter and its details. Removed Table “Inductive Boost Regulator AC Specifications”. Updated Table 11-7: Updated details of LBOOST, CBOOST parameters. Added CBAT parameter and its details. Added Figure 11-8, Figure 11-9, Figure 11-10, Figure 11-11, Figure 11-12, Figure 11-13, Figure 11-14. Removed Figure “Efficiency vs IOUT VBOOST = 3.3 V, LBOOST = 10 μH”. Removed Figure “Efficiency vs IOUT VBOOST = 3.3 V, LBOOST = 22 μH”. Updated Analog Peripherals: Updated Opamp: Updated Figure 11-19. Updated Delta-Sigma ADC: Updated Table 11-21: Added details of CMRRb parameter corresponding to condition “TA ≤ 105 °C”. Updated Table 11-22: Added details of SINAD16int parameter corresponding to condition “TA ≤ 105 °C”. Updated Voltage Reference: Updated Table 11-28: Added details of VREF parameter corresponding to condition “105 °C”. Updated Figure 11-32. Updated Current Digital-to-analog Converter (IDAC): Updated Figure 11-46, Figure 11-47, Figure 11-48, Figure 11-49, Figure 11-50, Figure 11-51. Updated Voltage Digital to Analog Converter (VDAC): Updated Figure 11-58, Figure 11-59, Figure 11-60, Figure 11-61, Figure 11-62, Figure 11-63. Updated Programmable Gain Amplifier: Updated Table 11-44: Added details of BW1 parameter corresponding to condition “TA ≤ 105 °C”. Updated Figure 11-69. Updated Temperature Sensor: Updated Table 11-45: Replaced 85 °C with 105 °C. Document Number: 001-84932 Rev. *H Page 137 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Document History Page (continued) Description Title: PSoC® 5LP: CY8C58LP Family Datasheet Programmable System-on-Chip (PSoC®) Document Number: 001-84932 Revision ECN Orig. of Change Submission Date Description of Change *H (cont.) 4698847 AVER / MKEA / GJV 03/24/2015 Updated Electrical Specifications: Updated Memory: Updated Flash: Updated Table 11-63: Updated details in “Conditions” column corresponding to “Flash data retention time” parameter. Added Note 78 and referred the same note in last condition corresponding to “Flash data retention time” parameter. Updated EEPROM: Updated Table 11-65: Updated details in “Conditions” column corresponding to “EEPROM data retention time” parameter. Added Note 78 and referred the same note in last condition corresponding to “EEPROM data retention time” parameter. Updated Nonvolatile Latches (NVL): Updated Table 11-67: Updated details in “Conditions” column corresponding to “NVL data retention time” parameter. Added Note 79 and referred the same note in last condition corresponding to “NVL data retention time” parameter. Updated Clocking: Updated Internal Main Oscillator: Updated Table 11-81: Replaced 85 °C with 105 °C. Updated Figure 11-78. Updated Ordering Information: Updated Table 12-1: Updated part numbers. Updated Part Numbering Conventions: Added “Q: Extended” as sub bullet under “g: Temperature Range”. Updated Packaging: Updated Table 13-1: Changed maximum value of TA parameter from 85 °C to 105 °C. Changed maximum value of TJ parameter from 100 °C to 120 °C. Updated Appendix: CSP Package Summary: Updated Packaging: spec 001-88034 – Changed revision from ** to *A. Document Number: 001-84932 Rev. *H Page 138 of 139 PSoC® 5LP: CY8C58LP Family Datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84932 Rev. *H Revised March 24, 2015 Page 139 of 139 Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. CapSense®, PSoC®3, PSoC®5, and PSoC® Creator™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All products and company names mentioned in this document may be the trademarks of their respective holders.