XK-1A

XK-1A Hardware Manual REV 1.1.0 2012/11/28 XMOS © 2012, All Rights Reserved. XK-1A Hardware Manual 1 2/15 Introduction The XK-1A is a low cost development board intended for exploring and designing multicore microcontroller designs. It comprises a single XS1-L1 device, 128KBytes SPI FLASH memory, four LEDs and two press-button switches. Two xCONNECT Links allow you to link multiple XK-1A boards together in a chain, two I/O expansion areas are provided for connecting additional components to the XK-1A, and an XTAG-2 debug adapter can be connected to debug the XK-1A board with a PC. The diagram below shows the layout of these components on the card. C G B C E A F B D H A B C D XS1-L1 Device XSYS IDC Headers User LEDs Push-Button Switches E E F G H 16-way Expansion Areas SPI Flash Memory 20MHz Crystal Oscillator 5V PSU An XK-1A board can be powered from the USB connection using an XTAG-2 debug adapter or by an external 5V power supply. Additional boards that have been chained together may be able to be powered by the XTAG-2 (depending on the length of the chain) or from an external 5V power supply. The rest of this document provide a detailed description of these components. REV 1.1.0 XK-1A Hardware Manual 2 3/15 XS1-L1 Device [A] The XK-1A is based on a single XS1-L1 device in a 128TQFP package. The XS1-L1 consists of a single xCORE Tile, which comprises a multicore microcontroller with tightly integrated general purpose I/O pins and 64 KBytes of on-chip RAM. The pins are brought out of the package and connected to the card’s components as follows: · Four yellow LEDs · Two push-button switches · Two XSYS 20-way IDC headers (one male and one female) · An SPI interface to FLASH memory · 12 I/O pins to the expansion areas The processor has ports that are directly connected to the I/O pins. Examples of how to write software that interfaces over these ports with the XK-1A components is provided in the document Programming XC for XMOS Devices available from the XMOS website. 3 User LEDs [C] The XK-1A provides four user LEDs that can be driven by software. The layout of these LEDs is shown below. Each LED is connected to a different pin, all of which are mapped to ports as described in the table below. Pin Port Processor XD28 P4F0 PORT_LED XD29 P4F1 PORT_LED XD30 P4F2 PORT_LED XD31 P4F3 PORT_LED The LED pins are active high. REV 1.1.0 XK-1A Hardware Manual 4 4/15 Push-Button Switches [D] The XK-1A provides two push-button switches whose states can be sampled at any time by software. The layout of these switches is shown below. The switches are connected to two pins, which are mapped to ports as described in the table below. Pin Port Processor XD34 P1K0 PORT_BUT_1 XD35 P1L0 PORT_BUT_2 The push-button switch pins are active low. REV 1.1.0 XK-1A Hardware Manual 5 5/15 XSYS Connectors [B] The XK-1A includes two XSYS 20-way IDC Headers, which can be used to link to an XTAG-2 debug adapter for debugging programs on the board, or to connect additional XK-1A boards together in a chain. The XSYS connector provides pins for JTAG control, system reset, processor debug, two UART links and two xCONNECT Links. Pin Signal Direction Description 1 3V3 Target to Host Power 2 3V3 Target to Host Power 3 TRST_N Host to Target JTAG Test Reset - Active Low 4 SENSE N/A Ground on TARGET, pull up on HOST 5 TDI/TDO Host to Target JTAG Test Data 6 XLC1_up/XLD1_up Target to Host xCONNECT Link 7 TMS Host to Target JTAG Test Mode Select 8 GND N/A Ground 9 TCK Host to Target JTAG Test Clock 10 XLC0_up/XLD0_up Target to Host xCONNECT Link 11 DEBUG Bidirectional Debug 12 GND N/A Ground 13 TDOC Target to Host JTAG Test Data 14 XLC0_dn/XLD0_dn Host to Target xCONNECT Link 15 RST_N Host to Target System Reset - Active Low. 16 GND N/A Ground 17 UART_RX Host to Target Serial Port (Down) 18 XLC1_dn/XLD1_dn Host to Target xCONNECT Link 19 UART_TX Target to Host Serial Port (Up) 20 GND N/A Ground The routing of these I/O pins along with the power pins is shown on the following page. REV 1.1.0 XK-1A Hardware Manual 6/15 20 19 GND XC1_dn GND XLC0_dn GND XLC0_up GND XLC1_up GND 5V 19 20 UART_TX UART_RX RST_N TDOC DEBUG TCK TMS TDI TRST_N 5V NC NC RST_N TDOC DEBUG TCK TMS TDO TRST_N 5V GND XLD1_dn GND XLD0_dn GND XLD0_up GND XLD1_up SENSE 5V 1 2 1 2 The XTAG-2 converts between XSYS and USB 2.0, allowing the XK-1A to be connected to most PCs. On power on, the XS1-L1 boots from the on-board flash memory. The XS1-L1 can then be put into JTAG mode by the PC, which then boots another program. No UART hardware is provided. Instead, two UART pins are mapped to ports, as shown in the table below. Pin Port Processor XD24 P1I0 PORT_UART_RX XD25 P1J0 PORT_UART_TX If a UART is required, it can be implemented in software by sampling and driving these ports at the required rate. The XTAG-2 performs a UART-to-USB conversion on these pins, which is interfaced by a proprietary XMOS terminal emulator. REV 1.1.0 XK-1A Hardware Manual 6 7/15 Expansion Areas [E] The I/O pins of the processor are brought out to expansion areas on the top and bottom of the card. These areas have 0.1" pitch through-plated holes and are populated with 0.1" right-angle IDC male connectors. The routing of I/O and power pins in the headers is shown below. GND XD11 XD9 XD7 GND XD5 XD3 XD1 5V XD10 XD8 XD6 3V3 XD4 XD2 XD0 XD12 XD14 XD16 3V3 XD18 XD20 XD22 5V XD13 XD15 XD17 GND XD19 XD21 XD23 GND Each expansion header provides a bank of 12 I/O pins, which are mapped to the ports as described in the table on the next page, and four power/ground pins. REV 1.1.0 XK-1A Hardware Manual 8/15 Pin Port 1b XD0 P1A0 XD1 P1B0 4b Processor 8b XD2 P4A0 P8A0 XD3 P4A1 P8A1 XD4 P4B0 P8A2 XD5 P4B1 P8A3 XD6 P4B2 P8A4 XD7 P4B3 P8A5 XD8 P4A2 P8A6 XD9 GPIO_A P4A3 P8A7 XD10 P1C0 XD11 P1D0 XD12 P1E0 XD13 P1F0 XD14 P4C0 P8B0 XD15 P4C1 P8B1 XD16 P4D0 P8B2 XD17 P4D1 P8B3 XD18 P4D2 P8B4 XD19 P4D3 P8B5 XD20 P4C2 P8B6 XD21 GPIO_B P4C3 P8B7 XD22 P1G0 XD23 P1H0 Eight pins from each bank can be configured as either two 4-bit ports or a single 8-bit port. The A and B expansion headers can alternatively be used together as a single 16-bit port. Narrower ports take priority over the pins where multiple ports are mapped to the same pins. REV 1.1.0 XK-1A Hardware Manual 6.1 9/15 xCONNECT Link Configuration Some of the I/O pins on the processor are configured as an additional 2-bit xCONNECT Link. The mapping of xCONNECT Links to the pins is shown in the table below. Pin xCONNECT Link XD52 XLC1_up XD53 XLC0_up XD54 XLC0_dn XD55 XLC1_dn XD64 XLD1_up XD65 XLD0_up XD66 XLD0_dn XD67 XLD1_dn Some of the I/O pins on the expansion areas can also be configured as 2-bit xCONNECT Links. The mapping of xCONNECT Links to the headers is shown in the table below. REV 1.1.0 Pin xCONNECT Link XD4 XLA1_out XD5 XLA0_out XD6 XLA0_in XD7 XLA1_in XD16 XLB1_out XD17 XLB0_out XD18 XLB0_in XD19 XLB1_in Expansion Area GPIO_A GPIO_B XK-1A Hardware Manual 7 10/15 SPI Flash Memory [F] The XK-1A provides 128KBytes of Serial Peripheral Interface (SPI) FLASH memory, which is interfaced by the four 1-bit connections described in the table below. Pin Port Processor XD36 P1M0 PORT_SPI_MISO XD37 P1N0 PORT_SPI_SS XD38 P1O0 PORT_SPI_CLK XD39 P1P0 PORT_SPI_MOSI The xTIMEcomposer tools include the XFLASH utility for programming compiled programs into the flash memory. XK-1A designs may also access the FLASH memory at run-time by interfacing with the above ports. The XK-1A does not use the SPI boot pins on the L1 (P1A0, P1B0, P1C0, P1D0) for the SPI flash. The XS1-L1 device on the XK-1A board has its OTP programmed with a bootloader, so that the XS1-L1 device uses the pins shown in the above table when booting from SPI. This pinout is not recommended for customer applications. Instead please refer to the XS1-L1 datasheets for information on the boot SPI pins. 8 20MHz Crystal Oscillator [G] The XS1-L1 is clocked at 20MHz by a crystal oscillator on the card. Each processor is clocked at 400MHz, the I/O ports at 100MHz, by an on-chip phase-locked loop (PLL). 9 Power Connector [H] An XK-1A can be powered from the XTAG-2 debug adapter or an external 5V power supply. Additional boards that have been chained together may be able to be powered by the XTAG-2 (depending on the length of the chain) or from an external 5V power supply. The voltage is converted by the on-board regulator to the 1V and 3V3 supplies used by the components. 10 Dimensions The XK-1A dimensions are 50 x 50mm. The mounting holes are 3mm in diameter. REV 1.1.0 XK-1A Hardware Manual 11 11/15 XK-1A Block Diagram The diagram below shows how the XK-1A components are connected to the XS1-L1. Processor 0 PORT_LED PORT_BUT_1, PORT_BUT_2 GPIO HEADERS A, B PORT_UART_RX TDI TDOC TMS TCK TRST_N TDO TDOC TMS TCK TRST_N XS1-L1 DEBUG DEBUG SS_RESET 5V PSU RST 1V PORT_SPI_MISO PORT_SPI_SS PORT_SPI_CLK PORT_SPI_MOSI 3V3 20MHz XTO REV 1.1.0 CLOCK SPI FLASH MEMORY XSYS_OUT XSYS_IN PORT_UART_TX XK-1A Hardware Manual 11.1 12/15 I/O Port-to-Pin Mapping The table below provides a full description of the port-to-pin mappings described throughout this document. Pin 1b XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 XD31 XD32 XD33 XD34 XD35 XD36 XD37 XD38 XD39 XD40 XD41 XD42 XD43 REV 1.1.0 4b Port 8b Processor 16b P1A0 P1B0 P4A0 P4A1 P4B0 P4B1 P4B2 P4B3 P4A2 P4A3 P8A0 P8A1 P8A2 P8A3 P8A4 P8A5 P8A6 P8A7 P16A0 P16A1 P16A2 P16A3 P16A4 P16A5 P16A6 P16A7 GPIO_A P4C0 P4C1 P4D0 P4D1 P4D2 P4D3 P4C2 P4C3 P8B0 P8B1 P8B2 P8B3 P8B4 P8B5 P8B6 P8B7 P16A8 P16A9 P16A10 P16A11 P16A12 P16A13 P16A14 P16A15 GPIO_B P1C0 P1D0 P1E0 P1F0 P1G0 P1H0 P1I0 P1J0 PORT_UART_RX PORT_UART_TX P4E0 P4E1 P4F0 P4F1 P4F2 P4F3 P4E2 P4E3 P1K0 P1L0 P1M0 P1N0 P1O0 P1P0 P8C0 P8C1 P8C2 P8C3 P8C4 P8C5 P8C6 P8C7 P8D0 P8D1 P8D2 P8D3 P8D4 P8D5 P8D6 P8D7 PORT_LED PORT_BUT_1 PORT_BUT_2 PORT_SPI_MISO PORT_SPI_SS PORT_SPI_CLK PORT_SPI_MOSI XD52 XD53 XD54 XD55 XLC1_up XLC0_up XLC0_dn XLC1_dn XD64 XD65 XD66 XD67 XLD1_up XLD0_up XLD0_dn XLD1_dn D1 2 D3 4 D5 6 8 GND D7 10 D9 12 D11 14 16 GND D12 1 D14 3 D16 5 VCC3V3 7 D18 9 VCC4V3 D20 11 D22 13 15 IOB H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 2 4 6 8 10 12 14 16 2 1 20MHz SMCLK GND OUT U5 OE VDD 3 4 VCC3V3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VCC1V 19 GND 20 21 VCC3V3 22 23 24 25 VCC3V3 26 D5 27 D4 28 VCC1V 29 D3 30 D55 31 VCC3V3 32 VCC3V3 D11 D61 D49 D10 D50 D9 D51 D52 D8 D53 VCC1V D54 D7 VCC3V3 D6 GND VDDIO1 D11 D61 D49 D10 D50 D9 D51 D52 D8 D53 VDD1 D54 D7 VDDIO2 D6 GND1 RESERVED PCU_VDD PCU_WAKE RST_N PCU_VDDIO PCU_GATE PCU_CLK CLK VDDIO3 D5 D4 VDD2 D3 D55 VDDIO4 U1 D13 D15 D17 GND D19 D21 D23 GND LED1 R9 1k LED0 R8 1k R10 1k LED2 1u C1 R1 4R7 VCC3V3 VCC1V 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 RST_N_BUF TCK_BUF TMS_BUF TRST_N_BUF D20 D43 D22 VDDIO10 GND17 GND16 D21 D23 GND15 D24 D25 D26 D27 VDD8 D36 D37 GND14 VDDIO9 GND13 VDD7 D38 D39 VDD6 VDDIO8 D32 GND12 D33 D34 VDD5 D35 GND11 GND10 R11 1k LED3 IO LEDs positioned either side of IOB near the top of the PCB XMOS XS1-L1-128 XMOS XK-1 REV.C L1-128 Breakout/Demo Board 100n C19 IOA H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 D12 D62 D13 D63 D64 VCC1V D65 D66 VCC3V3 D67 D14 D68 GND D15 D69 D16 D70 VCC3V3 D17 D28 VCC1V D18 D19 D29 D30 VCC3V3 D31 VCC1V D40 GND D41 D42 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 D12 D62 D13 D63 D64 VDD11 D65 D66 VDDIO13 D67 D14 D68 GND19 D15 D69 D16 D70 VDDIO12 D17 D28 VDD10 D18 D19 D29 D30 VDDIO11 D31 VDD9 D40 GND18 D41 D42 D56 D2 D57 D1 D0 D58 GND3 GND4 GND5 DEBUG GND6 VDDIO5 OTP_VDDIO OTP_VPP PLL_AGND PLL_AVDD VDD3 VDDIO6 MODE0 MODE1 MODE2 GND7 MODE3 TRST_N GND8 TMS VDD4 GND9 TCK TDI TDO VDDIO7 D56 33 D2 34 D57 35 D1 36 D0 37 D58 38 GND 39 GND 40 GND 41 DEBUG 42 GND 43 VCC3V3 44 VCC3V3 45 46 47 48 VCC1V 49 VCC3V3 50 MODE0 51 MODE1 52 MODE2 53 GND 54 MODE3 55 TRST_N_BUF 56 GND 57 58 VCC1V 59 GND 60 61 TDI 62 TDO 63 VCC3V3 64 REV 1.1.0 VCC3V3 6 5 4 6 5 4 D20 D43 D22 VCC3V3 GND GND D21 D23 GND D24 D25 D26 D27 VCC1V D36 D37 GND VCC3V3 GND VCC1V D38 D39 VCC1V VCC3V3 D32 GND D33 D34 VCC1V D35 GND GND NC7WZ17 Y1 A1 Vcc GND Y2 A2 U8 NC7WZ17 Y1 A1 Vcc GND Y2 A2 U7 3 1 1 2 3 1 2 3 U2 2 R6 47k 4 3 1 C22 47n 100n 100n C20 BUTTON_1 8 7 6 5 RST_N TCK TMS TRST_N R19 47K R7 47k C2 R17 47K R18 47K VCC3V3 AT25FS010N-SH27 NOTCS VCC SO NOTHLD NOTWP SCLK GND SI VCC3V3 BUTTON_2 1 2 3 4 VCC3V3 FLASH can be programmed for stand alone operation (the XMOS L1 also has on board OTP) 4 2 1 2 3 NCP1521 VIN LX GND EN FB U4 5VSK 1 2 3 R5 47K 1 TRST_N 3 TDI 5 TMS 7 TCK 9 DEBUG11 13 RST_N 15 RX D24 17 TX D25 19 R4 47K VCC3V3 33R R12 JTAGIN(PLUG) 2 H1 H2 H3 H4 4 IXU1 H5 H6 6 8 H7 H8 IXU0 H9 H10 10 12 H11 H12 IXD0 H13 H14 14 H15 H16 16IXD1 H17 H18 18 H19 H20 20 5VHD VCC3V3 4 5 6 U6 3 2 1 2 4 6 OXU1 8 10OXU0 12 14OXD0 16 18OXD1 20 DCINSMD 4 5 VCC4V3 CENT H1 GND H2 CONT JTAGOUT(SKT) 1 H2 TRST_N 3 H1 H3 H4 TDO 5 H5 H6 TMS 7 H7 H8 TCK 9 H9 H10 DEBUG11 H11 H12 TDOC 13 RST_N 15 H13 H14 H15 H16 17 H17 H18 19 H19 H20 5VSK Z I0 Vcc GND S I1 NC7SZ157 D 5VDCIN TR2 NTR4101P R13 47k VCC3V3 TDO TDOC 4 5 1 2 100n C5 VCC3V3 C18 22p L1 2u2H 100n C4 VCC3V3 R3 R2 150k 100n C7 100n C11 VCC1V 4u7 C10 220k GND1 100n C6 3V3 100n C13 1V GND2 100n C12 100n C8 100n C14 M4 M3 M2 M1 D65 D64 D66 D67 Date: Size A3 Title 100n C15 100n C16 Sheet L1-128-BREAKOUT XMOS XK-1 Friday, December 03, 2010 Document Number L1-128-BREAKOUT-1 OXD0 OXD1 OXU0 OXU1 Link Mapping D53 IXU0 D52 IXU1 D54 IXD0 D55 IXD1 100n C17 VCC1V 1 of 1 Rev C 4u7 C21 GND Mounting holes Mapping of XLINKS JTAG connections to data lines on the XMOS L1-128 These can be used to connect more than one XMOS device together to increase processing performance and IO Connections for XTAG (JTAG) input & outputs with auto JTAG chaining switching via U6 4 2u2 C3 5 R15 1k S 3V3 Power via U3 Linear Reg and 1V Power via U4 Switchmode 2u2 C9 U3 IN VOUT GND EN NC NCP699SN33 VCC4V3 VCC4V3 1 2 3 VCC4V3 5VHD Switching for two 5V inputs 5VSK R14 47k G 12 IO Ports (top and bottom on the PCB) D0 1 D2 3 D4 5 VCC3V3 7 D6 9 D8 11 D10 13 VCC4V3 15 XK-1A Hardware Manual 13/15 XK-1A Schematic XK-1A Hardware Manual 13 14/15 XK-1A XN File The XK-1A XN file is a platform specific file, similar to a # define. It defines the type of multicore microcontroller device on the board, and can be used to map the hardware features on the board to generic port identifiers, simplifying the process of writing projects and porting between platforms. The following table lists the defined identifiers defined in the XMOS Tools version 9.9.1 for the XK-1A: Port Location Generic Identifier XS1_PORT_1I PORT_UART_RX XS1_PORT_1J PORT_UART_TX XS1_PORT_1K PORT_BUT_1 XS1_PORT_1L PORT_BUT_2 XS1_PORT_1M PORT_SPI_MISO XS1_PORT_1N PORT_SPI_SS XS1_PORT_1O PORT_SPI_CLK XS1_PORT_1P PORT_SPI_MOSI XS1_PORT_4F PORT_LED To provide backward compatibility with source code written using the version 9.9.0 XN file, add the following to your source: # ifdef PORT \ _BUT_1 // 9.9.1 XN names found , add 9.9.0 XN names # define PORT_BUTTON_0 PORT_BUT_1 # define PORT_BUTTON_1 PORT_BUT_2 # else // 9.9.0 XN names found , add 9.9.1 XN names # define PORT_BUT_1 PORT_BUTTON_0 # define PORT_BUT_2 PORT_BUTTON_1 endif REV 1.1.0 XK-1A Hardware Manual 14 15/15 Related Documents The following documents (available from the XMOS website) provide more information on designing with the XK-1A: · XK-1A Development Kit Tutorial: provides an introduction to programming software on the XK-1A using the XC language. · XCore XS1 Architecture Tutorial: provides an overview of the XS1 instruction set architecture. The most up-to-date information on the XK-1A, including board schematics and product datasheets, is available from: · http://www.xmos.com/xk1a/ 15 Document History Date Release Comment 2011-01-28 1.0.0 First release 2012-04-19 1.0.1 Page 9: XLB1_in mapped to XD19 2012-11-28 1.1.0 SPI memory pin/port assignment note - page 7 Copyright © 2012, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of Xmos Ltd. in the United Kingdom and other countries, and may not be used without written permission. All other trademarks are property of their respective owners. Where those designations appear in this book, and XMOS was aware of a trademark claim, the designations have been printed with initial capital letters or in all capitals. REV 1.1.0