1
CONTENTS
Chapter 1 Introduction of the FPGA System of DE2i-150 Board.............................. 5
1-1 Layout and Components ............................................................................................................................ 5
1-2 Block Diagram of the DE2i-150 Board...................................................................................................... 7
Chapter 2 DE2i-150 Control Panel........................................................................ 10
2-1 Control Panel Setup.................................................................................................................................. 10
2-2 Controlling the LEDs, 7-segment Displays and LCD Display .............................................................. 12
2-3 Switches and Push-buttons ....................................................................................................................... 14
2-4 SDRAM/SSRAM/Flash Controller and Programmer .............................................................................. 15
2-5 SD Card .................................................................................................................................................... 17
2-6 RS-232 Communication ........................................................................................................................... 18
2-7 VGA ......................................................................................................................................................... 19
2-8 HSMC ...................................................................................................................................................... 20
2-9 IR Receiver............................................................................................................................................... 21
2-10 G-Sensor................................................................................................................................................. 22
2-11 Overall Structure of the DE2i-150 Control Panel .................................................................................. 23
Chapter 3 Using the DE2i-150 Board .................................................................... 25
3-1 Monitor Function for the Status of FPGA Configuration......................................................................... 25
3-2 Configuring the Cyclone IV GX FPGA ................................................................................................... 26
3-3 Using Push-buttons and Switches ............................................................................................................ 30
3-4 Using LEDs .............................................................................................................................................. 31
3-5 Using the 7-segment Displays .................................................................................................................. 33
3-6 Clock Circuitry ......................................................................................................................................... 35
3-7 Using the LCD Module ............................................................................................................................ 36
3-8 High Speed Mezzanine Card .................................................................................................................... 37
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3-9 Using the Expansion Header .................................................................................................................... 40
3-10 Using VGA............................................................................................................................................. 42
3-11 RS-232 Serial Port .................................................................................................................................. 45
3-12 Gigabit Ethernet Transceiver.................................................................................................................. 46
3-13 TV Decoder ............................................................................................................................................ 48
3-14 Implementing a TV Encoder .................................................................................................................. 50
3-15 Using IR ................................................................................................................................................. 50
3-16 Using SSRAM/SDRAM/FLASH/SD Card............................................................................................ 51
Chapter 4 DE2i-150 System Builder ..................................................................... 58
4-1 Introduction .............................................................................................................................................. 58
4-2 General Design Flow................................................................................................................................ 58
4-3 Using DE2i-150 System Builder .............................................................................................................. 59
Chapter 5 Examples of Advanced Demonstrations............................................... 67
5-1 DE2i-150 Factory Configuration ............................................................................................................. 67
5-2 TV Box Demonstration ............................................................................................................................ 68
5-3 SD Card Demonstration ........................................................................................................................... 70
5-4 IR Receiver Demonstration ...................................................................................................................... 73
5-5 Web Server Demonstration ...................................................................................................................... 77
Chapter 6 PCI Express Introduction ..................................................................... 87
6-1 PCI Express System Framework .............................................................................................................. 87
6-2 FPGA: PCI Express System Design......................................................................................................... 88
6-3 Linux Host: PCI Express System Design .............................................................................................. 89
6-4 Operation of Yocto ................................................................................................................................... 96
6-5 Installation of PCI Express Driver ........................................................................................................... 98
6-6 Demo: Fundamental Communication ...................................................................................................... 98
6-7 Demo: VGA Display .............................................................................................................................. 103
Chapter 7 Appendix .......................................................................................... 109
7-1 EPCS Programming via nios-2-flash-programmer ................................................................................ 109
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7-2 Making HAL CFI Flash drivers to work with Spansion F-lash ............................................................. 109
7-3 Revision History..................................................................................................................................... 110
7-4 Copyright Statement............................................................................................................................... 110
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Chapter 1
Introduction of the FPGA System of
DE2i-150 Board
This chapter presents the features and design characteristics of the DE2i-150 board.
1-1 Layout and Components
A photograph of the DE2i-150 board is shown in Figure 1-1 and Figure 1-2. It depicts the layout of
the board and indicates the location of the connectors and key components.
Figure 1-1
The DE2i-150 board (top view)
5
Figure 1-2 The DE2i-150 board (bottom view)
The DE2i-150 board has many features that allow users to implement a wide range of designed
circuits, from simple circuits to various multimedia projects.
The following hardware (FPGA System) is provided on the DE2i-150 board:
Altera Cyclone® IV 4CX150 FPGA device
Altera Serial Configuration device – EPCS64
USB Blaster (on board) for programming; both JTAG and Active Serial (AS) programming
modes are supported
Two 2MB SSRAM
Two 64MB SDRAM
64MB Flash memory
SD Card socket
4 Push-buttons
18 Slide switches
18 Red user LEDs
9 Green user LEDs
50MHz oscillator for clock sources
VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
Gigabit Ethernet PHY with RJ45 connectors
RS-232 transceiver and 9-pin connector
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IR Receiver
2 SMA connectors for external clock input/output
One 40-pin Expansion Header with diode protection
One High Speed Mezzanine Card (HSMC) connector
16x2 LCD module
In addition to these hardware features, the DE2i-150 board has software support for standard I/O
interfaces and a control panel facility for accessing various components. Also, the software is
provided for supporting a number of demonstrations that illustrate the advanced capabilities of the
DE2i-150 board.
In order to use the DE2i-150 board, the user has to be familiar with the Quartus II software. The
necessary knowledge can be acquired by reading the tutorials “My_First_Fpga”. These tutorials are
provided in the directory DE2i_150_tutorials on the DE2i-150 System CD that accompanies the DE2i-150 kit and
can also be found on Terasic‟s DE2i-150 web pages.
1-2 Block Diagram of the DE2i-150 Board
Figure 1-3 gives the block diagram of the DE2i-150 board. To provide maximum flexibility for the
user, all connections are made through the Cyclone IV GX FPGA device. Thus, the user can
configure the FPGA to implement any system design.
Figure 1-3 Block Diagram of DE2i-150
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Following is more detailed information about the blocks in Figure 1-3:
FPGA device
o
o
o
o
o
Cyclone IV EP4CGX150DF31 device
149,760 LEs
720 M9K memory blocks
6,480 Kbits embedded memory
8 PLLs
FPGA configuration
o JTAG and AS mode configuration
o EPCS64 serial configuration device
o On-board USB Blaster circuitry
Memory devices
o 128MB (32Mx32bit) SDRAM
o 4MB (1Mx32) SSRAM
o 64MB (4Mx16) Flash with 16-bit mode
SD Card socket
o Provides SPI and 4-bit SD mode for SD Card access
Connectors
o
o
o
o
o
o
Ethernet 10/100/1000 Mbps ports
High Speed Mezzanine Card (HSMC)
40-pin expansion port
VGA-out connector
VGA DAC (high speed triple DACs)
DB9 serial connector for RS-232 port with flow control
Clock
o Three 50MHz oscillator clock inputs
o SMA connectors (external clock input/output)
D is p la y
o 16x2 LCD module
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Switches and indicators
o 18 slide switches and 4 push-buttons switches
o 18 red and 9 green LEDs
o 8 7-segment displays
Other features
o Infrared remote-control receiver module
o TV decoder (NTSC/PAL/SECAM) and TV-in connector
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Chapter 2
DE2i-150 Control Panel
The DE2i-150 board comes with a Control Panel program that allows users to access various
components on the board from a host computer. The host computer communicates with the board
through a USB connection. The program can be used to verify the functionality of components on
the board or be used as a debug tool while developing RTL code.
This chapter first presents some basic functions of the Control Panel, then describes its structure in
the block diagram form, and finally describes its capabilities.
2-1 Control Panel Setup
The Control Panel Software Utility is located in the directory “Tools/ ControlPanel” in the DE2i-150
System CD. It's free of installation, just copy the whole folder to your host computer and launch the
control panel by executing the “DE2i_150_ControlPanel.exe”.
Specific control circuits should be downloaded to your FPGA board before the control panel can
request it to perform required tasks. The program will call Quartus II tools to download the control
circuit to the FPGA board through the USB-Blaster[USB-0] connection.
To activate the Control Panel, perform the following steps:
1.
Make sure Quartus II 12.1 or later version is installed successfully on your PC.
2.
Set the RUN/PROG switch to the RUN position.
3.
Connect the supplied USB cable to the USB Blaster port, connect the 12V power supply, and
turn the power switch ON.
4.
Start the executable DE2i_150_ControlPanel.exe on the host computer. The Control Panel user
interface shown in Figure 2-1 will appear.
5.
The DE2i_150_ControlPanel.sof bit stream is loaded automatically as soon as the
DE2i_150_control_panel.exe is launched.
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6.
In case the connection is disconnected, click on CONNECT where the .sof will be re-loaded
onto the board.
Please not that the Control Panel will occupy the USB port until you close that port; you cannot use Quartus II to
download a configuration file into the FPGA until the USB port is closed.
7.
The Control Panel is now ready for use; experience it by setting the ON/OFF status for some
LEDs and observing the result on the DE2i-150 board.
Figure 2-1
The DE2i-150 Control Panel
The concept of the DE2i-150 Control Panel is illustrated in Figure 2-2. The “Control Circuit” that
performs the control functions is implemented in the FPGA board. It communicates with the
Control Panel window, which is active on the host computer, via the USB Blaster link. The
graphical interface is used to send commands to the control circuit. It handles all the requests and
performs data transfers between the computer and the DE2i-150 board.
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Figure 2-2
The DE2i-150 Control Panel concept
The DE2i-150 Control Panel can be used to light up LEDs, change the values displayed on
7-segment and LCD displays, monitor buttons/switches status, read/write the SDRAM, SSRAM
and Flash Memory, output VGA color pattern to VGA monitor, verify functionality of HSMC
connector I/Os, communicate with PC via RS-232 interface, read SD Card specification information,
and display the resolution measurement of 3-axis accelerometer on the G-Sensor. The feature of
reading/writing a word or an entire file from/to the Flash Memory allows the user to develop
multimedia applications (Flash Audio Player, Flash Picture Viewer) without worrying about how to
build a Memory Programmer.
2-2 Controlling the LEDs, 7-segment Displays and LCD
Display
A simple function of the Control Panel is to allow setting the values displayed on LEDs, 7-segment
displays, and the LCD character display.
Choosing the LED tab leads to the window in Figure 2-3. Here, you can directly turn the LEDs on
or off individually or by clicking “Light All” or “Unlight All”.
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Figure 2-3
Controlling LEDs
Choosing the 7-SEG tab leads to the window shown in Figure 2-4. From the window, directly use
the left-right arrows to control the 7-SEG patterns on the DE2i-150 board which are updated
immediately. Note that the dots of the 7-SEGs are not enabled on DE2i-150 board.
Figure 2-4 Controlling 7-SEG display
Choosing the LCD tab leads to the window in Figure 2-5. Text can be written to the LCD display
by typing it in the LCD box then pressing the Set button.
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Figure 2-5
Controlling the LCD display
The ability to set arbitrary values into simple display devices is not needed in typical design
activities. However, it gives users a simple mechanism for verifying that these devices are
functioning correctly in case a malfunction is suspected. Thus, it can be used for troubleshooting
purposes.
2-3 Switches and Push-buttons
Choosing the Switches tab leads to the window in Figure 2-6. The function is designed to monitor
the status of slide switches and push-buttons in real time and show the status in a graphical user
interface. It can be used to verify the functionality of the slide switches and push-buttons.
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Figure 2-6
Monitoring switches and buttons
The ability to check the status of push-button and slide switch is not needed in typical design
activities. However, it provides users a simple mechanism for verifying if the buttons and switches
are functioning correctly. Thus, it can be used for troubleshooting purposes.
2-4 SDRAM/SSRAM/Flash Controller and Programmer
The Control Panel can be used to write/read data to/from the SDRAM, SSRAM and Flash chips on
the DE2i-150 board. As an example, we will describe how the SDRAM may be accessed; the same
approach is used to access the SSRAM, and Flash. Click on the Memory tab and select “SDRAM”
to reach the window in Figure 2-7.
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Figure 2-7
Accessing the SDRAM
A 16-bit word can be written into the SDRAM by entering the address of the desired location,
specifying the data to be written, and pressing the Write button. Contents of the location can be read
by pressing the Read button. Figure 2-7 depicts the result of writing the hexadecimal value 06CA
into offset address 200, followed by reading the same location.
The Sequential Write function of the Control Panel is used to write the contents of a file into the
SDRAM as follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be written in the Length box. If the entire file is to be loaded,
then a checkmark may be placed in the File Length box instead of giving the number of bytes.
3.
To initiate the writing process, click on the Write a File to Memory button.
4.
When the Control Panel responds with the standard Windows dialog box asking for the source
file, specify the desired file in the usual manner.
The Control Panel also supports loading files with a .hex extension. Files with a .hex extension are
ASCII text files that specify memory values using ASCII characters to represent hexadecimal
values. For example, a file containing the line
0123456789ABCDEF
Defines eight 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loaded
consecutively into the memory.
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The Sequential Read function is used to read the contents of the SDRAM and fill them into a file as
follows:
1.
Specify the starting address in the Address box.
2.
Specify the number of bytes to be copied into the file in the Length box. If the entire contents
of the SDRAM are to be copied (which involves all 128 Mbytes), then place a checkmark in
the Entire Memory box.
3.
Press Load Memory Content to a File button.
4.
When the Control Panel responds with the standard Windows dialog box asking for the
destination file, specify the desired file in the usual manner.
Users can use the similar way to access the SSRAM and Flash. Please note that users need to erase
the Flash before writing data to it.
2-5 SD Card
The function is designed to read the identification and specification information of the SD Card.
The 4-bit SD MODE is used to access the SD Card. This function can be used to verify the
functionality of the SD Card Interface. Follow the steps below to perform the SD Card exercise:
1.
Choosing the SD Card tab leads to the window in Figure 2-8.
2.
Insert an SD Card to the DE2i-150 board, and then press the Read button to read the SD Card.
The SD Card‟s identification, specification, and file format information will be displayed in the
control window.
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Figure 2-8
Reading the SD Card Identification and Specification
2-6 RS-232 Communication
The Control Panel allows users to verify the operation of the RS-232 serial communication interface
on the DE2i-150. The setup is established by connecting a RS-232 9-pin male to female cable from
the PC to the RS-232 port where the Control Panel communicates to the terminal emulator software
on the PC, or vice versa. Alternatively, a RS-232 loopback cable can also be used if you do not wish
to use the PC to verify the test. The Receive terminal window on the Control Panel monitors the
serial communication status. Follow the steps below to initiate the RS-232 communication:
1.
Choosing the RS-232 tab leads to the window in Figure 2-9.
2.
Plug in a RS-232 9-pin male to female cable from PC to RS-232 port or a RS-232 loopback
cable directly to RS-232 port.
3.
The RS-232 settings are provided below in case a connection from the PC is used:
Baud Rate: 115200
Parity Check Bit: None
Data Bits: 8
Stop Bits: 1
Flow Control (CTS/RTS): ON
4. To begin the communication, enter specific letters followed by clicking Send. During the
communication process, observe the status of the Receive terminal window to verify its operation.
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Figure 2-9
RS-232 Serial Communication
2-7 VGA
DE2i-150 Control Panel provides VGA pattern function that allows users to output color pattern to
LCD/CRT monitor using the DE2i-150 board. Follow the steps below to generate the VGA pattern
function:
1.
Choosing the Video tab leads to the window in Figure 2-10.
2.
Plug a D-sub cable to VGA connector of the DE2i-150 board and LCD/CRT monitor.
3.
The LCD/CRT monitor will display the same color pattern on the control panel window.
4.
Click the drop down menu shown in Figure 2-10 where you can output the selected color
individually.
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Figure 2-10
Controlling VGA display
2-8 HSMC
Select the HSMC tab to reach the window shown in Figure 2-11. This function is designed to verify
the functionality of the signals located on the HSMC connector. Before running the HSMC
loopback verification test, follow the instruction noted under the Loopback Installation section and
click on Verify. Please note to turn off the DE2i-150 board before the HSMC loopback adapter is
installed to prevent any damage to the board.
The HSMC loopback adapter is not provided in the kit package but can be purchased through the
website below:
(http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=78&No=495)
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Figure 2-11
HSMC loopback verification test performed under Control Panel
2-9 IR Receiver
From the control panel, we can test the IR receiver on the DE2i-150 by sending scan code from a
remote controller. Figure 2-12 depicts the IR receiver window when the IR tab is pressed. When the
scan code is received, the information will be displayed on the IR Receiver window represented in
hexadecimal. Also, the pressed button on the remote controller will be indicated on the graphic of
remote controller on the IR receiver window. Note that there exists several encoding form among
different brands of remote controllers. Only the remote controller comes with the kit is confirmed to
be compatible with this software.
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Figure 2-12
Testing the IR receiver using remote controller
2-10 G-Sensor
On the DE2i-150 board, the G-sensor function is being demonstrated by Spirit level .The user can
rotate the DE2i-150 board to different directions, up or down, left or right. The bubble will travel
quickly following your manners. Meanwhile, the control panel will show the accelerated data in
x-axis, y-axis and z-axis as shown in Figure 2-12.
Note that the resolution measurement of 3-axis accelerometer is set to +- 2g
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Figure 2-13
Testing the G-sensor
2-11 Overall Structure of the DE2i-150 Control Panel
The DE2i-150 Control Panel is based on a Nios II SOPC system instantiated in the Cyclone IV GX
FPGA with software running on the on-chip memory. The software part is implemented in C code;
the hardware part is implemented in Verilog HDL code with SOPC builder. The source code is not
available on the DE2i_150 System CD.
To run the Control Panel, users should make the configuration according to Section 3.1. Figure
2-14 depicts the structure of the Control Panel. Each input/output device is controlled by the Nios II
Processor instantiated in the FPGA chip. The communication with the PC is done via the USB
Blaster link. The Nios II interprets the commands sent from the PC and performs the corresponding
actions.
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Figure 2-14
The block diagram of the DE2i-150 control panel
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Chapter 3
Using the DE2i-150 Board
This chapter gives instructions for using the DE2i-150 board and describes each of its peripherals.
3-1 Monitor Function for the Status of FPGA Configuration
In the DE2i-150 power up sequence, there is a monitor circuit that monitors the status of the FPGA
configuration. After it confirms the configuration is complete, the power up sequence will go to
next state. If the configuration is not complete, the CPU will not initiate.
There is a 2-position dip-switch (SW20, as shown in Figure 3.1) on this circuit, which can be used
for two settings.
The first switch configures TIMEOUT, which sets a timer in the monitor circuit to ignore any FPGA
configuration failure. When the counter goes to the set value, the power up sequence state continue
powering up the CPU regardless of whether the FPGA has not been configured normally or not.
The second switch position configures CPU_DIS, which disables CPU power up.
Table 3-1 shows the detailed setting for SW20.
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Figure 3-1
The Power Up Sequence Control Switch
Table 3-1
Position Switch Name
TIMEOUT
CPU_DIS
Switch Setting for SW20
Function for Turning to “ON” Position
Enable the timeout function
Disable CPU function
Note: If there is no image file stored in the configuration device (EPCS), the monitor circuit
will pass the status as a successful configuration
3-2 Configuring the Cyclone IV GX FPGA
The procedure for downloading a circuit from a host computer to the DE2i-150 board is described
in the tutorial Quartus II Introduction. This tutorial is found in the DE2i_150_tutorials folder on the
DE2i-150 System CD. The user is encouraged to read the tutorial first, and treat the information
below as a short reference.
The DE2i-150 board contains a serial configuration device that stores configuration data for the
Cyclone IV GX FPGA. This configuration data is automatically loaded from the configuration
device into the FPGA every time while power is applied to the board. Using the Quartus II software,
it is possible to reconfigure the FPGA at any time, and it is also possible to change the non-volatile
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data that is stored in the serial configuration device. Both types of programming methods are
described below.
1.
JTAG programming: In this method of programming, named after the IEEE standards Joint
Test Action Group, the configuration bit stream is downloaded directly into the Cyclone IV GX
FPGA. The FPGA will retain this configuration as long as power is applied to the board; the
configuration information will be lost when the power is turned off.
2.
AS programming: In this method, called Active Serial programming, the configuration bit
stream is downloaded into the Altera EPCS64 serial configuration device. It provides
non-volatile storage of the bit stream, so that the information is retained even when the power
supply to the DE2i-150 board is turned off. When the board‟s power is turned on, the
configuration data in the EPCS64 device is automatically loaded into the Cyclone IV GX
FPGA.
JTAG Chain on DE2i-150 Board
To use JTAG interface for configuring FPGA device, the JTAG chain on DE2i-150 must form a
close loop that allows Quartus II programmer to detect FPGA device. Figure 3-2 illustrates the
JTAG chain on DE2i-150 board. Shorting pin1 and pin2 on JP2 can disable the JTAG signals on
HSMC connector that will form a close JTAG loop chain on DE2i-150 board (See Figure 3-3).
Thus, only the on board FPGA device (Cyclone IV GX) will be detected by Quartus II programmer.
If users want to include another FPGA device or interface containing FPGA device in the chain via
HSMC connector, short pin2 and pin3 on JP2 to enable the JTAG signal ports on the HSMC
connector.
Figure 3-2
The JTAG chain on DE2i-150 board
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Figure 3-3
The JTAG chain configuration header
The sections below describe the steps used to perform both JTAG and AS programming. For both
methods the DE2i-150 board is connected to a host computer via a USB cable. Using this
connection, the board will be identified by the host computer as an Altera USB Blaster device. The
process for installing on the host computer the necessary software device driver that communicates
with the USB Blaster is described in the tutorial “My_First_Fpga”. This tutorial is available on the
DE2i-150 System CD.
Configuring the FPGA in JTAG Mode
Figure 3-4 illustrates the JTAG configuration setup. To download a configuration bit stream into
the Cyclone IV GX FPGA, perform the following steps:
Ensure that power is applied to the DE2i-150 board
Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the
RUN position (See Figure 3-5)
Connect the supplied USB cable to the USB Blaster port on the DE2i-150 board (See Figure
1-1)
The FPGA can now be programmed by using the Quartus II Programmer to select a
configuration bit stream file with the .sof filename extension
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Figure 3-4
Figure 3-5
The JTAG configuration scheme
The RUN/PROG switch (SW19) is set in JTAG mode
Configuring the EPCS64 in AS Mode
Figure 3-6 illustrates the AS configuration setup. To download a configuration bit stream into the
EPCS64 serial configuration device, perform the following steps:
Ensure that power is applied to the DE2i-150 board.
Connect the supplied USB cable to the USB Blaster port on the DE2i-150 board (See Figure
3-6)
Configure the JTAG programming circuit by setting the RUN/PROG slide switch (SW19) to the
PROG position.
The EPCS64 chip can now be programmed by using the Quartus II Programmer to select a
configuration bit stream file with the .pof filename extension.
Once the programming operation is finished, set the RUN/PROG slide switch back to the RUN
position and then reset the board by turning the power switch off and back on; this action causes
the new configuration data in the EPCS64 device to be loaded into the FPGA chip.
29
Figure 3-6
The AS configuration scheme
3-3 Using Push-buttons and Switches
The DE2i-150 board provides four push-button switches as shown in Figure 3-7. Each of these
switches is debounced using a Schmitt Trigger circuit, as indicated in Figure 3-8. The four outputs
called KEY0, KEY1, KEY2, and KEY3 of the Schmitt Trigger devices are connected directly to the
Cyclone IV GX FPGA. Each push-button switch provides a high logic level when it is not pressed,
and provides a low logic level when depressed. Since the push-button switches are debounced, they
are appropriate for using as clock or reset inputs in a circuit.
Figure 3-7
Connections between the push-button and Cyclone IV GX FPGA
30
Pushbutton depressed
Pushbutton released
Before
Debouncing
Schmitt Trigger
Debounced
Figure 3-8
Switch debouncing
There are also 18 slide switches on the DE2i-150 board (See Figure 3-9). These switches are not
debounced, and are assumed for use as level-sensitive data inputs to a circuit. Each switch is
connected directly to a pin on the Cyclone IV GX FPGA. When the switch is in the DOWN position
(closest to the edge of the board), it provides a low logic level to the FPGA, and when the switch is
in the UP position it provides a high logic level.
Figure 3-9
Connections between the slide switches and Cyclone IV GX FPGA
3-4 Using LEDs
There are 27 user-controllable LEDs on the DE2i-150 board. Eighteen red LEDs are situated above
the 18 Slide switches, and eight green LEDs are found above the push-button switches (the 9th
green LED is in the middle of the 7-segment displays). Each LED is driven directly by a pin on the
Cyclone IV GX FPGA; driving its associated pin to a high logic level turns the LED on, and driving
the pin low turns it off. Figure 3-10 shows the connections between LEDs and Cyclone IV GX
FPGA.
31
Figure 3-10
Connections between the LEDs and Cyclone IV GX FPGA
A list of the pin names on the Cyclone IV GX FPGA that are connected to the slide switches is
given in Table 3-2. Similarly, the pins used to connect to the push-button switches and LEDs are
displayed in Table 3-3 and Table 3-4, respectively.
Table 3-2
Signal Name
SW[0]
SW[1]
SW[2]
SW[3]
SW[4]
SW[5]
SW[6]
SW[7]
SW[8]
SW[9]
SW[10]
SW[11]
SW[12]
SW[13]
SW[14]
SW[15]
SW[16]
SW[17]
FPGA Pin No.
PIN_V28
PIN_U30
PIN_V21
PIN_C2
PIN_AB30
PIN_U21
PIN_T28
PIN_R30
PIN_P30
PIN_R29
PIN_R26
PIN_N26
PIN_M26
PIN_N25
PIN_J26
PIN_K25
PIN_C30
PIN_H25
Table 3-3
Signal Name
KEY[0]
KEY[1]
KEY[2]
KEY[3]
FPGA Pin No.
PIN_AA26
PIN_AE25
PIN_AF30
PIN_AE26
Pin Assignments for Slide Switches
Description
Slide Switch[0]
Slide Switch[1]
Slide Switch[2]
Slide Switch[3]
Slide Switch[4]
Slide Switch[5]
Slide Switch[6]
Slide Switch[7]
Slide Switch[8]
Slide Switch[9]
Slide Switch[10]
Slide Switch[11]
Slide Switch[12]
Slide Switch[13]
Slide Switch[14]
Slide Switch[15]
Slide Switch[16]
Slide Switch[17]
I/O Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
Pin Assignments for Push-buttons
Description
Push-button[0]
Push-button[1]
Push-button[2]
Push-button[3]
32
I/O Standard
2.5V
2.5V
2.5V
2.5V
Table 3-4
Signal Name
LEDR[0]
LEDR[1]
LEDR[2]
LEDR[3]
LEDR[4]
LEDR[5]
LEDR[6]
LEDR[7]
LEDR[8]
LEDR[9]
LEDR[10]
LEDR[11]
LEDR[12]
LEDR[13]
LEDR[14]
LEDR[15]
LEDR[16]
LEDR[17]
LEDG[0]
LEDG[1]
LEDG[2]
LEDG[3]
LEDG[4]
LEDG[5]
LEDG[6]
LEDG[7]
LEDG[8]
FPGA Pin No.
PIN_T23
PIN_T24
PIN_V27
PIN_W25
PIN_T21
PIN_T26
PIN_R25
PIN_T27
PIN_P25
PIN_R24
PIN_P21
PIN_N24
PIN_N21
PIN_M25
PIN_K24
PIN_L25
PIN_M21
PIN_M22
PIN_AA25
PIN_AB25
PIN_F27
PIN_F26
PIN_W26
PIN_Y22
PIN_Y25
PIN_AA22
PIN_J25
Pin Assignments for LEDs
Description
LED Red[0]
LED Red[1]
LED Red[2]
LED Red[3]
LED Red[4]
LED Red[5]
LED Red[6]
LED Red[7]
LED Red[8]
LED Red[9]
LED Red[10]
LED Red[11]
LED Red[12]
LED Red[13]
LED Red[14]
LED Red[15]
LED Red[16]
LED Red[17]
LED Green[0]
LED Green[1]
LED Green[2]
LED Green[3]
LED Green[4]
LED Green[5]
LED Green[6]
LED Green[7]
LED Green[8]
I/O Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3-5 Using the 7-segment Displays
The DE2i-150 Board has eight 7-segment displays. These displays are arranged into two pairs and a
group of four, behaving the intent of displaying numbers of various sizes. As indicated in the
schematic in Figure 3-11, the seven segments (common anode) are connected to pins on Cyclone
IV GX FPGA. Applying a low logic level to a segment will light it up and applying a high logic
level turns it off.
Each segment in a display is identified by an index from 0 to 6, with the positions given in Figure
3-11. Table 3-5 shows the assignments of FPGA pins to the 7-segment displays.
33
Figure 3-11
Connections between the 7-segment display HEX0 and Cyclone IV GX FPGA
Table 3-5
Signal Name
HEX0[0]
HEX0[1]
HEX0[2]
HEX0[3]
HEX0[4]
HEX0[5]
HEX0[6]
HEX1[0]
HEX1[1]
HEX1[2]
HEX1[3]
HEX1[4]
HEX1[5]
HEX1[6]
HEX2[0]
HEX2[1]
HEX2[2]
HEX2[3]
HEX2[4]
HEX2[5]
HEX2[6]
HEX3[0]
HEX3[1]
HEX3[2]
HEX3[3]
HEX3[4]
HEX3[5]
HEX3[6]
HEX4[0]
HEX4[1]
Pin Assignments for 7-segment Displays
FPGA Pin No.
PIN_E15
PIN_E12
PIN_G11
PIN_F11
PIN_F16
PIN_D16
PIN_F14
PIN_G14
PIN_B13
PIN_G13
PIN_F12
PIN_G12
PIN_J9
PIN_G10
PIN_G8
PIN_G7
PIN_F7
PIN_AG30
PIN_F6
PIN_F4
PIN_F10
PIN_D10
PIN_D7
PIN_E6
PIN_E4
PIN_E3
PIN_D5
PIN_D4
PIN_A14
PIN_A13
Description
Seven Segment Digit 0[0]
Seven Segment Digit 0[1]
Seven Segment Digit 0[2]
Seven Segment Digit 0[3]
Seven Segment Digit 0[4]
Seven Segment Digit 0[5]
Seven Segment Digit 0[6]
Seven Segment Digit 1[0]
Seven Segment Digit 1[1]
Seven Segment Digit 1[2]
Seven Segment Digit 1[3]
Seven Segment Digit 1[4]
Seven Segment Digit 1[5]
Seven Segment Digit 1[6]
Seven Segment Digit 2[0]
Seven Segment Digit 2[1]
Seven Segment Digit 2[2]
Seven Segment Digit 2[3]
Seven Segment Digit 2[4]
Seven Segment Digit 2[5]
Seven Segment Digit 2[6]
Seven Segment Digit 3[0]
Seven Segment Digit 3[1]
Seven Segment Digit 3[2]
Seven Segment Digit 3[3]
Seven Segment Digit 3[4]
Seven Segment Digit 3[5]
Seven Segment Digit 3[6]
Seven Segment Digit 4[0]
Seven Segment Digit 4[1]
34
I/O Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
HEX4[2]
HEX4[3]
HEX4[4]
HEX4[5]
HEX4[6]
HEX5[0]
HEX5[1]
HEX5[2]
HEX5[3]
HEX5[4]
HEX5[5]
HEX5[6]
HEX6[0]
HEX6[1]
HEX6[2]
HEX6[3]
HEX6[4]
HEX6[5]
HEX6[6]
HEX7[0]
HEX7[1]
HEX7[2]
HEX7[3]
HEX7[4]
HEX7[5]
HEX7[6]
PIN_C7
PIN_C6
PIN_C5
PIN_C4
PIN_C3
PIN_D3
PIN_A10
PIN_A9
PIN_A7
PIN_A6
PIN_A11
PIN_B6
PIN_B9
PIN_B10
PIN_C8
PIN_C9
PIN_D8
PIN_D9
PIN_E9
PIN_E10
PIN_F8
PIN_F9
PIN_C10
PIN_C11
PIN_C12
PIN_D12
Seven Segment Digit 4[2]
Seven Segment Digit 4[3]
Seven Segment Digit 4[4]
Seven Segment Digit 4[5]
Seven Segment Digit 4[6]
Seven Segment Digit 5[0]
Seven Segment Digit 5[1]
Seven Segment Digit 5[2]
Seven Segment Digit 5[3]
Seven Segment Digit 5[4]
Seven Segment Digit 5[5]
Seven Segment Digit 5[6]
Seven Segment Digit 6[0]
Seven Segment Digit 6[1]
Seven Segment Digit 6[2]
Seven Segment Digit 6[3]
Seven Segment Digit 6[4]
Seven Segment Digit 6[5]
Seven Segment Digit 6[6]
Seven Segment Digit 7[0]
Seven Segment Digit 7[1]
Seven Segment Digit 7[2]
Seven Segment Digit 7[3]
Seven Segment Digit 7[4]
Seven Segment Digit 7[5]
Seven Segment Digit 7[6]
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3-6 Clock Circuitr y
The DE2i-150 board includes one oscillator that produces 50 MHz clock signal. The distributing
clock signals are connected to the FPGA that are used for clocking the user logic. The board also
includes two SMA connectors which can be used to connect an external clock source to the board or
to drive a clock signal out through the SMA connector. In addition, all these clock inputs are
connected to the phase locked loops (PLL) clock input pins of the FPGA to allow users to use these
clocks as a source clock for the PLL circuit.
The clock distribution on the DE2i-150 board is shown in Figure 3-12. The associated pin
assignments for clock inputs to FPGA I/O pins are listed in Table 3-6.
35
Figure 3-12
Table 3-6
Signal Name
CLOCK_50
CLOCK2_50
CLOCK3_50
SMA_CLKOUT
SMA_CLKIN
Block diagram of the clock distribution
Pin Assignments for Clock Inputs
FPGA Pin No.
PIN_AJ16
PIN_A15
PIN_V15
PIN_AF25
PIN_AK16
Description
50 MHz clock input
50 MHz clock input
50 MHz clock input
External (SMA) clock output
External (SMA) clock input
I/O Standard
3.3V
3.3V
2.5V
3.3V
3.3V
3-7 Using the LCD Module
The LCD module has built-in fonts and can be used to display text by sending appropriate
commands to the display controller called HD44780. Detailed information for using the display is
available in its datasheet, which can be found on the manufacturer‟s website, and from the
DE2i_150_datasheets\LCD folder on the DE2i-150 System CD. A schematic diagram of the LCD
module showing connections to the Cyclone IV GX FPGA is given in Figure 3-13. The associated
pin assignments appear in Table 3-7.
36
Figure 3-13
Connections between the LCD module and Cyclone IV GX FPGA
Table 3-7
Pin Assignments for LCD Module
Signal Name
FPGA Pin No. Description
LCD_DATA[7]
LCD_DATA[6]
LCD_DATA[5]
LCD_DATA[4]
LCD_DATA[3]
LCD_DATA[2]
LCD_DATA[1]
LCD_DATA[0]
LCD_EN
LCD_RW
LCD_RS
LCD_ON
PIN_AE4
PIN_AH4
PIN_AE3
PIN_AH2
PIN_AE5
PIN_AH3
PIN_AF3
PIN_AG4
PIN_AF4
PIN_AJ3
PIN_AG3
PIN_AF27
I/O
Standard
LCD Data[7]
3.3V
LCD Data[6]
3.3V
LCD Data[5]
3.3V
LCD Data[4]
3.3V
LCD Data[3]
3.3V
LCD Data[2]
3.3V
LCD Data[1]
3.3V
LCD Data[0]
3.3V
LCD Enable
3.3V
LCD Read/Write Select, 0 = Write, 1 = Read
3.3V
LCD Command/Data Select, 0 = Command, 1 = Data 3.3V
LCD Power ON/OFF
2.5V
3-8 High Speed Mezzanine Card
The DE2i-150 development board contains a HSMC interface to provide a mechanism for
extending the peripheral-set of a FPGA host board by means of add-on cards. This can address
37
today‟s high speed signaling requirement as well as low-speed device interface support. The HSMC
interface support JTAG, clock outputs and inputs, high speed LVDS and single-ended signaling. The
HSMC connector connects directly to the Cyclone IV GX FPGA with 82 pins. Table 3-8 shows the
maximum power consumption of the daughter card that connects to HSMC port.
Table 3-8
Power Supply of the HSMC
Supplied Voltage
Max. Current Limit
12V
1A
3.3V
1.5A
(1).Note the current levels indicated in Table 3-8 are based on 50% resource consumption. If the HSMC
interface is utilized with design resources exceeding 50%, please notify our support (support@terasic.com).
(2). There is a specially note to the J24, which can be used to control the HSMC 12V power supply. If the user sets
the J24 in the open status, the output of the HSMC 12V voltage would be cut off.
Additionally, when LVDS is used as the I/O standard of the HSMC connector, the LVDS receivers
need to assemble a 100 Ohm resistor between two input signals for each pairs as shown in Figure
3-14. Table 3-9 shows all the pin assignments of the HSMC connector.
Figure 3-14
LVDS interface on HSMC connector and Cyclone IV GX FPGA
Table 3-9
Signal Name
HSMC_CLKIN0
HSMC_CLKIN_N1
HSMC_CLKIN_N2
HSMC_CLKIN_P1
FPGA Pin
No.
PIN_K15
PIN_V30
PIN_T30
PIN_V29
Pin Assignments for HSMC connector
Description
I/O Standard
Dedicated clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
LVDS RX or CMOS I/O or differential clock input
2.5V
2.5V
2.5V
2.5V
38
HSMC_CLKIN_P2 PIN_T29
HSMC_CLKOUT0
PIN_G6
HSMC_CLKOUT_N1 PIN_AB28
HSMC_CLKOUT_N2 PIN_Y28
HSMC_CLKOUT_P1 PIN_AB27
HSMC_CLKOUT_P2 PIN_AA28
HSMC_D[0]
PIN_AC25
HSMC_D[1]
PIN_E27
HSMC_D[2]
PIN_AB26
HSMC_D[3]
PIN_E28
HSMC_RX_D_N[0] PIN_G27
HSMC_RX_D_N[1] PIN_G29
HSMC_RX_D_N[2] PIN_H27
HSMC_RX_D_N[3] PIN_K29
HSMC_RX_D_N[4] PIN_L28
HSMC_RX_D_N[5] PIN_M28
HSMC_RX_D_N[6] PIN_N30
HSMC_RX_D_N[7] PIN_P28
HSMC_RX_D_N[8] PIN_R28
HSMC_RX_D_N[9] PIN_U28
HSMC_RX_D_N[10] PIN_W28
HSMC_RX_D_N[11] PIN_W30
HSMC_RX_D_N[12] PIN_M30
HSMC_RX_D_N[13] PIN_Y27
HSMC_RX_D_N[14] PIN_AA29
HSMC_RX_D_N[15] PIN_AD28
HSMC_RX_D_N[16] PIN_AE28
HSMC_RX_D_P[0] PIN_G26
HSMC_RX_D_P[1] PIN_G28
HSMC_RX_D_P[2] PIN_J27
HSMC_RX_D_P[3] PIN_K28
HSMC_RX_D_P[4] PIN_L27
HSMC_RX_D_P[5] PIN_M27
HSMC_RX_D_P[6] PIN_N29
HSMC_RX_D_P[7] PIN_P27
HSMC_RX_D_P[8] PIN_R27
HSMC_RX_D_P[9] PIN_U27
HSMC_RX_D_P[10] PIN_W27
HSMC_RX_D_P[11] PIN_W29
HSMC_RX_D_P[12] PIN_M29
HSMC_RX_D_P[13] PIN_AA27
HSMC_RX_D_P[14] PIN_AB29
HSMC_RX_D_P[15] PIN_AD27
HSMC_RX_D_P[16] PIN_AE27
HSMC_TX_D_N[0] PIN_H28
LVDS RX or CMOS I/O or differential clock input
Dedicated clock output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O or differential clock input/output
LVDS TX or CMOS I/O
LVDS RX or CMOS I/O
LVDS TX or CMOS I/O
LVDS RX or CMOS I/O
LVDS RX bit 0n or CMOS I/O
LVDS RX bit 1n or CMOS I/O
LVDS RX bit 2n or CMOS I/O
LVDS RX bit 3n or CMOS I/O
LVDS RX bit 4n or CMOS I/O
LVDS RX bit 5n or CMOS I/O
LVDS RX bit 6n or CMOS I/O
LVDS RX bit 7n or CMOS I/O
LVDS RX bit 8n or CMOS I/O
LVDS RX bit 9n or CMOS I/O
LVDS RX bit 10n or CMOS I/O
LVDS RX bit 11n or CMOS I/O
LVDS RX bit 12n or CMOS I/O
LVDS RX bit 13n or CMOS I/O
LVDS RX bit 14n or CMOS I/O
LVDS RX bit 15n or CMOS I/O
LVDS RX bit 16n or CMOS I/O
LVDS RX bit 0 or CMOS I/O
LVDS RX bit 1 or CMOS I/O
LVDS RX bit 2 or CMOS I/O
LVDS RX bit 3 or CMOS I/O
LVDS RX bit 4 or CMOS I/O
LVDS RX bit 5 or CMOS I/O
LVDS RX bit 6 or CMOS I/O
LVDS RX bit 7 or CMOS I/O
LVDS RX bit 8 or CMOS I/O
LVDS RX bit 9 or CMOS I/O
LVDS RX bit 10 or CMOS I/O
LVDS RX bit 11 or CMOS I/O
LVDS RX bit 12 or CMOS I/O
LVDS RX bit 13 or CMOS I/O
LVDS RX bit 14 or CMOS I/O
LVDS RX bit 15 or CMOS I/O
LVDS RX bit 16 or CMOS I/O
LVDS TX bit 0n or CMOS I/O
39
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
HSMC_TX_D_N[1]
HSMC_TX_D_N[2]
HSMC_TX_D_N[3]
HSMC_TX_D_N[4]
HSMC_TX_D_N[5]
HSMC_TX_D_N[6]
HSMC_TX_D_N[7]
HSMC_TX_D_N[8]
HSMC_TX_D_N[9]
HSMC_TX_D_N[10]
HSMC_TX_D_N[11]
HSMC_TX_D_N[12]
HSMC_TX_D_N[13]
HSMC_TX_D_N[14]
HSMC_TX_D_N[15]
HSMC_TX_D_N[16]
HSMC_TX_D_P[0]
HSMC_TX_D_P[1]
HSMC_TX_D_P[2]
HSMC_TX_D_P[3]
HSMC_TX_D_P[4]
HSMC_TX_D_P[5]
HSMC_TX_D_P[6]
HSMC_TX_D_P[7]
HSMC_TX_D_P[8]
HSMC_TX_D_P[9]
HSMC_TX_D_P[10]
HSMC_TX_D_P[11]
HSMC_TX_D_P[12]
HSMC_TX_D_P[13]
HSMC_TX_D_P[14]
HSMC_TX_D_P[15]
HSMC_TX_D_P[16]
PIN_F29
PIN_D30
PIN_E30
PIN_G30
PIN_J30
PIN_K27
PIN_K30
PIN_T25
PIN_N28
PIN_V26
PIN_Y30
PIN_AC28
PIN_AD30
PIN_AE30
PIN_AH30
PIN_AG29
PIN_ J28
PIN_ F28
PIN_ D29
PIN_ F30
PIN_ H30
PIN_ J29
PIN_ K26
PIN_ L30
PIN_ U25
PIN_ N27
PIN_ V25
PIN_ AA30
PIN_ AC27
PIN_ AD29
PIN_ AE29
PIN_ AJ30
PIN_ AH29
LVDS TX bit 1n or CMOS I/O
LVDS TX bit 2n or CMOS I/O
LVDS TX bit 3n or CMOS I/O
LVDS TX bit 4n or CMOS I/O
LVDS TX bit 5n or CMOS I/O
LVDS TX bit 6n or CMOS I/O
LVDS TX bit 7n or CMOS I/O
LVDS TX bit 8n or CMOS I/O
LVDS TX bit 9n or CMOS I/O
LVDS TX bit 10n or CMOS I/O
LVDS TX bit 11n or CMOS I/O
LVDS TX bit 12n or CMOS I/O
LVDS TX bit 13n or CMOS I/O
LVDS TX bit 14n or CMOS I/O
LVDS TX bit 15n or CMOS I/O
LVDS TX bit 16n or CMOS I/O
LVDS TX bit 0 or CMOS I/O
LVDS TX bit 1 or CMOS I/O
LVDS TX bit 2 or CMOS I/O
LVDS TX bit 3 or CMOS I/O
LVDS TX bit 4 or CMOS I/O
LVDS TX bit 5 or CMOS I/O
LVDS TX bit 6 or CMOS I/O
LVDS TX bit 7 or CMOS I/O
LVDS TX bit 8 or CMOS I/O
LVDS TX bit 9 or CMOS I/O
LVDS TX bit 10 or CMOS I/O
LVDS TX bit 11 or CMOS I/O
LVDS TX bit 12 or CMOS I/O
LVDS TX bit 13 or CMOS I/O
LVDS TX bit 14 or CMOS I/O
LVDS TX bit 15 or CMOS I/O
LVDS TX bit 16 or CMOS I/O
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3-9 Using the Expansion Header
The DE2i-150 Board provides one 40-pin expansion header. The header connects directly to 36 pins
of the Cyclone IV GX FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC3P3), and two
GND pins. Figure 3-15 shows the I/O distribution of the GPIO connector. The maximum power
consumption of the daughter card that connects to GPIO port is shown in Table 3-10.
40
Figure 3-15
Table 3-10
Supplied Voltage
5V
3.3V
GPIO Pin Arrangement
Power Supply of the Expansion Header
Max. Current Limit
1A
1.5A
Each pin on the expansion headers is connected to two diodes and a resistor that provides protection
against high and low voltages. Figure 3-16 shows the protection circuitry for only one of the pin on
the header, but this circuitry is included for all 36 data pins.
Figure 3-16
Connections between the GPIO connector and Cyclone IV GX FPGA
41
Table 3-11 Pin Assignments for Expansion Headers
Signal Name
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
GPIO[4]
GPIO[5]
GPIO[6]
GPIO[7]
GPIO[8]
GPIO[9]
GPIO[10]
GPIO[11]
GPIO[12]
GPIO[13]
GPIO[14]
GPIO[15]
GPIO[16]
GPIO[17]
GPIO[18]
GPIO[19]
GPIO[20]
GPIO[21]
GPIO[22]
GPIO[23]
GPIO[24]
GPIO[25]
GPIO[26]
GPIO[27]
GPIO[28]
GPIO[29]
GPIO[30]
GPIO[31]
GPIO[32]
GPIO[33]
GPIO[34]
GPIO[35]
FPGA Pin No.
PIN_G16
PIN_F17
PIN_D18
PIN_F18
PIN_D19
PIN_K21
PIN_F19
PIN_K22
PIN_B21
PIN_C21
PIN_D22
PIN_D21
PIN_D23
PIN_D24
PIN_B28
PIN_C25
PIN_C26
PIN_D28
PIN_D25
PIN_F20
PIN_E21
PIN_F23
PIN_G20
PIN_F22
PIN_G22
PIN_G24
PIN_G23
PIN_A25
PIN_A26
PIN_A19
PIN_A28
PIN_A27
PIN_B30
PIN_AG28
PIN_AG26
PIN_Y21
Description
GPIO Connection DATA[0]
GPIO Connection DATA[1]
GPIO Connection DATA[2]
GPIO Connection DATA[3]
GPIO Connection DATA[4]
GPIO Connection DATA[5]
GPIO Connection DATA[6]
GPIO Connection DATA[7]
GPIO Connection DATA[8]
GPIO Connection DATA[9]
GPIO Connection DATA[10]
GPIO Connection DATA[11]
GPIO Connection DATA[12]
GPIO Connection DATA[13]
GPIO Connection DATA[14]
GPIO Connection DATA[15]
GPIO Connection DATA[16]
GPIO Connection DATA[17]
GPIO Connection DATA[18]
GPIO Connection DATA[19]
GPIO Connection DATA[20]
GPIO Connection DATA[21]
GPIO Connection DATA[22]
GPIO Connection DATA[23]
GPIO Connection DATA[24]
GPIO Connection DATA[25]
GPIO Connection DATA[26]
GPIO Connection DATA[27]
GPIO Connection DATA[28]
GPIO Connection DATA[29]
GPIO Connection DATA[30]
GPIO Connection DATA[31]
GPIO Connection DATA[32]
GPIO Connection DATA[33]
GPIO Connection DATA[34]
GPIO Connection DATA[35]
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3-10 Using VGA
The DE2i-150 board includes a 15-pin D-SUB connector for VGA output. The VGA
42
synchronization signals are provided directly from the Cyclone IV GX FPGA, and the Analog
Devices ADV7123 triple 10-bit high-speed video DAC (only the higher 8-bits are used) is used to
produce the analog data signals (red, green, and blue). It could support the SXGA standard
(1280*1024) with a bandwidth of 100MHz. Figure 3-17 gives the associated schematic.
Figure 3-17
Connections between FPGA and VGA
The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on
various educational website (for example, search for “VGA signal timing”). Figure 3-18 illustrates
the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An
active-low pulse of specific duration (time (a) in the figure) is applied to the horizontal
synchronization (hsync) input of the monitor, which signifies the end of one row of data and the
start of the next. The data (RGB) output to the monitor must be off (driven to 0 V) for a time period
called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c).
During the data display interval the RGB data drives each pixel in turn across the row being
displayed. Finally, there is a time period called the front porch (d) where the RGB signals must
again be off before the next hsync pulse can occur. The timing of the vertical synchronization
(vsync) is the similar as shown in Figure 3-18, except that a vsync pulse signifies the end of one
frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing).
Table 3-12 and Table 3-13 show different resolutions and durations of time periods a, b, c, and d
for both horizontal and vertical timing.
Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be
found on the manufacturer‟s website, or in the DE2i_150_datasheets\VIDEO-DAC folder on the
DE2i-150 System CD. The pin assignments between the Cyclone IV GX FPGA and the ADV7123
are listed in
Table 3-14. An example of code that drives a VGA display is described in Sections 6.2 and 6.3.
43
Note: The RGB data bus on DE2i-150 board is 8 bit instead of 10 bit on DE2/DE2-70 board.
Figure 3-18
Table 3-12
VGA horizontal timing specification
VGA Horizontal Timing Specification
VGA mode
Horizontal Timing Spec
Configuration
VGA(60Hz)
Resolution(HxV)
640x480
a(us)
3.8
b(us)
1.9
c(us)
25.4
d(us)
0.6
Pixel clock(MHz)
25
VGA(85Hz)
640x480
1.6
2.2
17.8
1.6
36
SVGA(60Hz)
800x600
3.2
2.2
20
1
40
SVGA(75Hz)
800x600
1.6
3.2
16.2
0.3
49
SVGA(85Hz)
800x600
1.1
2.7
14.2
0.6
56
XGA(60Hz)
1024x768
2.1
2.5
15.8
0.4
65
XGA(70Hz)
1024x768
1.8
1.9
13.7
0.3
75
XGA(85Hz)
1024x768
1.0
2.2
10.8
0.5
95
1280x1024(60Hz)
1280x1024
1.0
2.3
11.9
0.4
108
Table 3-13
VGA Vertical Timing Specification
VGA mode
Configuration
VGA(60Hz)
VGA(85Hz)
SVGA(60Hz)
SVGA(75Hz)
SVGA(85Hz)
XGA(60Hz)
XGA(70Hz)
XGA(85Hz)
1280x1024(60Hz)
Vertical Timing Spec
Resolution(HxV)
640x480
640x480
800x600
800x600
800x600
1024x768
1024x768
1024x768
1280x1024
a(lines)
2
3
4
3
3
6
6
3
3
44
b(lines)
33
25
23
21
27
29
29
36
38
c(lines)
480
480
600
600
600
768
768
768
1024
d(lines)
10
1
1
1
1
3
3
1
1
Pixel clock(MHz)
25
36
40
49
56
65
75
95
108
Table 3-14
Signal Name
VGA_R[0]
VGA_R[1]
VGA_R[2]
VGA_R[3]
VGA_R[4]
VGA_R[5]
VGA_R[6]
VGA_R[7]
VGA_G[0]
VGA_G[1]
VGA_G[2]
VGA_G[3]
VGA_G[4]
VGA_G[5]
VGA_G[6]
VGA_G[7]
VGA_B[0]
VGA_B[1]
VGA_B[2]
VGA_B[3]
VGA_B[4]
VGA_B[5]
VGA_B[6]
VGA_B[7]
VGA_CLK
VGA_BLANK_N
VGA_HS
VGA_VS
VGA_SYNC_N
FPGA Pin No.
PIN_A17
PIN_C18
PIN_B18
PIN_A18
PIN_E18
PIN_E19
PIN_B19
PIN_C19
PIN_D20
PIN_C20
PIN_A20
PIN_K19
PIN_A21
PIN_F21
PIN_A22
PIN_B22
PIN_E24
PIN_C24
PIN_B25
PIN_C23
PIN_F24
PIN_A23
PIN_G25
PIN_C22
PIN_D27
PIN_F25
PIN_B24
PIN_A24
PIN_AH20
Pin Assignments for ADV7123
Description
VGA Red[0]
VGA Red[1]
VGA Red[2]
VGA Red[3]
VGA Red[4]
VGA Red[5]
VGA Red[6]
VGA Red[7]
VGA Green[0]
VGA Green[1]
VGA Green[2]
VGA Green[3]
VGA Green[4]
VGA Green[5]
VGA Green[6]
VGA Green[7]
VGA Blue[0]
VGA Blue[1]
VGA Blue[2]
VGA Blue[3]
VGA Blue[4]
VGA Blue[5]
VGA Blue[6]
VGA Blue[7]
VGA Clock
VGA BLANK
VGA H_SYNC
VGA V_SYNC
VGA SYNC
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3-11 RS-232 Serial Por t
The DE2i-150 board uses the ZT3232 transceiver chip and a 9-pin DB9 connector for RS-232
communications. For detailed information on how to use the transceiver, please refer to the
datasheet, which is available on the manufacturer‟s website, or in the DE2i_150_datasheets\RS-232
folder on the DE2i-150 System CD. Figure 3-19 shows the related schematics, and Table 3-15 lists
the Cyclone IV GX FPGA pin assignments.
45
Figure 3-19
Connections between FPGA and ZT3232 (RS-232) chip
Table 3-15
Signal Name
UART_RXD
UART_TXD
UART_CTS
UART_RTS
FPGA Pin No.
PIN_B27
PIN_H24
PIN_D26
PIN_A29
RS-232 Pin Assignments
Description
UART Receiver
UART Transmitter
UART Clear to Send
UART Request to Send
I/O Standard
3.3V
3.3V
3.3V
3.3V
3-12 Gigabit Ether net Transceiver
The DE2i-150 board provides Ethernet support via a Marvell 88E1111 Ethernet PHY chip. The
88E1111 chip with integrated 10/100/1000 Mbps Gigabit Ethernet transceiver support MII/RGMII
MAC interfaces. Table 3-16 describes the default settings for both chips. Figure 3-20 shows the
connection setup between the Gigabit Ethernet PHY and FPGA.
Table 3-16
Configuration
PHYADDR[4:0]
ENA_PAUSE
ANEG[3:0]
ENA_XC
DIS_125
HWCFG[3:0]
DIS_FC
DIS_SLEEP
SEL_TWSI
INT_POL
75/50OHM
Default Configuration for Gigabit Ethernet
Description
PHY Address in MDIO/MDC Mode
Enable Pause
Auto negotiation configuration
for copper modes
Enable Crossover
Disable 125MHz clock
Hardware Configuration Mode
Disable fiber/copper interface
Energy detect
Interface select
Interrupt polarity
Termination resistance
46
Default Value
10000 for Enet0;10001 for Enet1
1-Default Register 4.11:10 to 11
1110-Auto-neg, advertise all capabilities, prefer
master
0-Disable
1-Disable 125CLK
1011/1111 RGMII to copper/GMII to copper
1-Disable
1-Disable energy detect
0-Select MDC/MDIO interface
1-INTn signal is active LOW
0-50 ohm termination for fiber
Here only RGMII and MII modes are supported on the board (The factory default mode is RGMII).
There is one jumper for each chip for switching work modes from RGMII to MII (See Figure 3-21).
You will need to perform a hardware reset after any change for enabling new settings. Table 3-17
and Table 3-17 describe the working mode settings for the PHY (U8).
In addition, it is dynamically configurable to support 10Mbps, 100Mbps (Fast Ethernet) or
1000Mbps (Gigabit Ethernet) operation using standard Cat 5e UTP cabling. The associated pin
assignments are listed in Table 3-18. For detailed information on how to use the 88E1111 refers to
its datasheet and application notes, which are available on the manufacturer‟s website.
Figure 3-20
Figure 3-21
Connections between FPGA and Ethernet
Working mode setup header for Ethernet PHY
47
Table 3-17
Jumper Settings for Working Mode of ENET0(U15)
JP1 Jumper Settings
Short Pins 1 and 2
Short Pins 2 and 3
ENET PHY Working Mode
RGMII Mode
MII Mode
Table 3-18
Signal Name
ENET_GTX_CLK
ENET_INT_N
ENET_LINK100
ENET_MDC
ENET_MDIO
ENET_RST_N
ENET_RX_CLK
ENET_RX_COL
ENET_RX_CRS
ENET_RX_DATA[0]
ENET_RX_DATA[1]
ENET_RX_DATA[2]
ENET_RX_DATA[3]
ENET_RX_DV
ENET_RX_ER
ENET_TX_CLK
ENET_TX_DATA[0]
ENET_TX_DATA[1]
ENET_TX_DATA[2]
ENET_TX_DATA[3]
ENET_TX_EN
ENET_TX_ER
FPGA Pin No.
PIN_ A12
PIN_ E16
PIN_ F5
PIN_ C16
PIN_ C15
PIN_ C14
PIN_ L15
PIN_ G15
PIN_ D6
PIN_ F15
PIN_ E13
PIN_ A5
PIN_ B7
PIN_ A8
PIN_ D11
PIN_ F13
PIN_ B12
PIN_ E7
PIN_ C13
PIN_ D15
PIN_ D14
PIN_ D13
Pin Assignments for Fast Ethernet
Description
GMII Transmit Clock 1
Interrupt open drain output 1
Parallel LED output of 100BASE-TX link 1
Management data clock reference 1
Management data 1
Hardware reset signal 1
GMII and MII receive clock 1
GMII and MII collision 1
GMII and MII carrier sense 1
GMII and MII receive data[0] 1
GMII and MII receive data[1] 1
GMII and MII receive data[2] 1
GMII and MII receive data[3] 1
GMII and MII receive data valid 1
GMII and MII receive error 1
MII transmit clock 1
MII transmit data[0] 1
MII transmit data[1] 1
MII transmit data[2] 1
MII transmit data[3] 1
GMII and MII transmit enable 1
GMII and MII transmit error 1
I/O Standard
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
3-13 TV Decoder
The DE2i-150 board is equipped with an Analog Device ADV7180 TV decoder chip. The
ADV7180 is an integrated video decoder that automatically detects and converts a standard analog
baseband television signals (NTSC, PAL, and SECAM) into 4:2:2 component video data
compatible with the 8-bit ITU-R BT.656 interface standard. The ADV7180 is compatible with a
broad range of video devices, including DVD players, tape-based sources, broadcast sources, and
security/surveillance cameras.
The registers in the TV decoder can be programmed by a serial I2C bus, which is connected to the
Cyclone IV GX FPGA as indicated in Figure 3-22. Note that the I2C address W/R of the TV
48
decoder (U6) is 0x40/0x41. The pin assignments are listed in Table 3-19. Detailed information of
the ADV7180 is available on the manufacturer‟s website, or in the DE2i_150_datasheets\TV
Decoder folder on the DE2i-150 System CD.
Figure 3-22
Connections between FPGA and TV Decoder
Table 3-19
Signal Name
TD_ DATA [0]
TD_ DATA [1]
TD_ DATA [2]
TD_ DATA [3]
TD_ DATA [4]
TD_ DATA [5]
TD_ DATA [6]
TD_ DATA [7]
TD_HS
TD_VS
TD_CLK27
TD_RESET_N
I2C_SCLK
I2C_SDAT
FPGA Pin No.
PIN_ C17
PIN_ D17
PIN_ A16
PIN_ B16
PIN_ G18
PIN_ G17
PIN_ K18
PIN_ K17
PIN_ C28
PIN_ E22
PIN_ B15
PIN_ E25
PIN_ C27
PIN_ G21
TV Decoder Pin Assignments
Description
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
TV Decoder
I2C Clock
I2C Data
49
Data[0]
Data[1]
Data[2]
Data[3]
Data[4]
Data[5]
Data[6]
Data[7]
H_SYNC
V_SYNC
Clock Input.
Reset
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3-14 Implementing a TV Encoder
Although the DE2i-150 board does not include a TV encoder chip, the ADV7123 (10-bit high-speed
triple ADCs) can be used to implement a professional-quality TV encoder with the digital
processing part implemented in the Cyclone IV GX FPGA. Figure 3-23 shows a block diagram of a
TV encoder implemented in this manner.
Figure 3-23
A TV Encoder that uses the Cyclone IV GX FPGA and the ADV7123
3-15 Using IR
The DE2i-150 provides an infrared remote-control receiver Module (model: IRM-V538N7/TR1),
whose datasheet is offered in the DE2i_150_datasheets\IR_Receiver folder on DE2i-150 system CD.
Note that for this all-in-one receiver module, it is only compatible with the 38KHz carrier Standard,
with a maximum data rate of about 4kbps for its product information. The accompanied remote
controller with an encoding chip of uPD6121G is very suitable of generating expected infrared
signals. Figure 3-24 shows the related schematic of the IR receiver, and the pin assignments of the
associated interface are listed in Table 3-20.
Figure 3-24
Connection between FPGA and IR
50
Table 3-20
Signal Name
IRDA_RXD
FPGA Pin No.
PIN_ AH28
IR Pin Assignments
Description
IR Receiver
I/O Standard
3.3V
3-16 Using SSRAM/SDRAM/FLASH/SD Card
SSRAM
The DE2i-150 board has 2MB SSRAM memory with 16-bit data width. Being featured with a
maximum performance frequency of about 125MHz under the condition of standard 3.3V single
power supply makes it suitable of dealing with high-speed media processing applications that need
ultra data throughput. The related schematic is shown in Figure 3-25.
Note: Note that the SSRAM and FLASH share the same address and data bus. User can not
use these two components at once.
Figure 3-25
Connections between FPGA and SSRAM
51
SDRAM
The board features 128MB of SDRAM, implemented using two 64MB SDRAM devices. Each
device consists of separate 16-bit data lines connected to the FPGA, and shared control and address
lines. These chips use the 3.3V LVCMOS signaling standard. Connections between FPGA and
SDRAM are shown in Figure 3-26.
Figure 3-26
Connections between FPGA and SDRAM
FLASH
The board is assembled with 8MB of flash memory using an 8-bit data bus. The device uses 3.3V
CMOS signaling standard. Because of its non-volatile property, it is usually used for storing
software binaries, images, sounds or other media. Connections between FPGA and Flash are shown
in Figure 3-27.
Note:
(1) The Flash on DE2i-150 is a new model, so it might not be working properly with Altera HAL
flash driver. In order to make the Flash function well with SOPC System, please refer to the
Section 6.2 to update the flash driver
(2) The SSRAM and FLASH share the same address and data bus. User can not use these two
components at once.
52
Figure 3-27
Connections between FPGA and Flash
SD Card
Many applications use a large external storage device, such as SD Card or CF card, for storing data.
The DE2i-150 board provides the hardware needed for SD Card access. Users can implement
custom controllers to access the SD Card in SPI mode and SD Card 4-bit or 1-bit mode. Figure
3-28 shows the related signals.
Finally, Table 3-21~Table 3-24 lists all the associated pins for interfacing FPGA respectively.
Figure 3-28
Connections between FPGA and SD Card Socket
53
Table 3-21
Signal Name
SSRAM_BE[0]
SSRAM_BE[1]
SSRAM_BE[2]
SSRAM_BE[3]
SSRAM0_CE_N
SSRAM1_CE_N
SSRAM_OE_N
SSRAM_WE_N
SSRAM_ADV_N
SSRAM_ADSP_N
SSRAM_GW_N
SSRAM_ADSC_N
SSRAM_CLK
FPGA Pin No.
PIN_AF22
PIN_AK22
PIN_AJ22
PIN_AF21
PIN_AJ21
PIN_AG23
PIN_AG24
PIN_AK24
PIN_ AH26
PIN_ AJ25
PIN_AK23
PIN_AK25
PIN_AF24
Description
SSRAM Byte Write Enable[0]
SSRAM Byte Write Enable[1]
SSRAM Byte Write Enable[2]
SSRAM Byte Write Enable[3]
SSRAM Chip Select
SSRAM Chip Select
SSRAM Output Enable
SSRAM Write Enable
SSRAM Burst Address Advance
SSRAM Processor Address Status
SSRAM Global Write Enable
SSRAM Controller Address Status
SSRAM Clock
Table 3-22
Signal Name
DRAM_ADDR[0]
DRAM_ADDR[1]
DRAM_ADDR[2]
DRAM_ADDR[3]
DRAM_ADDR[4]
DRAM_ADDR[5]
DRAM_ADDR[6]
DRAM_ADDR[7]
DRAM_ADDR[8]
DRAM_ADDR[9]
DRAM_ADDR[10]
DRAM_ADDR[11]
DRAM_ADDR[12]
DRAM_DQ[0]
DRAM_DQ[1]
DRAM_DQ[2]
DRAM_DQ[3]
DRAM_DQ[4]
DRAM_DQ[5]
DRAM_DQ[6]
DRAM_DQ[7]
DRAM_DQ[8]
DRAM_DQ[9]
DRAM_DQ[10]
DRAM_DQ[11]
DRAM_DQ[12]
DRAM_DQ[13]
FPGA Pin No.
PIN_ AG7
PIN_ AJ7
PIN_ AG8
PIN_ AH8
PIN_ AE16
PIN_ AF16
PIN_ AE14
PIN_ AE15
PIN_ AE13
PIN_ AE12
PIN_ AH6
PIN_ AE11
PIN_ AE10
PIN_ AD10
PIN_ AD9
PIN_ AE9
PIN_ AE8
PIN_ AE7
PIN_ AF7
PIN_ AF6
PIN_ AF9
PIN_ AB13
PIN_ AF13
PIN_ AF12
PIN_ AG9
PIN_ AA13
PIN_ AB11
SSRAM Pin Assignments
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
SDRAM Pin Assignments
Description
SDRAM Address[0]
SDRAM Address[1]
SDRAM Address[2]
SDRAM Address[3]
SDRAM Address[4]
SDRAM Address[5]
SDRAM Address[6]
SDRAM Address[7]
SDRAM Address[8]
SDRAM Address[9]
SDRAM Address[10]
SDRAM Address[11]
SDRAM Address[12]
SDRAM Data[0]
SDRAM Data[1]
SDRAM Data[2]
SDRAM Data[3]
SDRAM Data[4]
SDRAM Data[5]
SDRAM Data[6]
SDRAM Data[7]
SDRAM Data[8]
SDRAM Data[9]
SDRAM Data[10]
SDRAM Data[11]
SDRAM Data[12]
SDRAM Data[13]
54
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
DRAM_DQ[14]
DRAM_DQ[15]
DRAM_DQ[16]
DRAM_DQ[17]
DRAM_DQ[18]
DRAM_DQ[19]
DRAM_DQ[20]
DRAM_DQ[21]
DRAM_DQ[22]
DRAM_DQ[23]
DRAM_DQ[24]
DRAM_DQ[25]
DRAM_DQ[26]
DRAM_DQ[27]
DRAM_DQ[28]
DRAM_DQ[29]
DRAM_DQ[30]
DRAM_DQ[31]
DRAM_BA[0]
DRAM_BA[1]
DRAM_DQM[0]
DRAM_DQM[1]
DRAM_DQM[2]
DRAM_DQM[3]
DRAM_RAS_N
DRAM_CAS_N
DRAM_CKE
DRAM_CLK
DRAM_WE_N
DRAM_CS_N
PIN_ AA12
PIN_ AA15
PIN_ AH11
PIN_ AG11
PIN_ AH12
PIN_ AG12
PIN_ AH13
PIN_ AG13
PIN_ AG14
PIN_ AH14
PIN_ AH9
PIN_ AK8
PIN_ AG10
PIN_ AK7
PIN_ AH7
PIN_ AK6
PIN_ AJ6
PIN_ AK5
PIN_ AH5
PIN_ AG6
PIN_ AF10
PIN_ AB14
PIN_ AH15
PIN_ AH10
PIN_ AK4
PIN_AJ4
PIN_ AD6
PIN_ AE6
PIN_ AK3
PIN_ AG5
SDRAM Data[14]
SDRAM Data[15]
SDRAM Data[16]
SDRAM Data[17]
SDRAM Data[18]
SDRAM Data[19]
SDRAM Data[20]
SDRAM Data[21]
SDRAM Data[22]
SDRAM Data[23]
SDRAM Data[24]
SDRAM Data[25]
SDRAM Data[26]
SDRAM Data[27]
SDRAM Data[28]
SDRAM Data[29]
SDRAM Data[30]
SDRAM Data[31]
SDRAM Bank Address[0]
SDRAM Bank Address[1]
SDRAM byte Data Mask[0]
SDRAM byte Data Mask[1]
SDRAM byte Data Mask[2]
SDRAM byte Data Mask[3]
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Clock Enable
SDRAM Clock
SDRAM Write Enable
SDRAM Chip Select
Table 3-23
Signal Name
FS_ADDR[1]
FS_ADDR[2]
FS_ADDR[3]
FS_ADDR[4]
FS_ADDR[5]
FS_ADDR[6]
FS_ADDR[7]
FS_ADDR[8]
FS_ADDR[9]
FS_ADDR[10]
FS_ADDR[11]
FS_ADDR[12]
FPGA Pin No.
PIN_ AB22
PIN_ AH19
PIN_ AK19
PIN_ AJ18
PIN_ AA18
PIN_ AH18
PIN_ AK17
PIN_ Y20
PIN_ AK21
PIN_ AH21
PIN_ AG21
PIN_ AG22
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Flash Pin Assignments
Description
FLASH Address[0]
FLASH Address[1]
FLASH Address[2]
FLASH Address[3]
FLASH Address[4]
FLASH Address[5]
FLASH Address[6]
FLASH Address[7]
FLASH Address[8]
FLASH Address[9]
FLASH Address[10]
FLASH Address[11]
55
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
FS_ADDR[13]
FS_ADDR[14]
FS_ADDR[15]
FS_ADDR[16]
FS_ADDR[17]
FS_ADDR[18]
FS_ADDR[19]
FS_ADDR[20]
FS_ADDR[21]
FS_ADDR[22]
FS_ADDR[23]
FS_ADDR[24]
FS_ADDR[25]
FS_ADDR[26]
FS_DQ[0]
FS_DQ[1]
FS_DQ[2]
FS_DQ[3]
FS_DQ[4]
FS_DQ[5]
FS_DQ[6]
FS_DQ[7]
FS_DQ[8]
FS_DQ[9]
FS_DQ[10]
FS_DQ[11]
FS_DQ[12]
FS_DQ[13]
FS_DQ[14]
FS_DQ[15]
FS_DQ[16]
FS_DQ[17]
FS_DQ[18]
FS_DQ[19]
FS_DQ[20]
FS_DQ[21]
FS_DQ[22]
FS_DQ[23]
FS_DQ[24]
FS_DQ[25]
FS_DQ[26]
FS_DQ[27]
FS_DQ[28]
FS_DQ[29]
FS_DQ[30]
PIN_ AD22
PIN_ AE24
PIN_ AD23
PIN_ AB21
PIN_ AH17
PIN_ AE17
PIN_ AG20
PIN_ AK20
PIN_ AE19
PIN_ AA16
PIN_ AF15
PIN_ AG15
PIN_ Y17
PIN_ AB16
PIN_ AK29
PIN_ AE23
PIN_ AH24
PIN_ AH23
PIN_ AA21
PIN_ AE20
PIN_ Y19
PIN_ AA17
PIN_AB17
PIN_ Y18
PIN_AA20
PIN_AE21
PIN_AH22
PIN_AJ24
PIN_AE22
PIN_AK28
PIN_AK9
PIN_AJ10
PIN_AK11
PIN_AK12
PIN_AJ13
PIN_AK15
PIN_AC16
PIN_AH16
PIN_AG16
PIN_AD16
PIN_AJ15
PIN_AK14
PIN_AK13
PIN_AJ12
PIN_AK10
FLASH Address[12]
FLASH Address[13]
FLASH Address[14]
FLASH Address[15]
FLASH Address[16]
FLASH Address[17]
FLASH Address[18]
FLASH Address[19]
FLASH Address[20]
FLASH Address[21]
FLASH Address[22]
FLASH Address[23]
FLASH Address[24]
FLASH Address[25]
FLASH Data[0]
FLASH Data[1]
FLASH Data[2]
FLASH Data[3]
FLASH Data[4]
FLASH Data[5]
FLASH Data[6]
FLASH Data[7]
FLASH Data[8]
FLASH Data[9]
FLASH Data[10]
FLASH Data[11]
FLASH Data[12]
FLASH Data[13]
FLASH Data[14]
FLASH Data[15]
FLASH Data[16]
FLASH Data[17]
FLASH Data[18]
FLASH Data[19]
FLASH Data[20]
FLASH Data[21]
FLASH Data[22]
FLASH Data[23]
FLASH Data[24]
FLASH Data[25]
FLASH Data[26]
FLASH Data[27]
FLASH Data[28]
FLASH Data[29]
FLASH Data[30]
56
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
FS_DQ[31]
FL_CE_N
FL_OE_N
FL_RST_N
FL_RY
FL_WE_N
FL_WP_N
PIN_AJ9
PIN_ AG19
PIN_ AJ19
PIN_AG18
PIN_ AF19
PIN_ AG17
PIN_ AK18
FLASH Data[31]
FLASH Chip Enable
FLASH Output Enable
FLASH Reset
FLASH Ready/Busy output
FLASH Write Enable
FLASH Write Protect /Programming Acceleration
Table 3-24
Signal Name
SD_CLK
SD_CMD
SD_DAT[0]
SD_DAT[1]
SD_DAT[2]
SD_DAT[3]
SD_WP_N
FPGA Pin No.
PIN_ AH25
PIN_ AF18
PIN_ AH27
PIN_ AJ28
PIN_ AD24
PIN_ AE18
PIN_ AJ27
SD Card Socket Pin Assignments
Description
SD Clock
SD Command Line
SD Data[0]
SD Data[1]
SD Data[2]
SD Data[3]
SD Write Protect
57
I/O Standard
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
Chapter 4
DE2i-150 System Builder
This chapter describes how users can create a custom design project on the DE2i-150 board by
using DE2i-150 Software Tool – DE2i-150 System Builder.
4-1 Introduction
The DE2i-150 System Builder is a Windows based software utility, designed to assist users to create
a Quartus II project for the DE2i-150 board within minutes. The generated Quartus II project files
include:
Quartus II Project File (.qpf)
Quartus II Setting File (.qsf)
Top-Level Design File (.v)
Synopsis Design Constraints file (.sdc)
Pin Assignment Document (.htm)
By providing the above files, DE2i-150 System Builder prevents occurrence of situations that are
prone to errors when users manually edit the top-level design file or place pin assignments. The
common mistakes that users encounter are the following:
1.
Board damaged due to wrong pin/bank voltage assignments.
2.
Board malfunction caused by wrong device connections or missing pin counts for connected
ends.
3.
Performance degeneration because of improper pin assignments.
4-2 General Design Flow
This section will introduce the general design flow to build a project for the DE2i-150 board via the
DE2i-150 System Builder. The general design flow is illustrated in Figure 4-1.
Users should launch DE2i-150 System Builder and create a new project according to their design
58
requirements. When users complete the settings, the DE2i-150 System Builder will generate two
major files which include top-level design file (.v) and Quartus II setting file (.qsf).
The top-level design file contains top-level Verilog HDL wrapper for users to add their own
design/logic. The Quartus II setting file contains information such as FPGA device type, top-level
pin assignment, and I/O standard for each user-defined I/O pin.
Finally, Quartus II programmer must be used to download SOF file to DE2i-150 board using JTAG
interface.
Start
Launch
DE2-115 System Builder
Launch Quartus II and
Open Project
Create New
DE2-115 System Builder
Project
Add User Design/Logic
Generate
Quartus II Project
and Document
Compile to generate
.SOF
Configure FPGA
.QPF
.QSF
.V
.HTM
.SDC
Figure 4-1
End
The general design flow of building a design
4-3 Using DE2i-150 System Builder
This section provides the detailed procedures on how the DE2i-150 System Builder is used.
Install and launch the DE2i-150 System Builder
The DE2i-150 System Builder is located in the directory: " Tools\SystemBuilder" on the DE2i-150
System CD. Users can copy the whole folder to a host computer without installing the utility.
Launch the DE2i-150 System Builder by executing the DE2i_150_SystemBuilder.exe on the host
computer and the GUI window will appear as shown in Figure 4-2.
59
Figure 4-2
The DE2i-150 System Builder window
Input Project Name
Input project name as show in Figure 4-3.
Project Name: Type in an appropriate name here, it will automatically be assigned as the name of
your top-level design entity.
60
Figure 4-3
The DE2i-150 Board Type and Project Name
System Configuration
Under System Configuration users are given the flexibility of enabling their choice of included
components on the DE2i-150 as shown in Figure 4-4. Each component of the DE2i-150 is listed
where users can enable or disable a component according to their design by simply marking a check
or removing the check in the field provided. If the component is enabled, the DE2i-150 System
Builder will automatically generate the associated pin assignments including the pin name, pin
location, pin direction, and I/O standard.
61
Figure 4-4
System Configuration Group
GPIO Expansion
Users can connect GPIO expansion card onto GPIO header located on the DE2i-150 board as
shown in Figure 4-5. Select the appropriate daughter card you wish to include in your design from
the drop-down menu. The system builder will automatically generate the associated pin assignments
including the pin name, pin location, pin direction, and IO standard.
If a customized daughter board is used, users can select “GPIO Default” followed by changing the
pin name, pin direction, and IO standard according to the specification of the customized daughter
board.
62
Figure 4-5
GPIO Expansion Group
The “Prefix Name” is an optional feature which denotes the prefix pin name of the daughter card
assigned in your design. Users may leave this field empty.
HSMC Expansion
Users can connect HSMC-interfaced daughter cards onto HSMC located on the DE2i-150 board
shown in Figure 4-6. Select the daughter card you wish to add to your design under the appropriate
HSMC connector where the daughter card is connected to. The System Builder will automatically
generate the associated pin assignment including pin name, pin location, pin direction, and IO
standard.
63
Figure 4-6
HSMC Expansion Group
The “Prefix Name” is an optional feature that denotes the pin name of the daughter card assigned in
your design. Users may leave this field empty.
Project Setting Management
The DE2i-150 System Builder also provides functions to restore default setting, loading a setting,
and saving users‟ board configuration file shown in Figure 4-7. Users can save the current board
configuration information into a .cfg file and load it to the DE2i-150 System Builder.
64
Figure 4-7
Project Settings
Project Generation
When users press the Generate button, the DE2i-150 System Builder will generate the
corresponding Quartus II files and documents as listed in the Table 4-1:
Table 4-1
The files generated by DE2i-150 System Builder
No.
1
Filename
.v
Description
Top level Verilog HDL file for Quartus II
2
.qpf
Quartus II Project File
3
.qsf
Quartus II Setting File
4
.sdc
Synopsis Design Constraints file for Quartus II
5
.htm
Pin Assignment Document
65
Users can use Quartus II software to add custom logic into the project and compile the project to
generate the SSRAM Object File (.sof).
66
Chapter 5
Examples of Advanced Demonstrations
This chapter provides a number of examples of advanced circuits implemented on the DE2i-150
board. These circuits provide demonstrations of the major features on the board, such as its audio
and video capabilities, USB, and Ethernet connectivity. For each demonstration the Cyclone IV GX
FPGA (or EPCS64 serial EEPROM) configuration file is provided, as well as the full source code in
Verilog HDL. All of the associated files can be found in the \Demonstrations\FPGA folder on the
DE2i-150 System CD. For each demonstrations described in the following sections, the name of the
project directory for its files is given, which are subdirectories of the \Demonstrations\FPGA folder.
Installing the Demonstrations
To install the demonstrations on your computer:
Copy the directory Demonstrations into a local directory of your choice. It is important to ensure
that the path to your local directory contains no spaces – otherwise, the Nios II software will not
work. Note: Version Quartus II v9.1 SP2 or later is required for all DE2i-150 demonstrations to
support Cyclone IV GX device. Quartus II can be installed from the Altera Complete Design Suite
DVD provided.
5-1 DE2i-150 Factor y Configuration
The DE2i-150 board is shipped from the factory with a default configuration bit-stream that
demonstrates some of the basic features of the board. The setup required for this demonstration, and
the locations of its files are shown below.
Demonstration Setup, File Locations, and Instructions
Project directory: DE2i_150_Default
Bit stream used: DE2i_150_Default.sof or DE2i_150_Default.pof
Power on the DE2i-150 board, with the USB cable connected to the USB Blaster port. If
necessary (that is, if the default factory configuration of the DE2i-150 board is not currently
67
stored in EPCS64 device), download the bit stream to the board by using either JTAG or AS
programming
You should now be able to observe that the 7-segment displays are displaying a sequence of
characters, and the red and green LEDs are flashing. Also, “Welcome to the Altera DE2i-150” is
shown on the LCD display
Optionally connect a VGA display to the VGA D-SUB connector. When connected, the VGA
display should show a color picture
The Verilog HDL source code for this demonstration is provided in the DE2i_150_Default folder,
which also includes the necessary files for the corresponding Quartus II project. The top-level
Verilog HDL file, called DE2i_150_Default.v, can be used as a template for other projects, because
it defines ports that correspond to all of the user-accessible pins on the Cyclone IV GX FPGA.
5-2 TV Box Demonstration
This demonstration plays video and audio input from a DVD player using the VGA output, audio
CODEC, and one TV decoder (U6) on the DE2i-150 board. Figure 5-1 shows the block diagram of
the design. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The
TV_to_VGA block consists of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to
YUV444, YcrCb to RGB, and VGA Controller. The figure also shows the TV Decoder (ADV7180)
and the VGA DAC (ADV7123) chips used.
As soon as the bit stream is downloaded into the FPGA, the register values of the TV Decoder chip
are used to configure the TV decoder via the I2C_AV_Config block, which uses the I2C protocol to
communicate with the TV Decoder chip. Following the power-on sequence, the TV Decoder chip
will be unstable for a time period; the Lock Detector is responsible for detecting this instability.
The ITU-R 656 Decoder block extracts YcrCb 4:2:2 (YUV 4:2:2) video signals from the ITU-R 656
data stream sent from the TV Decoder. It also generates a data valid control signal indicating the
valid period of data output. Because the video signal from the TV Decoder is interlaced, we need to
perform de-interlacing on the data source. We used the SDRAM Frame Buffer and a field selection
multiplexer (MUX) which is controlled by the VGA controller to perform the de-interlacing
operation. Internally, the VGA Controller generates data request and odd/even selection signals to
the SDRAM Frame Buffer and filed selection multiplexer (MUX). The YUV422 to YUV444 block
converts the selected YcrCb 4:2:2 (YUV 4:2:2) video data to the YcrCb 4:4:4 (YUV 4:4:4) video
data format.
Finally, the YcrCb_to_RGB block converts the YcrCb data into RGB data output. The VGA
Controller block generates standard VGA synchronous signals VGA_HS and VGA_VS to enable
the display on a VGA monitor.
68
Figure 5-1
Block diagram of the TV box demonstration
Demonstration Setup, File Locations, and Instructions
Project directory: DE2i_150_TV
Bit stream used: DE2i_150_TV.sof or DE2i_150_TV.pof
Connect a DVD player‟s composite video output (yellow plug) to the Video-In RCA jack
(J12) of the DE2i-150 board. The DVD player has to be configured to provide:
o NTSC output
o 60Hz refresh rate
o 4:3 aspect ratio
o Non-progressive video
Connect the VGA output of the DE2i-150 board to a VGA monitor (both LCD and CRT type
of monitors should work)
Connect the audio output of the DVD player to the line-in port of the DE2i-150 board and
connect a speaker to the line-out port. If the audio output jacks from the DVD player are
RCA type, then an adaptor will be needed to convert to the mini-stereo plug supported on
the DE2i-150 board; this is the same type of plug supported on most computers
Load the bit stream into FPGA by execute the batch file „de2_115_tv.bat‟ under
DE2i_150_TV\demo_batch\ folder
Press KEY0 on the DE2i-150 board to reset the circuit
Note: If the HSMC loopback adapter is mounted, the I2C_SCL will be directly routed back to I2C_SDA.
Because audio chip, TV decoder chip and HSMC share one I2C bus, therefore audio and video chip won‟t
69
function correctly.
Figure 5-2 illustrates the setup for this demonstration.
Figure 5-2
The setup for the TV box demonstration
5-3 SD Card Demonstration
Many applications use a large external storage device, such as an SD Card or CF card to store data.
The DE2i-150 board provides the hardware and software needed for SD Card access. In this
demonstration we will show how to browse files stored in the root directory of an SD Card and how
to read the file contents of a specific file. The SD Card is required to be formatted as FAT File
System in advance. Long file name is supported in this demonstration.
Figure 5-3 shows the hardware system block diagram of this demonstration. The system requires a
50MHz clock provided by the board. The PLL generates a 100MHz clock for the Nios II processor
and other controllers. Four PIO pins are connected to the SD Card socket. SD 4-bit Mode is used to
access the SD Card hardware. The SD 4-bit protocol and FAT File System function are all
implemented by Nios II software. The software is stored in the on-chip memory.
70
Figure 5-3
Block Diagram of the SD Card Demonstration
Figure 5-4 shows the software stack of this demonstration. The Nios PIO block provides basic IO
functions to access hardware directly. The functions are provided from Nios II system and the
function prototype is defined in the header file . The SD Card block implements SD 4-bit
mode protocol for communication with SD Cards. The FAT File System block implements reading
function for FAT16 and FAT 32 file system. Long filename is supported. By calling the public FAT
functions, users can browse files under the root directory of the SD Card. Furthermore, users can
open a specified file and read the contents of the file.
The main block implements main control of this demonstration. When the program is executed, it
detects whether an SD Card is inserted. If an SD Card is found, it will check whether the SD Card is
formatted as FAT file system. If so, it searches all files in the root directory of the FAT file system
and displays their names in the nios2-terminal. If a text file named “test.txt” is found, it will dump
the file contents. If it successfully recognizes the FAT file system, it will turn on the green LED. On
the other hand, it will turn on the red LED if it fails to parse the FAT file system or if there is no SD
Card found in the SD Card socket of the DE2i-150 board. If users press KEY3 of the DE2i-150
board, the program will perform above process again.
71
Main
FAT File System
SD Card
Nios II PIO
Figure 5-4
Software Stack of the SD Card Demonstration
Demonstration Source Code
Project directory: DE2i_150_SD_CARD
Bit stream used: DE2i_150_SD_CARD.sof
Nios II Workspace: DE2i_150_SD_CARD\Software
Demonstration Batch File
Demo Batch File Folder: DE2i_150_SD_CARD \demo_batch
The demo batch file includes the following files:
Batch File: DE2i_150_SD_Card.bat, DE2i_150_SD_CARD_bashrc
FPGA Configure File: DE2i_150_SD_CARD.sof
Nios II Program: DE2i_150_SD_CARD.elf
Demonstration Setup
Make sure Quartus II and Nios II are installed on your PC.
Power on the DE2i-150 board.
Connect USB Blaster to the DE2i-150 board and install USB Blaster driver if necessary.
Execute the demo batch file “DE2i_150_SD_Card.bat” under the batch file folder,
DE2i_150_SD_CARD\demo_batch.
After Nios II program is downloaded and executed successfully, a prompt message will be
displayed in nios2-terminal.
Copy test files to the root directory of the SD Card.
Insert the SD Card into the SD Card socket of DE2i-150, as shown in Figure 5-5.
Press KEY3 of the DE2i-150 board to start reading SD Card.
The program will display SD Card information, as shown in Figure 5-6.
72
Figure 5-5
Insert SD Card for the SD Card Demonstration
Figure 5-6
Running results of the SD Card demonstration
5-4 IR Receiver Demonstration
In this demonstration, the key-related information that the user has pressed on the remote
controller(Figure 5-7，Table 5-1) will be displayed on the DE2i-150 board. Users only need to
73
point the remote controller to the IR receiver on DE2i-150 board and press the key. After the signal
being decoded and processed through FPGA, the related information will be displayed on the
7-segment displays in hexadecimal format, which contains Custom Code, Key Code and Inversed
Key Code. The Custom Code and Key Code are used to identify a remote controller and key on the
remote controller, respectively.
Next we will introduce how this information being decoded and then displayed in this demo.
When a key on the remote controller is pressed, the remote controller will emit a standard frame,
shown in Figure 5-8. The beginning of the frame is the lead code represents the start bit, and then is
the key-related information, and the last 1 bit end code represents the end of the frame.
Figure 5-7
Table 5-1
Key
Remote controller
Key code information for each Key on remote controller
Key Code
Key
Key Code
Key
Key Code
Key
Key Code
0x0F
0x13
0x10
0x12
0x01
0x02
0x03
0x1A
0x04
0x05
0x06
0x1E
0x07
0x08
0x09
0x1B
0x11
0x00
0x17
0x1F
0x16
0x14
0x18
0x0C
74
Lead Code 1bit
Figure 5-8
Custom Code 16bits Key Code 8bits
Inv Key Code
8bits
End
Code
1bit
The transmitting frame of the IR remote controller
After the IR receiver on DE2i-150 board receives this frame, it will directly transmit that to the
FPGA. In this demo, the IP of IR receiver controller is implemented in the FPGA. As Figure 5-9
shows, it includes Code Detector, State Machine, and Shift Register. First, the IR receiver
demodulates the signal inputs to Code Detector block .The Code Detector block will check the Lead
Code and feedback the examination result to State Machine block.
The State Machine block will change the state from IDLE to GUIDANCE once the Lead code is
detected. Once the Code Detector has detected the Custom Code status, the current state will change
from GUIDANCE to DATAREAD state. At this state, the Code Detector will save the Custom Code
and Key/Inv Key Code and output to Shift Register then displays it on 7-segment displays. Figure
5-10 shows the state shift diagram of State Machine block. Note that the input clock should be
50MHz.
Figure 5-9
The IR Receiver controller
75
Figure 5-10
State shift diagram of State Machine
We can apply the IR receiver to many applications, such as integrating to the SD Card Demo, and
you can also develop other related interesting applications with it.
Demonstration Setup, File Locations, and Instructions
Project directory: DE2i_150_IR
Bit stream used: DE2i_150_IR.sof
Load the bit stream into the FPGA by executing DE2i_150_IR\demo_batch\DE2i_150_IR.bat
file
Point the IR receiver with the remote-controller and press any button
Table 5-2 shows how the received code and key data display on eight 7-segment displays.
Table 5-2
Indicator Name
HEX0
HEX1
HEX2
HEX3
HEX4
HEX5
HEX6
HEX7
Detailed information of the indicators
Description
Inversed low byte of Key Code
Inversed high byte of Key Code
Low byte of Key Code
High byte of Key Code
Low byte of Custom Code
High byte of Custom Code
Repeated low byte of Custom Code
Repeated high byte of Custom Code
76
Figure 5-11 illustrates the setup for this demonstration.
Figure 5-11
The Setup of the IR receiver demonstration
5-5 Web Ser ver Demonstration
This design example shows a HTTP server using the sockets interface of the NicheStack™ TCP/IP
Stack Nios II Edition on MicroC/OS-II to serve web content from the DE2i-150 board. The server
can process basic requests to serve HTML, JPEG, GIF, PNG, JS, CSS, SWF, and ICO files from the
Altera read-only .zip file system. Additionally, it allows users to control various board components
from the web page.
As Part of the Nios II EDS, NicheStack™ TCP/IP Network Stack is a complete networking
software suite designed to provide an optimal solution for network related applications accompany
Nios II.
Using this demo, we assume that you already have a basic knowledge of TCP/IP protocols.
The following describes the related SOPC system. The SOPC system used in this demo contains
Nios II processor, On-Chip memory, JTAG UART, timer, Triple-Speed Ethernet, Scatter-Gather
DMA controller and other peripherals etc. In the configuration page of the Altera Triple-Speed
Ethernet Controller, users can either set the MAC interface as MII or RGMII as shown in Figure
5-12 and Figure 5-13 respectively.
77
Figure 5-12
MII interface MAC Configuration
78
Figure 5-13
RGMII interface MAC Configuration
In the MAC Options tab (See Figure 5-14), users should set up proper values for the PHY chip
88E1111. The MDIO Module should be included, as it is used to generate a 2.5MHz MDC clock for
the PHY chip from the controller's source clock(here a 100MHz clock source is expected) to divide
the MAC control register interface clock to produce the MDC clock output on the MDIO interface.
The MAC control register interface clock frequency is 100MHz and the desired MDC clock
frequency is 2.5MHz, so a host clock divisor of 40 should be used.
79
Figure 5-14
MAC Options Configuration
Once the Triple-Speed Ethernet IP configuration has been set and necessary hardware connections
have been made as shown in Figure 5-15, click on generate.
80
Figure 5-15
SOPC Builder
Figure 5-16 shows the connections for programmable 10/100Mbps Ethernet operation via MII.
Figure 5-16
PHY connected to the MAC via MII
Figure 5-17 shows the connections for programmable 10/100/1000Mbps Ethernet operation via
RGMII.
81
Figure 5-17
PHY connected to the MAC via RGMII
After the SOPC hardware project has been built, develop the SOPC software project, whose basic
architecture is shown in Figure 5-18. The top block contains the Nios II processor and the
necessary hardware to be implemented into the DE2i-150 host board. The software device drivers
contain the necessary device drivers needed for the Ethernet and other hardware components to
work. The HAL API block provides the interface for the software device drivers, while the Micro
C/OS-II provides communication services to the NicheStack™ and Web Server. The NicheStack™
TCP/IP Stack software block provides networking services to the application block where it
contains the tasks for Web Server.
82
Nios II Processor
Software Device Drivers
HAL API
MicroC/OS-II
NicheStack TCP/IP Software Component
Application Specific System Initialization
Web Server Application
Figure 5-18
Nios II Program Software Architecture
Finally, the detail descriptions for Software flow chart of the Web Server program are listed in
below:
Firstly, the Web Server program initiates the MAC and net device then calls the get_mac_addr()
function to set the MAC addresses for the PHY. Secondly, it initiates the auto-negotiation process to
check the link between PHY and gateway device. If the link exists, the PHY and gateway devices
will broadcast their transmission parameters, speed, and duplex mode. After the auto-negotiation
process has finished, it will establish the link. Thirdly, the Web Server program will prepare the
transmitting and receiving path for the link. If the path is created successfully, it will call the
get_ip_addr() function to set up the IP address for the network interface. After the IP address is
successfully distributed, the NicheStack™ TCP/IP Stack will start to run for Web Server application.
Figure 5-19 describes this demo setup and connections on DE2i-150. The Nios II processor is
running NicheStack™ on the MicroC/OS-II RTOS.
Note: your gateway should support DHCP because it uses DHCP protocol to request a valid IP from the
Gateway, or else you would need to reconfigure the system library to use static IP assignment. Furthermore, the
web server demonstration uses the RGMII or MII interface to access the TCP/IP. You can switch the MAC
Interface via JP1 and JP2 for Ethernet 0 and Ethernet 1 respectively. Table 5-3 shows the project name of web
server demonstration for each Ethernet Port and working mode.
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Table 5-3
Interface
Demo Directory Paths
Project
directory
RGMII interface
DE2i_150_Web_Server\
DE2i_150_WEB_SERVER_RGMII
MII interface
DE2i_150_Web_Server\
DE2i_150_WEB_SERVER_MII
Demonstration Setup, File Locations, and Instructions
The Following steps describe how to setup a Web Server demonstration on the ENET0 in RGMII
mode.
Copy project directory from Demonstrations\FPGA\DE2i_150_Web_Server in the DE2i-150
System CD to your host PC
Make sure the PHY device is working on RGMII mode (Short pin 1 and pin 2 of JP2)
Plug a CAT 5e cable into the Ethernet port (J11) on the DE2i-150 board (Make sure the Ethernet
cable is connected to router and the DHCP function is supported)
Execute the demo batch file “WEB_SERVER_FLASH.bat”from
DE2i_150_Web_Server\WEB_SERVER_FLASH to write web site content into flash on
DE2i-150 board
Execute the demo batch file “test.bat” from
DE2i_150_Web_Server\DE2i_150_WEB_SERVER_RGMII\demo_batch for downloading .sof
and .elf file for this demonstration
See Figure 5-20, when the message “Web Server Starting up” is shown on nios2-terminal. The
LCD on DE2i-150 board will show the valid IP address (It may take a while to get IP address
from Gateway)
Input the IP into your browser. (IP is shown on the LCD display)
You will see the brand new DE2i-150 webpage on your computer
On the web page, you could access the DE2i-150 board‟s peripherals from the left sidebar or
link to external pages from the right sidebar. Try check some LEDs on the left sidebar and then
press send will light up the specified LEDs on board. You also could send text to the LCD or set
the value for 7-segment displays on DE2i-150 board. Figure 5-21 gives a snapshot of the web
server page
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Figure 5-19
Figure 5-20
System Principle Diagram
Web Server Starting Success
85
Figure 5-21 Served web page for DE2i-150
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Chapter 6
PCI Express Introduction
This chapter describes how to use the PCI Express interface on the DE2i-150 board. A Terasic designed PCI
Express framework is provided with which users can easily communicate with FPGA from the Yocto Linux Host
system regardless of abstract PCI Express knowledge. In the framework, users can perform basic direct I/O
functions for control or data transmission, or high-speed data transmission via DMA. The discussion is based on
the assumption that the user has the basic knowledge of C language and Verilog hardware description language.
Also the user should be familiar with the Quartus II software and Linux operating system.
6-1 PCI Express System Framework
The PCI Express framework consists of two primary parts, the PCI express system in the FPGA and
the PCI express software development kit (SDK) in the host computer. The FPGA system is
developed based on the Altera Qsys Builder. In a host computer system, the PCI express SDK is
provided so the developer can easily design their applications to communicate with the FPGA.
Figure 6-1 shows the system framework.
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Figure 6-1 PCI Express System Framework
6-2FPGA: PCI Express System Design
The FPGA PCI Express system is built based on the Altera Qsys builder. In the framework, all
hardware controllers are connected with each other through the Avalon Memory-Mapped
(Avalon-MM) interface, so master controllers (e.g. DMA) can easily access slave controller (e.g.
memory) in a memory-mapped manner. Scatter-Gather DMA (SG-DMA) is included in the frame to
provide high-speed data transmission. Figure 6-2 shows the PCI Express framework under Altera
Qsys. In the framework, the host can directly control user logic (e.g. LED PIO Controllers) through
the PCI Express Avalon MM master port bar1_0. PCI Express bar2 Avalon MM master is provided
for host to configure the SG-DMA engine. The SGDMA can perform data transmission between
any two Avalon MM slave controllers.
88
Figure 6-2 PCIe Framework based on Altera Qsys
Note that in Qsys, the Avalon slave port address in the following table must be fixed, otherwise the
host SDK will not work as intended.
Avalon Slave Port
Fixed Address
pcie_ip: txs slave port
0x8000_0000
pcie_ip: cra slave port
0x0000_0000
sgdma: csr slave port
0x0000_4040
6-3 Linux Host: PCI Express System Design
The System CD contains a Linux based SDK to allow users to develop their 32-bits application
software application on 32-bits Linux.
PCI Express Software Stack
Figure 6-3 shows the software stack for the PCI Express application software on the built-in Yocto
Linux. The I/O and SG-DMA details are implemented in the share object terasic_pcie_qsys.so.
Users can develop their application software based on this shared object regardless of PCIe Express
knowledge.
89
Figure 6-3 PCI Express Software Stack on Yocto
PCI Express Driver
The PCI Express driver is located in the folder:
CDROM\Demonstrations\PCIe_SW_KIT\Linux\PCIe_DriverInstall
The folder includes:
terasic_qsys_pcie.ko: pcie kernel driver
load_terasic_qsys_pcie_driver.sh: batch to load kernel driver
de2i_150_config_file: config file for kernel driver:
unload_terasic_qsys_pcie_driver.sh: batch to unload kernel driver
If the developer modifies the PCI Express vender ID (VID) and device ID (DID) in the FPGA PCI
Express design, users need to modify the corresponding content in the de2i_150_config_file.
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Installation of PCI Express Driver
Before executing the PCI Express application, users need to load the driver first. Here are the
procedures to install the PCIe driver on a Yocto Host.
Copy the " CDROM\Demonstrations\PCIe_SW_KIT\Linux\PCIe_DriverInstall" folder to your
local disk
In the Yocto root terminal, type "sh ./load_terasic_qsys_pcie_driver.sh de2i_150_config_file"
The de2i_150_config_file configuration file is not necessary if the PCI express configuration has
not been changed in the FPGA PCI Express design.
PCI Express Library
The PCI Express driver located in the folder:
CDROM\Demonstrations\PCIe_SW_KIT\Linux\PCIe_Library
The folder includes:
terasic_pcie_qsys.so: pcie library, dynamically linked by user application
TERASIC_PCIE.h: header file for the library
PCIE.c: code body for dynamic load the shared object file terasic_pcie_qsys.so
PCIE.h: header file for the PCIe.c
The PCI Express Library is implemented as a shared object, called as terasic_pcie_qsys.so. With
the exported API in the shared object, users can easily communicate with the FPGA. The library
provides the following functions:
Direct I/O for control and data transmission
DMA for high speed data transmission
The TERASIC_PCIE.h defines the required data structure for using terasic_pcie_qsys.so. PCIE.c
and PCIE.h implement the function to dynamically load the shared object file terasic_pcie_qsys.so.
Users' application project can include the those files and calling the exported API regardless of
dynamic loading skill.
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Create a Software Application
Below lists the procedures to use the PCI Express library files in users‟ C/C++ project:
Create a project Makefile.
Copy TERASIC_PCIE.h, PCIE.c, and PCIe.h into project's folder.
Copy terasic_pcie_qsys.so to the folder where your application execution file is located.
Create your program files. Then, include "PCIE.h" in your program files, and call the PCI
Express API.
Add PCIE.c and your program files into the Makefile.
Add "-ldl" link option to the project Makefile to specify including the dynamic load library.
Call the exported API in terasic_pcie_qsys.so to implement the desired application.
Make the execution file.
terasic_pcie_qsys.so API
Using the exported software API in terasic_pcie_qsys.so, users can easily communicate with the
FPGA through the PCI Express bus. The API details are described below:
PCIE_Open
Function:
Open a specified PCIe card with vendor ID, device ID, and matched card index.
Prototype:
PCIE_HANDLE PCIE_Open(
WORD wVendorID,
WORD wDeviceID,
WORD wCardIndex);
Parameters:
wVendorID:
Specify the desired vendor ID. A zero value means to ignore the vendor ID.
wDeviceID:
Specify the desired device ID. A zero value means to ignore the device ID.
wCardIndex:
Note, these three parameters are ignored in Linux edition..
Return Value:
Return a handle to presents specified PCIe card. A positive value is return if the PCIe card is opened
successfully. A value zero means failed to connect the target PCIe card.
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This handle value is used as a parameter for other functions, e.g. PCIE_Read32.
Users need to call PCIE_Close to release handle once the handle is no more used.
PCIE_Close
Function:
Close a handle associated to the PCIe card.
Prototype:
void PCIE_Close(
PCIE_HANDLE hPCIE);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
Return Value:
None.
PCIE_Read32
Function:
Read a 32-bits data from the FPGA board.
Prototype:
bool PCIE_Read32(
PCIE_HANDLE hPCIE,
PCIE_BAR PcieBar,
PCIE_ADDRESS PcieAddress,
DWORD * pdwData);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
PcieBar:
Specify the target BAR.
PcieAddress:
Specify the target address in FPGA.
pdwData:
A buffer to retrieve the 32-bits data.
Return Value:
Return TRUE if read data is successful; otherwise FALSE is returned.
PCIE_Write32
Function:
Write a 32-bits data to the FPGA Board.
Prototype:
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bool PCIE_Write32(
PCIE_HANDLE hPCIE,
PCIE_BAR PcieBar,
PCIE_ADDRESS PcieAddress,
DWORD dwData);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
PcieBar:
Specify the target BAR.
PcieAddress:
Specify the target address in FPGA.
dwData:
Specify a 32-bits data which will be written to FPGA board.
Return Value:
Return TRUE if write data is successful; otherwise FALSE is returned.
PCIE_DmaRead
Function:
Read data from the memory-mapped memory of FPGA board in DMA function.
Prototype:
bool PCIE_DmaRead(
PCIE_HANDLE hPCIE,
PCIE_LOCAL_ADDRESS LocalAddress,
void *pBuffer,
DWORD dwBufSize
);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
LocalAddress:
Specify the target memory-mapped address in FPGA.
pBuffer:
A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger
the dwBufSize.
dwBufSize:
Specify the byte number of data retrieved from FPGA.
Return Value:
Return TRUE if read data is successful; otherwise FALSE is returned.
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PCIE_DmaWrite
Function:
Write data to the memory-mapped memory of FPGA board in DMA function.
Prototype:
bool PCIE_DmaWrite(
PCIE_HANDLE hPCIE,
PCIE_LOCAL_ADDRESS LocalAddress,
void *pData,
DWORD dwDataSize
);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
LocalAddress:
Specify the target memory mapped address in FPGA.
pData:
A pointer to a memory buffer to store the data which will be written to FPGA.
dwDataSize:
Specify the byte number of data which will be written to FPGA.
Return Value:
Return TRUE if write data is successful; otherwise FALSE is returned.
PCIE_DmaFIFORead
Function:
Read data from the memory FIFO of FPGA board in DMA function.
Prototype:
bool PCIE_DmaFIFORead(
PCIE_HANDLE hPCIE,
PCIE_LOCAL_FIFO_ID LocalFIFOId,
void *pBuffer,
DWORD dwBufSize
);
Parameters:
hPCIE:
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A PCIe handle return by PCIE_Open function.
LocalFIFOId:
Specify the target memory FIFO ID in FPGA.
pBuffer:
A pointer to a memory buffer to retrieved the data from FPGA. The size of buffer should be equal or larger
the dwBufSize.
dwBufSize:
Specify the byte number of data retrieved from FPGA.
Return Value:
Return TRUE if read data is successful; otherwise FALSE is returned.
PCIE_DmaFIFOWrite
Function:
Write data to the memory FIFO of FPGA board in DMA function.
Prototype:
bool PCIE_DmaFIFOWrite(
PCIE_HANDLE hPCIE,
PCIE_LOCAL_FIFO_ID LocalFIFOId,
void *pData,
DWORD dwDataSize
);
Parameters:
hPCIE:
A PCIe handle return by PCIE_Open function.
LocalFIFOId:
Specify the target memory FIFO ID in FPGA.
pData:
A pointer to a memory buffer to store the data which will be written to FPGA.
dwDataSize:
Specify the byte number of data which will be written to FPGA.
Return Value:
Return TRUE if write data is successful; otherwise FALSE is returned.
6-4 Operation of Yocto
This section will introduce some basic operation for Linux built by Yocto project, so users can
perform the following demo smoothly.
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Boot Operation System
Here are the procedures to boot Yocto on DE2i-150:
1.
2.
3.
4.
5.
6.
Connect USB keyboard and mouse to the USB-Port (J2 or J3)
Connect LCD display to the VGA port (J4) or HDMI Port(J1).
Make sure mSATA-Disk with pre-loaded Yocto image is installed on mini PCIe socket (J35
and J36)located in the bottom of DE2i-150 board.
Make sure the 12V Power supply is connected to DE2i-150
Clock the "Power On" button to boot the OS.
After the Yocto boot is completed, you will see the GUI as shown in Figure 6-4.
Figure 6-4 Linux built by Yocto Project
Copy file into Operation System
Here, describe how to copy files from an external USB-Storage into mSATA-Disk where Yocto is
running.
1.
2.
3.
In your working PC, copy the demo file from SYSTME CD into an USB-Storage
After Yocto booted, insert the USB-Strorage into DE2i-150 USB Port
Use mouse to click the "arrow symbol" to the "Utilites" group, then click "Termianl" icon
to enter Linux Terminal.
97
4.
5.
6.
7.
In terminal, you can type "pwd" Linux command to print current directory. "/home/root" is
expected.
Please make sure the USB-Storage had plug intoUSB Port(J2 or J3) on the DE2i-150, and
type "ls /media " to list all mounted removable device. We assume your USB-Storage is
mount with the device name "sdb1". Type "ls /media/sdb1" can list the root direct files in
your USB-Storage.
If you want copy the "PCIe_DriverInstall" folder on the USB storage into the Yocto
/home/root folder, please type "pc -r /media/sdb1/ PCIe_DriverInstall PCIe_DriverInstall".
To exit the terminal, can type "Exit". To shut down the Yocto, can type "poweroff", To
restart the Yocto, can type "reboot".
6-5Installation of PCI Express Driver
Before executing the PCI Express application, users need to load the driver first. Here are the
procedures to install PCIe driver on Yocto Host.
Copy the "CDROM\demonstrations\PCIe_SW_KIT\Linux\PCIe_DriverInstall" folder to local
disk
In Yocto terminal, type "sh ./load_terasic_qsys_pcie_driver.sh de2i_150_config_file"
The de2i_150_config_file configure file is not necessary if PCI express configuration has not been
changed in the FPGA PCI Express design.
6-6Demo: Fundamental Communication
The application reference design shows how to implement fundamental control and data transfer. In
the design, direct I/O is used to access the BUTTON and LED on the FPGA board. High-speed data
transfer is performed by SG-DMA on both On-Chip Memory and On-Chip FIFO.
Demonstration Files Location
The demo files are located in the folder:
CDROM\Demonstrations\FPGA\PCIE_Fundamental\demo_batch
The folder includes the following files:
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FPGA Configuration File: de2i_150_qsys_pcie.sof.
FPGA Programming Batch File: sof_download.bat
Host Application Software: app
Host PCI Express Shared Library: terasic_pcie_qsys.so
Demonstration Setup
1.
2.
3.
4.
5.
6.
7.
8.
Power on your DE2i-150 board.
Make sure Altera Quartus Programmer is installed on your PC
Copy all files in the demo_batch to your local hard disk in the Yocto Host.
Execute test.bat to configure FPGA by PCIE_Fundamental.sof in your PC.
In the Yocto terminal, type “reboot” to restart the Yocto Host
Load the PCI Express driver. For details, please see section 6.5 "Installation of PCI Express
Driver".
In the Yocto terminal, type "./app".
A menu will appear as shown below; select the desired function to test.
Development Tools
Quartus II 12.1
GNU GCC
Demonstration Source Code Location
Quartus Project: CDROM\Demonstration\PCIE_Fundamental
C Application Project: CDROM\Demonstration\PCIE_Fundamental\linux_app
FPGA Design
This PCI Express demonstration provides four functions:
Control LED by direct I/O
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Query button status by direct I/O
DMA write and read-back test for Memory-mapped memory
DMA write and read-back test for FIFO memory
錯誤! 找不到參照來源。 shows the block diagram in the FPGA based on the Terasic PCI Express
framework. The data transfer between On-Chip Memory/FIFO and host memory is performed by
the SG-DMA.
Figure 6-5 Block diagram of the PCI Express design in FPGA
Figure 6-5 shows the user logic components used in Altera Qsys.
100
Figure 6-6 User Logic components in Altera Qsys
Host Application Software Design
The application shows how to call the shared library terasic_pcie_qsys.so exported API under Yocto.
The application software includes the following files:
Name
Description
app.c
Main program
PCIE.c
SDK library file, implement dynamically load for the
PCIE.h
shared object library file terasic_pcie_qsys.so
TERASIC_PCIE.h
SDK library file, defines constant and data structure
Makefile
Makefile for gcc
The main program app.c includes the header file "PCIE.h" and defines the component address
according to the FPGA design.
101
Before accessing the FPGA through PCI Express, the application first calls PCIE_Open API to open
the PCI Express driver. If the return handle is zero, it means the driver cannot be accessed
successfully. In this case, please make sure:
The FPGA is configured with the associated bit-stream file and the Yocto host is rebooted.
The PCI express driver is loaded successfully.
The LED control is implemented by calling PCIE_Write32 API, as shown below:
The button status query is implemented by calling the PCIE_Read32 API, as shown below:
The memory-mapped memory read and write test is implemented by PCIE_DmaWrite and
PCIE_DmaRead API, as shown below:
The FIFO memory read and write test is implemented by PCIE_DmaFIFOWrite and
PCIE_DmaFIFORead API, as shown below:
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6-7 Demo: VGA Display
The application reference design shows how to send image data from host to FPGA, and display the
image on LCD monitor. For high-speed data transmission, SG-DMA is used to transfer image data
from Host to SDRAM. On the other hand, the Altera VIP suite is used to display the image. Here is
the image data flow:
1. The host generates pattern images and translates the image data to SDRAM via SGDMA
2. The Altera VIP Frame-Reader IP reads the image data from the SDRAM and sends data to
the Altera VIP Frame-Buffer IP
3. The Altera Frame-Buffer IP sends image data to the Altera VIP Video Output IP
4. The Altera Video Output IP sends data to the VGA encoder chip
5. The VGA encoder chip sends data to the monitor
Demonstration Files Location
The demo files are located in the folder:
CDROM\Demonstrations\FPGA\PCIE_Display\demo_batch
The folder includes following files:
1.
2.
3.
4.
FPGA Configuration File: de2i_150_qsys_pcie.sof.
FPGA Programming Batch File: sof_download.bat
Host Application Software: app
Host PCI Express Shared Library: terasic_pcie_qsys.so
Demonstration Setup
1.
2.
3.
4.
5.
6.
7.
Connect a monitor to the J8 FPGA VGA port (J18)
Power on your DE2i-150 board.
Make sure Altera Quartus Programmer is installed on your PC.
Copy all files in the demo_batch to local hard disk in the Yocto Host.
On your PC, execute test.bat to configure the FPGA via PCIE_Display.sof.
In the Yocto terminal, type “reboot” to restart the Yocto host
Load the PCI express driver. For details, please see the section "Installation of PCI Express
Driver"
8. In the Yocto terminal, type "./app", and you will see the following message in the terminal.
103
9. Also, you will see two test patterns alternatively displayed in the monitor as shown below.
Development Tools
1. Quartus II 12.1
2. GNU GCC
Demonstration Source Code Location
1. Quartus Project: CDROM\Demonstration\PCIE_Display
2. C Application Project: CDROM\Demonstration\PCIE_Display\linux_app
FPGA Design
Figure 6-7 shows the block diagram in the FPGA based on the Terasic PCI Express framework.
104
Figure 6-7 Block diagram of the PCI Express design in FPGA
Figure 6-8 shows the user logic components used in Altera Qsys.
105
Figure 6-8 User Logic components in Altera Qsys
Host Application Software Design
The application shows how to call the shared library terasic_pcie_qsys.so exported API under Yocto.
The application software includes the following files:
Name
app.c
PCIE.c
PCIE.h
TERASIC_PCIE.h
Makefile
Description
Main program
SDK library file, implement dynamically load for the
shared object library file terasic_pcie_qsys.so
SDK library file, defines constant and data structure
Makefile for gcc
The main program app.c includes the header file "PCIE.h" and defines the component address
according to the FPGA design.
106
Before accessing the FPGA through PCI Express, the application must first call PCIE_Open API to
access the PCI Express driver. If the return handle is zero, it means driver cannot be accessed
successfully. In this case, please make sure:
The FPGA is configured with the associated bit-stream file.
The PCI express driver is loaded successfully.
The Altera Frame-Reader IP can be specified with the image source address in run-time. We define
two frame source areas, frame-0 and frame-1, in SDRAM to enable smooth frame transitioning.
Here is control procedure:
1.
2.
3.
4.
5.
Send pattern image to frame-0
Configure Frame-Reader to read the source image from frame-0
Send next pattern image to frame-1
Configure Frame-Reader to read source image from frame-1
Start again from Step 1
The constant DEMO_PCIE_VGA_FRAME_ADDR is for the image frame-0 base address, and
DEMO_PCIE_VGA_FRAME_ADDR configures the SDRAM frame-1 base address.
Translating the image from host to the SDRAM is implemented by calling PCIE_DmaWrite, as
shown below:
The value of pPattern parameter can be
DEM0_PCIE_VGA_FRAME0_ADDR
107
or
DEMO_PCIE_VGA_FRAME1_ADDR.
Configuring the frame start address of the Altera Frame-Reader IP can be accomplished by calling
the PCIE_Write32. For details about the Frame-Reader IP configuration register, please refer to IP's
datasheet.
108
Chapter 7
Appendix
7-1 EPCS Programming via nios-2-flash-programmer
Before programming the EPCS via nios-2-flash-programmer, users must add an EPCS patch file
nios-flash-override.txt into the Nios II EDS folder. The patch file is available in the folder
Demonstrations\FPGA\EPCS_Patch of DE2i-150 System CD. Please copy this file to the folder
[QuartusInstalledFolder]\nios2eds\bin (e.g. C:\altera\12.1\nios2eds\bin)
If the patch file is not included into the Nios II EDS folder, an error will occur as shown in the Figure 7-1.
Figure 7-1 EPCS Message
7-2 Making HAL CFI Flash drivers to work with Spansion
F-lash
The 29GL-S FLASH, which is used onto the DE2i-150 board, is a new generation of Spansion product. It is so
new a flash device that Altera HAL flash driver cannot fully support it recently. In order to make HAL CFI Flash
drivers work with Spansion Flash you need to change the #define READ_ARRAY_MODE from (alt_u8) 0xFF to
(alt_u8) 0xF0 in the altera_avalon_cfi_flash_table.c.
For Quartus® II software version 6.1 and higher, you can locate this file at \sopc_builder_ip\altera_avalon_cfi_flash\HAL\src.
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If not to change the codes to #define READ_ARRAY_MODE (alt_u8) 0xF0 ，the operation to the Flash will be
abnormal, such as erase FLASH will not pass
7-3 Revision Histor y
Version
V1.0
V1.1
V1.2
V1.3
Change Log
Initial Version (Preliminary)
Update Ethernet demo and pin assignment of SW[3]
Add Section 6.4 "Operation of Yocto"
Modified the default demo description
7-4 Copyright Statement
Copyright © 2013 Terasic Technologies. All rights reserved.
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