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Cyclone V Device Datasheet ID: 683801 Online Version Send Feedback CV-51002 Version: 2019.11.27 Contents Contents Cyclone V Device Datasheet....................................................................................................................................................... 3 Electrical Characteristics...................................................................................................................................................... 4 Operating Conditions.................................................................................................................................................. 4 Switching Characteristics....................................................................................................................................................24 Transceiver Performance Specifications....................................................................................................................... 25 Core Performance Specifications.................................................................................................................................40 Periphery Performance..............................................................................................................................................45 HPS Specifications....................................................................................................................................................51 Configuration Specifications................................................................................................................................................ 67 POR Specifications....................................................................................................................................................68 FPGA JTAG Configuration Timing................................................................................................................................ 68 FPP Configuration Timing.......................................................................................................................................... 69 Active Serial (AS) Configuration Timing....................................................................................................................... 73 DCLK Frequency Specification in the AS Configuration Scheme....................................................................................... 75 Passive Serial (PS) Configuration Timing..................................................................................................................... 75 Initialization............................................................................................................................................................ 77 Configuration Files....................................................................................................................................................77 Minimum Configuration Time Estimation......................................................................................................................79 Remote System Upgrades......................................................................................................................................... 80 User Watchdog Internal Oscillator Frequency Specifications............................................................................................81 I/O Timing....................................................................................................................................................................... 81 Programmable IOE Delay.......................................................................................................................................... 82 Programmable Output Buffer Delay.............................................................................................................................82 Glossary.......................................................................................................................................................................... 83 Document Revision History for Cyclone V Device Datasheet.....................................................................................................89 Cyclone V Device Datasheet 2 Send Feedback 683801 | 2019.11.27 Send Feedback Cyclone V Device Datasheet This datasheet describes the electrical characteristics, switching characteristics, configuration specifications, and I/O timing for Cyclone® V devices. Cyclone V devices are offered in commercial and industrial grades. Commercial devices are offered in –C6 (fastest), –C7, and –C8 speed grades. Industrial grade devices are offered in the –I7 speed grade. Automotive devices are offered in the –A7 speed grade. Cyclone V SoC devices are also offered in a low-power variant, as indicated by the L power option in the device part number. These devices have 30% static power reduction for devices with 25K LE and 40K LE, and 20% static power reduction for devices with 85K LE and 110K LE. Note that the L power option devices are only available in –I7 speed grade, and have the equivalent operating conditions and timing specifications as the standard –I7 speed grade devices. Table 1. Low Power Variants Density Ordering Part Number (OPN) Static Power Reduction 25K LE 5CSEBA2U19I7LN 30% 5CSEBA2U23I7LN 5CSXFC2C6U23I7LN 40K LE 5CSEBA4U19I7LN 5CSEBA4U23I7LN 5CSXFC4C6U23I7LN 85K LE 5CSEBA5U19I7LN 20% 5CSEBA5U23I7LN 5CSXC5C6U23I7LN continued... Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2015 Registered Cyclone V Device Datasheet 683801 | 2019.11.27 Density Ordering Part Number (OPN) 110K LE 5CSEBA6U19I7LN Static Power Reduction 5CSEBA6U23I7LN 5CSXFC6C6U23I7LN To estimate total power consumption for a low-power device, listed in Table 1 on page 3: 1. Multiply the Total Static Power reported by the Early Power Estimator (EPE) by the appropriate scale factor: • For 25K LE and 40K LE devices, use 0.7 • For 85K LE and 110K LE devices, use 0.8 2. Add the result from Step 1 on page 4 to the Total Dynamic Power reported by the EPE. Related Information Cyclone V Device Overview Provides more information about the densities and packages of devices in the Cyclone V family. Electrical Characteristics The following sections describe the operating conditions and power consumption of Cyclone V devices. Operating Conditions Cyclone V devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of the Cyclone V devices, you must consider the operating requirements described in this section. Absolute Maximum Ratings This section defines the maximum operating conditions for Cyclone V devices. The values are based on experiments conducted with the devices and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied for these conditions. Caution: Conditions outside the range listed in the following table may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Cyclone V Device Datasheet 4 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Table 2. Absolute Maximum Ratings for Cyclone V Devices Symbol Description Minimum Maximum Unit VCC Core voltage and periphery circuitry power supply –0.5 1.43 V VCCPGM Configuration pins power supply –0.5 3.90 V VCC_AUX Auxiliary supply –0.5 3.25 V VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.90 V VCCPD I/O pre-driver power supply –0.5 3.90 V VCCIO I/O power supply –0.5 3.90 V VCCA_FPLL Phase-locked loop (PLL) analog power supply –0.5 3.25 V VCCH_GXB Transceiver high voltage power –0.5 3.25 V VCCE_GXB Transceiver power –0.5 1.50 V VCCL_GXB Transceiver clock network power –0.5 1.50 V VI DC input voltage –0.5 3.80 V VCC_HPS HPS core voltage and periphery circuitry power supply –0.5 1.43 V VCCPD_HPS HPS I/O pre-driver power supply –0.5 3.90 V VCCIO_HPS HPS I/O power supply –0.5 3.90 V VCCRSTCLK_HPS HPS reset and clock input pins power supply –0.5 3.90 V HPS PLL analog power supply –0.5 3.25 V VCC_AUX_SHARED HPS auxiliary power supply –0.5 3.25 V IOUT DC output current per pin –25 40 mA TJ Operating junction temperature –55 125 °C TSTG Storage temperature (no bias) –65 150 °C VCCPLL_HPS (1) (1) VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6 devices. Send Feedback Cyclone V Device Datasheet 5 Cyclone V Device Datasheet 683801 | 2019.11.27 Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage listed in the following table and undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns. The maximum allowed overshoot duration is specified as a percentage of high time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.00 V can only be at 4.00 V for ~15% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 1.5 years. Table 3. Maximum Allowed Overshoot During Transitions for Cyclone V Devices This table lists the maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage of device lifetime. Symbol Vi (AC) Description AC input voltage Condition (V) Overshoot Duration as % of High Time Unit 3.8 100 % 3.85 68 % 3.9 45 % 3.95 28 % 4 15 % 4.05 13 % 4.1 11 % 4.15 9 % 4.2 8 % 4.25 7 % 4.3 5.4 % 4.35 3.2 % 4.4 1.9 % 4.45 1.1 % continued... Cyclone V Device Datasheet 6 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Description Condition (V) Overshoot Duration as % of High Time Unit 4.5 0.6 % 4.55 0.4 % 4.6 0.2 % For an overshoot of 3.8 V, the percentage of high time for the overshoot can be as high as 100% over a 10-year period. Percentage of high time is calculated as ([delta T]/T) × 100. This 10-year period assumes that the device is always turned on with 100% I/O toggle rate and 50% duty cycle signal. Figure 1. Cyclone V Devices Overshoot Duration 4.1 V 4V 3.3 V DT T Recommended Operating Conditions This section lists the functional operation limits for the AC and DC parameters for Cyclone V devices. Send Feedback Cyclone V Device Datasheet 7 Cyclone V Device Datasheet 683801 | 2019.11.27 Recommended Operating Conditions Table 4. Recommended Operating Conditions for Cyclone V Devices This table lists the steady-state voltage values expected from Cyclone V devices. Power supply ramps must all be strictly monotonic, without plateaus. Symbol VCC Description Core voltage, periphery circuitry power supply, transceiver physical coding sublayer (PCS) power supply, and transceiver PCI Express* (PCIe*) hard IP digital power supply VCC_AUX (4) VCCPD VCCIO Auxiliary supply I/O pre-driver power supply I/O buffers power supply Condition Minimum(2) Typical Maximum(2) Unit Devices without internal scrubbing feature 1.07 1.1 1.13 V Devices with internal scrubbing feature (with SC suffix) (3) 1.12 1.15 1.18 V — 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.35 V 1.283 1.35 1.418 V 1.25 V 1.19 1.25 1.31 V 1.2 V 1.14 1.2 1.26 V continued... (2) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (3) The SEU internal scrubbing feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel sales representatives. (4) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25, or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V. VCCPD must be 3.3 V when VCCIO is 3.3 V. Cyclone V Device Datasheet 8 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol VCCPGM Description Configuration pins power supply Condition Minimum(2) Typical Maximum(2) Unit 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V VCCA_FPLL(5) PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCCBAT(6) Battery back-up power supply (For design security volatile key register) — 1.2 — 3.0 V VI DC input voltage — –0.5 — 3.6 V VO Output voltage — 0 — VCCIO V TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C Automotive –40 — 125 °C Standard POR 200µs — 100ms — Fast POR 200µs — 4ms — tRAMP(7) Power supply ramp time (2) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (5) PLL digital voltage is regulated from VCCA_FPLL. (6) If you do not use the design security feature in Cyclone V devices, connect VCCBAT to a 1.5-V, 2.5-V, or 3.0-V power supply. Cyclone V power-on reset (POR) circuitry monitors VCCBAT. Cyclone V devices do not exit POR if VCCBAT is not powered up. (7) This is also applicable to HPS power supply. For HPS power supply, refer to tRAMP specifications for standard POR when HPS_PORSEL = 0 and tRAMP specifications for fast POR when HPS_PORSEL = 1. Send Feedback Cyclone V Device Datasheet 9 Cyclone V Device Datasheet 683801 | 2019.11.27 Transceiver Power Supply Operating Conditions Table 5. Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices Symbol Description Minimum(8) Typical Maximum(8) Unit VCCH_GXBL Transceiver high voltage power (left side) 2.375 2.5 2.625 V VCCE_GXBL(9)(10) Transmitter and receiver power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 V VCCL_GXBL(9)(10) Clock network power (left side) 1.07/1.17 1.1/1.2 1.13/1.23 V Related Information • PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification. • 6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. (8) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (9) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (10) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Cyclone V Device Datasheet 10 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 HPS Power Supply Operating Conditions Table 6. HPS Power Supply Operating Conditions for Cyclone V SX and ST Devices This table lists the steady-state voltage and current values expected from Cyclone V system-on-a-chip (SoC) devices with Arm*-based hard processor system (HPS). Power supply ramps must all be strictly monotonic, without plateaus. Refer to the Recommended Operating Conditions for Cyclone V Devices table for the steady-state voltage values expected from the FPGA portion of the Cyclone V SoC devices. Symbol VCC_HPS VCCPD_HPS Description HPS core voltage and periphery circuitry power supply (12) VCCIO_HPS HPS I/O pre-driver power supply HPS I/O buffers power supply Condition Minimum(11) Typical Maximum(11) Unit — 1.07 1.1 1.13 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 V 1.8 V 1.71 1.8 1.89 V 1.5 V 1.425 1.5 1.575 V 1.283 1.35 1.418 V 1.2 V 1.14 1.2 1.26 V 3.3 V 3.135 3.3 3.465 V 3.0 V 2.85 3.0 3.15 V 2.5 V 2.375 2.5 2.625 1.35 V VCCRSTCLK_HPS HPS reset and clock input pins power supply (13) V continued... (11) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (12) VCCPD_HPS must be 2.5 V when VCCIO_HPS is 2.5, 1.8, 1.5, or 1.2 V. VCCPD_HPS must be 3.0 V when VCCIO_HPS is 3.0 V. VCCPD_HPS must be 3.3 V when VCCIO_HPS is 3.3 V. (13) VCCIO_HPS 1.35 V is supported for HPS row I/O bank only. Send Feedback Cyclone V Device Datasheet 11 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Description Condition Minimum(11) Typical Maximum(11) Unit 1.8 V 1.71 1.8 1.89 V VCCPLL_HPS HPS PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCC_AUX_SHARED(14) HPS auxiliary power supply — 2.375 2.5 2.625 V Related Information Recommended Operating Conditions on page 8 Provides the steady-state voltage values for the FPGA portion of the device. DC Characteristics Supply Current and Power Consumption Intel offers two ways to estimate power for your design—the Excel-based Early Power Estimator (EPE) and the Intel® Quartus® Prime Power Analyzer feature. Use the Excel-based EPE before you start your design to estimate the supply current for your design. The EPE provides a magnitude estimate of the device power because these currents vary greatly with the resources you use. The Intel Quartus Prime Power Analyzer provides better quality estimates based on the specifics of the design after you complete place-and-route. The Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities that, when combined with detailed circuit models, yields very accurate power estimates. Related Information • Early Power Estimator User Guide Provides more information about power estimation tools. • Power Analysis chapter, Intel Quartus Prime Handbook Provides more information about power estimation tools. (11) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. (14) VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6 devices. Cyclone V Device Datasheet 12 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 I/O Pin Leakage Current Table 7. I/O Pin Leakage Current for Cyclone V Devices Min Typ Max Unit II Symbol Input pin Description VI = 0 V to VCCIOMAX Condition –30 — 30 µA IOZ Tri-stated I/O pin VO = 0 V to VCCIOMAX –30 — 30 µA Bus Hold Specifications Table 8. Bus Hold Parameters for Cyclone V Devices The bus-hold trip points are based on calculated input voltages from the JEDEC* standard. Parameter Symbol Condition VCCIO (V) 1.2 1.5 1.8 Unit 2.5 3.0 3.3 Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold, low, sustaining current ISUSL VIN > VIL (max) 8 — 12 — 30 — 50 — 70 — 70 — µA Bus-hold, high, sustaining current ISUSH VIN < VIH (min) –8 — –12 — –30 — –50 — –70 — –70 — µA Bus-hold, low, overdrive current IODL 0 V < VIN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 µA Bus-hold, high, overdrive current IODH 0 V 700 Mbps 1.60 SLVS 2.375 2.5 2.625 100 VCM = 1.25 V — 0.05 — 1.80 — — — — — — Sub-LVDS 2.375 2.5 2.625 100 VCM = 1.25 V — 0.05 — 1.80 — — — — — — HiSpi 2.375 2.5 2.625 100 VCM = 1.25 V — 0.05 — 1.80 — — — — — — Related Information • AN522: Implementing Bus LVDS Interface in Supported Intel Device Families Provides more information about BLVDS interface support in Intel devices. • Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices on page 25 Provides the specifications for transmitter, receiver, and reference clock I/O pin. Switching Characteristics This section provides performance characteristics of Cyclone V core and periphery blocks. (21) The minimum VID value is applicable over the entire common mode range, VCM. (22) RL range: 90 ≤ RL ≤ 110 Ω. (23) This applies to default pre-emphasis setting only. (29) For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V to 1.95 V for data rate below 700 Mbps. Cyclone V Device Datasheet 24 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Transceiver Performance Specifications Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices Table 21. Reference Clock Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Min Supported I/O standards Input frequency from REFCLK input pins(32) Typ Max Transceiver Speed Grade 6 Min Typ 1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential Max LVPECL(31), Transceiver Speed Grade 7 Min Typ Max Unit HCSL, and LVDS — 27 — 550 27 — 550 27 — 550 MHz Rise time Measure at ±60 mV of differential signal(33) — — 400 — — 400 — — 400 ps Fall time Measure at ±60 mV of differential signal(33) — — 400 — — 400 — — 400 ps Duty cycle — 45 — 55 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 2000 200 — 2000 200 — 2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to – 0.5% — — 0 to – 0.5% — — 0 to – 0.5% — — — — 100 — — 100 — — 100 — Ω On-chip termination resistors continued... (30) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices. (31) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table. (32) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (33) REFCLK performance requires to meet transmitter REFCLK phase noise specification. Send Feedback Cyclone V Device Datasheet 25 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol/Description Condition Transceiver Speed Grade 5(30) Min Typ Min supply(34)(35) Typ Max Transceiver Speed Grade 7 Min Max — VICM (DC coupled) HCSL I/O standard for the PCIe reference clock 250 — 550 250 — 550 250 — 550 mV 10 Hz — — –50 — — –50 — — –50 dBc/Hz 100 Hz — — –80 — — –80 — — –80 dBc/Hz 1 KHz — — –110 — — –110 — — –110 dBc/Hz 10 KHz — — –120 — — –120 — — –120 dBc/Hz 100 KHz — — –120 — — –120 — — –120 dBc/Hz ≥1 MHz — — –130 — — –130 — — –130 dBc/Hz — — 2000 ±1% — — 2000 ±1% — — 2000 ±1% — Ω RREF VCCE_GXBL supply Typ Unit VICM (AC coupled) Transmitter REFCLK phase noise(36) VCCE_GXBL Max Transceiver Speed Grade 6 VCCE_GXBL supply V (30) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices. (34) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (35) Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. (36) The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12. Cyclone V Device Datasheet 26 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Table 22. Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Min Typ Max Min Typ Max Min Typ Max Unit fixedclk clock frequency PCIe Receiver Detect — 125 — — 125 — — 125 — MHz Transceiver Reconfiguration Controller IP (mgmt_clk_clk) clock frequency — 75 — 100/125(3 75 — 100/125( 75 — 100/125(3 MHz Table 23. 37) 7) Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Min Typ Supported I/O standards Data 7) rate(38) Max Transceiver Speed Grade 6 Min Typ Max Transceiver Speed Grade 7 Min Typ Max Unit 1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS — 614 — 5000/614 4(35) 614 — 3125 614 — 2500 Mbps Absolute VMAX for a receiver pin(39) — — — 1.2 — — 1.2 — — 1.2 V Absolute VMIN for a receiver pin — –0.4 — — –0.4 — — –0.4 — — V Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration — — — 1.6 — — 1.6 — — 1.6 V Maximum peak-to-peak differential input voltage VID (diff p-p) after device configuration — — — 2.2 — — 2.2 — — 2.2 V continued... (37) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled. (38) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. (39) The device cannot tolerate prolonged operation at this absolute maximum. Send Feedback Cyclone V Device Datasheet 27 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol/Description Minimum differential eye opening at the receiver serial input pins(40) Differential on-chip termination resistors VICM (AC coupled) Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit Min Typ Max Min Typ Max Min Typ Max — 110 — — 110 — — 110 — — mV 85-Ω setting — 85 — — 85 — — 85 — Ω 100-Ω setting — 100 — — 100 — — 100 — Ω 120-Ω setting — 120 — — 120 — — 120 — Ω 150-Ω setting — 150 — — 150 — — 150 — Ω 2.5 V PCML, LVPECL, and LVDS VCCE_GXBL supply(34)(35) VCCE_GXBL supply 1.5 V PCML 0.65/0.75/0.8 VCCE_GXBL supply V (41) V tLTR(42) — — — 10 — — 10 — — 10 µs tLTD (43) — — — 4 — — 4 — — 4 µs tLTD_manual(44) — — — 4 — — 4 — — 4 µs tLTR_LTD_manual(45) — 15 — — 15 — — 15 — — µs continued... (40) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. (41) The AC coupled VICM = 650 mV for Cyclone V GX and SX in PCIe mode only. The AC coupled VICM = 750mV for Cyclone V GT and ST in PCIe mode only. (42) tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset. (43) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high. (44) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is functioning in the manual mode. Cyclone V Device Datasheet 28 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol/Description Condition Transceiver Speed Grade 5(30) Min Programmable ppm detector(46) — Run length — Programmable equalization AC and DC gain Table 24. AC gain setting = 0 to 3 (47) DC gain setting = 0 to 1 Typ Max Transceiver Speed Grade 6 Min Typ Max Transceiver Speed Grade 7 Min Typ Unit Max ±62.5, 100, 125, 200, 250, 300, 500, and 1000 — — 200 — — 200 — ppm — 200 UI Refer to CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices and CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices diagrams. dB Transmitter Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Min Typ Max Supported I/O standards Transceiver Speed Grade 6 Min Typ Transceiver Speed Grade 7 Max Min Typ Max Unit 1.5 V PCML Data rate — 614 — 5000/614 4(35) 614 — 3125 614 — 2500 Mbps VOCM (AC coupled) — — 650 — — 650 — — 650 — mV 85-Ω setting — 85 — — 85 — — 85 — Ω 100-Ω setting — 100 — — 100 — — 100 — Ω 120-Ω setting — 120 — — 120 — — 120 — Ω 150-Ω setting — 150 — — 150 — — 150 — Differential on-chip termination resistors Ω continued... (45) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the CDR is functioning in the manual mode. (46) The rate matcher supports only up to ±300 parts per million (ppm). (47) The Intel Quartus Prime software allows AC gain setting = 3 for design with data rate between 614 Mbps and 1.25 Gbps only. Send Feedback Cyclone V Device Datasheet 29 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Unit Min Typ Max Min Typ Max Min Typ Max TX VCM = 0.65 V and slew rate of 15 ps — — 15 — — 15 — — 15 ps Intra-transceiver block transmitter channel-tochannel skew ×6 PMA bonded mode — — 180 — — 180 — — 180 ps Inter-transceiver block transmitter channel-tochannel skew ×N PMA bonded mode — — 500 — — 500 — — 500 ps Intra-differential pair skew Table 25. CMU PLL Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Transceiver Speed Grade 7 Min Typ Max Min Typ Max Min Typ Max Unit Supported data range — 614 — 5000/614 4(35) 614 — 3125 614 — 2500 Mbps fPLL supported data range — 614 — 3125 614 — 3125 614 — 2500 Mbps Transceiver Speed Grade 7 Unit Table 26. Transceiver-FPGA Fabric Interface Specifications for Cyclone V GX, GT, SX, and ST Devices Symbol/Description Condition Transceiver Speed Grade 5(30) Transceiver Speed Grade 6 Min Typ Max Min Typ Max Min Typ Max Interface speed (singlewidth mode) — 25 — 187.5 25 — 187.5 25 — 163.84 MHz Interface speed (doublewidth mode) — 25 — 163.84 25 — 163.84 25 — 156.25 MHz Related Information • CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain on page 32 • CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain on page 33 • PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification. Cyclone V Device Datasheet 30 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 • Send Feedback 6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. Cyclone V Device Datasheet 31 Cyclone V Device Datasheet 683801 | 2019.11.27 CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain Figure 3. Continuous Time-Linear Equalizer (CTLE) Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices Cyclone V Device Datasheet 32 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain Figure 4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain for Cyclone V GX, GT, SX, and ST Devices Send Feedback Cyclone V Device Datasheet 33 Cyclone V Device Datasheet 683801 | 2019.11.27 Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω Table 27. Typical TX VOD Setting for Cyclone V Transceiver Channels with termination of 100 Ω Symbol VOD differential peak-to-peak typical VOD Setting(48) VOD Value (mV) VOD Setting(48) VOD Value (mV) 6(49) 120 34 680 7(49) 140 35 700 8(49) 160 36 720 9 180 37 740 10 200 38 760 11 220 39 780 12 240 40 800 13 260 41 820 14 280 42 840 15 300 43 860 16 320 44 880 17 340 45 900 18 360 46 920 19 380 47 940 20 400 48 960 21 420 49 980 22 440 50 1000 23 460 51 1020 24 480 52 1040 continued... (48) Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. (49) Only valid for data rates ≤ 5 Gbps. Cyclone V Device Datasheet 34 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol VOD Setting(48) VOD Value (mV) VOD Setting(48) VOD Value (mV) 25 500 53 1060 26 520 54 1080 27 540 55 1100 28 560 56 1120 29 580 57 1140 30 600 58 1160 31 620 59 1180 32 640 60 1200 33 660 Transmitter Pre-Emphasis Levels The following table lists the simulation data on the transmitter pre-emphasis levels in dB for the first post tap under the following conditions: • Low-frequency data pattern—five 1s and five 0s • Data rate—2.5 Gbps The levels listed are a representation of possible pre-emphasis levels under the specified conditions only and the preemphasis levels may change with data pattern and data rate. Cyclone V devices only support 1st post tap pre-emphasis with the following conditions: (48) • The 1st post tap pre-emphasis settings must satisfy |B| + |C| ≤ 60 where |B| = VOD setting with termination value, RTERM = 100 Ω and |C| = 1st post tap pre-emphasis setting. • |B| – |C| > 5 for data rates < 5 Gbps and |B| – |C| > 8.25 for data rates > 5 Gbps. • (VMAX/VMIN – 1)% < 600%, where VMAX = |B| + |C| and VMIN = |B| – |C|. Convert these values to their binary equivalent form if you are using the dynamic reconfiguration mode for PMA analog controls. Send Feedback Cyclone V Device Datasheet 35 Cyclone V Device Datasheet 683801 | 2019.11.27 Exceptions for PCIe Gen2 design: • VOD setting = 50 and pre-emphasis setting = 22 are allowed for PCIe Gen2 design with transmit de-emphasis –6dB setting (pipe_txdeemp = 1’b0) using Intel PCIe Hard IP and PIPE IP cores. • VOD setting = 50 and pre-emphasis setting = 12 are allowed for PCIe Gen2 design with transmit de-emphasis –3.5dB setting (pipe_txdeemp = 1’b1) using Intel PCIe Hard IP and PIPE IP cores. For example, when VOD = 800 mV, the corresponding VOD value setting is 40. The following conditions show that the 1st post tap pre-emphasis setting = 2 is valid: • |B| + |C| ≤ 60→ 40 + 2 = 42 • |B| – |C| > 5→ 40 – 2 = 38 • (VMAX/VMIN – 1)% < 600%→ (42/38 – 1)% = 10.52% To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Cyclone V HSSI HSPICE models. Table 28. Transmitter Pre-Emphasis Levels for Cyclone V Devices Intel Quartus Prime 1st Post Tap Pre-Emphasis Setting Intel Quartus Prime VOD Setting Unit 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 0 0 0 0 0 0 0 0 dB 1 1.97 0.88 0.43 0.32 0.24 0.19 0.13 dB 2 3.58 1.67 0.95 0.76 0.61 0.5 0.41 dB 3 5.35 2.48 1.49 1.2 1 0.83 0.69 dB 4 7.27 3.31 2 1.63 1.36 1.14 0.96 dB 5 — 4.19 2.55 2.1 1.76 1.49 1.26 dB 6 — 5.08 3.11 2.56 2.17 1.83 1.56 dB 7 — 5.99 3.71 3.06 2.58 2.18 1.87 dB 8 — 6.92 4.22 3.47 2.93 2.48 2.11 dB 9 — 7.92 4.86 4 3.38 2.87 2.46 dB 10 — 9.04 5.46 4.51 3.79 3.23 2.77 dB continued... Cyclone V Device Datasheet 36 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Intel Quartus Prime 1st Post Tap Pre-Emphasis Setting Intel Quartus Prime VOD Setting Unit 10 (200 mV) 20 (400 mV) 30 (600 mV) 35 (700 mV) 40 (800 mV) 45 (900 mV) 50 (1000 mV) 11 — 10.2 6.09 5.01 4.23 3.61 — dB 12 — 11.56 6.74 5.51 4.68 3.97 — dB 13 — 12.9 7.44 6.1 5.12 4.36 — dB 14 — 14.44 8.12 6.64 5.57 4.76 — dB 15 — — 8.87 7.21 6.06 5.14 — dB 16 — — 9.56 7.73 6.49 — — dB 17 — — 10.43 8.39 7.02 — — dB 18 — — 11.23 9.03 7.52 — — dB 19 — — 12.18 9.7 8.02 — — dB 20 — — 13.17 10.34 8.59 — — dB 21 — — 14.2 11.1 — — — dB 22 — — 15.38 11.87 — — — dB 23 — — — 12.67 — — — dB 24 — — — 13.48 — — — dB 25 — — — 14.37 — — — dB 26 — — — — — — — dB 27 — — — — — — — dB 28 — — — — — — — dB 29 — — — — — — — dB 30 — — — — — — — dB 31 — — — — — — — dB Related Information SPICE Models for Intel Devices Provides the Cyclone V HSSI HSPICE models. Send Feedback Cyclone V Device Datasheet 37 Cyclone V Device Datasheet 683801 | 2019.11.27 Transceiver Compliance Specification The following table lists the physical medium attachment (PMA) specification compliance of all supported protocol for Cyclone V GX, GT, SX, and ST devices. For more information about the protocol parameter details and compliance specifications, contact your Intel Sales Representative. Table 29. Transceiver Compliance Specification for All Supported Protocol for Cyclone V GX, GT, SX, and ST Devices Protocol PCIe XAUI Serial RapidIO® (SRIO) Common Public Radio Interface (CPRI) Sub-protocol Data Rate (Mbps) PCIe Gen1 2,500 PCIe Gen2(50) 5,000 PCIe Cable 2,500 XAUI 2135 3,125 SRIO 1250 SR 1,250 SRIO 1250 LR 1,250 SRIO 2500 SR 2,500 SRIO 2500 LR 2,500 SRIO 3125 SR 3,125 SRIO 3125 LR 3,125 SRIO 5000 SR 5,000 SRIO 5000 MR 5,000 SRIO 5000 LR 5,000 CPRI E6LV 614.4 CPRI E6HV 614.4 CPRI E6LVII 614.4 continued... (50) For PCIe Gen2 sub-protocol, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which ensure full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Cyclone V Device Datasheet 38 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Protocol Sub-protocol Data Rate (Mbps) CPRI E12LV 1,228.8 CPRI E12HV 1,228.8 CPRI E12LVII 1,228.8 CPRI E24LV 2,457.6 CPRI E24LVII 2,457.6 CPRI E30LV 3,072 CPRI E30LVII 3,072 CPRI E48LVII(51) 4,915.2 CPRI E60LVII(51) 6,144 Gbps Ethernet (GbE) GbE 1250 1,250 OBSAI OBSAI 768 768 OBSAI 1536 1,536 OBSAI 3072 3,072 SDI 270 SD 270 SDI 1485 HD 1,485 SDI 2970 3G 2,970 VbyOne VbyOne 3750 3,750 HiGig+ HIGIG 3750 3,750 Serial digital interface (SDI) Related Information • (51) PCIe Supported Configurations and Placement Guidelines Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full compliance to the PCIe Gen2 transmit jitter specification. For CPRI E48LVII and E60LVII, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter. Send Feedback Cyclone V Device Datasheet 39 Cyclone V Device Datasheet 683801 | 2019.11.27 • 6.144-Gbps Support Capability in Cyclone V GT Devices Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps. Core Performance Specifications Clock Tree Specifications Table 30. Clock Tree Specifications for Cyclone V Devices Parameter Performance Unit –C6 –C7, –I7 –C8, –A7 Global clock and Regional clock 550 550 460 MHz Peripheral clock 155 155 155 MHz PLL Specifications Table 31. PLL Specifications for Cyclone V Devices This table lists the Cyclone V PLL block specifications. Cyclone V PLL block does not include HPS PLL. Symbol fIN Parameter Input clock frequency Condition –C6 speed grade –C7, –I7 speed grades Min 5 5 Typ Max Unit — 670(52) MHz — 622(52) MHz MHz MHz –C8, –A7 speed grades 5 — 500(52) fINPFD Integer input clock frequency to the phase frequency detector (PFD) — 5 — 325 fFINPFD Fractional input clock frequency to the PFD — 50 — 160 MHz continued... (52) This specification is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. Cyclone V Device Datasheet 40 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol fVCO (53) Parameter PLL voltage-controlled oscillator (VCO) operating range tEINDUTY Input clock or external feedback clock input duty cycle fOUT Output frequency for internal global or regional clock fOUT_EXT Output frequency for external clock output Condition Min Typ Max Unit –C6, –C7, –I7 speed grades 600 — 1600 MHz –C8, –A7 speed grades 600 — 1300 MHz — 40 — 60 % –C6, –C7, –I7 speed grades — — 550(54) MHz –C8, –A7 speed grades — — 460(54) MHz MHz –C6, –C7, –I7 speed grades — — 667(54) –C8, –A7 speed grades — — 533(54) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) — 45 50 55 % tFCOMP External feedback clock compensation time — — — 10 ns tDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 100 MHz tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-postscale counters/delays) — — — 1 ms fCLBW PLL closed-loop bandwidth Low — 0.3 — MHz Medium — 1.5 — MHz High(55) — 4 — MHz continued... (53) The VCO frequency reported by the Intel Quartus Prime software takes into consideration the VCO post divider value. Therefore, if the VCO post divider value is 2, the frequency reported can be lower than the fVCO specification. (54) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL. (55) High bandwidth PLL settings are not supported in external feedback mode. Send Feedback Cyclone V Device Datasheet 41 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Parameter Condition Min Typ Max Unit tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps tARESET Minimum pulse width on the areset signal — 10 — — ns FREF ≥ 100 MHz — — 0.15 UI (p-p) FREF < 100 MHz — — ±750 ps (p-p) FOUT ≥ 100 MHz — — 300 ps (p-p) FOUT < 100 MHz — — 30 mUI (p-p) (56)(57) tINCCJ tOUTPJ_DC(58) tFOUTPJ_DC(58) (58) tOUTCCJ_DC tFOUTCCJ_DC(58) tOUTPJ_IO(58)(60) Input clock cycle-to-cycle jitter Period jitter for dedicated clock output in integer PLL — 425(61), — — 42.5(61), FOUT ≥ 100 MHz — — FOUT < 100 MHz — — Period jitter for dedicated clock output in fractional PLL FOUT ≥ 100 MHz FOUT < 100 MHz Cycle-to-cycle jitter for dedicated clock output in integer PLL Cycle-to-cycle jitter for dedicated clock output in fractional PLL Period jitter for clock output on a regular I/O in integer PLL FOUT ≥ 100 MHz — — 300(59) 30(59) ps (p-p) mUI (p-p) 300 ps (p-p) 30 mUI (p-p) — 425(61), 300(59) 42.5(61), 30(59) FOUT < 100 MHz — — FOUT ≥ 100 MHz — — 650 FOUT < 100 MHz — — 65 ps (p-p) mUI (p-p) ps (p-p) mUI (p-p) continued... (56) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps. (57) FREF is fIN/N, specification applies when N = 1. (58) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Memory Output Clock Jitter Specification for Cyclone V Devices table. (59) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz. (60) External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Cyclone V Devices table. Cyclone V Device Datasheet 42 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Parameter Condition Min Typ Max Unit Period jitter for clock output on a regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) tOUTCCJ_IO(58)(60) Cycle-to-cycle jitter for clock output on regular I/O in integer PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) tFOUTCCJ_IO(58)(60)(61) Cycle-to-cycle jitter for clock output on regular I/O in fractional PLL FOUT ≥ 100 MHz — — 650 ps (p-p) FOUT < 100 MHz — — 65 mUI (p-p) Period jitter for dedicated clock output in cascaded PLLs FOUT ≥ 100 MHz — — 300 ps (p-p) FOUT < 100 MHz — — 30 mUI (p-p) tFOUTPJ_IO(58)(60)(61) tCASC_OUTPJ_DC(58)(62) tDRIFT Frequency drift after PFDENA is disabled for a duration of 100 µs — — — ±10 % dKBIT Bit number of Delta Sigma Modulator (DSM) — 8 24 32 Bits kVALUE Numerator of fraction — 128 8388608 2147483648 — fRES Resolution of VCO frequency fINPFD = 100 MHz 390625 5.96 0.023 Hz Related Information Memory Output Clock Jitter Specifications on page 49 Provides more information about the external memory interface clock output jitter specifications. (61) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz. (62) The cascaded PLL specification is only applicable with the following conditions: • Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz • Downstream PLL: Downstream PLL BW > 2 MHz Send Feedback Cyclone V Device Datasheet 43 Cyclone V Device Datasheet 683801 | 2019.11.27 DSP Block Performance Specifications Table 32. DSP Block Performance Specifications for Cyclone V Devices Mode Modes using One DSP Block Modes using Two DSP Blocks Performance Unit –C6 –C7, –I7 –C8, –A7 Independent 9 × 9 multiplication 340 300 260 MHz Independent 18 × 19 multiplication 287 250 200 MHz Independent 18 × 18 multiplication 287 250 200 MHz Independent 27 × 27 multiplication 250 200 160 MHz Independent 18 × 25 multiplication 310 250 200 MHz Independent 20 × 24 multiplication 310 250 200 MHz Two 18 × 19 multiplier adder mode 310 250 200 MHz 18 × 18 multiplier added summed with 36-bit input 310 250 200 MHz Complex 18 × 19 multiplication 310 250 200 MHz Memory Block Performance Specifications To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block clocking schemes. When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX. Table 33. Memory Block Performance Specifications for Cyclone V Devices Memory MLAB Mode Resources Used Performance Unit ALUTs Memory –C6 –C7, –I7 –C8, –A7 Single port, all supported widths 0 1 420 350 300 MHz Simple dual-port, all supported widths 0 1 420 350 300 MHz Simple dual-port with read and write at the same address 0 1 340 290 240 MHz continued... Cyclone V Device Datasheet 44 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Memory M10K Block Mode Resources Used Performance Unit ALUTs Memory –C6 –C7, –I7 –C8, –A7 ROM, all supported width 0 1 420 350 300 MHz Single-port, all supported widths 0 1 315 275 240 MHz Simple dual-port, all supported widths 0 1 315 275 240 MHz Simple dual-port with the read-during-write option set to Old Data, all supported widths 0 1 275 240 180 MHz True dual port, all supported widths 0 1 315 275 240 MHz ROM, all supported widths 0 1 315 275 240 MHz Periphery Performance This section describes the periphery performance, high-speed I/O, and external memory interface. Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. Send Feedback Cyclone V Device Datasheet 45 Cyclone V Device Datasheet 683801 | 2019.11.27 High-Speed I/O Specifications Table 34. High-Speed I/O Specifications for Cyclone V Devices When J = 1 or 2, bypass the serializer/deserializer (SERDES) block. For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network. The Cyclone V devices support the following output standards using true LVDS output buffer types on all I/O banks. • True RSDS output standard with data rates of up to 360 Mbps • True mini-LVDS output standard with data rates of up to 400 Mbps Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit Min Typ Max Min Typ Max Min Typ Max fHSCLK_in (input clock frequency) True Differential I/O Standards Clock boost factor W = 1 to 40(63) 5 — 437.5 5 — 420 5 — 320 MHz fHSCLK_in (input clock frequency) Single-Ended I/O Standards Clock boost factor W = 1 to 40(63) 5 — 320 5 — 320 5 — 275 MHz — 5 — 420 5 — 370 5 — 320 MHz SERDES factor J =4 to 10(64) (65) — 840 (65) — 740 (65) — 640 Mbps fHSCLK_OUT (output clock frequency) Transmitter True Differential I/O Standards fHSDR (data rate) continued... (63) Clock boost factor (W) is the ratio between the input data rate and the input clock rate. (64) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent and requires timing analysis. (65) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. Cyclone V Device Datasheet 46 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Condition –C6 Min –C7, –I7 –C8, –A7 Unit Typ Max Min Typ Max Min Typ Max SERDES factor J = 1 to 2, uses DDR registers (65) — (66) (65) — (66) (65) — (66) Mbps Emulated Differential I/O Standards with Three External Output Resistor Networks- fHSDR (data rate)(67) SERDES factor J = 4 to 10 (65) — 640 (65) — 640 (65) — 550 Mbps Emulated Differential I/O Standards with One External Output Resistor Network - fHSDR (data rate) SERDES factor J = 4 to 10 (65) — 170 (65) — 170 (65) — 170 Mbps tx Jitter -True Differential I/O Standards(67) Total Jitter for Data Rate, 600 Mbps – 840 Mbps — — 350 — — 380 — — 500 ps Total Jitter for Data Rate < 600Mbps — — 0.21 — — 0.23 — — 0.30 UI tx Jitter -Emulated Differential I/O Standards with Three External Output Resistor Networks Total Jitter for Data Rate < 640Mbps — — 500 — — 500 — — 500 ps tx Jitter -Emulated Differential I/O Standards with One External Output Resistor Network Total Jitter for Data Rate < 640Mbps — — 0.15 — — 0.15 — — 0.15 UI TX output clock duty cycle for both True and 45 50 55 45 50 55 45 50 55 % tDUTY continued... (66) The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing and the signal integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported. (67) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin. Send Feedback Cyclone V Device Datasheet 47 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Condition –C6 –C7, –I7 –C8, –A7 Unit Min Typ Max Min Typ Max Min Typ Max True Differential I/O Standards — — 200 — — 200 — — 200 ps Emulated Differential I/O Standards with Three External Output Resistor Networks — — 250 — — 250 — — 300 ps Emulated Differential I/O Standards with One External Output Resistor Network — — 300 — — 300 — — 300 ps True Differential I/O Standards — — 200 — — 250 — — 250 ps Emulated Differential I/O Standards with Three External Output Resistor Networks — — 300 — — 300 — — 300 ps Emulated Differential I/O Standards with One External Output Resistor Network — — 300 — — 300 — — 300 ps SERDES factor J =4 to 10(64) (65) — 875(67) (65) — 840(67) (65) — 640(67) Mbps SERDES factor J = 1 to 2, uses DDR registers (65) — (66) (65) — (66) (65) — (66) Mbps — — — 350 — — 350 — — 350 ps Emulated Differential I/O Standards tRISE and tFALL TCCS Receiver fHSDR (data rate) Sampling Window Cyclone V Device Datasheet 48 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 DLL Frequency Range Specifications Table 35. DLL Frequency Range Specifications for Cyclone V Devices Parameter DLL operating frequency range –C6 –C7, –I7 –C8 Unit 167 – 400 167 – 400 167 – 333 MHz DQS Logic Block Specifications Table 36. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Cyclone V Devices This error specification is the absolute maximum and minimum error. Number of DQS Delay Buffer –C6 –C7, –I7 –C8 Unit 2 40 80 80 ps Memory Output Clock Jitter Specifications Table 37. Memory Output Clock Jitter Specifications for Cyclone V Devices The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma. Intel recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance. Parameter Clock Network Symbol –C6 –C7, –I7 –C8 Unit Min Max Min Max Min Max Clock period jitter PHYCLK tJIT(per) –60 60 –70 70 –70 70 ps Cycle-to-cycle period jitter PHYCLK tJIT(cc) — 90 — 100 — 100 ps Send Feedback Cyclone V Device Datasheet 49 Cyclone V Device Datasheet 683801 | 2019.11.27 OCT Calibration Block Specifications Table 38. OCT Calibration Block Specifications for Cyclone V Devices Symbol Description Min Typ Max Unit OCTUSRCLK Clock required by OCT calibration blocks — — 20 MHz TOCTCAL Number of OCTUSRCLK clock cycles required for RS OCT/RT OCT calibration — 1000 — Cycles TOCTSHIFT Number of OCTUSRCLK clock cycles required for OCT code to shift out — 32 — Cycles TRS_RT Time required between the dyn_term_ctrl and oe signal transitions in a bidirectional I/O buffer to dynamically switch between RS OCT and RT OCT — 2.5 — ns Figure 5. Timing Diagram for oe and dyn_term_ctrl Signals RX Tristate TX Tristate RX oe dyn_term_ctrl TRS_RT Cyclone V Device Datasheet 50 TRS_RT Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Duty Cycle Distortion (DCD) Specifications Table 39. Worst-Case DCD on Cyclone V I/O Pins The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD. Symbol Output Duty Cycle –C6 –C7, –I7 –C8, –A7 Unit Min Max Min Max Min Max 45 55 45 55 45 55 % HPS Specifications This section provides HPS specifications and timing for Cyclone V devices. For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1. HPS Clock Performance Table 40. HPS Clock Performance for Cyclone V Devices Symbol/Description –C6 –C7, –I7 –A7 –C8 Unit mpu_base_clk (microprocessor unit clock) 925 800 700 600 MHz main_base_clk (L3/L4 interconnect clock) 400 400 350 300 MHz h2f_user0_clk 100 100 100 100 MHz h2f_user1_clk 100 100 100 100 MHz h2f_user2_clk 200 200 160 160 MHz Send Feedback Cyclone V Device Datasheet 51 Cyclone V Device Datasheet 683801 | 2019.11.27 HPS PLL Specifications HPS PLL VCO Frequency Range Table 41. HPS PLL VCO Frequency Range for Cyclone V Devices Description VCO range Speed Grade Minimum Maximum Unit –C7, –I7, –A7, –C8 320 1,600 MHz –C6 320 1,850 MHz HPS PLL Input Clock Range The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs. Related Information Clock Select, Booting and Configuration chapter Provides more information about the clock range for different values of clock select (CSEL). HPS PLL Input Jitter Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the denominator is 1 to 64. Maximum input jitter = Input clock period × Divide value (N) × 0.02 Table 42. Examples of Maximum Input Jitter Input Reference Clock Period Divide Value (N) Maximum Jitter Unit 40 ns 1 0.8 ns 40 ns 2 1.6 ns 40 ns 4 3.2 ns Cyclone V Device Datasheet 52 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Quad SPI Flash Timing Characteristics Table 43. Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices Symbol Description Min Typ Max Unit — — 108 MHz 2.32 — — ns Fclk SCLK_OUT clock frequency (External clock) Tqspi_clk QSPI_CLK clock period (Internal reference clock) Tdutycycle SCLK_OUT duty cycle 45 — 55 % Tdssfrst Output delay QSPI_SS valid before first clock edge — 1/2 cycle of SCLK_OUT — ns Tdsslst Output delay QSPI_SS valid after last clock edge –1 — 1 ns Tdio I/O data output delay –1 — 1 ns Tdin_start Input data valid start — — (2 + Rdelay) × Tqspi_clk – 7.52 (68) ns Tdin_end Input data valid end (2 + Rdelay) × Tqspi_clk – 1.21 (68) — — ns Figure 6. Quad SPI Flash Timing Diagram This timing diagram illustrates clock polarity mode 0 and clock phase mode 0. Tdsslst QSPI_SS Tdssfrst SCLK_OUT Tdio QSPI_DATA Data Out Tdin_start Data In Tdin_end (68) Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Intel provides automatic Quad SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Cyclone V Hard Processor System Technical Reference Manual. Send Feedback Cyclone V Device Datasheet 53 Cyclone V Device Datasheet 683801 | 2019.11.27 Related Information Quad SPI Flash Controller Chapter, Cyclone V Hard Processor System Technical Reference Manual Provides more information about Rdelay. SPI Timing Characteristics Table 44. SPI Master Timing Requirements for Cyclone V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Symbol Min Max Unit 16.67 — ns — ns Tclk CLK clock period Tsu SPI Master-in slave-out (MISO) setup time Th SPI MISO hold time 1 — ns Tdutycycle SPI_CLK duty cycle 45 55 % Tdssfrst Output delay SPI_SS valid before first clock edge 8 — ns Tdsslst Output delay SPI_SS valid after last clock edge 8 — ns Tdio Master-out slave-in (MOSI) output delay –1 1 ns (69) 8.35 (69) This value is based on rx_sample_dly = 1 and spi_m_clk = 120 MHz. spi_m_clk is the internal clock that is used by SPI Master to derive it’s SCLK_OUT. These timings are based on rx_sample_dly of 1. This delay can be adjusted as needed to accommodate slower response times from the slave. Note that a delay of 0 is not allowed. The setup time can be used as a reference starting point. It is very crucial to do a calibration to get the correct rx_sample_dly value because each SPI slave device may have different output delay and each application board may have different path delay. For more information about rx_sample_delay, refer to the SPI Controller chapter in the Hard Processor System Technical Reference Manual. Cyclone V Device Datasheet 54 Description Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 7. SPI Master Timing Diagram Tdsslst SPI_SS SPI_CLK (scpol = 0) Tdssfrst SPI_CLK (scpol = 1) Tdio SPI_MOSI (scph = 1) Tsu Th SPI_MISO (scph = 1) Tdio SPI_MOSI (scph = 0) Tsu Th SPI_MISO (scph = 0) Table 45. SPI Slave Timing Requirements for Cyclone V Devices The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode. Description Symbol Min Max Unit Tclk CLK clock period 20 — ns Ts MOSI Setup time 5 — ns Th MOSI Hold time 5 — ns Tsuss Setup time SPI_SS valid before first clock edge 8 — ns Thss Hold time SPI_SS valid after last clock edge 8 — ns Td MISO output delay — 6 ns Send Feedback Cyclone V Device Datasheet 55 Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 8. SPI Slave Timing Diagram Thss SPI_SS Tsuss SPI_CLK (scpol = 0) SPI_CLK (scpol = 1) Td SPI_MISO (scph = 1) Ts Th SPI_MOSI (scph = 1) Td SPI_MISO (scph = 0) Ts Th SPI_MOSI (scph = 0) Related Information SPI Controller, Cyclone V Hard Processor System Technical Reference Manual Provides more information about rx_sample_delay. Cyclone V Device Datasheet 56 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 SD/MMC Timing Characteristics Table 46. Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices After power up or cold reset, the Boot ROM uses drvsel = 3 and smplsel = 0 to execute the code. At the same time, the SD/MMC controller enters the Identification Phase followed by the Data Phase. During this time, the value of interface output clock SDMMC_CLK_OUT changes from a maximum of 400 kHz (Identification Phase) up to a maximum of 12.5 MHz (Data Phase), depending on the internal reference clock SDMMC_CLK and the CSEL setting. The value of SDMMC_CLK is based on the external oscillator frequency and has a maximum value of 50 MHz. After the Boot ROM code exits and control is passed to the preloader, software can adjust the value of drvsel and smplsel via the system manager. drvsel can be set from 1 to 7 and smplsel can be set from 0 to 7. While the preloader is executing, the values for SDMMC_CLK and SDMMC_CLK_OUT increase to a maximum of 200 MHz and 50 MHz respectively. Symbol Min Max Unit SDMMC_CLK clock period (Identification mode) 20 — ns SDMMC_CLK clock period (Default speed mode) 5 — ns SDMMC_CLK clock period (High speed mode) 5 — ns 2500 — ns SDMMC_CLK_OUT clock period (Default speed mode) 40 — ns SDMMC_CLK_OUT clock period (High speed mode) 20 — ns Tdutycycle SDMMC_CLK_OUT duty cycle 45 55 % Td SDMMC_CMD/SDMMC_D output delay (Tsdmmc_clk × drvsel)/2 – 1.23 (Tsdmmc_clk × drvsel)/2 + 1.69 (70) ns Tsu Input setup time 1.05 – (Tsdmmc_clk × smplsel)/2 — ns Th Input hold time — ns Tsdmmc_clk (internal reference clock) Tsdmmc_clk_out (interface output clock) Description SDMMC_CLK_OUT clock period (Identification mode) (70) (71) (70) drvsel is the drive clock phase shift select value. (71) smplsel is the sample clock phase shift select value. Send Feedback (Tsdmmc_clk × smplsel)/2 (71) Cyclone V Device Datasheet 57 Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 9. SD/MMC Timing Diagram SDMMC_CLK_OUT Td SDMMC_CMD & SDMMC_D (Out) Command/Data Out Tsu Th SDMMC_CMD & SDMMC_D (In) Command/Data In Related Information Booting and Configuration Chapter, Cyclone V Hard Processor System Technical Reference Manual Provides more information about CSEL pin settings in the SD/MMC Controller CSEL Pin Settings table. USB Timing Characteristics PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Table 47. USB Timing Requirements for Cyclone V Devices Symbol Min Typ Max Unit — 16.67 — ns 4.4 — 11 ns Tclk USB CLK clock period Td CLK to USB_STP/USB_DATA[7:0] output delay Tsu Setup time for USB_DIR/USB_NXT/USB_DATA[7:0] 2 — — ns Th Hold time for USB_DIR/USB_NXT/USB_DATA[7:0] 1 — — ns Cyclone V Device Datasheet 58 Description Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 10. USB Timing Diagram USB_CLK USB_STP USB_DATA[7:0] Td From PHY To PHY Tsu Th USB_DIR & USB_NXT Ethernet Media Access Controller (EMAC) Timing Characteristics Table 48. Reduced Gigabit Media Independent Interface (RGMII) TX Timing Requirements for Cyclone V Devices Symbol Description Min Typ Max Unit Tclk (1000Base-T) TX_CLK clock period — 8 — ns Tclk (100Base-T) TX_CLK clock period — 40 — ns Tclk (10Base-T) TX_CLK clock period — 400 — ns Tdutycycle TX_CLK duty cycle 45 — 55 % Td TX_CLK to TXD/TX_CTL output data delay –0.85 — 0.15 ns Figure 11. RGMII TX Timing Diagram TX_CLK TX_D[3:0] Td TX_CTL Send Feedback Cyclone V Device Datasheet 59 Cyclone V Device Datasheet 683801 | 2019.11.27 Table 49. RGMII RX Timing Requirements for Cyclone V Devices Symbol Description Min Typ Unit Tclk (1000Base-T) RX_CLK clock period — 8 ns Tclk (100Base-T) RX_CLK clock period — 40 ns Tclk (10Base-T) RX_CLK clock period — 400 ns Tsu RX_D/RX_CTL setup time 1 — ns Th RX_D/RX_CTL hold time 1 — ns Figure 12. RGMII RX Timing Diagram RX_CLK Tsu Th RX_D[3:0] RX_CTL Table 50. Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices Symbol Min Typ Max Unit Tclk MDC clock period — 400 — ns Td MDC to MDIO output data delay 10 — 20 ns Ts Setup time for MDIO data 10 — — ns Th Hold time for MDIO data 0 — — ns Cyclone V Device Datasheet 60 Description Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 13. MDIO Timing Diagram MDC Td MDIO_OUT Tsu Th MDIO_IN I2C Timing Characteristics Table 51. I2C Timing Requirements for Cyclone V Devices Symbol Description Standard Mode Fast Mode Unit Min Max Min Max Tclk Serial clock (SCL) clock period 10 — 2.5 — µs Tclkhigh SCL high time 4.7 — 0.6 — µs Tclklow SCL low time 4 — 1.3 — µs Ts Setup time for serial data line (SDA) data to SCL 0.25 — 0.1 — µs Th Hold time for SCL to SDA data 0 3.45 0 0.9 µs Td SCL to SDA output data delay — 0.2 — 0.2 µs Tsu_start Setup time for a repeated start condition 4.7 — 0.6 — µs Thd_start Hold time for a repeated start condition 4 — 0.6 — µs Tsu_stop Setup time for a stop condition 4 — 0.6 — µs Send Feedback Cyclone V Device Datasheet 61 Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 14. I2C Timing Diagram I2C_SCL Td Ts Tsu_start Thd_start Data Out I2C_SDA Tsu_stop Th Data In NAND Timing Characteristics Table 52. NAND ONFI 1.0 Timing Requirements for Cyclone V Devices The NAND controller supports Open NAND FLASH Interface (ONFI) 1.0 Mode 5 timing as well as legacy NAND devices. This table lists the requirements for ONFI 1.0 mode 5 timing. The HPS NAND controller can meet this timing by programming the C4 output of the main HPS PLL and timing registers provided in the NAND controller. Symbol Description (72) Write enable pulse width (72) Write enable hold time Twp Twh (72) Trp Treh(72) (72) Read enable pulse width Read enable hold time Tclesu Command latch enable to write enable setup time Tcleh(72) Command latch enable to write enable hold time Tcesu(72) Chip enable to write enable setup time Tceh(72) Chip enable to write enable hold time Talesu(72) Address latch enable to write enable setup time Taleh(72) Address latch enable to write enable hold time Tdsu(72) Data to write enable setup time Tdh(72) Data to write enable hold time Min Max Unit 10 — ns 7 — ns 10 — ns 7 — ns 10 — ns 5 — ns 15 — ns 5 — ns 10 — ns 5 — ns 10 — ns 5 — ns continued... (72) Timing of the NAND interface is controlled through the NAND configuration registers. Cyclone V Device Datasheet 62 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Description Min Max Unit Tcea Chip enable to data access time — 25 ns Trea Read enable to data access time — 16 ns Trhz Read enable to data high impedance — 100 ns Trr Ready to read enable low 20 — ns Figure 15. NAND Command Latch Timing Diagram NAND_CLE NAND_CE Tclesu Tcesu Tcleh Twp Tceh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Send Feedback Tdh Command Cyclone V Device Datasheet 63 Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 16. NAND Address Latch Timing Diagram NAND_CLE NAND_CE Tcesu Tclesu Twp Twh NAND_WE Talesu Taleh NAND_ALE Tdsu NAND_DQ[7:0] Cyclone V Device Datasheet 64 Tdh Address Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 17. NAND Data Write Timing Diagram NAND_CLE NAND_CE Tcleh Twp Tceh NAND_WE Talesu NAND_ALE Tdsu Tdh NAND_DQ[7:0] Send Feedback Din Cyclone V Device Datasheet 65 Cyclone V Device Datasheet 683801 | 2019.11.27 Figure 18. NAND Data Read Timing Diagram Tcea NAND_CE Trr Trp Treh NAND_RE Trhz NAND_RB Trea NAND_DQ[7:0] Dout Arm Trace Timing Characteristics Table 53. Arm Trace Timing Requirements for Cyclone V Devices Most debugging tools have a mechanism to adjust the capture point of trace data. Description Min Max Unit 12.5 — ns CLK maximum duty cycle 45 55 % CLK to D0 –D7 output data delay –1 1 ns CLK clock period UART Interface The maximum UART baud rate is 6.25 megasymbols per second. GPIO Interface The minimum detectable general-purpose I/O (GPIO) pulse width is 2 μs. The pulse width is based on a debounce clock frequency of 1 MHz. Cyclone V Device Datasheet 66 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 CAN Interface The maximum controller area network (CAN) data rate is 1 Mbps. HPS JTAG Timing Specifications Table 54. HPS JTAG Timing Parameters and Values for Cyclone V Devices Symbol Description Min Max Unit tJCP TCK clock period 30 — ns tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) TDI JTAG port setup time 2 — ns tJPSU (TMS) TMS JTAG port setup time 3 — ns tJPH JTAG port hold time 5 — ns — 12(73) ns — 14(73) ns — 14(73) ns tJPCO JTAG port clock to output tJPZX JTAG port high impedance to valid output tJPXZ JTAG port valid output to high impedance Configuration Specifications This section provides configuration specifications and timing for Cyclone V devices. (73) A 1-ns adder is required for each VCCIO _HPS voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO _HPS of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Send Feedback Cyclone V Device Datasheet 67 Cyclone V Device Datasheet 683801 | 2019.11.27 POR Specifications Table 55. Fast and Standard POR Delay Specification for Cyclone V Devices POR Delay Fast Standard Minimum Maximum Unit 4 12(74) ms 100 300 ms Related Information MSEL Pin Settings Provides more information about POR delay based on MSEL pin settings for each configuration scheme. FPGA JTAG Configuration Timing Table 56. FPGA JTAG Timing Parameters and Values for Cyclone V Devices Symbol Description Min 30, Max Unit 167(75) — ns tJCP TCK clock period tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) TDI JTAG port setup time 1 — ns tJPSU (TMS) TMS JTAG port setup time 3 — ns tJPH JTAG port hold time 5 — ns continued... (74) The maximum pulse width of the fast POR delay is 12 ms, providing enough time for the PCIe hard IP to initialize after the POR trip. (75) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2 V – 1.5 V when you perform the volatile key programming. Cyclone V Device Datasheet 68 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol tJPCO Description JTAG port clock to output tJPZX JTAG port high impedance to valid output tJPXZ JTAG port valid output to high impedance Min Max Unit — 11(76) ns — 14(76) ns — 14(76) ns FPP Configuration Timing DCLK-to-DATA[] Ratio (r) for FPP Configuration Fast passive parallel (FPP) configuration requires a different DCLK-to-DATA[] ratio when you turn on encryption or the compression feature. Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the DATA[] rate in byte per second (Bps) or word per second (Wps). For example, in FPP ×16 where the r is 2, the DCLK frequency must be 2 times the DATA[] rate in Wps. Cyclone V devices use additional clock cycles to decrypt and decompress the configuration data. If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into the Cyclone V device. Table 57. DCLK-to-DATA[] Ratio for Cyclone V Devices The specifications in this table are not applicable to Cyclone V QS package. Configuration Scheme FPP (8-bit wide) FPP (16-bit wide) Encryption Compression DCLK-to-DATA[] Ratio (r) Off Off 1 On Off 1 Off On 2 On On 2 Off Off 1 continued... (76) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO= 13 ns if VCCIO of the TDO I/O bank = 2.5 V, or 14 ns if it equals 1.8 V. Send Feedback Cyclone V Device Datasheet 69 Cyclone V Device Datasheet 683801 | 2019.11.27 Configuration Scheme Encryption Compression DCLK-to-DATA[] Ratio (r) On Off 2 Off On 4 On On 4 FPP Configuration Timing when DCLK-to-DATA[] = 1 When you enable decompression or the design security feature, the DCLK-to-DATA[] ratio varies for FPP ×8 and FPP ×16. For the respective DCLK-to-DATA[] ratio, refer to the DCLK-to-DATA[] Ratio for Cyclone V Devices table. Table 58. FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices The specifications in this table are not applicable to Cyclone V QS package. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506(77) µs — 1506(78) µs tCF2ST1 (79) nCONFIG high to nSTATUS high tCF2CK nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK(79) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK 0 — ns tCH DCLK high time 0.45 × 1/fMAX — s continued... (77) You can obtain this value if you do not delay configuration by extending the nCONFIG or the nSTATUS low pulse width. (78) You can obtain this value if you do not delay configuration by externally holding the nSTATUS low. (79) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. Cyclone V Device Datasheet 70 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Parameter Minimum Maximum Unit 0.45 × 1/fMAX — s 1/fMAX — s — 125 MHz 175 437 µs 4× maximum DCLK period — — tCL DCLK low time tCLK DCLK period fMAX DCLK frequency (FPP ×8/ ×16) tCD2UM CONF_DONE high to user mode(80) tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Minimum Maximum Unit Related Information • FPP Configuration Timing Provides the FPP configuration timing waveforms. • DCLK-to-DATA[] Ratio (r) for FPP Configuration on page 69 FPP Configuration Timing when DCLK-to-DATA[] >1 Table 59. FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices The specifications in this table are not applicable to Cyclone V QS package. Use these timing parameters when you use the decompression and design security features. Parameter Symbol tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs 268 1506(81) tSTATUS nSTATUS low pulse width µs continued... (80) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. (81) This value can be obtained if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. Send Feedback Cyclone V Device Datasheet 71 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol tCF2ST1 Parameter nCONFIG high to nSTATUS high Minimum Maximum Unit — 1506(82) µs (83) nCONFIG high to first rising edge on DCLK 1506 — µs tST2CK (83) nSTATUS high to first rising edge of DCLK 2 — µs tDSU DATA[] setup time before rising edge on DCLK 5.5 — ns tDH DATA[] hold time after rising edge on DCLK N – 1/fDCLK(84) — s tCH DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency (FPP ×8/ ×16) — 125 MHz tR Input rise time — 40 ns tF Input fall time — 40 ns tCD2UM CONF_DONE high to user mode(85) 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles tCF2CK Related Information FPP Configuration Timing Provides the FPP configuration timing waveforms. (82) This value can be obtained if you do not delay configuration by externally holding nSTATUS low. (83) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. (84) N is the DCLK-to-DATA[] ratio and fDCLK is the DCLK frequency of the system. (85) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Cyclone V Device Datasheet 72 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Active Serial (AS) Configuration Timing Table 60. AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices (For Non Cyclone V QS Packages) The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low. Symbol Condition Minimum Maximum Unit DCLK falling edge to the AS_DATA[3:0]/ASDO output — — 2 ns tSU(87) Data setup time before the falling edge on DCLK — 1.5 — ns tDH(87) Data hold time after the falling edge on DCLK –6 speed grade 2.3(88) — ns –7 or –8 speed grades 2.9(89)/2.7(88) — ns tCO (86) Parameter tCD2UM CONF_DONE high to user mode — 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization — 8,576 — Cycles (86) Load capacitance for DCLK = 6 pF and AS_DATA/ASDO = 8 pF. Intel recommends obtaining the tCO for a given link (including receiver, transmission lines, connectors, termination resistors, and other components) through IBIS or HSPICE simulation. (87) To evaluate the data setup (tSU) and data hold time (tDH) slack on your board in order to ensure you are meeting the tSU and tDH requirement, Intel recommends following the guideline in the "Evaluating Data Setup and Hold Timing Slack" chapter in AN822: Intel FPGA Configuration Device Migration Guideline. (88) Specification for the commercial grade devices. (89) Specification for the industrial and automotive grade devices. Send Feedback Cyclone V Device Datasheet 73 Cyclone V Device Datasheet 683801 | 2019.11.27 Table 61. AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices (For Cyclone V QS Package) The minimum and maximum numbers apply to both the internal oscillator and CLKUSR when either one is used as the clock source for device configuration. The tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for passive serial (PS) mode listed in PS Timing Parameters for Cyclone V Devices table. You can obtain the tCF2ST1 value if you do not delay configuration by externally holding nSTATUS low. Symbol tCO tSU Parameter tDH Condition Minimum Maximum Unit DCLK falling edge to the AS_DATA[3:0]/ASDO output — –1.3 0 ns Data setup time before the falling edge on DCLK — 2.9 — ns –6 speed grade 0.5(88) — ns –7 or –8 speed grades 1.3(90)/1.1(88) — ns Data hold time after the falling edge on DCLK tCD2UM CONF_DONE high to user mode — 175 437 µs tCD2CU CONF_DONE high to CLKUSR enabled — 4 × maximum DCLK period — — tCD2UMC CONF_DONE high to user mode with CLKUSR option on — tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization — 8,576 — Cycles Related Information (90) • Passive Serial (PS) Configuration Timing on page 75 • AS Configuration Timing Provides the AS configuration timing waveform. • Evaluating Data Setup and Hold Timing Slack chapter, AN822: Intel FPGA Configuration Device Migration Guideline Specification for the industrial grade devices. Cyclone V Device Datasheet 74 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 DCLK Frequency Specification in the AS Configuration Scheme Table 62. DCLK Frequency Specification in the AS Configuration Scheme The specifications in this table are applicable to both Cyclone V QS and non QS packages. This table lists the internal clock frequency specification for the AS configuration scheme. The DCLK frequency specification applies when you use the internal oscillator as the configuration clock source. The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz. Parameter Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz 10.6 15.7 25.0 MHz 21.3 31.4 50.0 MHz 42.6 62.9 100.0 MHz DCLK frequency in AS configuration scheme Passive Serial (PS) Configuration Timing Table 63. PS Timing Parameters for Cyclone V Devices The specifications in this table are not applicable to Cyclone V QS package. Symbol Parameter Minimum Maximum Unit tCF2CD nCONFIG low to CONF_DONE low — 600 ns tCF2ST0 nCONFIG low to nSTATUS low — 600 ns tCFG nCONFIG low pulse width 2 — µs tSTATUS nSTATUS low pulse width 268 1506(91) µs tCF2ST1 nCONFIG high to nSTATUS high — 1506(92) µs 1506 — (93) tCF2CK nCONFIG high to first rising edge on DCLK µs continued... (91) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width. (92) You can obtain this value if you do not delay configuration by externally holding nSTATUS low. (93) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification. Send Feedback Cyclone V Device Datasheet 75 Cyclone V Device Datasheet 683801 | 2019.11.27 Symbol Parameter Minimum Maximum Unit 2 — µs 5.5 — ns 0 — ns DCLK high time 0.45 × 1/fMAX — s tCL DCLK low time 0.45 × 1/fMAX — s tCLK DCLK period 1/fMAX — s fMAX DCLK frequency — 125 MHz 175 437 µs 4 × maximum DCLK period — — tST2CK(93) nSTATUS high to first rising edge of DCLK tDSU DATA[] setup time before rising edge on DCLK tDH DATA[] hold time after rising edge on DCLK tCH mode(94) tCD2UM CONF_DONE high to user tCD2CU CONF_DONE high to CLKUSR enabled tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (Tinit × CLKUSR period) — — Tinit Number of clock cycles required for device initialization 8,576 — Cycles Related Information PS Configuration Timing Provides the PS configuration timing waveform. (94) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device. Cyclone V Device Datasheet 76 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Initialization Table 64. Initialization Clock Source Option and the Maximum Frequency for Cyclone V Devices Initialization Clock Source Internal Oscillator CLKUSR(95) DCLK Configuration Scheme Maximum Frequency (MHz) Minimum Number of Clock Cycles AS, PS, and FPP 12.5 Tinit PS and FPP 125 AS 100 PS and FPP 125 Configuration Files Table 65. Uncompressed .rbf Sizes for Cyclone V Devices Use this table to estimate the file size before design compilation. Different configuration file formats, such as a hexadecimal file (.hex) or tabular text file (.ttf) format, have different file sizes. For the different types of configuration file and file sizes, refer to the Intel Quartus Prime software. However, for a specific version of the Intel Quartus Prime software, any design targeted for the same device has the same uncompressed configuration file size. The IOCSR raw binary file (.rbf) size is specifically for the Configuration via Protocol (CvP) feature. Variant Cyclone V E (97) Member Code Configuration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Configuration Device(96) A2 21,061,280 275,608 EPCQ64 A4 21,061,280 275,608 EPCQ64 A5 33,958,560 322,072 EPCQ128 A7 56,167,552 435,288 EPCQ128 continued... (95) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR) option in the Intel Quartus Prime software from the General panel of the Device and Pin Options dialog box. (96) The recommended EPCQ serial configuration devices are able to store more than one image. (97) No PCIe hard IP, configuration via protocol (CvP) is not supported in this family. Send Feedback Cyclone V Device Datasheet 77 Cyclone V Device Datasheet 683801 | 2019.11.27 Variant Cyclone V GX Cyclone V GT Cyclone V SE (97) Cyclone V SX Cyclone V ST (96) Configuration .rbf Size (bits) IOCSR .rbf Size (bits) Recommended EPCQ Serial Configuration Device(96) A9 102,871,776 400,408 EPCQ256 C3 14,510,912 320,280 EPCQ32 C4 33,958,560 322,072 EPCQ128 C5 33,958,560 322,072 EPCQ128 C7 56,167,552 435,288 EPCQ128 C9 102,871,776 400,408 EPCQ256 D5 33,958,560 322,072 EPCQ128 D7 56,167,552 435,288 EPCQ128 D9 102,871,776 400,408 EPCQ256 A2 33,958,560 322,072 EPCQ128 A4 33,958,560 322,072 EPCQ128 A5 56,057,632 324,888 EPCQ128 A6 56,057,632 324,888 EPCQ128 C2 33,958,560 322,072 EPCQ128 C4 33,958,560 322,072 EPCQ128 C5 56,057,632 324,888 EPCQ128 C6 56,057,632 324,888 EPCQ128 D5 56,057,632 324,888 EPCQ128 D6 56,057,632 324,888 EPCQ128 The recommended EPCQ serial configuration devices are able to store more than one image. Cyclone V Device Datasheet 78 Member Code Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Minimum Configuration Time Estimation Table 66. Minimum Configuration Time Estimation for Cyclone V Devices The estimated values are based on the configuration .rbf sizes in Uncompressed .rbf Sizes for Cyclone V Devices table. Variant Cyclone V E Cyclone V GX Cyclone V GT Cyclone V SE Active Serial(98) Member Code Fast Passive Parallel(99) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) A2 4 100 53 16 125 11 A4 4 100 53 16 125 11 A5 4 100 85 16 125 17 A7 4 100 140 16 125 28 A9 4 100 257 16 125 51 C3 4 100 36 16 125 7 C4 4 100 85 16 125 17 C5 4 100 85 16 125 17 C7 4 100 140 16 125 28 C9 4 100 257 16 125 51 D5 4 100 85 16 125 17 D7 4 100 140 16 125 28 D9 4 100 257 16 125 51 A2 4 100 85 16 125 17 A4 4 100 85 16 125 17 A5 4 100 140 16 125 28 A6 4 100 140 16 125 28 continued... (98) DCLK frequency of 100 MHz using external CLKUSR. (99) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. Send Feedback Cyclone V Device Datasheet 79 Cyclone V Device Datasheet 683801 | 2019.11.27 Variant Cyclone V SX Cyclone V ST Active Serial(98) Member Code Fast Passive Parallel(99) Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms) C2 4 100 85 16 125 17 C4 4 100 85 16 125 17 C5 4 100 140 16 125 28 C6 4 100 140 16 125 28 D5 4 100 140 16 125 28 D6 4 100 140 16 125 28 Related Information Configuration Files on page 77 Remote System Upgrades Table 67. Remote System Upgrade Circuitry Timing Specifications for Cyclone V Devices Parameter Minimum Unit tRU_nCONFIG(100) 250 ns tRU_nRSTIMER(101) 250 ns (98) DCLK frequency of 100 MHz using external CLKUSR. (99) Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic. (100) This is equivalent to strobing the reconfiguration input of the Remote Update Intel FPGA IP core high for the minimum timing specification. (101) This is equivalent to strobing the reset timer input of the Remote Update Intel FPGA IP core high for the minimum timing specification. Cyclone V Device Datasheet 80 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Related Information • Remote System Upgrade State Machine Provides more information about configuration reset (RU_CONFIG) signal. • User Watchdog Timer Provides more information about reset_timer (RU_nRSTIMER) signal. User Watchdog Internal Oscillator Frequency Specifications Table 68. User Watchdog Internal Oscillator Frequency Specifications for Cyclone V Devices Parameter User watchdog internal oscillator frequency Minimum Typical Maximum Unit 5.3 7.9 12.5 MHz I/O Timing Intel offers two ways to determine I/O timing—the Excel-based I/O timing and the Intel Quartus Prime Timing Analyzer. Excel-based I/O timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Intel Quartus Prime Timing Analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after you complete place-and-route. Related Information Cyclone V I/O Timing Spreadsheet Provides the Cyclone V Excel-based I/O timing spreadsheet. Send Feedback Cyclone V Device Datasheet 81 Cyclone V Device Datasheet 683801 | 2019.11.27 Programmable IOE Delay Table 69. I/O element (IOE) Programmable Delay for Cyclone V Devices Parameter(102 Available Settings Minimum Offset(103) D1 32 D3 ) Fast Model Slow Model Unit Industrial Commercial –C6 –C7 –C8 –I7 –A7 0 0.508 0.517 0.971 1.187 1.194 1.179 1.160 ns 8 0 1.761 1.793 3.291 4.022 3.961 3.999 3.929 ns D4 32 0 0.510 0.519 1.180 1.187 1.195 1.180 1.160 ns D5 32 0 0.508 0.517 0.970 1.186 1.194 1.179 1.179 ns Programmable Output Buffer Delay Table 70. Programmable Output Buffer Delay for Cyclone V Devices This table lists the delay chain settings that control the rising and falling edge delays of the output buffer. You can set the programmable output buffer delay in the Intel Quartus Prime software by setting the Output Buffer Delay Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the Output Buffer Delay assignment. Symbol DOUTBUF Parameter Rising and/or falling edge delay Typical Unit 0 (default) ps 50 ps 100 ps 150 ps (102) You can set this value in the Intel Quartus Prime software by selecting D1, D3, D4, and D5 in the Assignment Name column of Assignment Editor. (103) Minimum offset does not include the intrinsic delay. Cyclone V Device Datasheet 82 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Glossary Table 71. Glossary Term Differential I/O standards Definition Receiver Input Waveforms Single-Ended Waveform Positive Channel (p) = V IH VID Negative Channel (n) = VIL VCM Ground Differential Waveform VID p-n=0V VID Transmitter Output Waveforms continued... Send Feedback Cyclone V Device Datasheet 83 Cyclone V Device Datasheet 683801 | 2019.11.27 Term Definition Single-Ended Waveform Positive Channel (p) = V OH VOD Negative Channel (n) = VOL VCM Ground Differential Waveform VOD p-n=0V VOD fHSCLK Left/right PLL input clock frequency. fHSDR High-speed I/O block—Maximum/minimum LVDS data transfer rate (fHSDR =1/TUI). J High-speed I/O block—Deserialization factor (width of parallel data bus). JTAG timing specifications JTAG Timing Specifications continued... Cyclone V Device Datasheet 84 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Term Definition TMS TDI t JCP t JCH t JCL t JPSU t JPH TCK tJPZX tJPCO t JPXZ TDO PLL specifications Diagram of PLL specifications continued... Send Feedback Cyclone V Device Datasheet 85 Cyclone V Device Datasheet 683801 | 2019.11.27 Term Definition CLKOUT Pins Switchover CLK fOUT_EXT 4 fIN N fINPFD PFD Core Clock CP LF VCO fVCO Counters C0..C17 fOUT GCLK RCLK Delta Sigma Modulator Legend Reconfigurable in User Mode External Feedback Note: (1) Core Clock can only be fed by dedicated clock input pins or PLL outputs. RL Receiver differential input discrete resistor (external to the Cyclone V device). Sampling window (SW) Timing diagram—The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position in the sampling window, as shown: Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS continued... Cyclone V Device Datasheet 86 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Term Single-ended voltage referenced I/O standard Definition The JEDEC standard for the SSTL and HSTL I/O defines both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the DC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing. Single-Ended Voltage Referenced I/O Standard V CCIO V OH V IH (AC ) V REF V IH(DC ) V IL(DC ) V IL(AC ) V OL V SS tC High-speed receiver/transmitter input and output clock period. TCCS (channel-to-channel-skew) The timing difference between the fastest and slowest output edges, including the tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under SW in this table). tDUTY High-speed I/O block—Duty cycle on high-speed transmitter output clock. tFALL Signal high-to-low transition time (80–20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input continued... Send Feedback Cyclone V Device Datasheet 87 Cyclone V Device Datasheet 683801 | 2019.11.27 Term tOUTPJ_IO Period jitter on the GPIO driven by a PLL tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL tRISE Signal low-to-high transition time (20–80%) Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and the data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) VCM(DC) DC common mode input voltage. VICM Input common mode voltage—The common mode of the differential signal at the receiver. VID Input differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage—Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage— Minimum DC input differential voltage required for switching. VIH Voltage input high—The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage VIH(DC) High-level DC input voltage VIL Voltage input low—The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage VIL(DC) Low-level DC input voltage VOCM Output common mode voltage—The common mode of the differential signal at the transmitter. VOD Output differential voltage swing—The difference in voltage between the positive and complementary conductors of a differential transmission line at the transmitter. VSWING Differential input voltage VX Input differential cross point voltage VOX Output differential cross point voltage W High-speed I/O block—Clock boost factor Cyclone V Device Datasheet 88 Definition Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Document Revision History for Cyclone V Device Datasheet Document Version 2019.11.27 Changes • • • • 2019.01.25 2018.05.07 • Changed "VCO post-scale counter K value" to "VCO post divider value" in the fVCO note in the PLL Specifications for Cyclone V Devices table. • Updated the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices table. — Updated tDH specifications. These specifications are applicable to the commercial, industrial, and automotive grade devices. — Added note to tCO and tSU. • • • Added description about the low-power option ("L" suffix) for Cyclone V SE and SX devices. Added the Cyclone V Devices Overshoot Duration diagram. Removed the description on SD/MMC interface calibration support in the Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table. This feature is currently supported in the preloader. Removed the note to Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4 devices in the Uncompressed .rbf Sizes for Cyclone V Devices table. These devices are currently supported in the Intel Quartus Prime software. Removed PowerPlay text from tool name. Updated the IP name from ALTREMOTE_UPDATE to Remote Update Intel FPGA IP. Rebranded as Intel. Added the Low Power Variants table and the estimating power consumption steps to the "Cyclone V Device Datasheet" Overview section. Updated the minimum value for tDH to 2.5 for -6 speed grade/2.9 for -7 and -8 speed grade. • • • • • • Send Feedback Updated tCO parameter in the AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices (For Non Cyclone V QS Packages) table. Added active serial (AS) configuration timing for Cyclone V QS package. Added a note to indicate that the specifications are not applicable to Cyclone V QS package in the following tables: — DCLK-to-DATA[] Ratio for Cyclone V Devices — FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices — FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices — PS Timing Parameters for Cyclone V Devices Added a note to indicate that the specifications are applicable to both Cyclone V QS and non QS packages in the DCLK Frequency Specification in the AS Configuration Scheme table. Cyclone V Device Datasheet 89 Cyclone V Device Datasheet 683801 | 2019.11.27 Date December 2016 Version 2016.12.09 Changes • • • June 2016 2016.06.10 • • • • December 2015 2015.12.04 • • • • • • Updated VICM (AC coupled) specifications for 1.5 V PCML in Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices table. Added maximum specification for Td in Management Data Input/Output (MDIO) Timing Requirements for Cyclone V Devices table. Updated Tinit specifications in the following tables: — FPP Timing Parameters When DCLK-to-DATA[] Ratio is 1 for Cyclone V Devices — FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices — AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices — PS Timing Parameters for Cyclone V Devices Changed pin capacitance to maximum values. Updated SPI Master Timing Requirements for Cyclone V Devices table. — Added Tsu and Th specifications. — Removed Tdinmax specifications. Updated SPI Master Timing Diagram. Updated Tclk spec from maximum to minimum in I2C Timing Requirements for Cyclone V Devices table. Updated Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Cyclone V Devices table. — Updated Fclk, Tdutycycle, and Tdssfrst specifications. — Added Tqspi_clk, Tdin_start, and Tdin_end specifications. — Removed Tdinmax specifications. Updated the minimum specification for Tclk to 16.67 ns and removed the maximum specification in SPI Master Timing Requirements for Cyclone V Devices table. Updated Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Cyclone V Devices table. — Updated T clk to Tsdmmc_clk_out symbol. — Updated Tsdmmc_clk_out and Td specifications. — Added Tsdmmc_clk, Tsu, and Th specifications. — Removed Tdinmax specifications. Updated the following diagrams: — Quad SPI Flash Timing Diagram — SD/MMC Timing Diagram Updated configuration .rbf sizes for Cyclone V devices. Changed instances of Quartus II to Quartus Prime. continued... Cyclone V Device Datasheet 90 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Date June 2015 Version 2015.06.12 Changes • • • • • • March 2015 2015.03.31 • • January 2015 2015.01.23 • • • • • • Updated the supported data rates for the following output standards using true LVDS output buffer types in the HighSpeed I/O Specifications for Cyclone V Devices table: — True RSDS output standard: data rates of up to 360 Mbps — True mini-LVDS output standard: data rates of up to 400 Mbps Changed Queued Serial Peripheral Interface (QSPI) to Quad Serial Peripheral Interface (SPI) Flash. Updated Th location in I2C Timing Diagram. Updated Twp location in NAND Address Latch Timing Diagram. Updated the maximum value for tCO from 4 ns to 2 ns in AS Timing Parameters for AS ×1 and ×4 Configurations in Cyclone V Devices table. Moved the following timing diagrams to the Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices chapter. — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is 1 — FPP Configuration Timing Waveform When DCLK-to-DATA[] Ratio is >1 — AS Configuration Timing Waveform — PS Configuration Timing Waveform Added VCC specifications for devices with internal scrubbing feature (with SC suffix) in Recommended Operating Conditions table. Corrected the unit for tDH from ns to s in FPP Timing Parameters When DCLK-to-DATA[] Ratio is >1 for Cyclone V Devices table. Updated the transceiver specification for Cyclone V ST from 5 Gbps to 6.144 Gbps. Updated the note in the following tables: — Transceiver Power Supply Operating Conditions for Cyclone V GX, GT, SX, and ST Devices — Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices — Transceiver Compliance Specification for All Supported Protocol for Cyclone V Devices Updated the description for VCC_AUX_SHARED to “HPS auxiliary power supply”. Added a note to state that VCC_AUX_SHARED must be powered by the same source as VCC_AUX for Cyclone V SX C5, C6, D5, and D6 devices, and Cyclone V SE A5 and A6 devices. Updated in the following tables: — Absolute Maximum Ratings for Cyclone V Devices — HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices Added statement in I/O Standard Specifications: You must perform timing closure analysis to determine the maximum achievable frequency for general purpose I/O standards. Updated the conditions for transceiver reference clock rise time and fall time: Measure at ±60 mV of differential signal. Added a note to the conditions: REFCLK performance requires to meet transmitter REFCLK phase noise specification. Updated fVCO maximum value from 1400 MHz to 1600 MHz for –C7 and –I7 speed grades in the PLL specifications table. Updated the description in Periphery Performance Specifications to mention that proper timing closure is required in design. continued... Send Feedback Cyclone V Device Datasheet 91 Cyclone V Device Datasheet 683801 | 2019.11.27 Date Version Changes • • • • • • • • July 2014 3.9 Added the following notes in the High-Speed I/O Specifications for Cyclone V Devices table: — The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks. — The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true LVDS output buffer types on all I/O banks. Updated HPS Clock Performance main_base_clk specifications from 462 MHz to 400 MHz for –C6 speed grade. Updated HPS PLL VCO maximum frequency to 1,600 MHz (for –C7, –I7, –A7, and –C8 speed grades) and 1,850 MHz (for – C6 speed grade). Changed the symbol for HPS PLL input jitter divide value from NR to N. Removed “Slave select pulse width (Texas Instruments SSP mode)” parameter from the following tables: — SPI Master Timing Requirements for Cyclone V Devices — SPI Slave Timing Requirements for Cyclone V Devices Added descriptions to USB Timing Characteristics section in HPS Specifications: PHYs that support LPM mode may not function properly with the USB controller due to a timing issue. It is recommended that designers use the MicroChip USB3300 PHY device that has been proven to be successful on the development board. Added HPS JTAG timing specifications. Updated the configuration .rbf size (bits) for Cyclone V devices. • Added a note to Uncompressed .rbf Sizes for Cyclone V Devices table: The recommended EPCQ serial configuration devices are able to store more than one image. • Added a note in Table 3, Table 4, and Table 5: The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements. Added a note in Table 19: Differential inputs are powered by VCCPD which requires 2.5 V. Updated "Minimum differential eye opening at the receiver serial input pins" specification in Table 20. Updated h2f_user2_clk specification for –C6, –C7, and –I7 speed grades in Table 34. Updated description in “HPS PLL Specifications” section. Updated VCO range maximum specification in Table 35. Updated Td and Th specifications in Table 41. Added Th specification in Table 43 and Figure 10. Updated a note in Figure 17, Figure 18, and Figure 20 as follows: Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required. Removed “Remote update only in AS mode” specification in Table 54. Added DCLK device initialization clock source specification in Table 56. • • • • • • • • • • • • • Added description in “Configuration Files” section: The IOCSR .rbf size is specifically for the Configuration via Protocol (CvP) feature. Added "Recommended EPCQ Serial Configuration Device" values in Table 57. Removed fMAX_RU_CLK specification in Table 59. continued... Cyclone V Device Datasheet 92 Send Feedback Cyclone V Device Datasheet 683801 | 2019.11.27 Date Version Changes February 2014 3.8 • • Updated VCCRSTCLK_HPS maximum specification in Table 1. Added VCC_AUX_SHARED specification in Table 1. December 2013 3.7 • Updated Table 1, Table 3, Table 19, Table 20, Table 23, Table 25, Table 27, Table 34, Table 44, Table 51, Table 52, Table 55, and Table 61. Removed Preliminary tags for Table 1, Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, Table 9, Table 12, Table 13, Table 14, Table 15, Table 16, Table 17, Table 18, Table 19, Table 20, Table 24, Table 25, Table 26, Table 27, Table 28, Table 32, Table 33, Table 49, Table 50, Table 51, Table 52, Table 53, Table 54, Table 55, Table 57, Table 58, Table 59, Table 60, and Table 62. • November 2013 3.6 Updated Table 23, Table 30, and Table 31. October 2013 3.5 • • • • • Added “HPS PLL Specifications”. Added Table 23, Table 35, and Table 36. Updated Table 1, Table 5, Table 11, Table 19, Table 20, Table 21, Table 22, Table 25, Table 28, Table 34, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, Table 46, Table 47, and Table 53. Updated Figure 1, Figure 2, Figure 4, Figure 10, Figure 12, Figure 13, and Figure 16. Removed table: GPIO Pulse Width for Cyclone V Devices. June 2013 3.4 • • • Updated Table 20, Table 27, and Table 34. Updated “UART Interface” and “CAN Interface” sections. Removed the following tables: — Table 45: UART Baud Rate for Cyclone V Devices — Table 47: CAN Pulse Width for Cyclone V Devices May 2013 3.3 • • • Added Table 33. Updated Figure 5, Figure 6, Figure 17, Figure 19, and Figure 20. Updated Table 1, Table 4, Table 5, Table 10, Table 13, Table 19, Table 20, Table 26, Table 32, Table 35, Table 36, Table 43, Table 53, Table 54, Table 57, and Table 61. March 2013 3.2 • • • • Added HPS reset information in the “HPS Specifications” section. Added Table 57. Updated Table 1, Table 2, Table 17, Table 20, Table 52, and Table 56. Updated Figure 18. January 2013 3.1 Updated Table 4, Table 20, and Table 56. continued... Send Feedback Cyclone V Device Datasheet 93 Cyclone V Device Datasheet 683801 | 2019.11.27 Date November 2012 Version 3.0 Changes • • • June 2012 2.0 Updated for the Quartus Prime software v12.0 release: • Restructured document. • Removed “Power Consumption” section. • Updated Table 1,Table 3, Table 19, Table 20, Table 25, Table 27, Table 28, Table 30, Table 31, Table 34, Table 36, Table 37, Table 38, Table 39, Table 41, Table 43, and Table 46. • Added Table 22, Table 23, and Table 29. • Added Figure 1 and Figure 2. • Added “Initialization” and “Configuration Files” sections. February 2012 1.2 • • • • Added automotive speed grade information. Added Figure 2–1. Updated Table 2–3, Table 2–8, Table 2–9, Table 2–19, Table 2–20, Table 2–21, Table 2–22, Table 2–23, Table 2–24, Table 2–25, Table 2–26, Table 2–27, Table 2–28, Table 2–30, Table 2–35, and Table 2–43. Minor text edits. Added Table 2–5. Updated Table 2–3, Table 2–4, Table 2–11, Table 2–13, Table 2–20, and Table 2–21. November 2011 1.1 • • October 2011 1.0 Initial release. Cyclone V Device Datasheet 94 Updated Table 1, Table 4, Table 5, Table 9, Table 14, Table 16, Table 17, Table 19, Table 20, Table 25, Table 28, Table 52, Table 55, Table 56, and Table 59. Removed table: Transceiver Block Jitter Specifications for Cyclone V GX Devices. Added HPS information: — Added “HPS Specifications” section. — Added Table 33, Table 34, Table 35, Table 36, Table 37, Table 38, Table 39, Table 40, Table 41, Table 42, Table 43, Table 44, Table 45, and Table 46. — Added Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, and Figure 16. — Updated Table 3. Send Feedback