19-4078; Rev 1; 9/08
KIT
ATION
EVALU
E
L
B
AVAILA
20W Stereo Class D Speaker Amplifier
with Volume Control
Applications
Features
♦ Wide 4.5V to 14V Power-Supply Voltage Range
♦ Filterless Spread-Spectrum Modulation Lowers
Radiated RF Emissions from Speaker Cables
♦ 20W Stereo Output (4Ω, VDD = 12V, THD+N = 10%)
♦ Integrated Volume Control (I2C or Analog)
♦ Low 0.04% THD+N
♦ High 75dB PSRR
♦ High 93% Efficiency
♦ Integrated Click-and-Pop Suppression
♦ Low-Power Shutdown Mode
♦ Short-Circuit and Thermal-Overload Protection
♦ Available in a 44-Pin Thin QFN-EP (7mm x 7mm x
0.8mm)
Ordering Information
PART
MAX9744ETH+
TEMP RANGE
PIN-PACKAGE
-40°C to +85°C
44 TQFN-EP*
+Denotes a lead-free/RoHS-compliant package.
*EP = Exposed pad.
Flat-Panel Televisions
PC Speaker Systems
Multimedia Docking Stations
Pin Configuration appears at end of data sheet.
Simplified Block Diagram
4.5V TO 14V
40
35
VOLUME
CONTROL
CLASS D
MODULATOR
BIAS
MAX9744 EMI WITH FERRITE BEAD FILTERS
(VDD = 12V, 1m CABLE, 8Ω LOAD)
CLASS D
MODULATOR
MAX9744
OUTPUT MAGNITUDE (dBV)
3V TO 3.6V
MUTE
SHUTDOWN
CONTROL
I2C
SYNC
EN5022 B LIMIT
30
25
20
15
10
ANALOG
CONTROL
5
OSCILLATOR
SYNCOUT
30
100
60
80
140 180 220 260 300
120 160 200 240 280
FREQUENCY (MHz)
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX9744
General Description
The MAX9744 20W stereo Class D audio power amplifier provides Class AB amplifier performance with Class
D efficiency, conserving board space and eliminating
the need for a bulky heatsink. This device features single-supply operation, adjustable gain, shutdown mode,
a SYNC output, speaker mute, and industry-leading
click-and-pop suppression.
The MAX9744 features a 64-step dual-mode (analog or
digital), programmable volume control and mute function. The MAX9744 operates from a 4.5V to 14V single
supply and can deliver up to 20W per channel into a
4Ω speaker with a 14V supply.
The MAX9744 offers two modulation schemes: a fixedfrequency modulation mode that allows one of several
preset switching frequencies to be selected, and a
spread-spectrum modulation mode that helps to
reduce EMI-radiated emissions.
The MAX9744 features high 75dB PSRR, low 0.04%
THD+N, and SNR in excess of 90dB. Robust short-circuit and thermal-overload protection prevent device
damage during a fault condition. The MAX9744 is available in a 44-pin thin QFN-EP (7mm x 7mm x 0.8mm)
package and is specified over the extended -40°C to
+85°C temperature range.
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
ABSOLUTE MAXIMUM RATINGS
PVDD to PGND ....................................................................+16V
VDD to GND ...........................................................................+4V
FB_, SYNCOUT, SYNC, SDA/VOL, ADDR1,
ADDR2 to GND........................................-0.3V to (VDD + 0.3V)
BOOT_ to VDD ..........................................................-0.3V to +6V
BOOT_ to OUT_........................................................-0.3V to +6V
OUT_ to GND ..........................................-0.3V to (PVDD + 0.3V)
PGND to GND .......................................................-0.3V to +0.3V
Any Other Pin to GND ..............................................-0.3V to +4V
OUT_, Short-Circuit Duration......................................Continuous
Continuous Power Dissipation (TA = +70°C)
44-Pin Thin QFN (derate 27mW/°C above +70°C,
single-layer board) ...................................................2162mW
44-Pin Thin QFN (derate 37mW/°C above +70°C,
multilayer board) ......................................................2963mW
θJA, Single-Layer Board................................................37°C/W
θJA, Multilayer Board ................................................….27°C/W
Continuous Input Current (PVDD, PGND).............................6.4A
Continuous Output Current (OUT_) ......................................3.2A
Continuous Input Current (except OUT_).........................±20mA
Junction Temperature ......................................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_-, RL = ∞, unless otherwise stated, CBOOT_ = 0.1µF, CBIAS = 2.2µF, CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spreadspectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
14
V
3.6
V
GENERAL
Speaker Amplifier Supply Voltage
Range
Supply Voltage Range
Quiescent Current
Shutdown Current
Turn-On Time
Common-Mode Bias Voltage
PVDD
Inferred from PSRR test
4.5
VDD
Inferred from PSRR test
2.7
IDD
20
35
IPVDD
10
20
IVDDSHDN
TA = +25°C
0.1
1
IPVDDSHDN
TA = +25°C
0.1
1
mA
µA
tON
200
ms
VBIAS
1.5
V
Input Amplifier Output-Voltage
Swing High
VOH
Specified as VDD – VOH, RL = 2kΩ
connected to 1.5V
20
mV
Input Amplifier Output-Voltage
Swing Low
VOL
Specified as VOL – GND, RL = 2kΩ
connected to 1.5V
20
mV
±60
mA
1.8
MHz
Input Amplifier Output ShortCircuit Current Limit
Input Amplifier Gain-Bandwidth
Product
GBW
SPEAKER AMPLIFIERS
Gain
Output Offset
2
AVMAX
VOS
Maximum
volume setting
TA = 25°C
Output stage gain
29.5
Total gain (Note 2)
29.5
±2
_______________________________________________________________________________________
dB
±15
mV
20W Stereo Class D Speaker Amplifier
with Volume Control
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_-, RL = ∞, unless otherwise stated, CBOOT_ = 0.1µF, CBIAS = 2.2µF, CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spreadspectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Filterless
modulation
Efficiency (Note 3)
η
PWM
MIN
POUT = 10W, fIN = 1kHz,
8Ω load
POUT = 15W, fIN = 1kHz,
4Ω load
POUT = 10W, fIN = 1kHz,
8Ω load
POUT = 15W, fIN = 1kHz,
4Ω load
Output Power
POUT
VPVDD = 12V,
fIN = 1kHz
VPVDD = 14V,
fIN = 1kHz
%
92
%
88
1.4
RL = 8Ω, THD+N = 10%
1.8
RL = 4Ω, THD+N = 1%
2.6
RL = 4Ω, THD+N = 10%
3.6
RL = 8Ω, THD+N = 1%
8
RL = 8Ω, THD+N = 10%
10
RL = 4Ω, THD+N = 1%
14
RL = 4Ω, THD+N = 10%
17
RL = 8Ω, THD+N = 1%
10
RL = 8Ω, THD+N = 10%
13
RL = 4Ω, THD+N = 1%
17.5
Total Harmonic Distortion Plus
Noise
ISC
THD+N
POUT = 10W,
RL = 8Ω,
filterless
modulation
mode, BW =
22Hz to 22kHz
Signal-to-Noise Ratio
SNR
POUT = 10W,
RL = 8Ω, PWM
mode, BW =
22Hz to 22kHz
W
22.5
3.9
f = 1kHz, RL =
8Ω, POUT = 5W,
fIN = 1kHz
UNITS
87
RL = 4Ω, THD+N = 10%
Hard Output Current Limit
MAX
93
RL = 8Ω, THD+N = 1%
VPVDD = 5V,
fIN = 1kHz
TYP
5.5
Filterless modulation
0.04
PWM
0.04
Fixed-frequency
modulation, unweighted
91
Spread-spectrum,
unweighted
90
Fixed-frequency
modulation, A-weighted
94
Spread-spectrum,
A-weighted
94
Fixed-frequency
modulation, unweighted
91
Spread-spectrum,
unweighted
81
Fixed-frequency
modulation, A-weighted
94
Spread-spectrum,
A-weighted
89
A
%
dB
dB
_______________________________________________________________________________________
3
MAX9744
ELECTRICAL CHARACTERISTICS (continued)
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
ELECTRICAL CHARACTERISTICS (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_-, RL = ∞, unless otherwise stated, CBOOT_ = 0.1µF, CBIAS = 2.2µF, CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spreadspectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
Crosstalk
Power-Supply Rejection Ratio
PSRR
CONDITIONS
MIN
TYP
1kHz
85
20Hz to 20kHz
68
VDD = 2.7V to 3.6V, TA = 25°C,
MUTE = high
68
PVDD = 4.5V to 14V
50
75
SYNC = GND
1020
1200
1355
SYNC = unconnected
1280
1440
1640
fSW
SYNC = GND
255
300
338
SYNC = unconnected
320
360
410
kHz
300
±6
SYNC = VDD (spread-spectrum mode)
SYNC Frequency Lock Range
kHz
1200
±30
SYNC = VDD (spread-spectrum mode)
Class D Switching Frequency
dB
70
f = 1kHz, VRIPPLE = 200mVP-P on PVDD
fSYNC
UNITS
dB
83
f = 1kHz, VRIPPLE = 100mVP-P on VDD
SYNC Frequency
MAX
1000
1600
kHz
Minimum SYNC Frequency Lock
Duty Cycle
40
%
Maximum SYNC Frequency Lock
Duty Cycle
60
%
0.2
dB
Gain Matching
Full volume (ideal matching for RIN and RF)
Into shutdown
Click-and-Pop Level
KCP
Peak voltage, 32
samples/second,
A-weighted (Note 4)
-43
Out of shutdown
-43
Into mute
-46
Out of mute
-57
dBV
VOLUME CONTROL
VOL Input Leakage Current
±5
µA
Input Hysteresis
DC volume control mode
11
mV
9.5dB Gain Voltage
DC volume control mode
0.1 x VDD
V
Full Mute Voltage
DC volume control mode
0.9 x VDD
V
Full Mute Attenuation
f = 1kHz, relative to 9.5dB setting
-115
dB
DIGITAL INPUTS/OUTPUT (SHDN, MUTE, ADDR1, ADDR2, SCLK, SDA/VOL)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Leakage Current
ILK
Input Hysteresis
CIN
Output-Voltage Low
VIL
V
0.3 x VDD
TA = +25°C
SCLK, SDA/VOL
Input Capacitance
4
0.7 x VDD
±1
0.1 x VDD
V
5
IOL = 3mA
_______________________________________________________________________________________
V
µA
pF
0.4
V
20W Stereo Class D Speaker Amplifier
with Volume Control
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_-, RL = ∞, unless otherwise stated, CBOOT_ = 0.1µF, CBIAS = 2.2µF, CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spreadspectrum mode, filterless modulation mode, see the Functional Diagrams/Typical Application Circuits. TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT (SYNC)
Input-Voltage High
VSYNCIH
Input-Voltage Low
VSYNCIL
SYNC Input Leakage
ISYNCIN
2.3
TA = +25°C
V
±7.5
0.8
V
±13
µA
DIGITAL OUTPUT (SYNCOUT)
Output-Voltage High
VSYNCOUTIH ISOURCE = 1mA
Output-Voltage Low
VSYNCOUTIL ISINK = 1mA
Rise/Fall Time
VDD 0.3
V
0.3
CL = 10pF
50
V
V/µs
THERMAL PROTECTION
Thermal-Shutdown Threshold
+165
°C
Thermal-Shutdown Hysteresis
15
°C
I2C TIMING CHARACTERISTICS (Figure 3)
Serial Clock
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
400
kHz
1.3
µs
0.6
µs
Hold Time (Repeated) START
Condition
tHD, STA
Repeated START Condition
Setup Time
tSU, STA
0.6
µs
STOP Condition Setup Time
tSU, STO
0.6
µs
Data Hold Time
tHD,DAT
0
Data Setup Time
tSU,DAT
100
ns
SCL Clock Low Period
tLOW
1.3
µs
SCL Clock High Period
µs
(Note 5)
0.9
µs
tHIGH
0.6
Rise Time of SDA and SCL,
Receiving
tR
(Note 6)
20 +
0.1CB
300
ns
Fall Time of SDA and SCL,
Receiving
tF
(Note 6)
20 +
0.1CB
300
ns
0
50
ns
400
pF
Pulse Width of Spike Suppressed
tSP
Capacitive Load for Each Bus
Line
CB
All devices are 100% production tested at +25°C. All temperature limits are guaranteed by design.
See the Gain-Setting Resistors section.
Measured on the MAX9744 Evaluation Kit.
Testing performed with an 8Ω resistive load connected across BTL output. Mode transitions are controlled by SHDN or
MUTE pin, respectively.
Note 5: A master device must provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the
SCL’s falling edge.
Note 6: CB = total capacitance of one bus line in pF.
Note 1:
Note 2:
Note 3:
Note 4:
_______________________________________________________________________________________
5
MAX9744
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
0.1
fIN = 1kHz
0.01
1
0.1
fIN = 1kHz
0.01
fIN = 100Hz
4
6
8
10 12 14 16 18 20
MAX9744 toc03
fIN = 1kHz
fIN = 100Hz
0.001
4
0
8
12
16
3
0
20
6
9
12
OUTPUT POWER (W)
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
fIN = 1kHz
0.01
0.1
0.01
fIN = 100Hz
fIN = 100Hz
0.001
3
6
9
12
fIN = 100Hz
0
1
2
1
1
FFM
0.1
3
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
100
MAX9744 toc07
PVDD = 12V
RL = 4Ω
fIN = 1kHz
FILTERLESS MODULATION
2
OUTPUT POWER (W)
PVDD = 12V
RL = 8Ω
fIN = 1kHz
FILTERLESS MODULATION
10
THD+N (%)
THD+N (%)
0
4
3
OUTPUT POWER (W)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
10
fIN = 1kHz
0.001
OUTPUT POWER (W)
100
0.1
0.01
fIN = 1kHz
0.001
0
1
MAX9744 toc08
0.1
fIN = 6kHz
fIN = 6kHz
1
PVDD = 5V
RL = 4Ω
PWM MODE
10
THD+N (%)
THD+N (%)
fIN = 6kHz
1
PVDD = 5V
RL = 4Ω
FILTERLESS MODULATION
10
100
MAX9744 toc05
10
100
MAX9744 toc04
PVDD = 12V
RL = 8Ω
PWM MODE
MAX9744 toc06
OUTPUT POWER (W)
100
1
FFM
0.1
SSM
0.01
0.01
0.001
SSM
0.001
0
4
8
12
OUTPUT POWER (W)
6
0.1
0.01
0.001
2
fIN = 6kHz
1
fIN = 100Hz
0.001
0
PVDD = 12V
RL = 8Ω
FILTERLESS MODULATION
10
THD+N (%)
THD+N (%)
THD+N (%)
fIN = 6kHz
fIN = 6kHz
1
PVDD = 12V
RL = 4Ω
PWM MODE
10
100
MAX9744 toc02
PVDD = 12V
RL = 4Ω
FILTERLESS MODULATION
10
100
MAX9744 toc01
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
THD+N (%)
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
16
20
0
2
4
6
8
10
OUTPUT POWER (W)
_______________________________________________________________________________________
12
4
20W Stereo Class D Speaker Amplifier
with Volume Control
0.01
MAX9744 toc10
OUTPUT POWER = 10W
0.1
OUTPUT POWER = 5W
0.01
0.001
8
12
16
PVDD = 12V
RL = 4Ω
PWM MODE
1
OUTPUT POWER = 10W
0.1
0.01
OUTPUT POWER = 5W
0.001
0.001
4
0
20
10
100
1k
10k
10
100k
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
1
OUTPUT POWER = 6W
0.1
0.01
1
OUTPUT POWER = 6W
0.1
0.01
OUTPUT POWER = 3W
0.001
100
1k
100k
10k
100
1k
10k
0.1
OUTPUT POWER = 500mW
10
100k
100
OUTPUT POWER = 500mW
0.1
100
10
PVDD = 12V
RL = 4Ω
FILTERLESS MODULATION
POUT = 5W
0.001
100k
1
SSM
0.1
0.01
OUTPUT POWER = 1.5W
10k
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX9744 toc15
1
1k
FREQUENCY (Hz)
THD+N (%)
THD+N (%)
PVDD = 5V
RL = 4Ω
PWM MODE
0.01
OUTPUT POWER = 1.5W
FREQUENCY (Hz)
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
10
1
0.001
10
FREQUENCY (Hz)
100
10
PVDD = 5V
RL = 4Ω
FILTERLESS MODULATION
0.01
OUTPUT POWER = 3W
0.001
10
100
MAX9744 toc16
THD+N (%)
10
PVDD = 12V
RL = 8Ω
PWM MODE
THD+N (%)
100
MAX9744 toc12
10
PVDD = 12V
RL = 8Ω
FILTERLESS MODULATION
MAX9744 toc14
OUTPUT POWER (W)
100
THD+N (%)
1
SSM
10
THD+N (%)
FFM
100
MAX9744 toc13
THD+N (%)
1
0.1
PVDD = 12V
RL = 4Ω
FILTERLESS MODULATION
10
THD+N (%)
PVDD = 12V
RL = 4Ω
fIN = 1kHz
PWM MODE
10
100
MAX9744 toc09
100
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
MAX9744 toc11
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. OUTPUT POWER
FFM
0.001
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
_______________________________________________________________________________________
7
MAX9744
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX9744
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
SSM
1k
10k
5
40
4
30
3
20
2
20
1
10
0
0
0
100k
4
EFFICIENCY vs. OUTPUT POWER
2W
40
30
PVDD = 5V
fIN = 1kHz
RL = 4Ω
10
0W
2.5
MAX9744 toc21
THD+N = 1%
85
80
6
8
10
12
6
8
10
SUPPLY VOLTAGE (V)
MAX9744 toc23
24
80
fIN = 1kHz
RL = 4Ω
PWM MODE
20
OUTPUT POWER (W)
EFFICIENCY (%)
THD+N = 1%
75
16
THD+N = 10%
12
8
THD+N = 1%
4
70
0
4
6
8
10
SUPPLY VOLTAGE (V)
8
fIN = 1kHz
RL = 8Ω
FILTERLESS MODULATION
OUTPUT POWER vs. SUPPLY VOLTAGE
THD+N = 10%
85
80
4
14
EFFICIENCY vs. SUPPLY VOLTAGE
90
85
SUPPLY VOLTAGE (V)
fIN = 1kHz
RL = 4Ω
PWM MODE
12
10
70
4
OUTPUT POWER (W)
95
8
THD+N = 1%
90
75
70
3.0
6
THD+N = 10%
95
fIN = 1kHz
RL = 4Ω
FILTERLESS MODULATION
75
0
2.0
THD+N = 10%
90
4
MAX9744 toc24
20
100
2
100
EFFICIENCY (%)
50
EFFICIENCY (%)
POWER DISSIPATION
60
1.5
0W
0
EFFICIENCY vs. SUPPLY VOLTAGE
95
70
1.0
PVDD = 12V
fIN = 1kHz
RL = 8Ω
OUTPUT POWER (W)
(PER CHANNEL)
100
PWM MODE
0.5
30
16
12
FILTERLESS MODULATION
0
40
EFFICIENCY vs. SUPPLY VOLTAGE
MAX9744 toc20
80
50
OUTPUT POWER (W)
100
EFFICIENCY (%)
8
PWM MODE
60
6
PVDD = 12V, fIN = 1kHz, RL = 4Ω
5W
70
50
FREQUENCY (Hz)
90
80
7
0
100
10
8
60
10
0.001
90
FILTERLESS MODULATION
POWER DISSIPATION
FFM
0.1
PWM MODE
70
9
EFFICIENCY (%)
80
1
0.01
FILTERLESS MODULATION
MAX9744 toc19
100
10
POWER DISSIPATION (mW)
THD+N (%)
10
MAX9744 toc18
90
EFFICIENCY (%)
PVDD = 12V
RL = 8Ω
FILTERLESS MODULATION
POUT = 3W
EFFICIENCY vs. OUTPUT POWER
EFFICIENCY vs. OUTPUT POWER
100
MAX9744 toc17
100
MAX9744 toc22
TOTAL HARMONIC DISTORTION PLUS NOISE
vs. FREQUENCY
14
4
6
8
10
12
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
14
12
14
20W Stereo Class D Speaker Amplifier
with Volume Control
THD+N = 10%
8
4
THD+N = 1%
3
THD+N = 10%
12
8
THD+N = 1%
0
0
8
12
10
10
15
20
0
30
25
10
15
20
25
30
SUPPLY VOLTAGE (V)
LOAD RESISTANCE (Ω)
CASE TEMPERATURE
vs. OUTPUT POWER
CASE TEMPERATURE
vs. OUTPUT POWER
POWER-SUPPLY REJECTION RATIO (PVDD)
vs. FREQUENCY
50
PVDD = 12V
FILTERLESS MODULATION
25
0
PVDD = 14V
PWM MODE
-20
PVDD = 12V
PWM MODE
50
-30
PVDD = 12V
FILTERLESS MODULATION
25
9
12
15
2
4
6
8
10
PSRR (dB)
-30
PWM MODE
-50
-60
-70
FILTERLESS MODULATION
10k
100k
40
MAX9744 toc32
-20
1k
EMI WITH FERRITE BEAD FILTERS
(VDD = 12V, 1m CABLE, 8Ω LOAD)
35
OUTPUT MAGNITUDE (dBV)
MAX9744 toc31
VDD = 3.3V
VRIPPLE = 100mVP-P
100
FREQUENCY (Hz)
OUTPUT POWER (W)
0
-80
10
12
POWER-SUPPLY REJECTION RATIO (VDD)
vs. FREQUENCY
-40
FILTERLESS MODULATION
-100
0
18
OUTPUT POWER (W)
-10
-60
-80
0
6
PWM MODE
-50
-90
0
3
-40
-70
PVDD = 14V
FILTERLESS MODULATION
PVDD = 14V
FILTERLESS MODULATION
PVDD = 12V
VRIPPLE = 200mVP-P
-10
PSRR (dB)
PVDD = 12V
PWM MODE
fIN = 1kHz
RL = 8Ω
MAX9744 toc30
75
MAX9744 toc29
PVDD = 14V
PWM MODE
100
0
5
LOAD RESISTANCE (Ω)
fIN = 1kHz
RL = 4Ω
75
5
0
14
CASE TEMPERATURE (°C)
125
6
MAX9744 toc28
4
THD+N = 10%
2
1
THD+N = 1%
4
PVDD = 5V
f = 1kHz
PWM MODE
MAX9744 toc27
16
0
CASE TEMPERATURE (°C)
PVDD = 12V
f = 1kHz
FILTERLESS MODULATION
OUTPUT POWER (W)
12
4
MAX9744 toc26
MAX9744 toc25
20
OUTPUT POWER (W)
OUTPUT POWER (W)
RL = 8Ω
fIN = 1kHz
PWM MODE
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. LOAD RESISTANCE
OUTPUT POWER vs. SUPPLY VOLTAGE
16
EN5022 B LIMIT
30
25
20
15
10
-90
5
-100
10
100
1k
FREQUENCY (Hz)
10k
100k
30
100
60
80
140 180 220 260 300
120 160 200 240 280
FREQUENCY (MHz)
_______________________________________________________________________________________
9
MAX9744
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX9744
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
OUTPUT WAVEFORM (PWM)
OUTPUT FREQUENCY SPECTRUM
MAX9744 toc34
0
2V/div
2V/div
2V/div
2V/div
FFM MODE
VIN = -60dBV
f = 1kHz
RL = 4Ω
UNWEIGHTED
-20
OUTPUT MAGNITUDE (dBV)
MAX9744 toc33
-40
MAX9744 toc35
OUTPUT WAVEFORM
(FILTERLESS MODULATION)
-60
LEFT
-80
-100
-120
RIGHT
-140
0
-60
LEFT
-100
-40
-60
-80
5
10
15
20
1
-60
-80
0
100
10
1
WIDEBAND OUTPUT SPECTRUM
(SPREAD-SPECTRUM MODULATION MODE)
20
MAX9744 toc39
-20
-40
-60
-80
RBW = 1kHz
INPUT AC GROUNDED
PWM MODE
0
OUTPUT AMPLITUDE (dBV)
RBW = 1kHz
INPUT AC GROUNDED
FILTERLESS MODULATION
10
FREQUENCY (MHz)
FREQUENCY (MHz)
WIDEBAND OUTPUT SPECTRUM
(SPREAD-SPECTRUM MODULATION MODE)
0
-40
-120
0
FREQUENCY (kHz)
20
-20
-100
-120
0
-20
-40
-60
-80
-100
-100
-120
-120
0
1
10
FREQUENCY (MHz)
20
MAX9744 toc38
MAX9744 toc37
-20
RBW = 1kHz
INPUT AC GROUNDED
PWM MODE
0
-100
RIGHT
-140
10
20
MAX9744 toc40
-120
RBW = 1kHz
INPUT AC GROUNDED
FILTERLESS MODULATION
0
15
WIDEBAND OUTPUT SPECTRUM
(FIXED-FREQUENCY MODULATION MODE)
OUTPUT AMPLITUDE (dBV)
-40
OUTPUT AMPLITUDE (dBV)
OUTPUT MAGNITUDE (dBV)
-20
20
OUTPUT AMPLITUDE (dBV)
SSM MODE
VIN = -60dBV
f = 1kHz
RL = 4Ω
UNWEIGHTED
MAX9744 toc36
0
10
FREQUENCY (kHz)
WIDEBAND OUTPUT SPECTRUM
(FIXED-FREQUENCY MODULATION MODE)
OUTPUT FREQUENCY SPECTRUM
-80
5
1μs/div
1μs/div
100
0
1
10
FREQUENCY (MHz)
______________________________________________________________________________________
100
100
20W Stereo Class D Speaker Amplifier
with Volume Control
CROSSTALK vs. FREQUENCY
CROSSTALK vs. AMPLITUDE
RL = 8Ω
f = 1kHz
-10
-20
CROSSTALK (dB)
-40
-60
LEFT TO RIGHT
-80
SHDN
2V/div
-30
-40
-50
RIGHT TO LEFT
LEFT TO RIGHT
-60
-70
-100
OUTPUT
-80
RIGHT TO LEFT
-90
-120
-100
100
1k
100k
10k
-60
FREQUENCY (Hz)
-50
-40
-30
-20
-10
0
20
10
100ms/div
AMPLITUDE (dBV)
VOLUME CONTROL LEVEL
vs. VOLUME CONTROL VOLTAGE
14
SUPPLY CURRENT (mA)
VOLUME CONTROL LEVEL
16
-20
-40
-60
-80
MAX9744 toc45
0
SUPPLY CURRENT (PVDD)
vs. SUPPLY VOLTAGE
MAX9744 toc44
20
12
PWM MODE
10
8
6
FILTERLESS MODULATION
4
-100
2
-120
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
6
8
10
12
VVOL (V)
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (VDD)
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
0.8
MAX9744 toc46
30
FILTERLESS MODULATION
20
PWM MODE
15
SHUTDOWN CURRENT = IPVDD + IDD
VDD = 3.3V
SHUTDOWN CURRENT (μA)
25
14
MAX9744 toc47
VOLUME LEVEL (dB)
10
SUPPLY CURRENT (mA)
CROSSTALK (dB)
-20
MAX9744 toc43
MAX9744 toc42
VIN = 200mVRMS
TURN-ON/OFF RESPONSE
0
MAX9744 toc41
0
0.7
0.6
0.5
10
5
0.4
3.0
3.2
3.4
3.6
SUPPLY VOLTAGE (V)
3.8
4.0
4
6
8
10
12
14
SUPPLY VOLTAGE (V)
______________________________________________________________________________________
11
MAX9744
Typical Operating Characteristics (continued)
(VPVDD = 12V, VDD = 3.3V, VGND = VPGND = 0V, VMUTE = 0V; max volume setting; all speaker load resistors connected between
OUT_+ and OUT_- with an inductor in series, 8Ω load, L = 68µH, 4Ω load, L= 33µH. RL = ∞, unless otherwise stated, CBIAS = 2.2µF,
CIN = 0.47µF, RIN = 20kΩ, RF_ = 20kΩ, spread-spectrum mode, TA = +25°C, unless otherwise noted.)
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX9744
Pin Description
PIN
NAME
1
BOOTL+
2, 3
OUTL+
4, 5, 29, 30
PVDD
6, 10, 21, 28
VDD
Power-Supply Input. Bypass each with a 1µF capacitor to GND.
7, 11, 12, 15, 27
GND
Ground
8
SDA/VOL
9
Left-Channel Positive Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTL+ and OUTL+.
Left-Channel Speaker Output, Positive Phase
Speaker Amplifier Power-Supply Input. Bypass each with a 1µF capacitor to PGND.
I2C Serial Data I/O and Analog Volume Control Input
I2C Serial Clock Input and Modulation Scheme Select. In I2C mode (ADDR1 and ADDR2 ≠ GND),
SCLK/PWM acts as I2C serial clock input. When ADDR1 and ADDR2 = GND, set SCLK = 1 for standard PWM
output scheme, or set SCLK = 0 for filterless modulation output scheme.
13
ADDR1
Address Select Input 1. Sets device address for I2C address option. Connect ADDR1 and ADDR2
to GND to select analog volume control mode.
14
ADDR2
Address Select Input 2. Sets device address for I2C address option. Connect ADDR1 and ADDR2
to GND to select Analog Volume Control mode.
16
INL
Left-Channel Audio Input
17
FBL
Left-Channel Feedback. Connect feedback resistor between FBL and INL to set amplifier gain. See
the Gain-Setting Resistors section.
18
FBR
Right-Channel Feedback. Connect feedback resistor between FBR and INR to set amplifier gain.
See the Gain-Setting Resistors section.
19
INR
Right-Channel Input
20
BIAS
Common-Mode Bias Voltage. Bypass with a 2.2µF capacitor to GND.
22
SHDN
Shutdown Input. Drive SHDN low to disable the audio amplifiers. Connect SHDN to VDD or drive
high for normal operation.
23
N.C.
24
MUTE
Mute Input. Drive MUTE high to mute the speaker outputs. Connect MUTE to GND for normal
operation (mute function controls speaker outputs only).
SYNC
Frequency Select and External Clock Input.
SYNC = GND: Fixed-frequency mode with fSYNC = 1200kHz
SYNC = Unconnected: Fixed-frequency mode with fSYNC = 1440kHz
SYNC = VDD: Spread-spectrum mode with fSYNC = 1200kHz ±30kHz
SYNC = Clocked: Fixed-frequency mode with fSYNC = external clock frequency. fSW = 1/4 the
value of fSYNC.
25
12
FUNCTION
No Connection. Not internally connected.
______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
PIN
NAME
26
SYNCOUT
31, 32
OUTR+
33
BOOTR+
34, 35, 39,
43, 44
PGND
36, 37
OUTR-
FUNCTION
SYNC Signal Output
Right-Channel Positive Speaker Output
Right-Channel Positive Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTR+ and OUTR+.
Power Ground
Right-Channel Negative Speaker Output
38
BOOTR-
Right-Channel Negative Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTR- and OUTR-.
40
BOOTL-
Left-Channel Negative Speaker Output Boost Flying-Capacitor Connection. Connect a 0.1µF
ceramic capacitor between BOOTL- and OUTL-.
41, 42
OUTL-
—
EP
Left-Channel Negative Speaker Output
Exposed Pad. The external pad lowers the package’s thermal impedance by providing a direct
heat conduction path from the die to the PCB. Connect the exposed thermal pad to PGND.
Detailed Description
The MAX9744 20W filterless, stereo Class D audio
power amplifier offers Class AB performance with Class
D efficiency with a minimal board space solution. The
MAX9744 features a spread-spectrum modulation
scheme offering significant improvements to switchmode amplifier technology. This device features analog
or digitally adjustable volume control, externally set
input gain, shutdown mode, SYNC input and output,
mute, and industry-leading click-and-pop suppression.
The MAX9744 features extensive click-and-pop suppression circuitry that eliminates audible clicks-andpops at startup and shutdown.
The MAX9744 features a 64-step, dual-mode (analog
or I2C) volume control and mute function. In analog volume control mode, the voltage applied to SDA/VOL
sets the volume level. Two address inputs (ADDR1,
ADDR2) set the volume control function between analog and I2C mode and set the slave address. In I2C
mode, there are three selectable slave addresses
allowing for multiple devices on a single bus.
The MAX9744 offers spread-spectrum and fixed-frequency modes of operation with classic PWM or filterless modulation output schemes. The filterless
modulation scheme uses minimum pulse outputs when
the audio inputs are at the zero crossing. As the input
voltage increases or decreases, the duration of the
pulse at one output increases while the other output
pulse duration remains the same. This causes the net
voltage across the speaker (VOUT+ - VOUT-) to change.
The minimum-width pulse topology reduces EMI and
increases efficiency.
Operating Modes
Fixed-Frequency Modulation Mode
The MAX9744 features two fixed-frequency modes:
300kHz and 360kHz. Connect SYNC to GND to select
300kHz switching frequency; leave SYNC unconnected
to select the 360kHz switching frequency. The
MAX9744 frequency spectrum consists of the fundamental switching frequency and its associated harmonics
(see the Wideband Output Spectrum graphs in the Typical
Operating Characteristics). For applications where exact
spectrum placement of the switching fundamental is
important, program the switching frequency so that the
harmonics do not fall within a sensitive frequency band
(Table 1). Audio reproduction is not affected by changing the switching frequency.
______________________________________________________________________________________
13
MAX9744
Pin Description (continued)
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
Spread-Spectrum Modulation Mode
The MAX9744 features a unique spread-spectrum
mode that flattens the wideband spectral components,
improving EMI emissions that may be radiated by the
speaker and cables. This mode is enabled by setting
SYNC = VDD (Table 1). In spread-spectrum mode, the
switching frequency varies randomly by ±7.5kHz
around the center frequency (300kHz). The modulation
scheme remains the same, but the period of the triangle waveform changes from cycle to cycle. Instead of a
large amount of spectral energy present at multiples of
the switching frequency, the energy is now spread over
a bandwidth that increases with frequency. Above a
few megahertz, the wideband spectrum looks like white
noise for EMI purposes. A proprietary amplifier topology ensures this does not corrupt the noise floor in the
audio bandwidth.
External Clock Mode
The SYNC input allows the MAX9744 to be synchronized to an external clock or another Maxim Class D
amplifier, creating a fully synchronous system. This
minimizes clock intermodulation and allocates spectral
components of the switching harmonics to insensitive
frequency bands. Applying a clock signal between
1MHz and 1.6MHz to SYNC synchronizes the
MAX9744. The MAX9744 Class D amplifier operates at
1/4 of the SYNC frequency. For example, if SYNC is
1.6MHz, the Class D amplifier operates at 400kHz.
The external SYNC signal can be any CMOS clock
source with a 40% to 60% duty cycle. Spread-spectrum
clocks work well to reduce EMI; therefore, the
SYNCOUT signal from another MAX9744 in spreadspectrum mode is an excellent SYNC input.
Table 1. Operating Modes
SYNC
MODE
Fixed-frequency
modulation
1200
300
Unconnected
Fixed-frequency
modulation
1440
360
VDD
Spread-spectrum
modulation
1200 ±30
300 ±7.5
1000 to
1600
250 to
400
EXT
Filterless Modulation/PWM Modulation
The MAX9744 features two output modulation schemes:
filterless modulation or classic PWM. The MAX9744 output modulation schemes are selectable through
SCLK/PWM when the device is in analog mode (ADDR1
and ADDR2 = GND, Table 2) or through the I2C interface (Table 8). Maxim’s unique, filterless modulation
scheme eliminates the LC filter required by traditional
Class D amplifiers, reducing component count and conserving board space and system cost. Although the
MAX9744 meets FCC and other EMI limits with a lowcost ferrite bead filter, many applications still may want
to use a full LC-filtered output. If using a full LC filter,
audio performance is best with the MAX9744 configured
for classic PWM output.
Switching between schemes, the output is not click-andpop protected. To have click-and-pop protection when
switching between output schemes, the device must
enter shutdown mode and be configured to the new output scheme before the startup sequence is finished.
MAX9744
SYNC INPUT
OUTL+
OUTL-
SYNC
OUTR+
OUTR-
fSYNC (kHz) fSW (kHz)
GND
Clocked
SYNCOUT allows several Maxim amplifiers to be cascaded (Figure 1). The synchronized output minimizes
interference due to clock intermodulation caused by the
switching spread between single devices. Using
SYNCOUT and SYNC does not affect the audio performance of the MAX9744.
SYNCOUT
MAX9709
SYNC
OUT+
OUT-
Figure 1. Cascading Two Amplifiers’ External Clock Mode
14
______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
ADDR2
ADDR1
SDA/VOL
SCLK/PWM
0
0
Analog volume control
0
Filterless modulation
FUNCTION
0
0
Analog volume control
1
Classic PWM (50% duty cycle)
Efficiency
Thermal Shutdown
The high efficiency of a Class D amplifier is due to the
switching operation of the output stage transistors. In a
Class D amplifier, the output transistors act as currentsteering switches and consume negligible additional
power. Any power loss associated with the Class D output stage is mostly due to the I2R loss of the MOSFET
on-resistance, and quiescent current overhead.
The theoretical best efficiency of a linear amplifier is
78% at peak output power. Under normal operating levels (typical music reproduction levels), the efficiency
falls below 30%, whereas the MAX9744 exhibits > 80%
efficiency under the same conditions (Figure 2).
When the die temperature exceeds the thermal-shutdown threshold, +165°C (typ), the MAX9744 outputs
are disabled. Normal operation resumes when the die
temperature decreases by a factor equal to the
thermal-shutdown threshold minus the thermal-shutdown hysteresis, (typically below +150°C). The effect of
thermal shutdown is an output signal turning off for
approximately 3s in most applications, depending on
the thermal time constant of the audio system. Most
applications should never enter thermal shutdown.
Some of the possible causes of thermal shutdown are
too low of a load impedance, bad thermal contact
between the MAX9744’s exposed pad and PCB, high
ambient temperature, poor PCB layout and assembly,
or excessive output overdrive.
Current Limit
When the output current exceeds the current limit, 5.5A
(typ), the MAX9744 disables the outputs and initiates a
220µs startup sequence. The shutdown and startup
sequence is repeated until the output fault is removed.
Since the retry repetition is slow, the average supply
current is low. Most applications do not enter currentlimit mode unless the output is short circuited or incorrectly connected.
EFFICIENCY
vs. OUTPUT POWER
MAX9744/45 fig02
100
90
EFFICIENCY (%)
80
70
MAX9744
60
50
40
30
CLASS AB
20
PVDD = 12V
fIN = 1kHz
RL = 4Ω
10
Shutdown
The MAX9744 features a shutdown mode that reduces
power consumption and extends battery life. Driving
SHDN low places the device in low-power shutdown
mode. Connect SHDN to digital high for normal operation. In shutdown mode, the outputs are high impedance, SYNCOUT is pulled high, BIAS voltage decays to
zero, and the common-mode input voltage decays to
zero. The I2C register does not retain its contents during shutdown (MAX9744).
Mute Function
The MAX9744 features a clickless-and-popless mute
mode. When the device is muted, the outputs do not
stop switching; only the volume level is muted to the
speaker. Mute only affects the output stage and does
not shut down the device. To mute the MAX9744, drive
MUTE to logic-high. MUTE should be held high during
system power-up and power-down to ensure that pops
caused by circuits before the MAX9744 are eliminated.
To reduce clicks and pops, the device enters or exits
mute at zero crossing.
0
0
2
4
6
8
10
OUTPUT POWER (W)
Figure 2. MAX9744 Efficiency vs. Class AB Efficiency
______________________________________________________________________________________
15
MAX9744
Table 2. Modulation Scheme Selection
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
Volume Control
For maximum flexibility, the MAX9744 features volume
control operation using an analog voltage input or
through the I2C interface. To set the device to analog
mode, connect ADDR1 and ADDR2 to GND. In analog
mode, SDA/VOL is an analog input for volume control.
The analog input range is ratiometric between 0.9 x
VDD and 0.1 x VDD where 0.9 x VDD = full mute and 0.1
x VDD = full volume (Table 7).
Use ADDR1 and ADDR2 to select I2C mode. There are
three addresses that can be chosen, allowing for multiple devices on a single bus (Table 4). In I2C mode, volume is controlled by choosing the speaker volume
control register in the command byte (Table 5). There
are 64 volume settings, where the lowest setting is full
mute (Table 6). See the Write Byte section for more
information on formatting data and tables to set volume
levels. The default volume after power-up is position 40
(-7.1dB) (see Table 7).
I2C Interface
The MAX9744 features an I2C 2-wire serial interface
consisting of a serial-data line (SDA) and a serial-clock
line (SCL). SDA and SCL facilitate communication
between the MAX9744 and the master at clock rates up
to 400kHz. Figure 3 shows the 2-wire interface timing
diagram. The MAX9744 is a receive-only slave device,
relying on the master to generate the SCL signal. The
MAX9744 cannot write to the SDA bus except to
acknowledge the receipt of data from the master. The
master, typically a microcontroller, generates SCL and
initiates data transfer on the bus.
A master device communicates to the MAX9744 by
transmitting the proper address followed by the data
word. Each transmit sequence is framed by a START (S)
or Repeated START (Sr) condition and a STOP (P) condition. Each word transmitted over the bus is 8 bits long
and is always followed by an acknowledge clock pulse.
The MAX9744 SDA line operates as both an input and
an open-drain output. A pullup resistor, greater than
500Ω, is required on the SDA bus. The MAX9744 SCL
line operates as an input only. A pullup resistor, greater
than 500Ω, is required on SCL if there are multiple masters on the bus, or if the master in a single-master system has an open-drain SCL output. Series resistors in
line with SDA and SCL are optional. The SCL and SDA
inputs have Schmitt trigger and filter circuits that suppress noise spikes to assure proper device operation
even on a noisy bus.
SDA
tBUF
tSU, STA
tSU, DAT
tHD, STA
tHD, DAT
tLOW
tSP
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
START
CONDITION
REPEATED
START
CONDITION
STOP
CONDITION
Figure 3. 2-Wire Serial-Interface Timing Diagram
16
______________________________________________________________________________________
START
CONDITION
20W Stereo Class D Speaker Amplifier
with Volume Control
START and STOP Conditions
A master device initiates communication by issuing a
START condition. A START condition is a high to low
transition on SDA with SCL high. A STOP condition is a
low to high transition on SDA while SCL is high (Figure
4). A START (S) condition from the master signals the
beginning of a transmission to the MAX9744. The master terminates transmission, and frees the bus, by issuing a STOP (P) condition. The bus remains active if a
Repeated START (Sr) condition is generated instead of
a STOP condition.
S
Sr
P
SCL
SDA
Early STOP Conditions
The MAX9744 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition.
Slave Address
The slave address of the MAX9744 is 8 bits and consists of 3 fields: the first field is 5 bits wide and is fixed
(10010), the second is a 2 bit field which is set through
ADDR1 and ADDR2 (externally connected as logic-high
or logic-low), and the third field is a R/W flag bit. Set
R/W = 0 to write to the slave. A representation of the
slave address is shown in Table 3.
When ADDR1 and ADDR2 are connected to GND, serial interface communication is disabled. Table 4 summarizes the slave address of the device as a function of
ADDR1 and ADDR2.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9744 uses to handshake receipt of each byte of
data (see Figure 5). The MAX9744 pulls down SDA during the master-generated 9th clock pulse. The SDA line
must remain stable and low during the high period of
the acknowledge clock pulse. Monitoring ACK allows
for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is
busy or if a system fault has occurred. In the event of
an unsuccessful data transfer, the bus master may reattempt communication.
Figure 4. START, STOP, and Repeated START Conditions
Table 3. Slave Address Block
SA7 (MSB)
SA6
SA5
SA4
SA3
SA2
SA1
SA0 (LSB)
1
0
0
1
0
ADDR2
ADDR1
R/W
Table 4. Slave Address
ADDR2
ADDR1
SLAVE ADDRESS
0
0
I2C disabled
0
1
1001001_
1
0
1001010_
1
1
1001011_
CLOCK PULSE FOR
ACKNOWLEDGMENT
START
CONDITION
SCL
1
2
8
9
NOT ACKNOWLEDGE
SDA
ACKNOWLEDGE
Figure 5. Acknowledge
______________________________________________________________________________________
17
MAX9744
Bit Transfer
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period
of the SCL pulse. Changes in SDA while SCL is high
are control signals (see the START and STOP
Conditions section). SDA and SCL idle high when the
I2C bus is not busy.
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
Write Byte
A write to the MAX9744 includes transmission of a
START condition, the slave address with the R/W bit set
to 0 (see Table 3), one byte of data to the command
register, and a STOP condition. Figure 6 illustrates the
proper format for one frame.
A write to the MAX9744 consists of a 6-step sequence
as seen below:
1) The master sends a START condition.
2) The master sends the 7 bits slave ID plus a write
bit (low).
3) The addressed slave asserts an ACK on the data
line.
4) The master sends 8 data bits.
5) The active slave asserts an ACK (or NACK) on the
data line.
6) The master generates a stop condition.
Speaker Volume Control
The command register is used to control the volume
level of the speaker amplifier. The two MSBs (A1 and
A0) are set to 00, while V5–V0 is the data that is written
into the addresses register to set the volume level
(Tables 5 and 6).
WRITE BYTE FORMAT
S
SLAVE
ADDRESS
7 BITS
WR
ACK
DATA
P
8 BITS
0
SLAVE ADDRESS:
EQUIVALENT TO CHIPSELECT LINE OF A
3-WIRE INTERFACE.
ACK
DATA BYTE: GIVES A COMMAND.
Figure 6. Write Byte Format Example
Filterless Modulation/PWM
The MAX9744 features two output modulation schemes:
filterless modulation or classic PWM, selectable through
the I2C interface. Table 6 shows the register command
to set the output scheme.
When switching between schemes, the output is not
click-and-pop protected. To have click-and-pop protection when switching between output schemes, the
device must enter shutdown mode and be configured
to the new output scheme before the 220ms startup
sequence is terminated.
Table 5. Data Byte Format
D7 (MSB)
D6
D5
D4
D3
D2
D1
D0 (LSB)
A1
A0
V5
V4
V3
V2
V1
V0
Table 6. Command Register Programming
A0 A1
18
V5–V0
SETTING
A0 A1
V5–V0
XXXXXX
Reserved
SETTING
00
XXXXXX
Volume level (Table 7)
10
01
000000
Filterless modulation
11
000100
Increased volume
01
000001
Classic PWM
11
000101
Decreased volume
______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX9744
Table 7. Speaker Volume Levels
V5
V4
V3
V2
V1
V0
VOLUME
POSITION
SDA/VOL
VOLUME
VOLUME INPUT VOLTAGE (V)
ATTENUATION (dB)
1
1
1
1
1
1
63
0.100 x VDD
9.5
1
1
1
1
1
0
62
0.113 x VDD
8.8
1
1
1
1
0
1
61
0.125 x VDD
8.2
1
1
1
1
0
0
60
0.138 x VDD
7.6
1
1
1
0
1
1
59
0.151 x VDD
7.0
1
1
1
0
1
0
58
0.163 x VDD
6.5
1
1
1
0
0
1
57
0.176 x VDD
5.9
1
1
1
0
0
0
56
0.189 x VDD
5.4
1
1
0
1
1
1
55
0.202 x VDD
4.9
1
1
0
1
1
0
54
0.214 x VDD
4.4
1
1
0
1
0
1
53
0.227 x VDD
3.9
1
1
0
1
0
0
52
0.240 x VDD
3.4
1
1
0
0
1
1
51
0.252 x VDD
2.9
1
1
0
0
1
0
50
0.265 x VDD
2.4
1
1
0
0
0
1
49
0.278 x VDD
2.0
1
1
0
0
0
0
48
0.290 x VDD
1.6
1
0
1
1
1
1
47
0.303 x VDD
1.2
1
0
1
1
1
0
46
0.316 x VDD
0.5
1
0
1
1
0
1
45
0.329 x VDD
-0.5
1
0
1
1
0
0
44
0.341 x VDD
-1.9
1
0
1
0
1
1
43
0.354 x VDD
-3.4
1
0
1
0
1
0
42
0.367 x VDD
-5.0
1
0
1
0
0
1
41
0.379 x VDD
-6.0
1
0
1
0
0
0
40
0.392 x VDD
-7.1
1
0
0
1
1
1
39
0.405 x VDD
-8.9
1
0
0
1
1
0
38
0.417 x VDD
-9.9
1
0
0
1
0
1
37
0.430 x VDD
-10.9
1
0
0
1
0
0
36
0.443 x VDD
-12.0
1
0
0
0
1
1
35
0.456 x VDD
-13.1
1
0
0
0
1
0
34
0.468 x VDD
-14.4
1
0
0
0
0
1
33
0.481 x VDD
-15.4
1
0
0
0
0
0
32
0.494 x VDD
-16.4
______________________________________________________________________________________
19
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
Table 7. Speaker Volume Levels (continued)
20
V5
V4
V3
V2
V1
V0
VOLUME
POSITION
SDA/VOL
VOLUME
VOLUME INPUT VOLTAGE (V)
ATTENUATION (dB)
0
1
1
1
1
1
31
0.506 x VDD
-17.5
0
1
1
1
1
0
30
0.519 x VDD
-19.7
0
1
1
1
0
1
29
0.532 x VDD
-21.6
0
1
1
1
0
0
28
0.544 x VDD
-23.5
0
1
1
0
1
1
27
0.557 x VDD
-25.2
0
1
1
0
1
0
26
0.570 x VDD
-27.2
0
1
1
0
0
1
25
0.583 x VDD
-29.8
0
1
1
0
0
0
24
0.595 x VDD
-31.5
0
1
0
1
1
1
23
0.608 x VDD
-33.4
0
1
0
1
1
0
22
0.621 x VDD
-36.0
0
1
0
1
0
1
21
0.633 x VDD
-37.6
0
1
0
1
0
0
20
0.646 x VDD
-39.6
0
1
0
0
1
1
19
0.659 x VDD
-42.1
0
1
0
0
1
0
18
0.671 x VDD
-43.7
0
1
0
0
0
1
17
0.684 x VDD
-45.6
0
1
0
0
0
0
16
0.697 x VDD
-48.1
0
0
1
1
1
1
15
0.710 x VDD
-50.6
0
0
1
1
1
0
14
0.722 x VDD
-54.2
0
0
1
1
0
1
13
0.735 x VDD
-56.7
0
0
1
1
0
0
12
0.748 x VDD
-60.2
0
0
1
0
1
1
11
0.760 x VDD
-62.7
0
0
1
0
1
0
10
0.773 x VDD
-66.2
0
0
1
0
0
1
9
0.786 x VDD
-68.7
0
0
1
0
0
0
8
0.798 x VDD
-72.2
0
0
0
1
1`
1
7
0.811 x VDD
-74.7
0
0
0
1
1
0
6
0.824 x VDD
-78.3
0
0
0
1
0
1
5
0.837 x VDD
-80.8
0
0
0
1
0
0
4
0.849 x VDD
-84.3
0
0
0
0
1
1
3
0.862 x VDD
-86.8
0
0
0
0
1
0
2
0.875 x VDD
-90.3
0
0
0
0
0
1
1
0.887 x VDD
-92.8
0
0
0
0
0
0
0
0.900 x VDD
MUTE
______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
Filterless Class D Operation
The MAX9744 meets common EMC radiation limits without a filter when the speaker leads are less than approximately 10cm. Using lengths beyond 10cm is possible
verifying against the appropriate EMC standard.
For longer speaker wire lengths, up to approximately
1m, use a simple ferrite bead and capacitor filter to
meet EMC limits. Select a ferrite bead with 100Ω to
600Ω impedance, and rated for at least 3A. The capacitor value varies based on the ferrite bead chosen and
the actual speaker lead length. Select the capacitor
value based on EMC performance. See Figure 7 for the
correct connections of these components.
When evaluating the device without a filter or a ferrite
bead filter, include a series inductor (68µH for 8Ω load
and 33µH for 4Ω load) to model the actual loudspeaker’s behavior. Omitting this inductor reduces the efficiency, the THD+N performance, and the output power
of the MAX9744.
Inductor-Based Output Filters
Some applications use the MAX9744 with a full inductor/capacitor-based (LC) output filter. This is common
for longer speaker lead lengths and to gain increased
margin to EMC limits. Select the PWM output mode and
use fixed-frequency modulation mode for best audio
performance. See Figure 8 for the correct connections
of these components.
The component selection is based on the load impedance of the speaker. Table 8 lists suggested values for
a variety of load impedances.
Inductors L1 and L2 and capacitor C1 form the primary
output filter. In addition to these primary filter components, other components in the filter improve its functionality. Capacitors C4 and C5 plus resistors R1 and
R2 form a Zobel at the output. A Zobel corrects the output loading to compensate for the rising impedance of
the loudspeaker. Without a Zobel, the filter has a peak
in its response near the cutoff frequency. Capacitors
C2 and C3 provide common-mode noise suppression
to reduce radiated emissions.
Table 8. Suggested Values for LC filter
BOOT_+
OUT_+
CBOOT
0.1μF
MAX9744
CFILT
470pF
RL (Ω)
L1, L2
(µH)
C1 (µF)
C2, C3
(µF)
R1, R2
(Ω)
C4, C5
(µF)
4
10
0.47
0.47
10
0.47
6
15
0.33
0.22
15
0.33
8
22
0.22
0.22
22
0.22
OUT_-
BOOT_-
CFILT
470pF
CBOOT
0.1μF
Figure 7. Ferrite Bead Filter
4
1, 2
BOOT+
OUT+
CBOOT
0.1μF
L1
MAX9744
C2
C4
R1
RL
C1
14, 18
15
L2
OUT-
BOOT-
CBOOT
0.1μF
C3
C5
R2
Figure 8. Output Filter for PWM Mode
______________________________________________________________________________________
21
MAX9744
Applications Information
Component Selection
Gain-Setting Resistors
External feedback resistors set the gain of the
MAX9744. The output stage has an internal 20dB gain
in addition to the externally set input stage gain. Set the
maximum gain by using resistors RF and RIN (Figure 9)
as follows:
⎛R ⎞
A V = −30 ⎜ F ⎟ V / V
⎝ RIN ⎠
Choose R F between 10kΩ and 50kΩ. Note that the
actual gain of the amplifier is dependent on the volume
level setting. For example, with the volume set to
+9.5dB, the amplifier gain would be 9.5dB plus 20dB,
assuming RIN = RF.
The input amplifier can be configured into a variety of
circuits. The FB terminal is an actual operational amplifier output, allowing the MAX9744 to be configured as a
summing amplifier, a filter, or an equalizer, for example.
Input Capacitor
An input capacitor (CIN) in conjunction with the input
impedance of the MAX9744 form a highpass filter that
removes the DC bias from an incoming signal. The ACcoupling capacitor allows the amplifier to automatically
bias the signal to an optimum DC level. Assuming zero
source impedance, the -3dB point of the highpass filter
is given by:
f−3dB =
1
2πRINCIN
Choose CIN that f-3dB is well below the lowest frequency of interest. Use capacitors whose dielectrics have
low-voltage coefficients, such as tantalum or aluminum
electrolytic. Capacitors with high-voltage coefficients,
such as ceramics, may result in increased distortion at
low frequencies.
DC-Coupled Input
The input amplifier can accept DC-coupled inputs that
are biased to the amplifier’s bias voltage. DC-coupling
eliminates input-coupling capacitors, reducing component count to potentially one external component. In this
configuration the highpass filtering effect of the capacitors
is lost, allowing low-frequency signals to be amplified.
Power Supplies
The MAX9744 features separate supplies for each portion of the device, allowing for the optimum combination
of headroom power dissipation and noise immunity. The
speaker amplifier is powered from PVDD and can range
from 4.5V to 14V. The remainder of the device is powered by VDD. Power supplies are independent of each
other so sequencing is not necessary. Power may be
supplied by separate sources or derived from a single
higher source using a linear regulator (Figure 10).
BIAS Capacitor
BIAS is the output of the internally generated DC bias
voltage. The BIAS bypass capacitor, CBIAS, improves
PSRR and THD+N by reducing power supply and other
noise sources at the common-mode bias node, and
also generates the clickless/popless, startup/shutdown,
DC bias waveforms for the speaker amplifiers. Bypass
BIAS with a 2.2µF capacitor to GND.
4.5V TO 14.5V
MAX9744
AUDIO CIN
INPUT
BOOT+
IN
IN
RF
FB
OUT+
VOLUME
CONTROL
9.5dB (max)
PVDD
1μF
1μF
RIN
CLASS D
20dB
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
OUT
3.3V
SHDN
VDD
MAX1615
MAX9744
OUT-
GND
BOOT-
GND
Figure 9. Setting Gain
22
Figure 10. Using a Linear Regulator to Produce 3.3V from a
Higher Power Supply
______________________________________________________________________________________
20W Stereo Class D Speaker Amplifier
with Volume Control
Use large, low-resistance output traces. Current drawn
from the outputs increase as load impedance decreases. High output trace resistance decreases the power
delivered to the load. Large output, supply, and GND
traces allow more heat to move from the MAX9744 to
the air, decreasing the thermal impedance of the circuit.
The MAX9744 thin QFN package features an exposed
thermal pad on its underside. This pad lowers the package’s thermal resistance by providing a direct heat conduction path from the die to the PCB. Connect the
exposed thermal pad to PGND by using a large pad and
multiple vias to the PGND plane. The exposed pad must
be connected to PGND for proper device operation.
Proper layout and grounding are essential for optimum
performance. Use large traces for the power-supply
inputs and amplifier outputs to minimize losses due to
parasitic trace resistance. Large traces also aid in moving heat away from the package. Proper grounding
improves audio performance, minimizes crosstalk
between channels, and prevents any switching noise
from coupling into the audio signal. Connect PGND and
GND together at a single point on the PCB. Route all
traces that carry switching transients away from GND
and the traces/components in the audio signal path.
Connect all PVDD power supplies together and bypass
with a 1µF capacitor to PGND. Connect all VDD power
supplies together and bypass with a 1µF capacitor to
GND. Place a bulk capacitor between PVDD and PGND
if needed.
N.C.
MUTE
SYNC
SYNCOUT
GND
VDD
PVDD
PVDD
OUTR+
BOOTR+
TOP VIEW
OUTR+
Pin Configuration
33 32 31 30 29 28 27 26 25 24 23
PGND
34
22
SHDN
PGND
35
21
VDD
OUTR-
36
20
BIAS
OUTR-
37
19
INR
BOOTR-
38
18
FBR
PGND
39
17
FBL
INL
MAX9744
BOOTL-
40
16
OUTL-
41
15
GND
OUTL-
42
14
ADDR2
PGND
43
13
ADDR1
PGND
44
12
GND
OUTL+
PVDD
PVDD
7
8
9
10 11
GND
OUTL+
6
VDD
5
SCLK/PWM
4
SDA/VOL
3
VDD
2
GND
1
BOOTL+
+
TQFN
(7mm x 7mm)
______________________________________________________________________________________
23
MAX9744
Supply Bypassing, Layout,
and Grounding
20W Stereo Class D Speaker Amplifier
with Volume Control
MAX9744
Functional Diagrams/Typical Application Circuits
I2C MODE
3V TO 3.6V
4.5V TO 14V
VDD
PVDD
1μF
6, 10, 21, 28
RF
20kΩ
RIN
20kΩ
4, 5, 29, 30
1 BOOTL+
FBL 17
MAX9744
CLASS D
CIN
0.47μF
100μF
1μF
INL 16
CBOOT
0.1μF
2, 3 OUTL+
41, 42 OUTL-
CBOOT
0.1μF
40 BOOTLBIAS
CIN
0.47μF
RIN
20kΩ
VOLUME
CONTROL
INR 19
PVDD
33 BOOTR+
RF
20kΩ
MUTE 24
SHDN 22
SDA/VOL 8
TO μC
VDD
VDD
CLASS D
FBR 18
MUTE
CBOOT
0.1μF
31, 32 OUTR+
36, 37 OUTR-
CBOOT
0.1μF
38 BOOTR-
SHUTDOWN
CONTROL
SCLK 9
ADDR1 13
I2C
ADDR2 14
ANALOG
CONTROL
SYNC 25
N.C.
26
OSCILLATOR
BIAS
23
7, 11, 12,
15, 27
GND
SYNCOUT
20 BIAS
34, 35, 39, 43, 44
PGND
(SHOWN IN I2C MODE, AV = 29.5dB, f-3dB = 17Hz, SPREAD-SPECTRUM MODE, MUTE OFF, SLAVE ADDRESS = 1001011_)
24
______________________________________________________________________________________
CBIAS
2.2μF
20W Stereo Class D Speaker Amplifier
with Volume Control
ANALOG MODE
3V TO 3.6V
4.5V TO 14V
VDD
PVDD
1μF
6, 10, 21, 28
RF
20kΩ
RIN
20kΩ
4, 5, 29, 30
1 BOOTL+
FBL 17
MAX9744
CLASS D
CIN
0.47μF
INL 16
2, 3 OUTL+
BIAS
RIN
20kΩ
VOLUME
CONTROL
INR 19
CBOOT
0.1μF
41, 42 OUTL40 BOOTL-
CIN
0.47μF
100μF
1μF
CBOOT
0.1μF
PVDD
33 BOOTR+
RF
20kΩ
MUTE 24
SHDN 22
VDD
SDA/VOL 8
SCLK/PWM 9
ADDR1 13
ADDR2 14
VDD
SYNC 25
N.C.
CLASS D
FBR 18
MUTE
SHUTDOWN
CONTROL
31, 32 OUTR+
CBOOT
0.1μF
36, 37 OUTR38 BOOTR-
CBOOT
0.1μF
I2C
OUTPUT
MODULATION
ANALOG
CONTROL
26
OSCILLATOR
BIAS
23
7, 11, 12,
15, 27
GND
34, 35, 39, 43, 44
SYNCOUT
20 BIAS
CBIAS
2.2μF
PGND
(SHOWN IN ANALOG MODE, AV = 29.5dB, f-3dB = 17Hz, SPREAD-SPECTRUM MODE, MUTE OFF, SLAVE ADDRESS = 1001011_)
______________________________________________________________________________________
25
MAX9744
Functional Diagrams/Typical Application Circuits (continued)
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
E
DETAIL A
32, 44, 48L QFN.EPS
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
(NE-1) X e
E/2
k
e
D/2
C
L
(ND-1) X e
D
D2
D2/2
b
L
E2/2
C
L
k
E2
C
L
C
L
L
L
e
A1
A2
e
A
PACKAGE OUTLINE,
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
26
______________________________________________________________________________________
G
1
2
20W Stereo Class D Speaker Amplifier
with Volume Control
PACKAGE OUTLINE,
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
21-0144
Chip Information
PROCESS: BICMOS
G
2
2
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
44 TQFN-EP
T4477-3
21-0144
______________________________________________________________________________________
27
MAX9744
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX9744
20W Stereo Class D Speaker Amplifier
with Volume Control
Revision History
REVISION
NUMBER
REVISION
DATE
0
3/08
Initial release
1
9/08
Updated EC table for single pass flow
DESCRIPTION
PAGES
CHANGED
—
2, 4, 5
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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