TLC5940
PWP
www.ti.com
RHB
NT
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
16 CHANNEL LED DRIVER WITH DOT CORRECTION AND GRAYSCALE PWM CONTROL
FEATURES
APPLICATIONS
• 16 Channels
• 12 bit (4096 Steps) Grayscale PWM Control
• Dot Correction
– 6 bit (64 Steps)
– Storable in Integrated EEPROM
• Drive Capability (Constant-Current Sink)
– 0 mA to 60 mA (VCC < 3.6 V)
– 0 mA to 120 mA (VCC > 3.6 V)
• LED Power Supply Voltage up to 17 V
• VCC = 3 V to 5.5 V
• Serial Data Interface
• Controlled In-Rush Current
• 30MHz Data Transfer Rate
• CMOS Level I/O
• Error Information
– LOD: LED Open Detection
– TEF: Thermal Error Flag
•
•
•
•
1
2
VCC
GND
SCLK
DESCRIPTION
The TLC5940 is a 16-channel, constant-current sink
LED driver. Each channel has an individually
adjustable 4096-step grayscale PWM brightness
control and a 64-step, constant-current sink (dot
correction). The dot correction adjusts the brightness
variations between LED channels and other LED
drivers. The dot correction data is stored in an
integrated EEPROM. Both grayscale control and dot
correction are accessible via a serial interface. A
single external resistor sets the maximum current
value of all 16 channels.
The TLC5940 features two error information circuits.
The LED open detection (LOD) indicates a broken or
disconnected LED at an output terminal. The thermal
error flag (TEF) indicates an overtemperature
condition.
SIN
XLAT
VPRG
IREF
Max. OUTn
Current
VREF =1.24 V
VPRG
1
DCPRG
CNT
1 0
GS Register
0
DCPRG
1
DC Register
0
GS Counter
CNT
5
LED Open Detection
CNT
192
12−Bit Grayscale
PWM Control
GS Register
12
23
DCPRG
1
96
95
1 0
VPRG
96
6 DC EEPROM11
Temperature
Error Flag
(TEF)
0
Constant Current
Driver
OUT1
Delay
x1
LED Open Detection
VPRG
CNT
Blank
1
6−Bit Dot
Correction
DC Register
11 0
6
96
LED Open
Detection
(LOD)
OUT0
Delay
x0
VPRG
96
192
Constant Current
Driver
6−Bit Dot
Correction
0
0 DC EEPROM 5
Input
Shift
Register
Status 0
Information:
LOD,
TED,
DC DATA
191
12−Bit Grayscale
PWM Control
11
0
0
GSCLK
BLANK
Monocolor, Multicolor, Full-Color LED Displays
LED Signboards
Display Backlighting
General, High-Current LED Drive
Input
Shift
Register
12−Bit Grayscale
PWM Control
GS Register
180
191
DCPRG
1
XERR
90
191
90
SOUT
DC Register
95 0
DC EEPROM
95
Constant Current
Driver
OUT15
Delay
x15
6−Bit Dot
Correction
LED Open Detection
VPRG
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
TLC5940
www.ti.com
SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
PACKAGE (1)
PART NUMBER
28-pin HTSSOP PowerPAD™
TLC5940PWP
32-pin 5mm x 5mm QFN
TLC5940RHB
28-pin PDIP
TLC5940NT
TA
–40°C to 85°C
(1)
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS.
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VI
Input voltage range (2)
IO
Output current (dc)
VI
Input voltage range
VO
VCC
–0.3V to 6V
130mA
Output voltage range
EEPROM program range
V(BLANK), V(DCPRG), V(SCLK), V(XLAT), V(SIN), V(GSCLK), V(IREF)
–0.3V to VCC +0.3V
V(SOUT), V(XERR)
–0.3V to VCC +0.3V
V(OUT0) to V(OUT15)
–0.3V to 18V
V(VPRG)
–0.3V to 24V
EEPROM write cycles
50
ESD rating
HBM (JEDEC JESD22-A114, Human Body Model)
2kV
CBM (JEDEC JESD22-C101, Charged Device Model)
500V
Tstg
Storage temperature range
TA
Operating ambient temperature range
Package thermal impedance
(1)
(2)
(3)
(4)
2
–55°C to 150°C
(3)
–40°C to 85°C
HTSSOP (PWP) (4)
31.58°C/W
QFN (RHB)
35.9°C/W
PDIP (NP)
48°C/W
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The package thermal impedance is calculated in accordance with JESD 51-7.
With PowerPAD soldered on PCB with 2 oz. (56,7 grams) trace of copper. See SLMA002 for further information.
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
DC CHARACTERISTICS
VCC
Supply Voltage
VO
Voltage applied to output (OUT0–OUT15)
3
VIH
High-level input voltage
VIL
Low-level input voltage
IOH
High-level output current
VCC = 5V at SOUT
IOL
Low-level output current
VCC = 5V at SOUT, XERR
5.5
V
17
V
0.8 VCC
VCC
V
GND
0.2 VCC
V
–1
mA
1
mA
OUT0 to OUT15, VCC < 3.6V
60
mA
OUT0 to OUT15, VCC > 3.6V
120
mA
23
V
85
°C
IOLC
Constant output current
V(VPRG)
EEPROM program voltage
TA
Operating free-air temperature range
20
22
-40
AC CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
f(SCLK)
Data shift clock frequency
SCLK
30
MHz
f(GSCLK)
Grayscale clock frequency
GSCLK
30
MHz
twh0/twl0
SCLK pulse duration
SCLK = H/L (see Figure 11)
16
ns
twh1/twl1
GSCLK pulse duration
GSCLK = H/L (see Figure 11)
16
ns
twh2
XLAT pulse duration
XLAT = H (see Figure 11)
20
ns
twh3
BLANK pulse duration
BLANK = H (see Figure 11)
20
ns
5
ns
tsu0
SIN to SCLK ↑ (1) (see Figure 11)
tsu1
SCLK ↓ to XLAT ↑ (see Figure 11)
10
ns
tsu2
VPRG ↑ ↓ to SCLK ↑ (see Figure 11)
10
ns
VPRG ↑ ↓XLAT ↑ (see Figure 11)
10
ns
tsu4
BLANK ↓ to GSCLK ↑ (see Figure 11)
10
ns
tsu5
XLAT ↑ to GSCLK ↑ (see Figure 11)
30
ns
tsu6
VPRG ↑ to DCPRG ↑ (see Figure 16)
1
ms
th0
SCLK ↑ to SIN (see Figure 11)
3
ns
th1
XLAT ↓ to SCLK ↑ (see Figure 11)
10
ns
th2
SCLK ↑ to VPRG ↑ ↓ (see Figure 11)
10
ns
XLAT ↓ to VPRG ↑ ↓ (see Figure 11)
10
ns
th4
GSCLK ↑ to BLANK ↑ (see Figure 11)
10
ns
th5
DCPRG ↓ to VPRG ↓ (see Figure 11)
1
ms
tprog
Programming time for EEPROM (see Figure 16)
20
ms
tsu3
Hold Time
th3
(1)
Setup time
↑ and ↓ indicates a rising edge, and a falling edge respectively.
DISSIPATION RATINGS
(1)
PACKAGE
POWER RATING
TA < 25°C
DERATING FACTOR
ABOVE TA = 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
28-pin HTSSOP with
PowerPAD™ (1)soldered
3958mW
31.67mW/C
2533mW
2058mW
28-pin HTSSOP with PowerPAD™
unsoldered
2026mW
16.21mW/°C
1296mW
1053mW
32-pin QFN (1)
3482mW
27.86mW/°C
2228mW
1811mW
28-pin PDIP
2456mW
19.65mW/°C
1572mW
1277mW
The PowerPAD is soldered to the PCB with a 2 oz. (56,7 grams) copper trace. See SLMA002 for further information.
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS
VCC = 3 V to 5.5 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
High-level output voltage
IOH = -1mA, SOUT
VOL
Low-level output voltage
IOL = 1mA, SOUT
II
Input current
MIN
TYP
Supply current
VI = VCC or GND; BLANK, DCPRG, GSCLK, SCLK, SIN,
XLAT
–1
1
VI = GND; VPRG
–1
1
µA
50
4
10
No data transfer, all output OFF,
VO = 1V, R(IREF) = 10kΩ
0.9
6
No data transfer, all output OFF,
VO = 1V, R(IREF) = 1.3kΩ
5.2
12
Data transfer 30MHz, all output ON,
VO = 1V, R(IREF) = 1.3kΩ
16
25
Data transfer 30MHz, all output ON,
VO = 1V, R(IREF) = 640Ω
30
60
61
69
mA
0.1
µA
Constant sink current (see
Figure 2)
All output ON, VO = 1V, R(IREF) = 640Ω
Ilkg
Leakage output current
All output OFF, VO = 15V, R(IREF) = 640Ω,
OUT0 to OUT15
ΔIO(LC0)
V
VI = 22V; VPRG; DCPRG = VCC
IO(LC)
Constant sink current error
(see Figure 2)
UNIT
V
0.5
VI = VCC; VPRG
ICC
MAX
VCC –0.5
mA
mA
54
All output ON, VO = 1V, R(IREF) = 640Ω,
OUT0 to OUT15, –20°C to 85°C
1
±4
All output ON, VO = 1V, R(IREF) = 640Ω,
OUT0 to OUT15 (1)
1
8
All output ON, VO = 1V, R(IREF) = 320Ω,
OUT0 to OUT15, –20°C to 85°C
1
6
All output ON, VO = 1V, R(IREF) = 320Ω,
VCC = 4.5V to 5.5V, OUT0 to OUT15 (1)
±1
±8
%
ΔIO(LC1)
Constant sink current error
(see Figure 2)
Device to device, Averaged current from OUT0 to
OUT15, R(IREF) = 1920Ω (20mA) (2)
–2
+0.4
4
%
ΔIO(LC2)
Constant sink current error
(see Figure 2)
Device to device, Averaged current from OUT0 to
OUT15, R(IREF) = 480Ω (80mA) (2)
–2.7
+2
±4
%
All output ON, VO = 1V, R(IREF) = 640Ω
OUT0 to OUT15, VCC = 3V to 5.5V (3)
1
±4
%/V
All output ON, VO = 1V, R(IREF) = 320Ω ,
OUT0 to OUT15, VCC = 3V to 5.5V (3)
±1
±6
%/V
All output ON, VO = 1V to 3V, R(IREF) = 640Ω,
OUT0 to OUT15 (4)
±2
±6
%/V
All output ON, VO = 1V to 3V, R(IREF) = 320Ω,
OUT0 to OUT15 (4)
2
8
%/V
ΔIO(LC3)
ΔIO(LC4)
Line regulation (see Figure 2)
Load regulation (see Figure 2)
T(TEF)
Thermal error flag threshold
V(LED)
LED open detection threshold
V(IREF)
Reference voltage
output
(1)
(2)
(3)
(4)
(5)
4
Junction temperature (5)
R(IREF) = 640Ω
150
1.20
170
C
0.3
0.4
V
1.24
1.28
V
The deviation of each output from the average of OUT0-15 constant current. It is calculated by Equation 1 in Table 1.
The deviation of average of OUT1-15 constant current from the ideal constant-current value. It is calculated by Equation 2 in Table 1.
The ideal current is calculated by Equation 3 in Table 1.
The line regulation is calculated by Equation 4 in Table 1.
The load regulation is calculated by Equation 5 in Table 1.
Not tested. Specified by design
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
Table 1. Test Parameter Equations
D(%) =
D(%) =
I OUTn - I OUTavg _ 0 -15
IOUTavg _ 0 -15
IOUTavg - I OUT (IDEAL )
I OUT (IDEAL )
´ 100
(1)
´ 100
(2)
æ 1.24 V ö
÷÷
IOUT (IDEAL ) = 31.5 ´ çç
è R IREF ø
D(% / V ) =
D(% / V ) =
(3)
(IOUTn at VCC = 5.5 V ) - (I OUTn at VCC = 3.0 V ) 100
´
(I OUTn at VCC = 3.0 V )
2.5
(4)
(IOUTn at VOUTn = 3.0 V ) - (IOUTn at VOUTn = 1.0 V ) 100
´
(IOUTn at VOUTn = 1.0 V )
2 .0
(5)
SWITCHING CHARACTERISTICS
VCC = 3V to 5.5V, TA = -40°C to 85°C (unless otherwise noted)
PARAMETER
tr0
tr1
tf0
tf1
Rise time
Fall time
TEST CONDITIONS
MIN
TYP
SOUT
MAX
16
OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh
10
SOUT
30
16
OUTn, VCC = 5V, TA = 60°C, DCn = 3Fh
10
30
UNIT
ns
ns
tpd0
SCLK to SOUT (see Figure 11)
30
ns
tpd1
BLANK to OUT0
60
ns
tpd2
OUTn to XERR (see Figure 11 )
1000
ns
tpd3
Propagation delay time
GSCLK to OUT0 (see Figure 11 )
60
ns
tpd4
XLAT to IOUT (dot correction) (see Figure 11 )
60
ns
tpd5
DCPRG to OUT0 (see Figure 11)
30
ns
20
30
ns
–50
–90
ns
td
Output delay time
OUTn to OUT(n+1) (see Figure 11 )
ton-err
Output on-time error
touton– Tgsclk (see Figure 11), GSn = 01h, GSCLK = 11 MHz
10
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
DEVICE INFORMATION
PWP PACKAGE
(TOP VIEW)
GND
BLANK
XLAT
SCLK
SIN
VPRG
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Thermal
PAD
NT PACKAGE
(TOP VIEW)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
IREF
DCPRG
GSCLK
SOUT
XERR
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
OUT1
1
28
OUT0
OUT2
2
27
VPRG
OUT3
3
26
SIN
OUT4
4
25
SCLK
OUT5
5
24
XLAT
OUT6
6
23
BLANK
OUT7
7
22
GND
OUT8
8
21
VCC
OUT9
9
20
IREF
OUT10
10
19
DCPRG
OUT11
11
18
GSCLK
OUT12
12
17
SOUT
OUT13
13
16
XERR
OUT14
14
15
OUT15
OUT14
OUT13
OUT12
OUT11
20
18
17
OUT15
21
19
SOUT
XERR
23
22
GSCLK
24
RHB PACKAGE
(TOP VIEW)
DCPRG
25
16
OUT10
IREF
26
15
OUT9
VCC
27
14
OUT8
13
NC
NC
28
THERMAL
PAD
OUT6
9
OUT5
OUT4 8
10
32
OUT3 7
31
XLAT
OUT2 6
BLANK
OUT1 5
OUT7
OUT0 4
NC
11
SIN 2
12
30
VPRG 3
29
SCLK 1
NC
GND
NC − No internal connection
6
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
TERMINAL FUNCTION
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DIP
PWP
RHB
BLANK
23
2
31
I
Blank all outputs. When BLANK = H, all OUTn outputs are forced OFF. GS counter is also
reset. When BLANK = L, OUTn are controlled by grayscale PWM control.
DCPRG
19
26
25
I
Switch DC data input. When DCPRG = L, DC is connected to EEPROM. When DCPRG = H,
DC is connected to the DC register.
DCPRG also controls EEPROM writing, when VPRG = V(PRG). EEPROM data = 3Fh (default)
GND
22
1
30
G
Ground
GSCLK
18
25
24
I
Reference clock for grayscale PWM control
IREF
20
27
26
I
Reference current terminal
NC
–
–
12, 13,
28, 29
OUT0
28
7
4
O
Constant current output
OUT1
1
8
5
O
Constant current output
OUT2
2
9
6
O
Constant current output
OUT3
3
10
7
O
Constant current output
OUT4
4
11
8
O
Constant current output
OUT5
5
12
9
O
Constant current output
OUT6
6
13
10
O
Constant current output
OUT7
7
14
11
O
Constant current output
OUT8
8
15
14
O
Constant current output
OUT9
9
16
15
O
Constant current output
OUT10
10
17
16
O
Constant current output
OUT11
11
18
17
O
Constant current output
OUT12
12
19
18
O
Constant current output
OUT13
13
20
19
O
Constant current output
OUT14
14
21
20
O
Constant current output
OUT15
15
22
21
O
Constant current output
SCLK
25
4
1
I
Serial data shift clock
SIN
26
5
2
I
Serial data input
SOUT
17
24
23
O
Serial data output
VCC
21
28
27
I
Power supply voltage
VPRG
27
6
3
I
Multifunction input pin. When VPRG = GND, the device is in GS mode. When VPRG = VCC, the
device is in DC mode. When VPRG = V(VPRG), DC register data can programmed into DC
EEPROM with DCPRG=HIGH. EEPROM data = 3Fh (default)
XERR
16
23
22
O
Error output. XERR is an open-drain terminal. XERR goes L when LOD or TEF is detected.
XLAT
24
3
32
I
Level triggered latch signal. When XLAT = high, the TLC5940 writes data from the input shift
register to either GS register (VPRG = low) or DC register (VPRG = high). When XLAT = low,
the data in GS or DC register is held constant.
No connection
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PARAMETER MEASUREMENT INFORMATION
PIN EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
Resistor values are equivalent resistances, and they are not tested.
INPUT EQUIVALENT CIRCUIT
(BLANK, XLAT, SCLK, SIN, GSCLK, DCPRG)
OUTPUT EQUIVALENT CIRCUIT (SOUT)
VCC
VCC
23 W
400 W
INPUT
SOUT
23 W
GND
GND
INPUT EQUIVALENT CIRCUIT (IREF)
V(IREF)
OUTPUT EQUIVALENT CIRCUIT (XERR)
VCC
_
400 W
INPUT
23 W
Amp
XERR
+
100 W
GND
GND
INPUT EQUIVALENT CIRCUIT (VCC)
OUTPUT EQUIVALENT CIRCUIT (OUT)
INPUT
OUT
GND
INPUT EQUIVALENT CIRCUIT (VPRG)
INPUT
GND
GND
Figure 1. Input and Output Equivalent Circuits
8
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PARAMETER MEASUREMENT INFORMATION (continued)
tr0, tf0, tpd0
tr1, tf1, tpd1, tpd2, tpd3, tpd4, tpd5, td
VO = 4V
Testpoint
SOUT
RL = 51W
CL = 15pF
Testpoint
OUTn
CL = 15pF
IO(LC), DIO(LC0), DIO(LC1), DIO(LC2), DIO(LC3)
OUTn
DIO(LC4)
OUTn
VO = 1V
VO = 1V to 3V
V(IREF)
tpd3
VCC
Testpoint
IREF
R (IREG) = 640W
470kΩ
XERR
Figure 2. Parameter Measurement Circuits
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SLVS515C – DECEMBER 2004 – REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
REFERENCE RESISTOR
vs
OUTPUT CURRENT
POWER DISSIPATION RATE
vs
FREE-AIR TEMPERATURE
4k
10 k
TLC5940PWP
PowerPAD Soldered
Power Dissipation Rate - mW
Reference Resistor, R(IREF) - W
7.68 kΩ
1.92 kΩ
1k
0.96 kΩ
0.64 kΩ
0.48 kΩ
0.38 kΩ
0.32 kΩ
100
0
20
40
60
80
100
TLC5940RHB
3k
TLC5940NT
2k
TLC5940PWP
PowerPAD Unsoldered
1k
0
-40
120
-20
IO − Output Current − mA
80
60
100
TA − Free-Air Temperature − C
Figure 4.
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
OUTPUT CURRENT
vs
OUTPUT VOLTAGE
65
TA = 25°C,
VCC = 5 V
IO = 120 mA
IO = 60 mA,
VCC = 5 V
64
TA = 85°C
63
IO = 100 mA
IO - Output Current - mA
IO - Output Current - mA
40
Figure 3.
100
IO = 80 mA
80
IO = 60 mA
60
IO = 40 mA
40
62
61
60
TA = 25°C
TA = -40°C
59
58
IO = 20 mA
57
IO = 5 mA
56
20
55
0
0
0.5
1
1.5
2
VO - Output Voltage - V
2.5
3
0
0.5
1
1.5
2
2.5
3
VO - Output Voltage - V
Figure 5.
10
20
o
140
120
0
Figure 6.
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TYPICAL CHARACTERISTICS (continued)
CONSTANT OUTPUT CURRENT, ΔIOLC
vs
AMBIENT TEMPERATURE
CONSTANT OUTPUT CURRENT, ΔIOLC
vs
OUTPUT CURRENT
8
8
TA = 25°C,
VCC = 5 V
6
6
Δ IOLC - Constant Output Current - %
Δ IOLC - Constant Output Current - %
IO = 60 mA
4
VCC = 3.3 V
2
0
-2
VCC = 5 V
-4
-6
-8
-40
0
20
40
60
80
TA - Ambient Temperature - °C
0
-2
-4
-6
0
100
20
40
60
IO - Output Current - mA
80
Figure 7.
Figure 8.
OUTPUT CURRENT
vs
DOT CORRECTION LINEARITY (ABS VALUE)
OUTPUT CURRENT
vs
DOT CORRECTION LINEARITY (ABS VALUE)
70
TA = 25°C,
VCC = 5 V
IO = 60 mA,
VCC = 5 V
IO = 120 mA
60
100
IO = 80 mA
80
IO = 60 mA
60
40
IO = 30 mA
20
IO - Output Current - mA
IO - Output Current - mA
2
-8
-20
140
120
4
TA = 25°C
TA = 85°C
50
TA = -40°C
40
30
20
10
IO = 5 mA
0
0
0
10
20
30
40
50
Dot Correction Data - dec
60
70
0
Figure 9.
10
20
30
40
50
Dot Correction Data - dec
Figure 10.
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PRINCIPLES OF OPERATION
SERIAL INTERFACE
The TLC5940 has a flexible serial interface, which can be connected to microcontrollers or digital signal
processors in various ways. Only 3 pins are needed to input data into the device. The rising edge of SCLK signal
shifts the data from the SIN pin to the internal register. After all data is clocked in, a high-level pulse of XLAT
signal latches the serial data to the internal registers. The internal registers are level-triggered latches of XLAT
signal. All data are clocked in with the MSB first. The length of serial data is 96 bit or 192 bit, depending on the
programming mode. Grayscale data and dot correction data can be entered during a grayscale cycle. Although
new grayscale data can be clocked in during a grayscale cycle, the XLAT signal should only latch the grayscale
data at the end of the grayscale cycle. Latching in new grayscale data immediately overwrites the existing
grayscale data. Figure 11 shows the timing chart. More than two TLC5940s can be connected in series by
connecting an SOUT pin from one device to the SIN pin of the next device. An example of cascading two
TLC5940s is shown in Figure 12 and the timing chart is shown in Figure 13. The SOUT pin can also be
connected to the controller to receive status information from TLC5940 as shown in Figure 22.
VPRG
DC Data Input Mode
GS Data Input Mode
th3
tsu3
twh2
XLAT
1st GS Data Input Cycle
DC
MSB
SIN
th2
SCLK
GS1
LSB
tsu2
GS2
MSB
GS2
LSB
th1
tsu1
1
96
1
2nd GS Data Input Cycle
GS1
MSB
DC
LSB
GS3
MSB
tsu0
twh0
192
193
th0
193
192
1
tpd0
twl0
-
SOUT
DC
MSB
-
GS1
MSB
-
1
SID1 SID1
MSB MSB-1
SID2 SID2
MSB MSB-1
SID1 GS2
LSB MSB
twh3
BLANK
1st GS Data Output Cycle
tsu5
GSCLK
2nd GS Data Output Cycle
1
tpd4
4096
1
tpd3
tpd1
Tgsclk
tpd3
OUT0
(current)
td
tpd1 + td
twh1
tsu4
th4
tpd3 + td
twl1
touton
OUT1
(current)
15 x td
tpd1 + 15 x td
OUT15
(current)
tpd2
XERR
Figure 11. Serial Data Input Timing Chart
SIN(a)
SIN
SOUT
TLC5940 (a)
SIN
SOUT
SOUT(b )
TLC5940 (b)
SCLK, XLAT,
BLANK,
GSCLK,
DCPRG,
VPRG
Figure 12. Cascading Two TLC5940 Devices
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VPRG
XLAT
SIN(a )
SCLK
DCb
MSB
DCa
LSB
GSb1
MSB
1
192
1
384
96X2
-
SOUT(b )
GSb2
MSB
GSa1
LSB
385
GSa2
LSB
GSb3
MSB
385
384
1
1
192X2
DCb
MSB
-
SIDb1 SIDb1
MSB MSB-1
GSb1
MSB
-
SIDa1
LSB
SIDb2 SIDb2
MSB MSB-1
GSb2
MSB
BLANK
1
GSCLK
1
4096
OUT0
(current)
OUT1
(current)
OUT15
(current)
XERR
Figure 13. Timing Chart for Two Cascaded TLC5940 Devices
ERROR INFORMATION OUTPUT
The open-drain output XERR is used to report both of the TLC5940 error flags, TEF and LOD. During normal
operating conditions, the internal transistor connected to the XERR pin is turned off. The voltage on XERR is
pulled up to VCC through an external pullup resistor. If TEF or LOD is detected, the internal transistor is turned
on, and XERR is pulled to GND. Since XERR is an open-drain output, multiple ICs can be OR'ed together and
pulled up to VCC with a single pullup resistor. This reduces the number of signals needed to report a system error
(see Figure 22).
To differentiate LOD and TEF signal from XERR pin, LOD can be masked out with BLANK = HIGH.
Table 2. XERR Truth Table
ERROR CONDITION
ERROR INFORMATION
TEMPERATURE
OUTn VOLTAGE
TEF
LOD
TJ < T(TEF)
Don't Care
L
X
TJ > T(TEF)
Don't Care
H
X
OUTn > V(LED)
L
L
OUTn < V(LED)
L
H
OUTn > V(LED)
H
L
OUTn < V(LED)
H
H
TJ < T(TEF)
TJ > T(TEF)
SIGNALS
BLANK
XERR
H
H
L
H
L
L
L
L
TEF: THERMAL ERROR FLAG
The TLC5940 provides a temperature error flag (TEF) circuit to indicate an overtemperature condition of the IC. If
the junction temperature exceeds the threshold temperature (160C typical), TEF becomes H and XERR pin goes
to low level. When the junction temperature becomes lower than the threshold temperature, TEF becomes L and
XERR pin becomes high impedance. TEF status can also be read out from the TLC5940 status register.
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LOD: LED OPEN DETECTION
The TLC5940 has an LED-open detector that detects broken or disconnected LEDs. The LED open detector
pulls the XERR pin to GND when an open LED is detected. XERR and the corresponding error bit in the Status
Information Data is only active under the following open-LED conditions.
1. OUTn is on and the time tpd2 (1 µs typical) has passed.
2. The voltage of OUTn is < 0.3V (typical)
The LOD status of each output can be also read out from the SOUT pin. See STATUS INFORMATION OUTPUT
section for details. The LOD error bits are latched into the Status Information Data when XLAT returns to a low
after a high. Therefore, the XLAT pin must be pulsed high then low while XERR is active in order to latch the
LOD error into the Status Information Data for subsequent reading via the serial shift register.
DELAY BETWEEN OUTPUTS
The TLC5940 has graduated delay circuits between outputs. These circuits can be found in the constant current
driver block of the device (see the functional block diagram). The fixed-delay time is 20ns (typical), OUT0 has no
delay, OUT1 has 20ns delay, and OUT2 has 40ns delay, etc. The maximum delay is 300ns from OUT0 to
OUT15. The delay works during switch on and switch off of each output channel. These delays prevent large
inrush currents which reduces the bypass capacitors when the outputs turn on.
OUTPUT ENABLE
All OUTn channels of the TLC5940 can be switched off with one signal. When BLANK is set high, all OUTn
channels are disabled, regardless of logic operations of the device. The grayscale counter is also reset. When
BLANK is set low, all OUTn channels work under normal conditions. If BLANK goes low and then back high
again in less than 300ns, all outputs programmed to turn on still turn on for either the programmed number of
grayscale clocks, or the length of time that the BLANK signal was low, which ever is lower. For example, if all
outputs are programmed to turn on for 1ms, but the BLANK signal is only low for 200ns, all outputs still turn on
for 200ns, even though some outputs are turning on after the BLANK signal has already gone high.
Table 3. BLANK Signal Truth Table
BLANK
OUT0 - OUT15
LOW
Normal condition
HIGH
Disabled
SETTING MAXIMUM CHANNEL CURRENT
The maximum output current per channel is programmed by a single resistor, R(IREF), which is placed between
IREF pin and GND pin. The voltage on IREF is set by an internal band gap V(IREF) with a typical value of
1.24V. The maximum channel current is equivalent to the current flowing through R(IREF) multiplied by a factor of
31.5. The maximum output current per channel can be calculated by Equation 6:
V
(IREF)
I max +
31.5
R
(IREF)
(6)
where:
V(IREF) = 1.24 V
R(IREF) = User-selected external resistor.
Imax must be set between 5 mA and 120 mA. The output current may be unstable if Imax is set lower than 5 mA.
Output currents lower than 5 mA can be achieved by setting Imax to 5 mA or higher and then using dot
correction.
Figure 3 shows the maximum output current IO versus R(IREF). R(IREF) is the value of the resistor between IREF
terminal to GND, and IO is the constant output current of OUT0 to OUT15. A variable power supply may be
connected to the IREF pin through a resistor to change the maximum output current per channel. The maximum
output current per channel is 31.5 times the current flowing out of the IREF pin.
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POWER DISSIPATION CALCULATION
The device power dissipation must be below the power dissipation rating of the device package to ensure correct
operation. Equation 7 calculates the power dissipation of device:
DC n
x dPWM x N
PD = VCC x ICC + VOUT x IMAX x
63
(7)
(
)
(
)
where:
VCC: device supply voltage
ICC: device supply current
VOUT: TLC5940 OUTn voltage when driving LED current
IMAX: LED current adjusted by R(IREF) Resistor
DCn: maximum dot correction value for OUTn
N: number of OUTn driving LED at the same time
dPWM: duty cycle defined by BLANK pin or GS PWM value
OPERATING MODES
The TLC5940 has operating modes depending on the signals DCPRG and VPRG. Table 4 shows the available
operating modes. The TPS5940 GS operating mode (see Figure 11) and shift register values are not defined
after power up. One solution to solve this is to set dot correction data after TLS5940 power-up and switch back
to GS PWM mode. The other solution is to overflow the input shift register with 193 bits of dummy data and latch
it while TLS540 is in GS PWM mode. The values in the input shift register, DC register and GS register are
unknown just after power on. The DC and GS register values should be properly stored through the serial
interface before starting the operation.
Table 4. TLC5940 Operating Modes Truth Table
SIGNAL
DCPRG
L
H
L
H
INPUT SHIFT REGISTER
MODE
GND
192 bit
Grayscale PWM Mode
VCC
96 bit
Dot Correction Data Input Mode
V(VPRG)
X
EEPROM Programming Mode
VPRG
DC VALUE
EEPROM
DC Register
EEPROM
DC Register
L
H
EEPROM
Write dc register value to EEPROM. (Default
data: 3Fh)
SETTING DOT CORRECTION
The TLC5940 has the capability to fine adjust the output current of each channel OUT0 to OUT15 independently.
This is also called dot correction. This feature is used to adjust the brightness deviations of LEDs connected to
the output channels OUT0 to OUT15. Each of the 16 channels can be programmed with a 6-bit word. The
channel output can be adjusted in 64 steps from 0% to 100% of the maximum output current Imax. Dot correction
for all channels must be entered at the same time. Equation 8 determines the output current for each output n:
I
+ I max DCn
OUTn
63
(8)
where:
Imax = the maximum programmable output current for each output.
DCn = the programmed dot correction value for output n (DCn = 0 to 63).
n = 0 to 15
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Figure 14 shows the dot correction data packet format which consists of 6 bits x 16 channel, total 96 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc. The DC
15.5 in Figure 14 stands for the 5th most significant bit for output 15.
MSB
LSB
95
90
DC 15.5
89
6
DC 15.0 DC 14.5
DC 1.0
DC OUT15
5
0
DC 0.5
DC 0.0
DC OUT0
DC OUT14 − DC OUT2
Figure 14. Dot Correction Data Packet Format
When VPRG is set to VCC, the TLC5940 enters the dot correction data input mode. The length of input shift
register becomes 96 bits. After all serial data are shifted in, the TLC5940 writes the data in the input shift register
to DC register when XLAT is high, and holds the data in the DC register when XLAT is low. The DC register is a
level triggered latch of XLAT signal. Since XLAT is a level-triggered signal, SCLK and SIN must not be changed
while XLAT is high. After XLAT goes low, data in the DC register is latched and does not change. BLANK signal
does not need to be high to latch in new data. XLAT has setup time (tsu1) and hold time (th1) to SCLK as shown
in Figure 15.
DC Mode Data
Input Cycle n
DC Mode Data
Input Cycle n+1
VCC
VPRG
SIN
DC n−1
LSB
DC n
MSB
DC n
MSB−1
DC n
MSB−2
DC n
LSB+1
DC n
LSB
DC n+1
MSB
DC n+1
MSB−1
twh0
SCLK
1
2
3
95
96
1
2
twl0
SOUT
DC n−1
MSB
DC n−1
MSB−1
DC n−1
MSB−2
DC n−1
LSB+1
DC n−1
LSB
tsu1
DC n
MSB
DC n
MSB−1
DC n
MSB−2
twh2
th1
XLAT
Figure 15. Dot Correction Data Input Timing Chart
The TLC5940 also has an EEPROM to store dot correction data. To store data from the dot correction register to
EEPROM, DCPRG is set to high after applying VPRG to the VPRG pin. Figure 16 shows the EEPROM
programming timings. The EEPROM has a default value of all 1s.
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V(PRG)
VPRG
VCC
tsu6
tprog
th5
DCPRG
XLAT
SIN
DC
MSB
SCLK
1
DC
LSB
96
-
SOUT
DC
MSB
Figure 16. EEPROM Programming Timing Chart
DCPRG
tpd5
tpd5
OUT0
(Current)
OUT15
(Current)
Figure 17. DCPRG and OUTn Timing Diagram
SETTING GRAYSCALE
The TLC5940 can adjust the brightness of each channel OUTn using a PWM control scheme. The use of 12 bits
per channel results in 4096 different brightness steps, respective 0% to 100% brightness. Equation 9 determines
the brightness level for each output n:
Brightness in % + GSn
100
4095
(9)
where:
GSn = the programmed grayscale value for output n (GSn = 0 to 4095)
n = 0 to 15
Grayscale data for all OUTn
Figure 18 shows the grayscale data packet format which consists of 12 bits x 16 channels, totaling 192 bits. The
format is Big-Endian format. This means that the MSB is transmitted first, followed by the MSB-1, etc.
MSB
191
180
179
12
GS 15.0 GS 14.11
GS 15.11
GS OUT15
GS 1.0
GS OUT14 − GS OUT2
11
LSB
0
GS 0.11
GS 0.0
GS OUT0
Figure 18. Grayscale Data Packet Format
When VPRG is set to GND, the TLC5940 enters the grayscale data input mode. The device switches the input
shift register to 192-bit width. After all data is clocked in, a rising edge of the XLAT signal latches the data into
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the grayscale register (see Figure 11). New grayscale data immediately becomes valid at the rising edge of the
XLAT signal; therefore, new grayscale data should be latched at the end of a grayscale cycle when BLANK is
high.The first GS data input cycle after dot correction requires an additional SCLK pulse after the XLAT signal to
complete the grayscale update cycle. All GS data in the input shift register is replaced with status information
data (SID) after updated the grayscale register.
STATUS INFORMATION OUTPUT
The TLC5940 does have a status information register, which can be accessed in grayscale mode (VPRG=GND).
After the XLAT signal latches the data into the GS register the input shift register data will be replaced with status
information data (SID) of the device (see Figure 18). LOD, TEF, and dot correction EEPROM data
(DCPRG=LOW) or dot correction register data (DCPRG=HIGH) can be read out at SOUT pin. The status
information data packet is 192 bits wide. Bits 0-15 contain the LOD status of each channel. Bit 16 contains the
TEF status. If DCPRG is low, bits 24-119 contain the data of the dot-correction EEPROM. If DCPRG is high, bits
24-119 contain the data of the dot-correction register.The remaining bits are reserved. The complete status
information data packet is shown in Figure 19.
SOUT outputs the MSB of the SID at the same time the SID are stored in the SID register, as shown Figure 20.
The next SCLK pulse, which will be the clock for receiving the SMB of the next grayscale data, transmits MSB-1
of SID. If output voltage is < 0.3 V (typical) when the output sink current turns on, LOD status flage becomes
active. The LOD status flag is an internal signal that pulls XERR pin down to low when the LOD status flag
becomes active. The delay time, tpd2 (1 µs maximum), is from the time of turning on the output sink current to
the time LOD status flage becomes valid. The timing for each channel's LOD status to become valid is shifted by
the 30-ns (maximum) channel-to-channel turn-on time. After the first GSCLK goes high, OUT0 LOD status is
valid; tpd3 + tpd2 = 60 ns + 1 µs. OUT1 LOD status is valid; tpd3 + td + tpd2 = 60 ns + 30 ns + 1 µs = 1.09 µs.
OUT2 LOD status is valid; tpd3 + 2*td + tpd2 = 1.12 µs, and so on. It takes 1.51 µs maximum (tpd3 + 15*td +
tpd2) from the first GSCLK rising edge until all LOD become valid; tsuLOD must be > 1.51 µs (see Figure 20) to
ensure that all LOD data are valid.
LSB
MSB
0
15
16
LOD 15
LOD 0
TEF
LOD Data
X
23
24
119
120
191
X
DC 15.5
DC 0.0
X
X
TEF
DC Values
Reserved
Figure 19. Status Information Data Packet Format
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VPRG
GS Data Input Mode
XLAT
1st GS Data Input Cycle
GS1
MSB
SIN
2nd GS Data Input Cycle
GS1
LSB
GS2
MSB
> tpd4 + 15 x td + tpd3
tsuLOD
1
SCLK
SOUT
-
192
-
GS2
LSB
193
GS1
MSB
SID1
MSB
192
1
SID1
MSB-1
SID1
LSB
GS2
MSB
(1st GS Data Output Cycle)
BLANK
GSCLK
4096
1
tpd3
OUT0
(current)
td
OUT1
(current)
15 x td
OUT15
(current)
tpd2
XERR
tpd3 + 15 x td + tpd2
Figure 20. Readout Status Information Data (SID) Timing Chart
GRAYSCALE PWM OPERATION
The grayscale PWM cycle starts with the falling edge of BLANK. The first GSCLK pulse after BLANK goes low
increases the grayscale counter by one and switches on all OUTn with grayscale value not zero. Each following
rising edge of GSCLK increases the grayscale counter by one. The TLC5940 compares the grayscale value of
each output OUTn with the grayscale counter value. All OUTn with grayscale values equal to the counter values
are switched off. A BLANK=H signal after 4096 GSCLK pulses resets the grayscale counter to zero and
completes the grayscale PWM cycle (see Figure 21). When the counter reaches a count of FFFh, the counter
stops counting and all outputs turn off. Pulling BLANK high before the counter reaches FFFh immediately resets
the counter to zero.
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GS PWM
Cycle n
BLANK
t wl1
t wh1
t h4
GSCLK
1
t wl1
t wh3
4096
3
t su4
1
t pd3
nxt d
t pd1 + td
OUT1
(Current)
2
t pd3
t pd1
OUT0
(Current)
GS PWM
Cycle n+1
t pd3+ n x t d
t pd1 + 15 x td
OUT15
(Current)
t pd2
XERR
Figure 21. Grayscale PWM Cycle Timing Chart
SERIAL DATA TRANSFER RATE
Figure 22 shows a cascading connection of n TLC5940 devices connected to a controller, building a basic
module of an LED display system. The maximum number of cascading TLC5940 devices depends on the
application system and is in the range of 40 devices. Equation 10 calculates the minimum frequency needed:
f
+ 4096
f
(GSCLK)
(update)
f
(SCLK)
+ 193
f
(update)
n
(10)
where:
f(GSCLK): minimum frequency needed for GSCLK
f(SCLK): minimum frequency needed for SCLK and SIN
f(update): update rate of whole cascading system
n: number cascaded of TLC5940 device
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APPLICATION EXAMPLE
VCC
V(LED)
V(LED)
V(LED)
V(LED)
100 k
OUT0
SIN
XERR
SCLK
SCLK
VCC
100 nF
TLC5940
GSCLK
DCPRG
DCPRG
BLANK
BLANK
SOUT
VPRG
OUT15
SIN
SOUT
XERR
VCC
SCLK
XLAT
GSCLK
OUT0
SOUT
XERR
XLAT
Controller
OUT15
SIN
IREF
100 nF
XLAT
GSCLK
TLC5940
DCPRG
IREF
BLANK
IC 0
VPRG
IC n
W_EEPROM
7
VPRG_D
VPRG_OE
V(22V)
50 k
V(22V)
50 k
50 k
50 k
50 k
50 k
VPRG
Figure 22. Cascading Devices
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TLC5940NT
ACTIVE
PDIP
NT
28
13
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
TLC5940NTG4
ACTIVE
PDIP
NT
28
13
Green (RoHS &
no Sb/Br)
CU NIPDAU
N / A for Pkg Type
TLC5940PWP
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLC5940PWPG4
ACTIVE
HTSSOP
PWP
28
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLC5940PWPR
ACTIVE
HTSSOP
PWP
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLC5940PWPRG4
ACTIVE
HTSSOP
PWP
28
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLC5940RHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TLC5940RHBRG4
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
TLC5940PWPR
HTSSOP
PWP
28
2000
330.0
TLC5940RHBR
QFN
RHB
32
3000
330.0
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
16.4
7.1
10.4
1.6
12.0
16.0
Q1
12.4
5.3
5.3
1.5
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-May-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TLC5940PWPR
HTSSOP
PWP
28
2000
346.0
346.0
33.0
TLC5940RHBR
QFN
RHB
32
3000
346.0
346.0
29.0
Pack Materials-Page 2
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