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CONTENTS CHAPTER 1 INTRODUCTION ............................................................................................................. 3 1.1 Key Features ............................................................................................................................................... 4 1.2 About the Kit .............................................................................................................................................. 6 1.3 Power On Test ............................................................................................................................................ 7 1.4 System CD and Linux BSP ........................................................................................................................ 8 1.5 Getting Help ............................................................................................................................................... 8 CHAPTER 2 ARCHITECTURE ............................................................................................................ 9 2.1 Layout and Components ............................................................................................................................. 9 2.2 Block Diagram.......................................................................................................................................... 10 2.3 ITG Adapter .............................................................................................................................................. 11 CHAPTER 3 USING DE1-SOC-MTL2 ................................................................................................ 13 3.1 Using FPGA ............................................................................................................................................. 13 3.2 Pin Definition of 2x20 GPIO Connector .................................................................................................. 13 3.3 Using LCD................................................................................................................................................ 15 3.4 Using Terasic Multi-touch IP.................................................................................................................... 17 CHAPTER 4 LINUX BSP ................................................................................................................... 20 4.1 Board Support Package ............................................................................................................................ 20 4.2 Linux Image Files ..................................................................................................................................... 21 4.3 Quarts Project ........................................................................................................................................... 21 4.4 QT Libraries ............................................................................................................................................. 22 CHAPTER 5 PAINTER DEMONSTRATION ....................................................................................... 23 5.1 Operation Description .............................................................................................................................. 23 5.2 System Description ................................................................................................................................... 25 5.3 Demonstration Setup ................................................................................................................................ 25 5.4 Demonstration Source Code ..................................................................................................................... 26 DE1-SoC-MTL2 User Manual 1 www.terasic.com December 18, 2014 CHAPTER 6 APPENDIX .................................................................................................................... 27 6.1 Revision History ....................................................................................................................................... 27 6.2 Copyright Statement ................................................................................................................................. 27 DE1-SoC-MTL2 User Manual 2 www.terasic.com December 18, 2014 Chapter 1 Introduction The DE1-SoC-MTL2 Development Kit is a comprehensive design environment with everything embedded developers need to create processing-based systems. The DE1-SoC-MTL2 delivers an integrated platform including hardware, design tools, and reference designs for developing embedded software and hardware platforms in a wide range of applications. The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application. The DE1-SoC-MTL2 features a DE1-SoC development board targeting Altera Cyclone® V SoC FPGA, as well as a 5-Point capacitive LCD multimedia color touch panel which natively supports five points multi-touch and gestures. The all-in-one embedded solution offered on the DE1-SoC-MTL2, in combination of a LCD touch panel and digital image module, provides embedded developers the ideal platform for multimedia applications with unparallel processing performance. Developers can benefit from the use of FPGA-based embedded processing system such as mitigating design risk and obsolescence, design reuse, lowering bill of material (BOM) costs by integrating powerful graphics engines within the FPGA. For SoC reference design in Linux for touch-screen display, please refer to the “Programming Guide for Touch-Screen Display” document in the System CD of DE1-SoC-MTL2. Figure 1-1 shows a photo of DE1-SoC-MTL2. Figure 1-1 DE1-SoC-MTL2 User Manual The DE1-SoC-MTL2 platform 3 www.terasic.com December 18, 2014 1.1 Key Features The key features of this kit are listed below:  Cyclone V SE SoC—5CSEMA5F31C6N o o o o o  Dual-core ARM Cortex-A9 (HPS) 85K programmable logic elements 4,450 Kbits embedded memory 6 fractional PLLs 2 hard memory controllers Configuration Sources o Quad serial configuration device – EPCS128 for the FPGA o On-board USB Blaster II (normal type B USB connector)  Memory Devices o 64MB (32Mx16) SDRAM for the FPGA o 1GB (2x256MBx16) DDR3 SDRAM for the HPS o microSD card socket for the HPS  Peripherals o o o o o o  Two port USB 2.0 Host (ULPI interface with USB type A connector) UART to USB (USB Mini B connector) 10/100/1000 Ethernet PS/2 mouse/keyboard IR emitter/receiver I2C multiplexer Connectors o Two 40-pin expansion headers o One 10-pin ADC input header o One LTC connector (one Serial Peripheral Interface (SPI) master ,one I2C bus, and one GPIO interface) DE1-SoC-MTL2 User Manual 4 www.terasic.com December 18, 2014  Display o 24-bit VGA DAC  Audio o 24-bit CODEC, line-in, line-out, and microphone-in jacks  Video Input o TV decoder (NTSC/PAL/SECAM) and Video-in connector  ADC o o o o  Switches, Buttons and LEDs o o o o o  Fast throughput rate: 1 MSPS Channel number: 8 Resolution: 12-bit Analog input range : 0 ~ 2.5 V or 0 ~ 5V by selecting the RANGE bit in the control register 5 user keys (4 for the FPGA and 1 for the HPS) 10 user switches for the FPGA 11 user LEDs (10 for the FPGA and 1 for the HPS) 2 HPS reset buttons (HPS_RESET_n and HPS_WARM_RST_n) Six 7-segment displays Sensor o G-sensor for the HPS  Power o 12V DC input  Capacitive LCD Touch Screen o Equipped with an 7-inch Amorphous-TFT-LCD (Thin Film Transistor Liquid Crystal Display) module o 800x600x3(RGB) Resolution DE1-SoC-MTL2 User Manual 5 www.terasic.com December 18, 2014 o 24-bit parallel RGB interface o Supports 5-point touch Table 1-1 shows the general physical specifications of the touch-screen (Note*). Table 1-1 General physical specifications of the LCD Item Specification Unit LCD size 7-inch (Diagonal) - Resolution 800 x3(RGB) x 480 dot Display mode Normally White, Transmissive - Dot pitch 0.0642(W) x0.1790 (H) mm Active area 154.08 (W) x 85.92 (H) mm Module size 179.4(W) x 117.4(H) x 7.58(D) mm Surface treatment Anti-Glare - Color arrangement RGB-stripe - Interface Backlight power consumption Panel power consumption Digital - 1.674(Typ.) W 0.22(Typ.) W 1.2 About the Kit The kit includes everything users need to run the demonstrations and develop custom designs, as shown in Figure 1-2. Figure 1-2 Contents of DE1-SoC-MTL2 kit package DE1-SoC-MTL2 User Manual 6 www.terasic.com December 18, 2014 1.3 Power On Test The 8GB microSD card included in the kit is pre-programmed with LXDE Linux desktop. Users can perform a power on test from the microSD card. The procedures to perform the power on test are: 1. 2. 3. 4. 5. 6. 7. Please make sure the microSD card is inserted to the microSD card socket (J11) onboard. Set MSEL[4:0] = 00000, as shown in Figure 1-3. Plug in a USB keyboard to the USB host on the DE1-SoC board. Plug in the 12V DC power supply to the DE1-SoC board. Power on the DE1-SoC board. The LXDE Desktop will appear on the LCD display. Use the touch-screen to select the system menu, as shown in Figure 1-4. Figure 1-3 MSEL[4:0] = 00000 DE1-SoC-MTL2 User Manual 7 www.terasic.com December 18, 2014 Figure 1-4 LXDE desktop on DE1-SoC-MTL2 platform 1.4 System CD and Linux BSP The DE1-SoC-MTL2 System CD contains the touch-screen documentations and supporting materials, including the user manual, reference designs, and device datasheets. Users can download the System CD form the link: http://cd-de1-soc-mtl2.terasic.com. This site also provides the Linux image files for creating a bootable microSD card. Table 1-1 shows the contents of DE1-SoC-MTL2 System CD. For the system CD of DE1-SoC mainboard, users can download it from the link: http://cd-de1-soc.terasic.com. Table 1-1 Contents of DE1-SoC-MTL2 System CD Folder Name Description Datasheet Specifications for major components on the touch-screen display module Demonstrations FPGA and SoC design examples Manual Including user manual and software programming guide Schematic Schematic of the touch-screen display module 1.5 Getting Help Here is the contact information should you encounter any problem:  Terasic Technologies  Tel: +886-3-575-0880  Email: support@terasic.com DE1-SoC-MTL2 User Manual 8 www.terasic.com December 18, 2014 Chapter 2 Architecture This chapter provides information regarding the features and architecture of DE1-SoC-MTL2. The kit is composed of DE1-SoC mainboard and MTL (Multi-Touch LCD) module. The MTL module is connected to a 2x20 GPIO expansion header on DE1-SoC board through an ITG (IDE to GPIO) adaptor. For more information about the DE1-SoC mainboard, please refer to the user manual in DE1-SoC System CD, which can be download from the link: http://cd-de1-soc.terasic.com. 2.1 Layout and Components Figure 2-1 and Figure 2-2 show photos of DE1-SoC-MTL2. It depicts the layout of the board and indicates the locations of connectors and key components. Figure 2-1 DE1-SoC-MTL2 (top view) DE1-SoC-MTL2 User Manual 9 www.terasic.com December 18, 2014 Figure 2-2 DE1-SoC-MTL2 (bottom view) 2.2 Block Diagram Figure 2-3 shows the block diagram of MTL2 module. The IDE connector bridges all the wires from the peripherals to the FPGA through an ITG adapter. Figure 2-3 Block diagram of MTL2 DE1-SoC-MTL2 User Manual 10 www.terasic.com December 18, 2014 Figure 2-4 illustrates the connection of MTL2 to Terasic FPGA board. Figure 2-4 Connection Diagram of MTL2 Kit with Terasic FPGA boards 2.3 ITG Adapter The IDE to GPIO (ITG) adapter is designed to remap IDE pins to GPIO pins. Component and Layout Figure 2-5 and Figure 2-6 show the top and bottom view of ITG adapter, respectively. The J1 connector is used to connect the FPGA board. The J2 connector is used to interface with the IDE cable. DE1-SoC-MTL2 User Manual 11 www.terasic.com December 18, 2014 Figure 2-5 ITG adapter (top view) Figure 2-6 ITG adapter (bottom view) DE1-SoC-MTL2 User Manual 12 www.terasic.com December 18, 2014 Chapter 3 Using DE1-SoC-MTL2 This chapter provides information on how to control the Multi-touch LCD Module Second Edition (MTL2) hardware, which includes the definition of 2x20 GPIO interface, LCD control, and multi-touch control signals. 3.1 Using FPGA The DE1-SoC-MTL2 is composed of DE1-SoC SoC development board and 7" touch panel daughter card. The DE1-SoC SoC development board with the FPGA device is considered as the main part. The DE1-SoC user manual and CD are available at: http://cd-de1-soc.terasic.com 3.2 Pin Definition of 2x20 GPIO Connector The 2x20 GPIO female connector directly connects to the 2x20 GPIO male connector on the Terasic FPGA development boards. Figure 3-1 shows the signal names of the 2x20 GPIO from the ITG adapter. DE1-SoC-MTL2 User Manual 13 www.terasic.com December 18, 2014 Figure 3-1 Signals of 2x20 GPIO connector Table 3-1 shows the recommended pin assignments for the 2x20 GPIO pins in Quartus II. Table 3-1 Recommended Pin Assignments of 2x20 GPIO in Quartus II Pin Numbers Pin Name Direction IO Standard 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MTL_DCLK MTL_R[0] MTL_R[1] MTL_R[2] MTL_R[3] MTL_R[4] MTL_R[5] MTL_R[6] MTL_R[7] MTL_G[0] MTL_G[1] MTL_G[2] MTL_G[3] Output Output Output Output Output Output Output Output Output Output Output Output Output 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL DE1-SoC-MTL2 User Manual 14 www.terasic.com December 18, 2014 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Output MTL_G[4] Output MTL_G[5] Output MTL_G[6] Output MTL_B[0] MTL_G[7] Output Output MTL_B[1] Output MTL_B[2] Output MTL_B[3] Output MTL_B[4] Output MTL_B[5] Output MTL_B[6] Output MTL_B[7] MTL_HSD Output MTL_VSD Output MTL_TOUCH_I2C_SCL Output MTL_TOUCH_I2C_SDA Inout MTL_TOUCH_INT_n Input - 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL - 3.3 Using LCD The LCD features 800x480 pixel resolution and runs at 33 MHz pixel rate. There is no configuration required to drive the LCD. The timing specification is defined as in the Table 3-2, Table 3-3, Figure 3-2 and Figure 3-3. Table 3-2 LCD Horizontal Timing Specifications Item Symbol Horizontal Display Area thd DCLK Frequency fclk One Horizontal Line th HS pulse width thpw HS Blanking thb HS Front Porch thfp DE1-SoC-MTL2 User Manual Typical Value Min. Typ. Max. 26.4 862 1 46 16 15 Unit 800 - DCLK 33.3 46.8 MHz 1056 1200 DCLK 40 DCLK 46 46 DCLK 210 354 DCLK www.terasic.com December 18, 2014 Table 3-3 LCD Vertical Timing Specifications Item Symbol Vertical Display Area VS period time VS pulse width VS Blanking HS Front Porch tvd tv tvpw tvb tvfp Typical Value Min. Typ. Max. Unit - 480 - TH 510 525 650 TH 1 20 TH 23 23 23 TH 7 22 147 TH Figure 3-2 Horizontal input timing waveform Figure 3-3 Vertical input timing waveform DE1-SoC-MTL2 User Manual 16 www.terasic.com December 18, 2014 3.4 Using Terasic Multi-touch IP Terasic Multi-touch IP is provided for developers to retrieve user inputs, including multi-touch gestures and single-touch. The file name of this IP is i2c_touch_config.v, which is located in System CD \IP folder. The IP decodes I2C information and outputs coordinates and gesture information. The inputs and outputs of this IP module is shown below The purpose of signals for this IP is described in Table 3-4. The IP requires a 50 MHz signal as a reference clock to the iCLK pin and system reset signal to the iRSTN. INT_n, The signals of I2C_SCLK, and I2C_SDAT pins should be connected to the MTL2_TOUCH_INT_n, MTL2_TOUCH_I2C_SCL, and MTL2_TOUCH_I2C_SDA signals in the 2x20 GPIO header, respectively. When touch activity occurs, the control application should check whether the value of oREG_GESTURE matches a pre-defined gesture ID defined in Table 3-4 and the relative X/Y coordinates can be derived from oREG_X and oREG_Y. Figure 3-1 shows the signaltap II waveform of the IP. When the oREADY rises, it indicates touch activity, and the associated information can be collected from the oREG_X1~ oREG_X5, oREG_Y1~ oREG_Y5, oREG_TOUCH_COUNT, and oREG_GESTURE pins. DE1-SoC-MTL2 User Manual 17 www.terasic.com December 18, 2014 Figure 3-4 Signaltap II Waveform for Multi-Touch IP Table 3-4 Definition of Terasic Multi-touch IP Signals Pin Name Direction Description iCLK iRSTN INT_n oREADY Input Input Input Output oREG_X1 oREG_Y1 oREG_X2 oREG_Y2 oREG_X3 oREG_Y3 oREG_X4 oREG_Y4 oREG_X5 oREG_Y5 oREG_TOUCH_COUNT oREG_GESTURE I2C_SCLK I2C_SDAT Output Output Output Output Output Output Output Output Output Output Output Output Output Inout Connect to 50MHz clock Connect to system reset signal Connect to interrupt pin of touch IC Triggered when the data of following six outputs are valid 10-bit X coordinate of first touch point 9-bit Y coordinate of first touch point 10-bit X coordinate of second touch point 9-bit Y coordinate of second touch point 10-bit X coordinate of first touch point 9-bit Y coordinate of second touch point 10-bit X coordinate of first touch point 9-bit Y coordinate of second touch point 10-bit X coordinate of first touch point 9-bit Y coordinate of second touch point 2-bit touch count. Valid value is 0, 1, or 2. 8-bit gesture ID (See Table 3-5) Connect to I2C clock pin of touch IC Connect to I2C data pin of touch IC The gestures and IDs supported are shown in Table 3-5. DE1-SoC-MTL2 User Manual 18 www.terasic.com December 18, 2014 Table 3-5 Gestures and Its IDs Gesture ID (hex) Move Up Move Left Move Down Move Right Zoom In Zoom Out No Gesture 0x10 0x14 0x18 0x1C 0x48 0x49 0x00 Note: The Terasic IP Multi-touch IP can also be found under the \IP folder in the system CD, as well as the reference designs. DE1-SoC-MTL2 User Manual 19 www.terasic.com December 18, 2014 Chapter 4 Linux BSP This chapter describes how to use the Linux BSP (Board Support Package) provide by Terasic. Users can develop touch-screen GUI program easily with the BPS including QT 5.3.1 library. 4.1 Board Suppor t Package Figure 4-1 shows the block diagram of Linux BSP for DE1-SoC-MTL2 kit. The BPS incudes three major parts:  Linux image files  Quartus project  QT library with touch-screen function included The Linux image files are implemented on HPS/ARM and the Quartus project is implemented on FPGA/Qsys. The Linux image files include the pre-built Linux system. Users can create a Linux bootable microSD card with the image files. The Quartus project includes the controller for VGA display and the touch-screen controller for touch-screen panel. The BSP includes not only precompiled QT library and touch-screen library in the Linux image files, but also the document that show how to cross-compile these libraries, as well as to develop touch-screen GUI program based on these libraries. Figure 4-1 Block diagram of Linux BSP for DE1-SoC-MTL2 kit DE1-SoC-MTL2 User Manual 20 www.terasic.com December 18, 2014 4.2 Linux Image Files LXDE desktop Linux image file is provided for DE1-SoC-MTL2. It is available from the link: http://cd-de1-soc-mtl2.terasic.com. Developers can use a tool named Win32 Disk Imager to write the image file into a microSD card. For details about how to create a bootable microSD card or booting Linux from the DE1-SoC board, please refer to the chapter 5 of DE1-SoC_Getting_Started_Guide.pdf, which is included in the DE1-SoC System CD, which is available from the link: http://cd-de1-soc.terasic.com. Figure 4-2 shows a screenshot of LXDE desktop after booting. The LXDE desktop is displayed on the LCD touch panel. This image file also includes the QT library and touch-screen library. To perform these demos, users need to double click the icons of the demos on desktop. Figure 4-2 Screenshot of LXDE desktop 4.3 Quar ts Project The Quartus project is designed based on Altera Qsys tool. There are three major parts:  VGA display  Touch-screen  HPS component The VGA display part is designed to display the Linux console or desktop on the LCD touch panel. Altera Video and Image Processing (VIP) suite is used to implement this function. The Linux frame DE1-SoC-MTL2 User Manual 21 www.terasic.com December 18, 2014 buffer driver fills up the DDR3 with data to be displayed, and the VIP frame-reader component reads the data from the DDR3 in a DMA manner. The video data is streamed into the VIP Clocked Video Output component. Finally, the VIP Clocked Video Output component drives the VGA DAC chip to display the video data. An I2C master controller in Qsys is used to communicate with the touch-screen panel. The component interfaces with the touch-screen panel through I2C protocol. The HPS communicate with the FPGA through AXI bridge. The components in FPGA are mapped into user memory of the linux system through memory-mapped interface. Then the user software can access the IPs in FPGA portion. The Quartus project is located under the folder “Demonstrations/SoC_FPGA/MTL2_HPS” in the DE1-SoC-MTL2 system CD. 4.4 QT Libraries Users can develop touch-screen GUI program based on the QT library. For more information, please refer to the document “Software Development Guide for touch-screen display.pdf” included in the DE1-SoC-MTL2 system CD. The precompiled libraries can be found from the folder “Demonstrations/SoC_FPGA/Libraries” in the DE1-SoC-MTL2 system CD. DE1-SoC-MTL2 User Manual 22 www.terasic.com December 18, 2014 Chapter 5 Painter Demonstration This chapter shows how to implement a painter demo on the Multi-touch LCD module based on Altera Qsys tool and the Video and Image Processing (VIP) suite. It demonstrates how to use multi-touch gestures and resolution. The GUI of this demonstration is controlled by the program in Nios II. 5.1 Operation Description Figure 5-1 shows the Graphical User Interface (GUI) of Painter demo. The GUI is classified into four separate areas: Painting Area, Gesture Indicator, Clear Button, and Color Palette. Users can select a color from the color palette and start painting in the paint area. If a gesture is detected, the associated gesture symbol will be shown in the gesture area. To clear the painting area, click the “Clear” button. Figure 5-1 GUI of Painter Demo DE1-SoC-MTL2 User Manual 23 www.terasic.com December 18, 2014 Figure 5-2 shows the single-finger painting of canvas area. Figure 5-2 Single-finger painting Figure 5-3 shows the zoom-in gesture. Figure 5-3 Zoom-in gesture Figure 5-4 5-Point painting of canvas area. Figure 5-4 5-Point painting DE1-SoC-MTL2 User Manual 24 www.terasic.com December 18, 2014 5.2 System Description For LCD display processing, the reference design is developed based on Altera’s Video and Image Processing (VIP) suite. The Frame Reader VIP is used for reading data to be displayed from the associated video memory, and the VIP Video Out is used to display the video data. The data is drawn by the Nios II processor according to user input. For multi-touch processing, When touch activity occurs, a I2C Controller IP is used to retrieve serial data from the I2C interface, the associated touch information including multi-touch gestures and 5 Point touch coordinates can be calculated through the data in NIOS II. Note: the license for this IP must be installed before compiling the Quartus II project including this encrypted component. Figure 5-5 shows the system generic block diagram of painter demonstration. Figure 5-5 System block diagram of painter demonstration 5.3 Demonstration Setup Please follow the procedures below to setup the demonstration: DE1-SoC-MTL2 User Manual 25 www.terasic.com December 18, 2014 1. Connect the DE1-SoC-MTL2 USB-Blaster II USB port to the PC USB Port with a USB Cable. 2. Power on the DE1-SoC-MTL2. 3. Please make sure Quartus II v14.0 has been installed on the host PC. 4. Copy the folder \Demonstrations\FPGA\DE1_SoC_MTL2_PAINTER\demo_batch. 5. Execute “DE1_SoC_MTL2_PAINTER.bat”. 6. The painter GUI will show up on the LCD panel. 5.4 Demonstration Source Code The locations of this demonstration source code are shown in Table 5-1. Note: The project is built under Quartus II v14.0. Both Altera VIP license is required to rebuild the project. Table 5-1 Locations of Painter Demonstration Source Code Project Location Quartus II Nios II Demonstrations\FPGA\DE1_SoC_MTL_PAINTER Demonstrations\FPGA\DE1_SoC_MTL_PAINTER\software DE1-SoC-MTL2 User Manual 26 www.terasic.com December 18, 2014 Chapter 6 Appendix 6.1 Revision Histor y Version Change Log V1.0 Initial Version (Preliminary) 6.2 Copyright Statement Copyright © 2014 Terasic Technologies. All rights reserved. DE1-SoC-MTL2 User Manual 27 www.terasic.com December 18, 2014