EVAL-KXTIA-1006

PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Product Description The KXTIA is a tri-axis +/-2g, +/-4g or +/-8g silicon micromachined accelerometer with integrated orientation, tap/double tap, and activity detecting algorithms. The sense element is fabricated using Kionix’s proprietary plasma micromachining process technology. Acceleration sensing is based on the principle of a differential capacitance arising from acceleration-induced motion of the sense element, which further utilizes common mode cancellation to decrease errors from process variation, temperature, and environmental stress. The sense element is hermetically sealed at the wafer level by bonding a second silicon lid wafer to the device using a glass frit. A separate ASIC device packaged with the sense element provides signal conditioning, and intelligent userprogrammable application algorithms. The accelerometer is delivered in a 3 x 3 x 0.9 mm LGA plastic package operating from a 1.8 – 3.6V DC supply. Voltage regulators are used to maintain constant internal operating voltages over the range of input supply voltages. This results in stable operating characteristics over the range of input supply voltages and virtually undetectable ratiometric error. The SPI digital protocol is used to communicate with the chip to configure and check for updates to the orientation, Directional TapTM detection and activity monitoring algorithms. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 1 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Functional Diagram X Sensor Vdd 5 IO Vdd 1 GN D 4 Y Sensor Charge Amp Z Sensor Temp Sensor A/D Digital Filter SPI Digital Engine 6 nCS 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com 8 SDO 9 10 SCLK SDI 7 IN T © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 2 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Product Specifications Table 1. Mechanical (specifications are for operation at 2.6V and T = 25C unless stated otherwise) Parameters Units Min Typical Operating Temperature Range Zero-g Offset Zero-g Offset Variation from RT over Temp. ºC mg Sensitivity (8-bit) 1 1 GSEL1=0, GSEL0=1 (± 4g) GSEL1=1, GSEL0=0 (± 8g) GSEL1=0, GSEL0=0 (± 2g) GSEL1=0, GSEL0=1 (± 4g) GSEL1=1, GSEL0=0 (± 8g) Sensitivity Variation from RT over Temp. Self Test Output change on Activation Mechanical Resonance (-3dB) Non-Linearity Cross Axis Sensitivity 2 counts/g counts/g Max 85 ±125 988 ±25 0.7 (xy) 0.4 (z) 1024 494 512 530 247 61 30 15 256 64 32 16 0.01 (xy) 0.03 (z) 0.7 (xy) 0.5 (z) 3500 (xy) 1800 (z) 0.6 2 265 67 34 17 mg/ºC GSEL1=0, GSEL0=0 (± 2g) Sensitivity (12-bit) -40 - %/ºC g Hz % of FS % 1060 Notes: 1. Resolution and acceleration ranges are user selectable via SPI. 2. Resonance as defined by the dampened mechanical sensor. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 3 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Table 2. Electrical (specifications are for operation at 2.6V and T = 25C unless stated otherwise) Parameters Units Min Typical Max Supply Voltage (Vdd) Operating I/O Pads Supply Voltage (VIO) All On (RES = 1) Directional Tap™ (RES = 0, ODR = 400Hz) Current Consumption Low Power (RES = 0, ODR ≤ 25Hz) Standby Output Low Voltage Output High Voltage Input Low Voltage Input High Voltage Input Pull-down Current RES = 0 RES = 1, ODR = 12.5Hz RES = 1, ODR = 25 Hz RES = 1, ODR = 50Hz 1 Start Up Time RES = 1, ODR = 100Hz RES = 1, ODR = 200Hz RES = 1, ODR = 400Hz RES = 1, ODR = 800Hz 2 Power Up Time SPI Communication Rate 3 Output Data Rate (ODR) RES = 0 4 Bandwidth (-3dB) RES = 1 Notes: 1. 2. 3. 4. V V 1.71 1.7 2.6 3.6 Vdd 325 165 A 100 V V V V A 0.8 * Vio 0.8 * Vio ms ms MHz Hz KHz Hz 10 0 0.050 81 41 21 11 6 4 2.5 10 0.2 * Vio 0.2 * Vio - 20 12.5 50 800 1.59 ODR/2 Start up time is from PC1 set to valid outputs. Power up time is from Vdd valid to device boot completion. User selectable through SPI. User selectable and dependant on ODR and RES. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 4 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Table 3. Environmental Units Min Typical Max Supply Voltage (Vdd) Absolute Limits Operating Temperature Range Storage Temperature Range Parameters V ºC ºC -0.5 -40 -55 - Mech. Shock (powered and unpowered) g - - ESD V - - 3.63 85 150 5000 for 0.5ms 10000 for 0.2ms 2000 HBM Caution: ESD Sensitive and Mechanical Shock Sensitive Component, improper handling can cause permanent damage to the device. This product conforms to Directive 2002/95/EC of the European Parliament and of the Council of the European Union (RoHS). Specifically, this product does not contain lead, mercury, cadmium, hexavalent chromium, polybrominated biphenyls (PBB), or polybrominated diphenyl ethers (PBDE) above the maximum concentration values (MCV) by weight in any of its homogenous materials. Homogenous materials are "of uniform composition throughout." HF This product is halogen-free per IEC 61249-2-21. Specifically, the materials used in this product contain a maximum total halogen content of 1500 ppm with less than 900-ppm bromine and less than 900-ppm chlorine. Soldering Soldering recommendations are available upon request or from www.kionix.com. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 5 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Application Schematic SDI 10 IO Vdd 1 9 SCLK 2 8 SDO 3 7 INT 4 6 CS KXTIA 5 C1 Vdd Table 4. KXTIA Pin Descriptions Pin Name Description 1 2 3 IO Vdd DNC DNC The power supply input for the digital communication bus Reserved – Do Not Connect Reserved – Do Not Connect 4 GND Ground 5 6 7 8 9 10 Vdd nCS INT SDO SCLK SDI The power supply input. Decouple this pin to ground with a 0.1uF ceramic capacitor. SPI Enable Interrupt SPI Serial Data Output SPI Serial Clock SPI Serial Data Input 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 6 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Test Specifications ! Special Characteristics: These characteristics have been identified as being critical to the customer. Every part is tested to verify its conformance to specification prior to shipment. Table 5. Test Specifications Parameter Zero-g Offset @ RT Sensitivity @ RT 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com Specification 0 +/- 128 counts 1024 +/- 35.8 counts/g Test Conditions 25C, Vdd = 2.6 V 25C, Vdd = 2.6 V © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 7 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Package Dimensions and Orientation 3 x 3 x 0.9 mm LGA All dimensions and tolerances conform to ASME Y14.5M-1994 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 8 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com KXTIA-1006 Rev. 4 Dec-2012 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 9 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Orientation +Y Pin 1 +X +Z When device is accelerated in +X, +Y or +Z direction, the corresponding output will increase. Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=0 (± 2g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 12 8 12 8 12 8 0 1024 64 0 0 0 -1024 -64 1024 64 0 0 -1024 -64 0 0 0 0 0 0 0 0 0 0 0 0 + 0 + 0 0 0 0 0 0 5 Top 6 Bottom Bottom Top 12 8 12 8 0 0 0 0 0 0 0 0 1024 64 -1024 -64 0 0 + 0 0 - (1g) Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 10 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=0, GSEL0=1 (± 4g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 512 32 0 0 0 0 + 0 12 512 0 0 8 32 0 0 12 0 -512 0 + 0 0 8 0 -32 0 12 -512 0 0 0 0 8 -32 0 0 0 0 5 Top 6 Bottom Bottom Top 12 0 0 512 8 0 0 32 12 0 0 -512 0 0 + 8 0 0 -32 0 0 - (1g) Earth’s Surface Static X/Y/Z Output Response versus Orientation to Earth’s surface (1g): GSEL1=1, GSEL0=0 (± 8g) Position 1 2 3 4 Diagram Resolution (bits) X (counts) Y (counts) Z (counts) X-Polarity Y-Polarity Z-Polarity 12 8 0 0 256 16 0 0 0 0 + 0 12 256 0 0 8 16 0 0 + 0 0 12 0 -256 0 8 0 -16 0 0 0 (1g) 12 -256 0 0 8 -16 0 0 0 0 5 Top 6 Bottom Bottom Top 12 0 0 256 0 0 + 8 0 0 16 12 0 0 -256 8 0 0 -16 0 0 - Earth’s Surface 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 11 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 KXTIA Digital Interface The Kionix KXTIA digital accelerometer has the ability to communicate on the SPI digital serial interface bus. This flexibility allows for easy system integration by eliminating analog-to-digital converter requirements and by providing direct communication with system micro-controllers. The serial interface terms and descriptions as indicated in Table 6 below will be observed throughout this document. Term Transmitter Receiver Master Slave Description The device that transmits data to the bus. The device that receives data from the bus. The device that initiates a transfer, generates clock signals, and terminates a transfer. The device addressed by the Master. Table 6. Serial Interface Terminologies 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 12 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 4-Wire SPI Communications KXTIA 4-Wire SPI Timing Diagram t3 t t1 t2 t4 t9 nCS CLK SDI bit 7 bit 6 bit 1 5 bit 0 SDO bit 7 5 bit 7 5 t5 bit 6 t7 t6 t8 bit 6 bit 1 5 bit 1 5 bit 0 bit 0 t10 Table 7. 4-Wire SPI Timing Number t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Notes 1. 2. 3. Description CLK pulse width: high CLK pulse width: low nCS low to first CLK rising edge nCS low after the final CLK rising edge SDI valid to CLK rising edge CLK rising edge to SDI invalid CLK falling edge to SDO valid CLK falling edge to SDO valid bit CLK rising edge to SDO valid bit CLK rising edge to SDO invalid MIN 24 26 13 20 13 11 19 19 15 MAX t2 25 23 Units ns ns ns ns ns ns ns ns ns ns t7 is only present during reads. Timings are for Vdd of 1.8V to 3.6V with 1K pull-up resistor and maximum 20pF load capacitor on SDO. Falling Edge timing of Bit 7 applies only to first byte in auto-increment read and not subsequent bytes. For Bit 7 Max is t2/2. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 13 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 KXTIA 3-Wire SPI Timing Diagram t3 t1 t2 t4 nCS CLK SDI bit 7 bit 6 t5 t6 bit 1 5 bit 0 bit 7 t7 bit 1 5 bit 0 MIN 15 15 8 12 8 14 15 MAX 18 t8 Table 8. 3-Wire SPI Timing Number t1 t2 t3 t4 t5 t6 t7 t8 Notes 1. 2. Description CLK pulse width: high CLK pulse width: low nCS low to first CLK rising edge nCS low after the final CLK falling edge SDI valid to CLK rising edge CLK rising edge to SDI input invalid CLK extra clock cycle rising edge to SDI output becomes valid CLK rising edge to SDI output becomes valid - Units ns ns ns ns ns ns ns ns t7 and t8 are only present during reads. Timings are for Vdd of 1.8V to 3.6V with 1K pull-up resistor and maximum 20pF load capacitor on SDI. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 14 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 4-Wire SPI Interface The KXTIA also utilizes an integrated 4-Wire Serial Peripheral Interface (SPI) for digital communication. The SPI interface is primarily used for synchronous serial communication between one Master device and one or more Slave devices. The Master, typically a micro controller, provides the SPI clock signal (SCLK) and determines the state of Chip Select (nCS). The KXTIA always operates as a Slave device during standard Master-Slave SPI operation. 4-wire SPI is a synchronous serial interface that uses two control and two data lines. With respect to the Master, the Serial Clock output (SCLK), the Data Output (SDI or MOSI) and the Data Input (SDO or MISO) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. The Slave Data Output (SDO) line, remains in a high-impedance (hi-z) state when the device is not selected, so it does not interfere with any active devices. This allows multiple Slave devices to share a master SPI port as shown in Figure 2 below. Master Serial Clock CS0 CS1 Slave 0 SCLK CS KXTIA MCU SDI MOSI (Data Out) MISO (Data In) SDO Slave 1 SCLK CS KXTIA SDI SDO Figure 2 KXTIA 4-wire SPI Connections 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 15 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Read and Write Registers The registers embedded in the KXTIA have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register and “1” when reading from the register. This operation occurs over 16 clock cycles. All commands are sent MSB first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 3 below shows the timing diagram for carrying out an 8-bit register write operation. Write Address First 8 bits Second 8 bits Last 8 bits CLK SDI SDO A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D2 D1 D0 HI-Z HI-Z CS Figure 3 Timing Diagram for 8-Bit Register Write Operation In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. This operation also occurs over 16 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 4 shows the timing diagram for an 8-bit register read operation. Read Address Second 8 bits First 8 bits Last 8 bits CLK SDI SDO A7 A6 A5 A4 A3 A2 A1 A0 HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D2 D1 D0 HI-Z CS Figure 4 Timing Diagram for 8-Bit Register Read Operation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 16 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 3-Wire SPI Interface The KXTIA also utilizes an integrated 3-Wire Serial Peripheral Interface (SPI) for digital communication. 3wire SPI is a synchronous serial interface that uses two control lines and one data line. With respect to the Master, the Serial Clock output (SCLK), the Data Output/Input (SDI) are shared among the Slave devices. The Master generates an independent Chip Select (nCS) for each Slave device that goes low at the start of transmission and goes back high at the end. This allows multiple Slave devices to share a master SPI port as shown in Figure 6 below. Master Serial Clock CS0 CS1 Slave 0 SCLK CS KXTIA MCU SDI MOSI/MISO (Data Out/In) Slave 1 SCLK CS KXTIA SDI Figure 5 KXTIA 3-wire SPI Connections Read and Write Registers The registers embedded in the KXTIA have 8-bit addresses. Upon power up, the Master must write to the accelerometer’s control registers to set its operational mode. On the falling edge of nCS, a 2-byte command is written to the appropriate control register. The first byte initiates the write to the appropriate register, and is followed by the user-defined, data byte. The MSB (Most Significant Bit) of the register address byte will indicate “0” when writing to the register and “1” when reading from the register. A read operation occurs over 17 clock cycles and a write operation occurs over 16 clock cycles. All commands are sent MSB first, and the host must return nCS high for at least one clock cycle before the next address transmission. Figure 6 below shows the timing diagram for carrying out an 8-bit register write operation. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 17 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 SCLK SDI A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (MSB) CS Figure 6 Timing Diagram for 8-Bit Register Write Operation In order to read an 8-bit register, an 8-bit register address must be written to the accelerometer to initiate the read. The MSB of this register address byte will indicate “0” when writing to the register and “1” when reading from the register. Upon receiving the address, the accelerometer returns the 8-bit data stored in the addressed register. For 3-wire read operations, one extra clock cycle between the address byte and the data output byte is required. Therefore, this operation occurs over 17 clock cycles. All returned data is sent MSB first, and the host must return nCS high for at least one clock cycle before the next data request. Figure 7 shows the timing diagram for an 8-bit register read operation. SCLK SDI D7 D6 D5 D4 D3 D2 D1 D0 HI-Z A7 A6 A5 A4 A3 A2 A1 A0 (MSB) (MSB) CS Figure 7 Timing Diagram for 8-Bit Register Read Operation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 18 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 KXTIA Embedded Registers The KXTIA has 44 embedded 8-bit registers that are accessible by the user. This section contains the addresses for all embedded registers and also describes bit functions of each register. Table 9 below provides a listing of the accessible 8-bit registers and their addresses. Register Name XOUT_HPF_L XOUT_HPF_H YOUT_HPF_L YOUT_HPF_H ZOUT_HPF_L ZOUT_HPF_H XOUT_L XOUT_H YOUT_L YOUT_H ZOUT_L ZOUT_H DCST_RESP Not Used Not Used WHO_AM_I TILT_POS_CUR TILT_POS_PRE Kionix Reserved Kionix Reserved Kionix Reserved INT_SRC_REG1 INT_SRC_REG2 Not Used STATUS_REG Not Used INT_REL CTRL_REG1* CTRL_REG2* 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com Type Read/Write R R R R R R R R R R R R R R R R R R R R R/W R/W SPI Write Address Hex Binary 0x00 0000 0000 0x01 0000 0001 0x02 0000 0010 0x03 0000 0011 0x04 0000 0100 0x05 0000 0101 0x06 0000 0110 0x07 0000 0111 0x08 0000 1000 0x09 0000 1001 0x0A 0000 1010 0x0B 0000 1011 0x0C 0000 1100 0x0D 0000 1101 0x0E 0000 1110 0x0F 0000 1111 0x10 0001 0000 0x11 0001 0001 0x12 0001 0010 0x13 0001 0011 0x14 0001 0100 0x15 0001 0101 0x16 0001 0110 0x17 0001 0111 0x18 0001 1000 0x19 0001 1001 0x1A 0001 1010 0x1B 0001 1011 0x1C 0001 1100 SPI Read Address Hex Binary 0x80 1000 0000 0x81 1000 0001 0x82 1000 0010 0x83 1000 0011 0x84 1000 0100 0x85 1000 0101 0x86 1000 0110 0x87 1000 0111 0x88 1000 1000 0x89 1000 1001 0x8A 1000 1010 0x8B 1000 1011 0x8C 1000 1100 0x8D 1000 1101 0x8E 1000 1110 0x8F 1000 1111 0x90 1001 0000 0x91 1001 0001 0x92 1001 0010 0x93 1001 0011 0x94 1001 0100 0x95 1001 0101 0x96 1001 0110 0x97 1001 0111 0x98 1001 1000 0x99 1001 1001 0x9A 1001 1010 0x9B 1001 1011 0x9C 1001 1100 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 19 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications CTRL_REG3* INT_CTRL_REG1* INT_CTRL_REG2* INT_CTRL_REG3* DATA_CTRL_REG* Not Used TILT_TIMER* WUF_TIMER* Not Used TDT_TIMER* TDT_H_THRESH* TDT_L_THRESH* TDT_TAP_TIMER* TDT_TOTAL_TIMER* TDT_LATENCY_TIMER* TDT_WINDOW_TIMER* BUF_CTRL1* BUF_CTRL2* BUF_STATUS_REG1 BUF_STATUS_REG2 BUF_CLEAR Reserved SELF_TEST Reserved WUF_THRESH* Reserved TILT_ANGLE* Reserved HYST_SET* BUF_READ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R W R/W R/W R/W R/W R 0x1D 0x1E 0x1F 0x20 0x21 0x22 – 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 – 0x39 0x3A 0x3B – 0x59 0x5A 0x5B 0x5C 0x5D – 0x5E 0x6F 0x7F KXTIA-1006 Rev. 4 Dec-2012 0001 1101 0x9D 1001 1101 0001 1110 0x9E 1001 1110 0001 1111 0x9F 1001 1111 0010 0000 0xA0 1010 0000 0010 0001 0xA1 1010 0001 0xA2 – 0xA7 0010 1000 0xA8 1010 1000 0010 1001 0xA9 1010 1001 0010 1010 0xAA 1010 1010 0010 1011 0xAB 1010 1011 0010 1100 0xAC 1010 1100 0010 1101 0xAD 1010 1101 0010 1110 0xAE 1010 1110 0010 1111 0xAF 1010 1111 0011 0000 0xB0 1011 0000 0011 0001 0xB1 1011 0001 0011 0010 0xB2 1011 0010 0011 0011 0xB3 1011 0011 0011 0100 0xB4 1011 0100 0011 0101 0xB5 1011 0101 0011 0110 0xB6 1011 0110 0xB7 - 0xB9 0011 1010 0xBA 1011 1010 0xBB – 0xD9 0101 1010 0xDA 1101 1010 0101 1011 0xDB 1101 1011 0101 1100 0xDC 1101 1100 0xDD – 0xDE 0110 1111 0xEF 1110 1111 0111 1111 0xFF 1111 1111 * Note: When changing the contents of these registers, the PC1 bit in CTRL_REG1 must first be set to “0”. Table 9. KXTIA Register Map 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 20 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 KXTIA Register Descriptions Accelerometer Outputs These registers contain up to 12-bits of valid acceleration data for each axis depending on the setting of the RES bit in CTRL_REG1, where the acceleration outputs are represented in 12-bit valid data when RES = ‘1’ and 8-bit valid data when RES = ‘0’. The data is updated every user-defined ODR period, is protected from overwrite during each read, and can be converted from digital counts to acceleration (g) per Figure 1 below. The register acceleration output binary data is represented in N-bit 2’s complement format. For example, if N = 12 bits, then the Counts range is from -2048 to 2047, and if N = 8 bits, then the Counts range is from -128 to 127. 12-bit Register Data (2’s complement) 0111 1111 1111 0111 1111 1110 … 0000 0000 0001 0000 0000 0000 1111 1111 1111 … 1000 0000 0001 1000 0000 0000 8-bit Register Data (2’s complement) 0111 1111 0111 1110 … 0000 0001 0000 0000 1111 1111 … 1000 0001 1000 0000 Equivalent Counts in decimal 2047 2046 … 1 0 -1 … -2047 -2048 Range = +/-2g +1.999g +1.998g … +0.001g 0.000g -0.001g … -1.999g -2.000g Range = +/-4g +3.998g +3.996g … +0.002g 0.000g -0.002g … -3.998g -4.000g Range = +/-8g +7.996g +7.992g … +0.004g 0.000g -0.004g … -7.996g -8.000g Equivalent Counts in decimal 127 126 … 1 0 -1 … -127 -128 Range = +/-2g +1.984g +1.968g … +0.016g 0.000g -0.016g … -1.984g -2.000g Range = +/-4g +3.968g +3.936g … +0.032g 0.000g -0.032g … -3.968g -4.000g Range = +/-8g +7.936g +7.872g … +0.064g 0.000g -0.064g … -7.936g -8.000g Figure 1. Acceleration (g) Calculation 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 21 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Note: The High Pass Filter outputs are only available if the Wake Up Function is enabled. XOUT_HPF_L X-axis high-pass filtered accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x00h SPI Read Address: 0x80h XOUT_HPF_H X-axis high-pass filtered accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 R XOUTD8 Bit4 R XOUTD7 Bit3 R R R XOUTD6 XOUTD5 XOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x01h SPI Read Address: 0x81h YOUT_HPF_L Y-axis high-pass filtered accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x02h SPI Read Address: 0x82h YOUT_HPF_H Y-axis high-pass filtered accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R YOUTD8 Bit4 R YOUTD7 Bit3 R R R YOUTD6 YOUTD5 YOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x03h SPI Read Address: 0x83h © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 22 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 ZOUT_HPF_L Z-axis high-pass filtered accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x04h SPI Read Address: 0x84h ZOUT_HPF_H Z-axis high-pass filtered accelerometer output most significant byte R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 R ZOUTD8 Bit4 R ZOUTD7 Bit3 R R R ZOUTD6 ZOUTD5 ZOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x05h SPI Read Address: 0x85h XOUT_L X-axis accelerometer output least significant byte R XOUTD3 Bit7 R XOUTD2 Bit6 R XOUTD1 Bit5 R XOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x06h SPI Read Address: 0x86h XOUT_H X-axis accelerometer output most significant byte R R R XOUTD11 XOUTD10 XOUTD9 Bit7 Bit6 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R XOUTD8 Bit4 R XOUTD7 Bit3 R R R XOUTD6 XOUTD5 XOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x07h SPI Read Address: 0x87h © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 23 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 YOUT_L Y-axis accelerometer output least significant byte R YOUTD3 Bit7 R YOUTD2 Bit6 R YOUTD1 Bit5 R YOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x08h SPI Read Address: 0x88h YOUT_H Y-axis accelerometer output most significant byte R R R YOUTD11 YOUTD10 YOUTD9 Bit7 Bit6 Bit5 R YOUTD8 Bit4 R YOUTD7 Bit3 R R R YOUTD6 YOUTD5 YOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x09h SPI Read Address: 0x89h ZOUT_L Z-axis accelerometer output least significant byte R ZOUTD3 Bit7 R ZOUTD2 Bit6 R ZOUTD1 Bit5 R ZOUTD0 Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x0Ah SPI Read Address: 0x8Ah ZOUT_H Z-axis accelerometer output most significant byte R R R ZOUTD11 ZOUTD10 ZOUTD9 Bit7 Bit6 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R ZOUTD8 Bit4 R ZOUTD7 Bit3 R R R ZOUTD6 ZOUTD5 ZOUTD4 Bit2 Bit1 Bit0 SPI Write Address: 0x0Bh SPI Read Address: 0x8Bh © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 24 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 DCST_RESP This register can be used to verify proper integrated circuit functionality. It always has a byte value of 0x55h unless the DCST bit in CTRL_REG3 is set. At that point this value is set to 0xAAh. The byte value is returned to 0x55h after reading this register. R DCSTR7 Bit7 R DCSTR6 Bit6 R DCSTR5 Bit5 R DCSTR4 Bit4 R DCSTR3 Bit3 R R R DCSTR2 DCSTR1 DCSTR0 Bit2 Bit1 Bit0 SPI Write Address: 0x0Ch SPI Read Address: 0x8Ch Reset Value 01010101 WHO_AM_I This register can be used for supplier recognition, as it can be factory written to a known byte value. The default value is 0x06h. R WIA7 Bit7 R WIA6 Bit6 R WIA5 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R WIA4 Bit4 R WIA3 Bit3 R R R WIA2 WIA1 WIA0 Bit2 Bit1 Bit0 SPI Write Address: 0x0Fh SPI Read Address: 0x8Fh Reset Value 00000110 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 25 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Tilt Position Registers These two registers report previous and current tilt position data that is updated at the user-defined ODR frequency and is protected during register read. Table 10 describes the reported position for each bit value. TILT_POS_CUR Current tilt position register R 0 Bit7 R 0 Bit6 R LE Bit5 R RI Bit4 R DO Bit3 R R R UP FD FU Bit2 Bit1 Bit0 SPI Write Address: 0x10h SPI Read Address: 0x90h R DO Bit3 R R R UP FD FU Bit2 Bit1 Bit0 SPI Write Address: 0x11h SPI Read Address: 0x91h Reset Value 00100000 TILT_POS_PRE Previous tilt position register R 0 Bit7 R 0 Bit6 R LE Bit5 R RI Bit4 Bit LE RI DO UP FD FU Reset Value 00100000 Description Left State (X-) Right State (X+) Down State (Y-) Up State (Y+) Face-Down State (Z-) Face-Up State (Z+) Table 10. KXTIA Tilt Position 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 26 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Interrupt Source Registers These two registers report function state changes. This data is updated when a new state change or event occurs and each application’s result is latched until the interrupt release register is read. The motion interrupt bit WUFS can be configured to report data in an unlatched manner via the interrupt control registers. INT_SRC_REG1 This register reports which axis and direction detected a single or double tap event, per Table 11. R 0 Bit7 R 0 Bit6 R TLE Bit5 R TRI Bit4 R TDO Bit3 Bit TLE TRI TDO TUP TFD TFU R R R TUP TFD TFU Bit2 Bit1 Bit0 SPI Write Address: 0x15h SPI Read Address: 0x95h Description X Negative (X-) Reported X Positive (X+) Reported Y Negative (Y-) Reported Y Positive (Y+) Reported Z Negative (Z-) Reported Z Positive (Z+) Reported Table 11. KXTIA Directional TapTM Reporting 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 27 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 INT_SRC_REG2 This register reports which function caused an interrupt. Reading from the interrupt release register will clear the entire contents of this register. R 0 Bit7 R 0 Bit6 R WMI Bit5 R DRDY Bit4 R TDTS1 Bit3 R R R TDTS0 WUFS TPS Bit2 Bit1 Bit0 SPI Write Address: 0x16h SPI Read Address: 0x96h DRDY indicates that new acceleration data is available. This bit is cleared when acceleration data is read or the interrupt release register is read. DRDY = 0 – new acceleration data not available DRDY = 1 – new acceleration data available TDTS1, TDTS0 indicates whether a single or double-tap event was detected per Table 12. TDTS1 TDTS0 Event 0 0 No Tap 0 1 Single Tap 1 0 Double Tap 1 1 DNE Table 12. Directional TapTM Event Description WUFS - Wake up, This bit is cleared when acceleration data is read or the interrupt release register is read. 0 = No motion 1 = Motion has activated the interrupt TPS reflects the status of the tilt position function. TPS = 0 – tilt position state has not changed TPS = 1 – tilt position state has changed WMI indicates that the buffer’s sample threshold has been reached when in FIFO, FILO, or Stream mode. Not used in Trigger mode. WMI = 0 – sample threshold has not been reached WMI = 1 – sample threshold has been reached 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 28 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 STATUS_REG This register reports the status of the interrupt. R 0 Bit7 R 0 Bit6 R 0 Bit5 R INT Bit4 R 0 Bit3 R R R 0 0 0 Bit2 Bit1 Bit0 SPI Write Address: 0x18h SPI Read Address: 0x98h INT reports the combined interrupt information of all enabled functions. This bit is released to 0 when the interrupt source latch register (1Ah) is read. INT = 0 – no interrupt event INT = 1 – interrupt event has occurred INT_REL Latched interrupt source information (INT_SRC_REG1 and INT_SRC_REG2), the status register, and the physical interrupt pin (7) are cleared when reading this register. R X Bit7 R X Bit6 R X Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R X Bit4 R X Bit3 R R R X X X Bit2 Bit1 Bit0 SPI Write Address: 0x1Ah SPI Read Address: 0x9Ah © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 29 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 CTRL_REG1 Read/write control register that controls the main feature set. R/W PC1 Bit7 R/W RES Bit6 R/W DRDYE Bit5 R/W GSEL1 Bit4 R/W GSEL0 Bit3 R/W R/W R/W TDTE WUFE TPE Bit2 Bit1 Bit0 SPI Write Address: 0x1Bh SPI Read Address: 0x9Bh Reset Value 00000000 PC1 controls the operating mode of the KXTIA. PC1 = 0 - stand-by mode PC1 = 1 – operating mode RES determines the performance mode of the KXTIA. Note that to change the value of this bit, the PC1 bit must first be set to “0”. RES = 0 – low current, 8-bit valid RES = 1- high current, 12-bit valid DRDYE enables the reporting of the availability of new acceleration data as an interrupt. Note that to change the value of this bit, the PC1 bit must first be set to “0”. DRDYE = 0 - new acceleration data not available DRDYE = 1- new acceleration data available GSEL1, GSEL0 selects the acceleration range of the accelerometer outputs per Table 13. Note that to change the value of this bit, the PC1 bit must first be set to “0”. GSEL1 GSEL0 0 0 0 1 1 0 1 1 Range +/-2g +/-4g +/-8g NA Table 13. Selected Acceleration Range 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 30 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TDTE enables the Directional TapTM function that will detect single and double tap events. Note that to change the value of this bit, the PC1 bit must first be set to “0”. TDTE = 0 – disable TDTE = 1- enable WUFE enables the Wake Up (motion detect) function that will detect a general motion event. Note that to change the value of this bit, the PC1 bit must first be set to “0”. WUFE = 0 – disable WUFE = 1- enable TPE enables the Tilt Position function that will detect changes in device orientation. Note that to change the value of this bit, the PC1 bit must first be set to “0”. TPE = 0 – disable TPE = 1- enable CTRL_REG2 Read/write control register that primarily controls tilt position state enabling. Per Table 14, if a state’s bit is set to one (1), a transition into the corresponding orientation state will generate an interrupt. If it is set to zero (0), a transition into the corresponding orientation state will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W OTDTH Bit7 R/W 0 Bit6 R/W LEM Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W RIM Bit4 R/W DOM Bit3 R/W R/W R/W UPM FDM FUM Bit2 Bit1 Bit0 SPI Write Address: 0x1Ch SPI Read Address: 0x9Ch Reset Value 00111111 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 31 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 OTDTH determines the range of the Directional TapTM Output Data Rate (ODR). See Table 16 for additional clarification. OTDTH = 0 – slower range of Directional TapTM ODR’s are available. SRST = 1 – faster range of Directional TapTM ODR’s are available. Bit LEM RIM DOM UPM FDM FUM Description Left State Right State Down State Up State Face-Down State Face-Up State Table 14. Tilt Position State Enabling CTRL_REG3 Read/write control register that provides more feature set control. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W SRST Bit7 R/W OTPA Bit6 R/W OTPB Bit5 R/W DCST Bit4 R/W OTDTA Bit3 R/W R/W R/W OTDTB OWUFA OWUFB Bit2 Bit1 Bit0 SPI Write Address: 0x1Dh SPI Read Address: 0x9Dh Reset Value 01001101 SRST initiates software reset, which performs the RAM reboot routine. This bit will remain 1 until the RAM reboot routine is finished. SRST = 0 – no action SRST = 1 – start RAM reboot routine OTPA, OTPB sets the output data rate for the Tilt Position function per Table 15. The default Tilt Position ODR is 12.5Hz. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 32 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications OTPA 0 0 1 1 OTPB 0 1 0 1 KXTIA-1006 Rev. 4 Dec-2012 Output Data Rate 1.6Hz 6.3Hz 12.5Hz 50Hz Table 15. Tilt Position Function Output Data Rate DCST initiates the digital communication self-test function. DCST = 0 – no action DCST = 1 – sets ST_RESP register to 0xAAh and when ST_RESP is read, sets this bit to 0 and sets ST_RESP to 0x55h OTDTA, OTDTB sets the output data rate for the Directional TapTM function per Table 16. The default Directional TapTM ODR is 400Hz. OTDTH OTDTA OTDTB Output Data Rate 0 0 0 50Hz 0 0 1 100Hz 0 1 0 200Hz 0 1 1 400Hz 1 0 0 12.5Hz 1 0 1 25Hz 1 1 0 800Hz 1 1 1 1600Hz Table 16. Directional TapTM Function Output Data Rate 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 33 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 OWUFA, OWUFB sets the output data rate for the general motion detection function and the high-pass filtered outputs per Table 17. The default Motion Wake Up ODR is 50Hz. OWUFA OWUFB Output Data Rate 0 0 25Hz 0 1 50Hz 1 0 100Hz 1 1 200Hz Table 17. Motion Wake Up Function Output Data Rate INT_CTRL_REG1 This register controls the settings for the physical interrupt pin (7). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W IEN Bit5 R/W IEA Bit4 R/W IEL Bit3 R/W R/W R/W IEU 0 SPI3E Bit2 Bit1 Bit0 SPI Write Address: 0x1Eh SPI Read Address: 0x9Eh Reset Value 00010000 IEN enables/disables the physical interrupt pin (7) IEN = 0 – physical interrupt pin (7) is disabled IEN = 1 – physical interrupt pin (7) is enabled IEA sets the polarity of the physical interrupt pin (7) IEA = 0 – polarity of the physical interrupt pin (7) is active low IEA = 1 – polarity of the physical interrupt pin (7) is active high IEL sets the response of the physical interrupt pin (7) IEL = 0 – the physical interrupt pin (7) latches until it is cleared by reading INT_REL IEL = 1 – the physical interrupt pin (7) will transmit one pulse with a period of approximately 0.03 - 0.05ms IEU sets an alternate unlatched response for the physical interrupt pin (7) when the motion interrupt feature (WUF) only is enabled. IEU = 0 – the physical interrupt pin (7) latches or pulses per the IEL bit until it is cleared by reading INT_REL IEU = 1 – the physical interrupt pin (7) will follow an unlatched response if the motion interrupt feature is enabled 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 34 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com KXTIA-1006 Rev. 4 Dec-2012 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 35 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 SPI3E sets SPI protocol to 3-wire or 4-wire SPI. SPI3E = 0 – 4-wire SPI enabled SPI3E = 1 – 3-wire SPI enabled INT_CTRL_REG2 This register controls motion detection axis enabling. Per Table 18, if an axis’ bit is set to one (1), a motion on that axis will generate an interrupt. If it is set to zero (0), a motion on that axis will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W XBW Bit7 R/W YBW Bit6 R/W ZBW Bit5 R/W 0 Bit4 R/W 0 Bit3 R/W 0 Bit2 R/W 0 Bit1 R/W 0 Bit0 Reset Value 11100000 SPI Write Address: 0x1Fh SPI Read Address: 0x9Fh Bit XBW YBW ZBW Description X-Axis Motion Y-Axis Motion Z-Axis Motion Table 18. Motion Detection Axis Enabling 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 36 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 INT_CTRL_REG3 This register controls the tap detection direction axis enabling. Per Table 14, if a direction’s bit is set to one (1), a single or double tap in that direction will generate an interrupt. If it is set to zero (0), a single or double tap in that direction will not generate an interrupt. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W TMEN Bit6 R/W TLEM Bit5 R/W TRIM Bit4 R/W TDOM Bit3 Bit TLEM TRIM TDOM TUPM TFDM TFUM R/W R/W R/W TUPM TFDM TFUM Bit2 Bit1 Bit0 SPI Write Address: 0x20h SPI Read Address: 0xA0h Reset Value 00111111 Description X Negative (X-) X Positive (X+) Y Negative (Y-) Y Positive (Y+) Z Negative (Z-) Z Positive (Z+) Table 19. Directional TapTM Axis Mask TMEN enables/disables alternate tap masking scheme TMEN = 0 – alternate tap masking scheme disabled TMEN = 1 – alternate tap masking scheme enabled 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 37 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 DATA_CTRL_REG Read/write control register that configures the acceleration outputs. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W 0 Bit7 R/W 0 Bit6 R/W HPFROA Bit5 R/W HPROB Bit4 R/W 0 Bit3 R/W R/W R/W OSAA OSAB OSAC Bit2 Bit1 Bit0 SPI Write Address: 0x21h SPI Read Address: 0xA1h Reset Value 00000010 HPFROA, HPFROB sets the roll-off frequency for the first-order high-pass filter in conjunction with the output data rate (OWUFA, OWUFB) that is chosen for the HPF acceleration outputs that are used in the Motion Wake Up (WUF) application per Table 20. Note that this roll-off frequency is also applied to the X, Y and Z high-pass filtered outputs. High-Pass Filter Configuration HPFROA HPFROB Beta HPF Roll-Off (Hz) 0 0 7/8 ODR / 50 0 1 15/16 ODR / 100 1 0 31/32 ODR / 200 1 1 63/64 ODR / 400 Table 20. High-Pass Filter Roll-Off Frequency OSAA, OSAB, OSAC sets the output data rate (ODR) for the low-pass filtered acceleration outputs per Table 21. OSAA 0 0 0 0 1 1 1 1 OSAB 0 0 1 1 0 0 1 1 OSAC 0 1 0 1 0 1 0 1 Output Data Rate 12.5Hz 25Hz 50Hz 100Hz 200Hz 400Hz 800Hz Does Not Exist LPF Roll-Off 6.25Hz 12.5Hz 25Hz 50Hz 100Hz 200Hz 400Hz Does Not Exist Table 21. LPF Acceleration Output Data Rate (ODR) 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 38 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TILT_TIMER This register is the initial count register for the tilt position state timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the Tilt Position ODR is user-defined per Table 15. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TSC7 Bit7 R/W TSC6 Bit6 R/W TSC5 Bit5 R/W TSC4 Bit4 R/W TSC3 Bit3 R/W R/W R/W TSC2 TSC1 TSC0 Bit2 Bit1 Bit0 SPI Write Address: 0x28h SPI Read Address: 0xA8h Reset Value 00000000 WUF_TIMER This register is the initial count register for the motion detection timer (0 to 255 counts). Every count is calculated as 1/ODR delay period, where the Motion Wake Up ODR is user-defined per Table 17. A new state must be valid as many measurement periods before the change is accepted. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W WUFC7 Bit7 R/W WUFC6 Bit6 R/W WUFC5 Bit5 R/W WUFC4 Bit4 R/W WUFC3 Bit3 R/W WUFC2 Bit2 R/W WUFC1 Bit1 R/W WUFC0 Bit0 Reset Value 00000000 SPI Write Address: 0x29h SPI Read Address: 0xA9h 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 39 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TDT_TIMER This register contains counter information for the detection of a double tap event. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is userdefined per Table 16. TDT_TIMER represents the minimum time separation between the first tap and the second tap in a double tap event. The Kionix recommended default value is 0.3 seconds (0x78h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TDTC7 Bit7 R/W TDTC6 Bit6 R/W TDTC5 Bit5 R/W TDTC4 Bit4 R/W TDTC3 Bit3 R/W R/W R/W TDTC2 TDTC1 TDTC0 Bit2 Bit1 Bit0 SPI Write Address: 0x2Bh SPI Read Address: 0xABh Reset Value 01111000 TDT_H_THRESH This register represents the 8-bit jerk high threshold to determine if a tap is detected. Though this is an 8-bit register, the KXTIA internally multiplies the register value by two in order to set the high threshold. This multiplication results in a range of 0d to 510d with a resolution of two counts. The Performance Index (PI) is the jerk signal that is expected to be less than this threshold, but greater than the TDT_L_THRESH threshold during single and double tap events. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. The Kionix recommended default value is 203 (0xCBh) and the Performance Index is calculated as: X’ = X(current) – X(previous) Y’ = Y(current) – Y(previous) Z’ = Z(current) – Z(previous) PI = |X’| + |Y’| + |Z’| Equation 1. Performance Index R/W TTH7 Bit7 R/W TTH6 Bit6 R/W TTH5 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W TTH4 Bit4 R/W TTH3 Bit3 R/W R/W R/W TTH2 TTH1 TTH0 Bit2 Bit1 Bit0 SPI Write Address: 0x2Ch SPI Read Address: 0xACh Reset Value 11001011 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 40 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TDT_L_THRESH This register represents the 8-bit (0d– 255d) jerk low threshold to determine if a tap is detected. The Performance Index (PI) is the jerk signal that is expected to be greater than this threshold and less than the TDT_H_THRESH threshold during single and double tap events. This register also contains the LSB of the TDT_H_THRESH threshold. The Kionix recommended default value is 26 (0x1Ah). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TTH7 Bit7 R/W TTL6 Bit6 R/W TTL5 Bit5 R/W TTL4 Bit4 R/W TTL3 Bit3 R/W R/W R/W TTL2 TTL1 TTL0 Bit2 Bit1 Bit0 SPI Write Address: 0x2Dh SPI Read Address: 0xADh Reset Value 00011010 TDT_TAP_TIMER This register contains counter information for the detection of any tap event. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is userdefined per Table 16. In order to ensure that only tap events are detected, these time limits are used. A tap event must be above the performance index threshold (TDT_THRESH) for at least the low limit (FTDL0 – FTDL2) and no more than the high limit (FTDH0 – FTDH4). The Kionix recommended default value for the high limit is 0.05 seconds and for the low limit is 0.005 seconds (0xA2h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W FTDH4 Bit7 R/W FTDH3 Bit6 R/W FTDH2 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W FTDH1 Bit4 R/W FTDH0 Bit3 R/W R/W R/W FTDL2 FTDL1 FTDL0 Bit2 Bit1 Bit0 SPI Write Address: 0x2Eh SPI Read Address: 0xAEh Reset Value 10100010 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 41 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TDT_TOTAL_TIMER This register contains counter information for the detection of a double tap event. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is userdefined per Table 16. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the two taps in a double tap event can be above the PI threshold (TDT_L_THRESH). The Kionix recommended default value for TDT_TOTAL_TIMER is 0.09 seconds (0x24h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W STD7 Bit7 R/W STD6 Bit6 R/W STD5 Bit5 R/W STD4 Bit4 R/W STD3 Bit3 R/W R/W R/W STD2 STD1 STD0 Bit2 Bit1 Bit0 SPI Write Address: 0x2Fh SPI Read Address: 0xAFh Reset Value 00100100 TDT_LATENCY_TIMER This register contains counter information for the detection of a tap event. When the Directional Tap TM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional Tap TM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional TapTM ODR is user-defined per Table 16. In order to ensure that only tap events are detected, this time limit is used. This register sets the total amount of time that the tap algorithm will count samples that are above the PI threshold (TDT_L_THRESH) during a potential tap event. It is used during both single and double tap events. However, reporting of single taps on the physical interrupt pin (7) will occur at the end of the TDT_WINDOW_TIMER. The Kionix recommended default value for TDT_LATENCY_TIMER is 0.1 seconds (0x28h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TLT7 Bit7 R/W TLT6 Bit6 R/W TLT5 Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W TLT4 Bit4 R/W TLT3 Bit3 R/W R/W R/W TLT2 TLT1 TLT0 Bit2 Bit1 Bit0 SPI Write Address: 0x30h SPI Read Address: 0xB0h Reset Value 00101000 © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 42 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 TDT_WINDOW_TIMER This register contains counter information for the detection of single and double taps. When the Directional TapTM ODR is 400Hz or less, every count is calculated as 1/ODR delay period. When the Directional TapTM ODR is 800Hz, every count is calculated as 2/ODR delay period. When the Directional TapTM ODR is 1600Hz, every count is calculated as 4/ODR delay period. The Directional Tap TM ODR is user-defined per Table 16. It defines the time window for the entire tap event, single or double, to occur. Reporting of single taps on the physical interrupt pin (7) will occur at the end of this tap window. The Kionix recommended default value for TDT_WINDOW_TIMER is 0.4 seconds (0xA0h). Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W R/W R/W R/W R/W R/W R/W R/W TWS7 TWS6 TWS5 TWS4 TWS3 TWS2 TWS1 TWS0 Reset Value Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 10100000 SPI Write Address: 0x31h SPI Read Address: 0xB1h BUF_CTRL1 Read/write control register that controls the buffer sample threshold. R/W Bit7 R/W R/W R/W R/W R/W R/W R/W SMP_TH6 SMP_TH5 SMP_TH4 SMP_TH3 SMP_TH2 SMP_TH1 SMP_TH0 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Reset Value 00000000 SPI Write Address: 0x32h SPI Read Address: 0xB2h SMP_TH[6:0] Sample Threshold; determines the number of samples that will trigger a watermark interrupt or will be saved prior to a trigger event. When BUF_RES=1, the maximum number of samples is 41; when BUF_RES=0, the maximum number of samples is 84. Buffer Model Bypass FIFO Stream Trigger FILO Sample Function None Specifies how many buffer sample are needed to trigger a watermark interrupt. Specifies how many buffer samples are needed to trigger a watermark interrupt. Specifies how many buffer samples before the trigger event are retained in the buffer. Specifies how many buffer samples are needed to trigger a watermark interrupt. Table 22. Sample Threshold Operation by Buffer Mode 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 43 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 BUF_CTRL2 Read/write control register that controls sample buffer operation. R/W BUFE Bit7 R/W BUF_RES Bit6 R/W 0 Bit5 R/W 0 Bit4 R/W 0 Bit3 R/W R/W R/W 0 BUF_M1 BUF_M0 Bit2 Bit1 Bit0 SPI Write Address: 0x33h SPI Read Address: 0xB3h Reset Value 00000000 BUFE controls activation of the sample buffer. BUFE = 0 – sample buffer inactive BUFE = 1 – sample buffer active BUF_RES determines the resolution of the acceleration data samples collected by the sample buffer. BUF_RES = 0 – 8-bit samples are accumulated in the buffer BUF_RES = 1 – 12-bit samples are accumulated in the buffer BUF_M1, BUF_M0 selects the operating mode of the sample buffer per Table 23. BUF_M1 BUF_M0 Mode 0 0 FIFO 0 1 Stream 1 0 Trigger 1 1 FILO Description The buffer collects 84 sets of 8-bit low resolution values or 41 sets of 12bit high resolution values and then stops collecting data, collecting new data only when the buffer is not full. The buffer holds the last 84 sets of 8-bit low resolution values or 41 sets of 12bit high resolution values. Once the buffer is full, the oldest data is discarded to make room for newer data. When a trigger event occurs, the buffer holds the last data set of SMP[6:0] samples before the trigger event and then continues to collect data until full. New data is collected only when the buffer is not full. The buffer holds the last 84 sets of 8-bit low resolution values or 41 sets of 12bit high resolution values. Once the buffer is full, the oldest data is discarded to make room for newer data. Reading from the buffer in this mode will return the most recent data first. Table 23. Selected Buffer Mode 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 44 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 BUF_STATUS_REG1 This register reports the status of the sample buffer. R/W R/W R/W R/W R/W R/W R/W R/W SMP_LEV7 SMP_LEV6 SMP_LEV5 SMP_LEV4 SMP_LEV3 SMP_LEV2 SMP_LEV1 SMP_LEV0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPI Write Address: 0x34h SPI Read Address: 0xB4h SMP_LEV[7:0] Sample Level; reports the number of data bytes that have been stored in the sample buffer. When BUF_RES=1, this count will increase by 6 for each 3-axis sample in the buffer; when BUF_RES=0, the count will increase by 3 for each 3-axis sample. If this register reads 0, no data has been stored in the buffer. BUF_STATUS_REG2 This register reports the status of the sample buffer trigger function. R/W BUF_TRIG Bit7 R/W 0 Bit6 R/W 0 Bit5 R/W 0 Bit4 R/W 0 Bit3 R/W R/W R/W 0 0 0 Bit2 Bit1 Bit0 SPI Write Address: 0x35h SPI Read Address: 0xB5h BUF_TRIG reports the status of the buffer’s trigger function if this mode has been selected. When using trigger mode, a buffer read should only be performed after a trigger event. BUF_CLEAR Latched buffer status information and the entire sample buffer are cleared when any data is written to this register. R/W X Bit7 R/W X Bit6 R/W X Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W X Bit4 R/W X Bit3 R/W R/W R/W X X X Bit2 Bit1 Bit0 SPI Write Address: 0x36h SPI Read Address: 0xB6h © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 45 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 SELF_TEST When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to this register will return the accelerometer to normal operation. R/W 1 Bit7 R/W 1 Bit6 R/W 0 Bit5 R/W 0 Bit4 R/W 1 Bit3 R/W R/W R/W 0 1 0 Bit2 Bit1 Bit0 SPI Write Address: 0x3Ah SPI Read Address: 0xBAh Reset Value 00000000 WUF_THRESH This register sets the acceleration threshold, WUF Threshold that is used to detect a general motion input. WUF_THRESH scales with GSEL1-GSEL0 in CTRL_REG1, and the KXTIA will ship from the factory with this value set to correspond to a change in acceleration of 0.5g when configured to +/8g. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W R/W R/W R/W R/W R/W R/W R/W WUFTH7 WUFTH6 WUFTH5 WUFTH4 WUFTH3 WUFTH2 WUFTH1 WUFTH0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SPI Write Address: 0x5Ah SPI Read Address: 0xDAh Reset Value 00001000 TILT_ANGLE This register sets the tilt angle that is used to detect the transition from Face-up/Face-down states to Screen Rotation states. The KXTIA ships from the factory with tilt angle set to a low threshold of 26° from horizontal. A different default tilt angle can be requested from the factory. Note that the minimum suggested tilt angle is 10°. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W TA7 Bit7 R/W TA6 Bit6 R/W TA5 Bit5 R/W TA4 Bit4 R/W TA3 Bit3 R/W TA2 Bit2 R/W TA1 Bit1 R/W TA0 Bit0 Reset Value 00001100 SPI Write Address: 0x5Ch SPI Read Address: 0xDCh 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 46 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 HYST_SET This register sets the Hysteresis that is placed in between the Screen Rotation states. The KXTIA ships from the factory with HYST_SET set to +/-15° of hysteresis. A different default hysteresis can be requested from the factory. Note that when writing a new value to this register the current values of RES0, RES1 and RES2 must be preserved. These values are set at the factory and must not change. Note that to properly change the value of this register, the PC1 bit in CTRL_REG1 must first be set to “0”. R/W RES2 Bit7 R/W RES1 Bit6 R/W RES0 Bit5 R/W HYST4 Bit4 R/W HYST3 Bit3 R/W HYST2 Bit2 R/W HYST1 Bit1 R/W HYST0 Bit0 Reset Value ---10100 SPI Write Address: 0x6Fh SPI Read Address: 0xEFh BUF_READ Data in the buffer can be read according to the BUF_RES and BUF_M settings in BUF_CTRL2 by executing this command. More samples can be retrieved by continuing to toggle SCL after the read command is executed. Data should only be read by set (6 bytes for high-resolution samples and 3 bytes for low-resolution samples) and by using auto-increment. Additional samples cannot be written to the buffer while data is being read from the buffer using auto-increment mode. Output data is in 2’s Complement format. R/W X Bit7 R/W X Bit6 R/W X Bit5 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com R/W X Bit4 R/W X Bit3 R/W R/W R/W X X X Bit2 Bit1 Bit0 SPI Write Address: 0x7Fh SPI Read Address: 0xFFh © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 47 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 KXTIA Embedded Applications Orientation Detection Feature The orientation detection feature of the KXTIA will report changes in face up, face down, +/- vertical and +/horizontal orientation. This intelligent embedded algorithm considers very important factors that provide accurate orientation detection from low cost tri-axis accelerometers. Factors such as: hysteresis, device orientation angle and delay time are described below as these techniques are utilized inside the KXTIA. Hysteresis A 45° tilt angle threshold seems like a good choice because it is halfway between 0° and 90°. However, a problem arises when the user holds the device near 45°. Slight vibrations, noise and inherent sensor error will cause the acceleration to go above and below the threshold rapidly and randomly, so the screen will quickly flip back and forth between the 0° and the 90° orientations. This problem is avoided in the KXTIA by choosing a 30° threshold angle. With a 30° threshold, the screen will not rotate from 0° to 90° until the device is tilted to 60° (30° from 90°). To rotate back to 0°, the user must tilt back to 30°, thus avoiding the screen flipping problem. This example essentially applies +/- 15° of hysteresis in between the four screen rotation states. Table 24 shows the acceleration limits implemented for  T =30°. Orientation X Acceleration (g) Y Acceleration (g) 0°/360° -0.5 < ax < 0.5 ay > 0.866 90° ax > 0.866 -0.5 < ay < 0.5 180° -0.5 < ax < 0.5 ay < -0.866 270° ax < -0.866 -0.5 < ay < 0.5 Table 24. Acceleration at the four orientations with +/- 15° of hysteresis The KXTIA allows the user to change the amount of hysteresis in between the four screen rotation states. By simply writing to the HYST_SET register, the user can adjust the amount of hysteresis up to +/- 45°. The plot in Figure 9 shows the typical amount of hysteresis applied for a given digital count value of HYST_SET. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 48 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 HYST_SET vs Hysteresis 50 45 Hysteresis (+/- degrees) 40 35 30 25 Hysteresis 20 15 10 5 0 0 5 10 15 20 25 30 HYST_SET Value (Counts) Figure 9. HYST_SET vs Hysteresis Device Orientation Angle (aka Tilt Angle) To ensure that horizontal and vertical device orientation changes are detected, even when it isn’t in the ideal vertical orientation – where the angle θ in Figure 10 is 90°, the KXTIA considers device orientation angle in its algorithm. Angle  Figure 10. Device Orientation Angle As the angle in Figure 2 is decreased, the maximum gravitational acceleration on the X-axis or Y-axis will also decrease. Therefore, when the angle becomes small enough, the user will not be able to make 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 49 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 the screen orientation change. When the device orientation angle approaches 0° (device is flat on a desk or table), ax = ay = 0g, az = +1g, and there is no way to determine which way the screen should be oriented, the internal algorithm determines that the device is in either the face-up or face-down orientation, depending on the sign of the z-axis. The KXTIA will only change the screen orientation when the orientation angle is above the factory-defaulted/user-defined threshold set in the TILT_ANGLE register. Equation 2 can be used to determine what value to write to the TILT_ANGLE register to set the device orientation angle. TILT_ANGLE (counts) = sin θ * (32 (counts/g)) Equation 2. Tilt Angle Threshold Tilt Timer The 8-bit register, TILT_TIMER can be used to qualify changes in orientation. The KXTIA does this by incrementing a counter with a size that is specified by the value in TILT_TIMER for each set of acceleration samples to verify that a change to a new orientation state is maintained. A user defined output data rate (ODR) determines the time period for each sample. Equation 3 shows how to calculate the TILT_TIMER register value for a desired delay time. TILT_TIMER (counts) = Delay Time (sec) x ODR (Hz) Equation 3. Tilt Position Delay Time Motion Interrupt Feature Description The Motion interrupt feature of the KXTIA reports qualified changes in the high-pass filtered acceleration based on the Wake Up (WUF) threshold. If the high-pass filtered acceleration on any axis is greater than the user-defined wake up threshold (WUF_THRESH), the device has transitioned from an inactive state to an active state. When configured in the unlatched mode, the KXTIA will report when the motion event finished and the device has returned to an inactive state. Equation 4 shows how to calculate the WUF_THRESH register value for a desired wake up threshold. Note that this calculation varies based on the configured grange of the part. WUF_THRESH (counts) = Wake Up Threshold (g) x Sensitivity (counts/g) Equation 4. Wake Up Threshold 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 50 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 A WUF (WUF_TIMER) 8-bit raw unsigned value represents a counter that permits the user to qualify each active/inactive state change. Note that each WUF Timer count qualifies 1 (one) user-defined ODR period (OWUF). Equation 5 shows how to calculate the WUF_TIMER register value for a desired wake up delay time. WUF_TIMER (counts) = Wake Up Delay Time (sec) x OWUF (Hz) Equation 5. Wake Up Delay Time Figure 11 below shows the latched response of the motion detection algorithm with WUF Timer = 10 counts. Typical Motion Interrupt Example HPF Acceleration WUF Threshold 0g 10 WUF Timer Ex: Delay Counter = 10 Motion Inactive Figure 11. Latched Motion Interrupt Response Figure 12 below shows the unlatched response of the motion detection algorithm with WUF Timer = 10 counts. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 51 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Typical Motion Interrupt Example HPF Acceleration WUF Threshold 0g 10 WUF Timer Ex: Delay Counter = 10 Motion Inactive Figure 12. Unlatched Motion Interrupt Response 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 52 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Directional Tap Detection Feature Description The Directional Tap Detection feature of the KXTIA recognizes single and double tap inputs and reports the acceleration axis and direction that each tap occurred. Eight performance parameters, as well as a userselectable ODR are used to configure the KXTIA for a desired tap detection response. Performance Index The Directional TapTM detection algorithm uses low and high thresholds to help determine when a tap event has occurred. A tap event is detected when the previously described jerk summation exceeds the low threshold (TDT_L_THRESH) for more than the tap detection low limit, but less than the tap detection high limit as contained in TDT_TAP_TIMER. Samples that exceed the high limit (TDT_H_THRESH) will be ignored. Figure 13 shows an example of a single tap event meeting the performance index criteria. Calculated Performance Index PI 180 : Sampled Data 160 140 jerk (counts) 120 100 80 60 40 20TDT_L_THRESH 0 3.14 3.15 3.16 3.17 3.18 time(sec) 3.19 3.2 3.21 Figure 13. Jerk Summation vs Threshold 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 53 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Single Tap Detection The latency timer (TDT_LATENCY_TIMER) sets the time period that a tap event will only be characterized as a single tap. A second tap has to occur outside of the latency timer. If a second tap occurs inside the latency time, it will be ignored as it occurred too quickly. The single tap will be reported at the end of the TDT_WINDOW_TIMER. Figure 14 shows a single tap event meeting the PI, latency and window requirements. Calculated Performance Index 160 PI 140 TDT_WINDOW_TIMER 120 jerk (counts) 100 TDT_LATENCY_TIMER 80 60 40 TDT_L_THRESH 20 0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 time(sec) 2.8 2.9 3 3.1 Figure 14. Single Directional TapTM Timing 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 54 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Double Tap Detection An event can be characterized as a double tap only if the second tap crosses the performance index (TDT_L_THRESH) outside the TDT_TIMER. This means that the TDT_TIMER determines the minimum time separation that must exist between the two taps of a double tap event. Similar to the single tap, the second tap event must exceed the performance index for the time limit contained in TDT_TAP_TIMER. The double tap will be reported at the end of the second TDT_LATENCY_TIMER. Figure 15 shows a double tap event meeting the PI, latency and window requirements. Calculated Performance Index PI TDT_WINDOW_TIMER 200 150 jerk (counts) TDT_TIMER 100 TDT_LATENCY_TIMER TDT_LATENCY_TIMER 50 TDT_L_THRESH 0 3.1 3.2 3.3 3.4 3.5 time(sec) 3.6 3.7 3.8 3.9 Figure 15. Double Directional TapTM Timing 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 55 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Sample Buffer Feature Description The sample buffer feature of the KXTIA accumulates and outputs acceleration data based on how it is configured. There are 4 buffer modes available, and samples can be accumulated at either low (8-bit) or high (12-bit) resolution. Acceleration data is collected at the ODR specified by OSAA:OSAD in the Output Data Control Register. Each buffer mode accumulates data, reports data, and interacts with status indicators in a slightly different way. FIFO Mode Data Accumulation Sample collection stops when the buffer is full. Data Reporting Data is reported with the oldest byte of the oldest sample first (X_L or X based on resolution). Status Indicators A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 6). BUF_RES=0: SMPX = SMP_LEV[7:0] / 3 – SMP_TH[6:0] BUF_RES=1: SMPX = SMP_LEV[7:0] / 6 – SMP_TH[6:0] Equation 6. Samples Above Sample Threshold Stream Mode Data Accumulation Sample collection continues when the buffer is full; older data is discarded to make room for newer data. Data Reporting Data is reported with the oldest sample first (uses FIFO read pointer). Status Indicators A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 1). 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 56 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications KXTIA-1006 Rev. 4 Dec-2012 Trigger Mode Data Accumulation When a physical interrupt is caused by one of the digital engines, the trigger event is asserted and SMP[6:0] samples prior to the event are retained. Sample collection continues until the buffer is full. Data Reporting Data is reported with the oldest sample first (uses FIFO read pointer). Status Indicators When a physical interrupt occurs and there are at least SMP[6:0] samples in the buffer, BUF_TRIG in BUF_STATUS_REG2 is asserted. FILO Mode Data Accumulation Sample collection continues when the buffer is full; older data is discarded to make room for newer data. Data Reporting Data is reported with the newest byte of the newest sample first (Z_H or Z based on resolution). Status Indicators A watermark interrupt occurs when the number of samples in the buffer reaches the Sample Threshold. The watermark interrupt stays active until the buffer contains less than this number of samples. This can be accomplished through clearing the buffer or explicitly reading greater than SMPX samples (calculated with Equation 1). Buffer Operation The following diagrams illustrate the operation of the buffer conceptually. Actual physical implementation has been abstracted to offer a simplified explanation of how the different buffer modes operate. Figure 1 represents a high-resolution 3-axis sample within the buffer. Figures 2-10 represent a 10-sample version of the buffer (for simplicity), with Sample Threshold set to 8. Regardless of the selected mode, the buffer fills sequentially, one byte at a time. Figure 16 shows one 6-byte data sample. Note the location of the FILO read pointer versus that of the FIFO read pointer. 36 Thornwood Dr. – Ithaca, NY 14850 tel: 607-257-1080 – fax:607-257-1146 www.kionix.com - info@kionix.com © 2011 Kionix – All Rights Reserved 579-4177-1212201147 Page 57 of 63 PART NUMBER: ± 2g / 4g / 8g Tri-axis Digital Accelerometer Specifications buffer write pointer ----> Index 0 1 2 3 4 5 6 Byte X_L X_H Y_L Y_H Z_L Z_H KXTIA-1006 Rev. 4 Dec-2012