XA-SK-SDRAM

XA-SK-SDRAM Slice Card hardware Guide REV A Publication Date: 2012/10/23 XMOS © 2012, All Rights Reserved. XA-SK-SDRAM Slice Card hardware Guide 2/4 Table of Contents 1 Slice Card Overview 1.1 Pack Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Random Access Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Reduced Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 3 3 2 XA-SK-SDRAM Functional Pins 4 REV A 1 Slice Card Overview IN THIS CHAPTER · Pack Contents · Random Access Memory · Reduced Pinout 1.1 Pack Contents · One XA-SK-SDRAM Slice Card 1.2 Random Access Memory This slice provides 8 Megebytes of random access memory via an ISSI 6400 Synchronous DRAM. It is suitable for burst access only, random access is possible but performance will be very significantly degraded. The associated SDRAM Controll xSOFTip component can operate this memory at clock speeds up to 40 MHz, yielding an aggregate performance of 80 MBytes/sec. 1.3 Reduced Pinout The SDRAM slice uses a technique of reusing the same XCore GPIO pins for both Address and Data. This optimisation is made possible tahnks to the soft nature of the associated xSOFTip sdram controller component. In addition, a NOR gate on the slice generates the data strobes (UDQM and LDQM on the memory chip) from CAS# and WE#. These features are described more fully in the SDRAM Controller xSOFTip component documentation. Taken together, these features permit the addition of a high performance SDRAM subsystem to any XCore application using only 20 pins. REV A XA-SK-SDRAM Slice Card hardware Guide 4/4 2 XA-SK-SDRAM Functional Pins This table shows the port mapping for each of the Slice Card Signal IO, and the Slicekit Slot connector pin it is located on. Function STAR TRIANGLE SQUARE PIN Description SD_WE SD_CAS SD_RAS SD_CLK SD_ADQ0 SD_ADQ1 SD_ADQ2 SD_ADQ3 SD_ADQ4 SD_ADQ5 SD_ADQ6 SD_ADQ7 SD_ADQ8 SD_ADQ9 SD_ADQ10 SD_ADQ11 SD_ADQ12 SD_DQ13/BA0 SD_DQ14/BA1 SD_DQ15 1C 1B 1G 1F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 1K 1J 1I 1L B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 1C 1B 1G 1F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 B10 A8 B15 A15 B6 B7 B9 B11 A9 A11 A6 A7 B12 B13 B17 B18 A17 A18 A12 A13 SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Write Enable CAS RAS Clock drivern from XCore Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Address and Data Bank Address and Data Bank Address and Data Data Copyright © 2012, All Rights Reserved. Xmos Ltd. is the owner or licensee of this design, code, or Information (collectively, the “Information”) and is providing it to you “AS IS” with no warranty of any kind, express or implied and shall have no liability in relation to its use. Xmos Ltd. makes no representation that the Information, or any particular implementation thereof, is or will be free from any claims of infringement and again, shall have no liability in relation to any such claims. XMOS and the XMOS logo are registered trademarks of Xmos Ltd. in the United Kingdom and other countries, and may not be used without written permission. All other trademarks are property of their respective owners. Where those designations appear in this book, and XMOS was aware of a trademark claim, the designations have been printed with initial capital letters or in all capitals. REV A