AS2702-20T

A S2702 AS-Interface Slave IC D ATA SHEET G eneral Description A S2702 (SAP4.1) is a new generation AS-Interface slave device, which supports AS-Interface bus systems with up to 62 slave modules. Each slave module is equipped with an AS2702 device, which interfaces the module to the unshielded 2-wire ASInterface bus for serial bidirectional data communication and power extraction. Data communication over the AS-Interface takes place in master slave fashion, which foresees that all slave devices AS2702 connected to the bus are sequentially and cyclicly addressed by a single, central master unit. Data on the ASInterface bus are Manchester encoded and can be found as sin2-pulses with a Vpp of between 3V and 8V on top of the bus’ dc voltage of nominally 30V. AS2702 regulates the nominal dc bus voltage of 30V i nternally d own to 5V to supply it’s internal circuitry including a 16 x 8 bits EEPROM, as well as down to a nominal supply level 24V with a max. loading of 35mA for the actuators and sensors connected to it at the field side. Each slave device AS2702 may interface to up to 4 sensors or 3 actuators. An AS-Interface bus system based on AS2702 may hence link as many as 248 sensors and 186 actuators to a single master unit. Slave device AS2702 (SAP4.1) is system compatible with predecessor device AS2701A (ISA3+): slave modules equipped with AS2702 (SAP4.1) will run in existing AS-Interface bus systems based on AS2701A (ISA3+). The AS-Interface concept is well established as a standardized digital bus system for industrial automation. K ey Features • • I nterface device to connect actuators and sensors to an AS-Interface bus F lexible system solution offering 2 package options: SOIC 20 for full functionality; SOIC 16 for applications not requiring the parameter port D C power extraction from the AS-Interface bus S erial bidir. data communication with the bus D ata communication watchdog 4 -bit bidir. data port plus strobe to poll the sensors and control the actuators connected 4 -bit parameter port plus strobe to provide settings to the sensors and actuators 2 4V power supply for the sensors and actuators P eriphery fault input to signal hardware failure of the sensors and actuators I ntegrated 16 x 8 bit EEPROM to store (5 + 1)-bit slave address and settings 2 L ED outputs to optically flag slave unit operation status O perating temperature Ta: - 25°C … + 85°C O perating supply voltage/bus DC voltage: typ. 30V O perating current (Osc. on, outputs idle): ≤ 6 mA • S upply for sensors/actuators: typ. 24V, ≤ 3 5mA • • • • • • • • • • • • R evision 1.3, 21-Aug-08 Page 1 of 13 A S2702 – AS-Interface Slave IC B lock Diagram CDC LTGP VLTGP-6V + THERMODETECTOR UOUT U5R U5R U5R U5R OSC1 OSCILLATOR OSC2 RECEIVE TRANSMIT JABBER INHIBIT RESET threshold 11 U5R IMP_POS IMP_NEG LTGN LOGIC BLOCK POR BANDGAP + - U5R 16 x 8 BIT SERIAL E2PROM PFAULT D0...D3 LED2 LED1 SDA SCL 4 4 P0...P3 DSTBn PSTBn TRIMMING F igure 1 Block diagram P in Assignment and Description S OIC 20 P in No. 1 2 3 4 5 6 7 8 9 10 11 12 13 S OIC 16 P in No. 1 2 3 4 5 6 7 8 9 10 11 P1 P0 D1 D0 D STBn L ED1 O SC2 O SC1 U 5R LTGN LTGP CDC UOUT I/O, digital, pull-up 1 , 2 I/O, digital, pull-up 1 , 2 I/O, digital I/O, digital I/O, digital, pull-up 1 I/O, digital, pull-up 1 O, analog I, analog O, power I, power I, power I/O, analog O, power Bidir. parameter port bit 1 Bidir. parameter port bit 0 Bidir. data port bit 1 Bidir. data port bit 0 D ata port strobe output; reset-input L ED output 1 (IC test input) Output to quartz crystal Input from quartz crystal Nom. 5V power supply output Neg. supply pin, connected to neg. AS-Interface bus line, ground reference Pos. supply pin, connected to pos. AS-Interface bus line Pin for ext. buffer capacitor Nom. 24V power supply output N ame T ype N ote D escription Revision 1.3, 21-Aug-08 Page 2 of 13 A S2702 – AS-Interface Slave IC S OIC 20 14 15 16 17 18 19 20 S OIC 16 12 13 14 15 16 - N ame PFAULT LED2 PSTBn D3 D2 P3 P2 T ype I, digital, pull-up N ote 1 D escription Low-active input to flag failure of the sensors/actuators circuitry connected L ED output 2 (IC test input) P arameter port strobe output (IC test input) Bidir. data port bit 3 Bidir. data port bit 2 Bidir. parameter port bit 3 Bidir. parameter port bit 2 I/O, digital, pull-up 1 I/O, digital, pull-up 1 I/O, digital I/O, digital I/O, digital, pull-up 1 , 2 I/O, digital, pull-up 1 , 2 N otes: 1 T he pull-up structure is a passive high-side current source with a nom. 10µA current. 2 T he passive pull-up current source as per note 1 on these parameter port pins is off, if the slave device is programmed with I/O-configuration code 7 and a master data call is present. F unctional, Electrical and Timing Characteristics A ll voltages are referenced to ground pin LTGN. Timing is valid for a quartz crystal frequency of 5.333MHz. A bsolute Maximum Ratings S ymbol V LTGP V CDC V U5R I IN E SD1 E SD2 T stg T body P tot R THJA R THJA P arameter Voltage at the positive supply pin Voltage at pin for ext. buffer capacitor Voltage at pins U5R, OSC1, OSC2 Input current at any pin, except for LTGP, CDC Electrostatic discharge voltage Electrostatic discharge voltage Storage temperature Soldering conditions Max. power dissipation Thermal resistance SOIC 16 Thermal resistance SOIC 20 61.2 58.5 M in -0.3 -0.3 -0.3 -50 1500 300 -55 125 260 1 74.8 71.5 M ax 40 VLTGP + 0.3V 7 50 U nit V V V mA V V V °C W °K/W °K/W 5) 6) 7) 7) 2) 3) 4) N ote 1) N otes: 1) 5 0V during t > 50µs; repetition rate < 0.5Hz 2) L atch-up immunity test. Please observe max. power dissipation allowed 3) H uman body model: R = 1.5kOhm; C = 100pF 4) M achine model; applies only for LTGP 5) T he reflow peak soldering temperature (body temperature) is specified according IPC/JEDEC J-STD-020C. 6) F ree convection, see Figure 2 7) N o forced cooling. PCB-surface: 21 cm 2 ; still air volume around the device. 10 cm 3 Revision 1.3, 21-Aug-08 Page 3 of 13 A S2702 – AS-Interface Slave IC Pv/ W 1 Pv/ W 1 0.5 0.5 50 100 t/ °C 50 100 t/ °C SOIC16 F igure 2 Max. acceptable power dissipation relative to ambient temperature SOIC20 R ecommended Operating Conditions S ymbol V LTGP I LTG OA FC P arameter Positive supply voltage/dc portion Supply current consumption Ambient temperature Quartz frequency S ensitivity against moisture - 25 25 5.333333 M in 22.5 N om M ax 34 6 85 U nit V mA °C MHz N ote 1 2 3 4 5 N otes: 1 F alse-poling protection diode to be inserted between pos. AS-Interface bus line and LTGP-pin. LTGP-pin to be protected furthermore with a voltage clamp between LTGP and LTGN. 2 O scillator on; data transmission stage off; no loads connected 3 P ower dissipation restrictions as per Figure 2 to be observed 4 A S-Interface Quartz 5 L evel 5 acc. to JEDEC-standard JESD22-A112 S upply Pin LTGP P ositive supply pin connected to positive AS-Interface bus line and clamped relative to neg. supply pin/ground LTGN as described under Recommended Operating Conditions. VLTGP and ILTG specified under Recommended Operating Conditions as well. S ymbol V SIG Z P arameter VPP of sin2-data-pulses on top of dc supply voltage I nput impedance between 50kHz and 300kHz 18 50 M in 3 N om M ax 8 40 U nit V pF kOhm mH CCDC = 100nF N ote Revision 1.3, 21-Aug-08 Page 4 of 13 A S2702 – AS-Interface Slave IC B uffer Pin CDC A n external buffer capacitor with a recommended value of 100nF should be connected to this pin to ensure a sufficiently high input impedance Z at power supply pin LTGP. Voltage at this pin can be as high as VLTGP. N om. 24V Power Supply Output UOUT T he supply output voltage at UOUT is directly derived from VLTGP and regulated to a level with an offset of about -6V relative to VLTGP. UOUT provides bias to the sensors and actuators circuitry connected to the slave device as well as to the LEDs connected to outputs LED1 and LED2. UOUT is equipped with a thermal overload protection, which foresees that VUOUT is switched off as soon as the slave device’s substrate temperature TJ passes a threshold value in the range of (155 ± 20)°C. After TJ has come down and has passed a temperature threshold about (15 ± 5)°C lower than (155 ± 20)°C and after a consecutive minimum delay time of 1s has elapsed, VUOUT is switched on again. S ymbol V UOUT I UOUT P arameter Power supply output voltage Load current 9.5 10 b elow which data transmission is inhibited C UOUT Buffer capacitor µF 2 M in VLTGP - 6.3V M ax VLTGP - 5.3V 50 10.5 U nit V mA V 1 N ote V COMOFF UOUT voltage level N otes: 1 I n case IUOUT >40mA and presence of sin2-data pulses on LTGP with VSIG >3V, VUOUT may drop as much as 1V below it’s level in unloaded condition 2 E lectrolytic and rf filter capacitor in parallel N om. 5V Power Supply Output U5R T he voltage at U5R is derived from the voltage present at UOUT, as long as UOUT is not switched off due to overload. In the latter case U5R is derived from an alternative voltage out of the UOUT voltage regulator, which is more or less similar to VUOUT in non switched off condition of UOUT. As a result VU5R is not affected by overload condition at UOUT and will remain. S ymbol V U5R I U5R C U5R P arameter Power supply output voltage Load current Buffer capacitor 470 M in 4.85 M ax 5.15 1 U nit V mA nF O scillator Pins OSC1 and OSC2 T he only component to be connected to these pins is a quartz crystal with a resonance frequency of 5.333333 MHz (AS-Interface quartz crystal). S ymbol C X2 P arameter Stray capacitance M in M ax 10 U nit pF Revision 1.3, 21-Aug-08 Page 5 of 13 A S2702 – AS-Interface Slave IC D ata Port Pins D3, …, D0 and Data Strobe Pin DSTBn B asically data port D3, …, D0 is designed for bidirectional data transfer out of and into the slave device. Each data port pin is equipped with both a low-side open-drain output stage as well as an input stage to this purpose. Depending on the so-called IO-configuration code, written and stored in the slave device, each data port pin is individually set to behave as • o utput, or • o utput/input, or • i nput. The timing of the data transfer is presented in Figure 3. Strobe signal DSTBn flags and governs the data transfer as follows: a) d ata port pin is set ‘output’: output data become valid upon the HL-edge of the strobe and will remain so until the next HL-edge, hence during the entire strobe cycle; b) d ata port pin is set ‘output/input’: output data become valid upon the HL-edge of the strobe and will remain so until it’s LH-edge; input data to be valid within a specific time window relative to the HL-edge, after completion of the strobe’s L-phase; c) d ata port pin is set ‘input’: input data to be valid within a specific time window relative to the HL-edge of the strobe, after completion of the strobe’s L-phase. If necessary, output data as per a) and b) can be easily latched with the LH-edge of strobe DSTBn as they will remain valid for about 0.4µs beyond as a minimum. Care must be taken however, that signal delay added by external circuitry is lower for the strobe than for the data. Dx t Dx t Data out DSTBn Data in + 0.4 µs STB Data out t DSTBn Data in + tOUTOFF DSTBn t DSTBn t INPmin t INPmax F igure 3 Timing of data transfer at data port D3, …, D0 relative to strobe DSTBn T he following table specifies the timing parameters relating to Figure 3: S ymbol t STB t DSTBn t OUTOFF t INP P arameter Delay DSTBn HL-edge to Dx output data valid DSTBn strobe width Delay DSTBn LH-edge to Dx output off Input data valid time window 6 0.2 10.5 M in M ax 1.5 6.8 1 12.5 U nit µs µs µs µs 1 2 3 N ote Revision 1.3, 21-Aug-08 Page 6 of 13 A S2702 – AS-Interface Slave IC N otes: 1 P ulse width depends substantially on value of external pull-up resistor 2 A pplies only to data port pins set to 'output/input' operation 3 T iming reference is DSTBn HL-edge. Applies only to data port pins set to either 'output/input' or 'input' operation The dc-parameters of the data port pins D3, …, D0 are specified as follows: S ymbol I OUTLO I OUTHI V SCHLT V IN P arameter Sink current @ output L Leakage current @ output off Input threshold voltage Acceptable input voltage @ output off M in 10 -1 2.5 -0.3 1 3.5 40 M ax U nit mA µA V V N ote VOUT = 1V 1 2 N otes: 1 O utput stage is low-side open-drain; ext. pull-up resistor required as no pull-up structure on chip 2 N o hysteresis implemented T o govern the data transfer at data port D3, …,D0 strobe pin DSTBn is equipped with a low-side open-drain output switch plus a passive high-side current source with a nom. 10µA pull-up current capability. However a second function is assigned to the DSTBn pin which requires it to be input as well: if a low-pulse is imposed on DSTBn by external means with a pulse width of at least 50 to 100ms, the slave device will be put in RESET condition, as described in section “Reset”. The dc-and timing parameters of strobe pin DSTBn are specified as follows: S ymbol I OUTLO I OUTHI I INLO V SCHLT V IN t NORESET t RESET C PINEXT P arameter Sink current @ output L Leakage current @ output off Input current @ VIN = 1V Input threshold voltage Acceptable input voltage @ output off DSTBn L-phase width, not triggering RESET DSTBn L-phase width, triggering RESET Max. stray capacity 100 20 M in 10 -10 -5 1.5 -0.3 10 -20 3.5 40 50 M ax U nit mA µA µA V V ms ms pF N ote VOUT = 1V VOUT = 5V 1 2 N otes: 1 D STBn is equipped with an on-chip pull-up current source, which ensures a sufficiently fast LH-edge upon output switch-off in open-pin condition, to prevent erroneous RESET triggering. If DSTBn has an external load connected to it, an additional external pull-up resistor may be needed to prevent erroneous RESET triggering upon output switch-off. 2 N o hysteresis implemented P arameter Port Pins P3, …, P0 and Parameter Strobe Pin PSTBn ( Note that parameter port pins P3, …, P0 are only available on AS2702 package option SOIC 20, not on the SOIC 16 option.) The transfer of data at P3, …, P0 and the supporting strobe action at pin PSTBn takes place similarly as at D3, …, D0 resp. DSTBn. Each parameter port pin P3, …, P0 is equipped with both a low-side open-drain output switch plus a passive, but switchable highside current source with a nom. 10 µA pull-up current capability, and with an input stage. Though equipped for bidirectional data transfer as D3, …, D0, the parameter port is nevertheless less flexible than the data port. Basically the parameter port is set to behave portwise as Revision 1.3, 21-Aug-08 Page 7 of 13 A S2702 – AS-Interface Slave IC • o utput, or • i nput depending on the IO-configuration code, written and stored in the slave device. The timing of the data transfer is presented in Figure 4. Strobe signal PSTBn flags and governs the data transfer as follows: a) p arameter port is set ‘output’: output data become valid upon the HL-edge of the strobe and will remain so until the next HL-edge, hence during the entire strobe cycle; b) parameter port is set ‘input’: input data to be valid within a specific time window relative to the HL-edge of the strobe, after completion of the strobe’s Lphase. Output data as per a) could be easily latched with the LH-edge of strobe PSTBn, if at all necessary. Px t STB Parameter out Parameter out Px t PSTBn t PSTBn PSTBn Data in + tOUTOFF t INPmin t INPmax F igure 4 Timing of data transfer at parameter port P3, …, P0 relative to strobe PSTBn T he following table specifies the timing parameters relating to Figure 4: S ymbol t STB t PSTBn t INP P arameter Delay PSTBn HL-edge to Px output data valid PSTBn strobe width Input data valid time window 6 10.5 M in M ax 1.5 6.8 12.5 U nit µs µs µs 1 2 N ote N otes: 1 P ulse width depends substantially on value of external pull-up resistor 2 T iming reference is PSTBn HL-edge. Applies only to parameter port set to 'input' operation The dc-parameters of the parameter port pins P3, …, P0 are specified as follows: S ymbol I OUTLO I OUTHI I OUTHI7 I INLO P arameter Sink current @ output L Leakage current @ output off Leakage current @ output off; pull-up current source off Input current @ VIN = 1V M in 10 -10 -1 -5 10 1 -20 M ax U nit N ote mA µA µA µA VOUT = 1V VOUT = 5V VOUT = 5V; IO-conf. = 7 1 Revision 1.3, 21-Aug-08 Page 8 of 13 A S2702 – AS-Interface Slave IC S ymbol V SCHLT V IN P arameter Input threshold voltage Acceptable input voltage @ output off M in 2.5 -0.3 M ax 3.5 40 U nit N ote V V 2 N otes: 1 T he passive high-side current-source provides an about constant input current @ 0V