LP3983SAB5F-08

Preliminary Datasheet LP3983S 300mA,Ultra-low noise, Small Package Ultra-Fast CMOS LDO Regulator General Description Features The LP3983S is designed for portable RF and wireless  Ultra-Low-Noise for RF Application applications with demanding performance and space  2V- 6V Input Voltage Range requirements. The LP3983S performance is optimized  Low Dropout : 210mV @ 300mA  300mA Output Current, 550mA Peak Current  High PSRR: -70dB at 217Hz  < 0.1uA Standby Current When Shutdown  Available in SOT23-5 Package  Current Limiting and Thermal Shutdown for battery-powered systems to deliver ultra low noise and low quiescent current. A noise bypass pin is available for further reduction of output noise. Regulator ground current increases only slightly in dropout, further prolonging the battery life. The Protection LP3983S also works with low-ESR ceramic capacitors, reducing the amount of board space necessary for power applications, critical in hand-held wireless devices. The LP3983S consumes less than 0.01µA in shutdown mode and has fast turn-on time less than 50µs. The other features include ultra low dropout voltage, high output accuracy, current limiting Applications  Portable Media Players/MP3 players  Cellular and Smart mobile phone  LCD  DSC Sensor  Wireless Card protection, and high ripple rejection ratio. It is available in SOT23-5 packages. Typical Application Circuit Vin Vout 1 Order Information LP3983S □ □ □ VIN 2.2uF OUT 5 22pF (Option) □ - □ □ FB Voltage Chip Enable 3 EN 08: 0.8V ADJ GND R1 4 2 R2 F: Pb-Free Package Type Marking Information B5: SOT23-5 Device Marking Package Shipping LP3983SAB5F-08 LPS SOT23-5 3K/REEL Output Type A：Adjustable 1FYWX Marking indication: Y:Production year W:Production week X:Production batch LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 1 of 8 2.2uF Preliminary Datasheet LP3983S Functional Pin Description Package Type Pin Configurations EN GND 3 2 VIN 1 (MARKING) SOT23-5 4 5 ADJ VOUT SOT23-5 Pin Description Pin Name 1 VIN Power Input Voltage. 2 GND Ground. 3 EN 4 ADJ 5 VOUT LP3983S-07 May.-2018 Description Chip Enable (Active High). There is an integrated pull low 1MΩ resistor connected to GND when the control signal is floating. Adjustable pin. Output Voltage. Vout=VFB ×（1+R1/R2） Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 2 of 8 Preliminary Datasheet LP3983S Function Diagram Absolute Maximum Ratings  Supply Input Voltage -------------------------------------------------------------------------------------------------------- 7V  EN Pin Voltage -------------------------------------------------------------------------------------------- -0.3V to Vin+0.3V Power Dissipation, PD @ TA = 25°C  Maximum Power Dissipation ( PD,TA=25°C) --------------------------------------------------------------------- 0.5W Package Thermal Resistance  Thermal Resistance (JA) ------------------------------------------------------------------------------------------- 195℃/W  Thermal Resistance (JC) --------------------------------------------------------------------------------------------- 60℃/W  Maximum Junction Temperature ----------------------------------------------------------------------------------- 150°C  Maximum Soldering Temperature (at leads, 10 sec) -------------------------------------------------------- 260°C  Storage Temperature Range --------------------------------------------------------------------------- −65°C to 165°C ESD Susceptibility  HBM (Human Body Mode) ------------------------------------------------------------------------------------------------ 2kV  MM(Machine-Mode) ------------------------------------------------------------------------------------------------------ 200V Recommended Operating Conditions  Supply Input Voltage ------------------------------------------------------------------------------------------------ 2V to 6V  Operation Junction Temperature Range ------------------------------------------------------------ −40°C to 125°C  Operation Ambient Temperature Range -------------------------------------------------------------- −40°C to 85°C LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 3 of 8 Preliminary Datasheet LP3983S Electrical Characteristics (VIN = VOUT + 1V, CIN = COUT =2.2µF, CFB = 22pF, TA = 25° C, unless otherwise specified) Parameter Symbol Test Conditions Min Output Loading Current ILOAD VEN=VIN,VIN>2.5V 300 Current Limit ILIM RLOAD = 1Ω VFB IOUT=1mA Quiescent Current IQ Dropout Voltage VDROP Line Regulation ΔVLINE Load Regulation ΔVLOAD 1mA < IOUT < 300mA Standby Current ISTBY VEN = GND, Shutdown 0.1 EN Input Bias Current IIBSD VEN = GND or VIN 5 VIL VIN=3V to 5.5V, Shutdown VIH VIN=3V to 5.5V, Start-Up Adjustable voltage reference Logic-Low EN Voltage Threshold Logic-High Voltage Power Supply f = 217Hz Rejection Rate f = 1kHz Thermal Shutdown Temperature LP3983S-07 May.-2018 mA 550 0.784 Units mA 0.816 V VEN ≥ 1.2V, IOUT = 0mA 100 130 μA IOUT = 200mA, VOUT > 2.8V 140 180 mV IOUT = 300mA, VOUT > 2.8V 210 270 mV 0.2 % 2 % 1 μA VIN = (VOUT + 1V) to 5.5V, IOUT = 1mA COUT=1µF PSRR Max 0.8 10Hz to 100kHz, IOUT=200mA Output Noise Voltage Typ IOUT = 100mA TSD Email: marketing@lowpowersemi.com uA 0.4 VIN+ 1.4 0.3 V V 300 uVRMS −70 dB −58 dB 150 °C www.lowpowersemi.com Page 4 of 8 Preliminary Datasheet LP3983S Typical Operating Characteristics LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 5 of 8 Preliminary Datasheet LP3983S Applications Information Like any low-dropout regulator, the external Start-up Function Enable Function capacitors used with the LP3983S must be carefully selected for regulator stability and performance. Using a capacitor whose value is >1µF on the LP3983S input and the amount of capacitance can be increased without limit. The input capacitor must be located a distance of not more than 0.5 inch from the input pin of the IC and returned to a clean analog ground. Any good quality ceramic or tantalum can be used for this capacitor. The capacitor with larger value and lower ESR (equivalent series resistance) provides better PSRR and line-transient response. The output capacitor must meet both requirements for minimum amount of capacitance and ESR in all LDOs application. The LP3983S is designed specifically to work with low ESR ceramic output capacitor in space-saving and performance consideration. Using a ceramic capacitor whose value is at least 1µF with ESR is > 25mΩ on the LP3983S output ensures stability. The LP3983S still works well with output capacitor of other types due to the wide stable ESR range. Output capacitor of The LP3983S features an LDO regulator enable/disable function. To assure the LDO regulator will switch on, the EN turn on control level must be greater than 1.4 volts. The LDO regulator will go into the shutdown mode when the voltage on the EN pin falls below 0.4 volts. For to protecting the system, the LP3983S have a quick-discharge function. If the enable function is not needed in a specific application, it may be tied to VIN to keep the LDO regulator in a continuously on state. Feedback Capacitor larger capacitance can reduce noise and improve For adjustable version, connecting a 22pF between load transient response, stability, and PSRR. The output pin and FB pin significantly reduces output output capacitor should be located not more than 0.5 voltage ripple, it is critical that the capacitor inch from the VOUT pin of the LP3983S and returned connection should be direct and PCB traces should to a clean analog ground. be as short as possible. The output voltage of LDO could be set by the formula below: Vout=VFB ×（1+R1/R2） Considering the practical application, we may add a small capacitor with R1 in parallel which could be 22pF or 47pF. LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 6 of 8 Preliminary Datasheet LP3983S Thermal Considerations Thermal protection limits power dissipation in LP3983S. When the operation junction temperature exceeds 150°C, the OTP circuit starts the thermal shutdown function turn the pass element off. The pass element turns on again after the junction temperature cools by 25°C. For continue operation, do not exceed absolute maximum operation junction temperature 125°C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the surroundings airflow and difference between junction to temperature ambient. and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of LP3983S, where TJ(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The dependent) for SOT23-5 package is 195°C/W. PD = (VIN−VOUT) x IOUT + VIN x IQ of temperature 125°C, TA is the ambient temperature junction to ambient thermal resistance (θ JA is layout The power dissipation definition in device is: rate Where TJ(MAX) is the maximum operation junction The PD(MAX) = (125°C−25°C) /195 = 500mW The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. maximum power dissipation can be calculated by following formula: PD(MAX) = ( TJ(MAX) − TA ) /θJA LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 7 of 8 Preliminary Datasheet LP3983S Packaging Information SOT23-5 LP3983S-07 May.-2018 Email: marketing@lowpowersemi.com www.lowpowersemi.com Page 8 of 8