ES8336

ES8336 FEATURES Low Power Audio CODEC DAC System • • • • • • • High performance and low power multibit delta-sigma audio ADC and DAC I2S/PCM master or slave serial data port Two pairs of analog input with differential input option 256/384Fs and USB 12/24 MHz system clocks I2C interface • • • Low Power • • ADC • • • • • • 24-bit, 8 to 96 kHz sampling frequency 93 dB signal to noise ratio, -85 dB THD+N Ground centered headphone driver Headphone and external mic detection Pop and click noise suppression 24-bit, 8 to 96 kHz sampling frequency 92 dB signal to noise ratio, -85 dB THD+N Low noise pre-amplifier Auto level control (ALC) and noise gate Mic bias Support digital mic 1.8V to 3.3V operation 7 mW playback; 16 mW playback and record APPLICATIONS • • • MID/Tablet Wireless audio Portable audio ORDERING INFORMATION ES8336 -40°C ~ +85°C QFN-32 1 Everest Semiconductor 1. 2. 3. 4. 5. 6. 7. Confidential ES8336 BLOCK DIAGRAM ................................................................................................................... 5 PIN OUT AND DESCRIPTION ................................................................................................ 6 TYPICAL APPLICATION CIRCUIT.......................................................................................... 7 CLOCK MODES AND SAMPLING FREQUENCIES ............................................................... 8 MICRO-CONTROLLER CONFIGURATION INTERFACE ...................................................... 8 DIGITAL AUDIO INTERFACE.................................................................................................. 9 ELECTRICAL CHARACTERISTICS ..................................................................................... 10 ABSOLUTE MAXIMUM RATINGS................................................................................................ 10 RECOMMENDED OPERATING CONDITIONS .............................................................................. 10 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 11 DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS ........................................ 11 POWER CONSUMPTION CHARACTERISTICS .............................................................................. 12 SERIAL AUDIO PORT SWITCHING SPECIFICATIONS ................................................................... 12 I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) ........................... 13 8. CONFIGURATION REGISTER DEFINITION ........................................................................ 14 REGISTER 0X00 – RESET, DEFAULT 0X03 ................................................................................... 14 REGISTER 0X01 – CLOCK MANAGER, DEFAULT 0X03 ................................................................ 14 REGISTER 0X02 – CLOCK MANAGER, DEFAULT 0X00 ................................................................ 15 REGISTER 0X03 – CLOCK MANAGER, DEFAULT 0X20 ................................................................ 15 REGISTER 0X04 – CLOCK MANAGER, DEFAULT 0X11 ................................................................ 15 REGISTER 0X05 – CLOCK MANAGER, DEFAULT 0X00 ................................................................ 15 REGISTER 0X06 – CLOCK MANAGER, DEFAULT 0X11 ................................................................ 15 REGISTER 0X07 – CLOCK MANAGER, DEFAULT 0X00 ................................................................ 15 REGISTER 0X08 – CLOCK MANAGER, DEFAULT 0X00 ................................................................ 16 REGISTER 0X09 – SERIAL DATA PORT, DEFAULT 0X01 .............................................................. 16 REGISTER 0X0A – SERIAL DATA PORT, DEFAULT 0X00 .............................................................. 16 REGISTER 0X0B – SERIAL DATA PORT, DEFAULT 0X00 .............................................................. 17 REGISTER 0X0C – SYSTEM, DEFAULT 0XF8 ................................................................................ 17 REGISTER 0X0D – SYSTEM, DEFAULT 0X3F ................................................................................ 17 REGISTER 0X0E – SYSTEM, DEFAULT 0X00 ................................................................................ 17 REGISTER 0X0F – SYSTEM, DEFAULT 0X00 ................................................................................ 18 REGISTER 0X10 – SYSTEM, DEFAULT 0X01 ................................................................................ 18 REGISTER 0X11 – SYSTEM, DEFAULT 0XFC ................................................................................ 18 REGISTER 0X12 – SYSTEM, DEFAULT 0X28 ................................................................................ 18 Revision 3.0 2 February 2021 Everest Semiconductor Confidential ES8336 REGISTER 0X14 – HEADPHONE MIXER, DEFAULT 0X00............................................................. 18 REGISTER 0X15 – HEADPHONE MIXER, DEFAULT 0X33............................................................. 19 REGISTER 0X16 – HEADPHONE MIXER, DEFAULT 0X00............................................................. 19 REGISTER 0X17 – HEADPHONE, DEFAULT 0X00 ........................................................................ 19 REGISTER 0X18 – HEADPHON , DEFAULT 0X88 ......................................................................... 19 REGISTER 0X19 – HEADPHONE, DEFAULT 0X06 ........................................................................ 20 REGISTER 0X1A – HEADPHONE, DEFAULT 0X22 ........................................................................ 20 REGISTER 0X1B – HEADPHONE, DEFAULT 0X03 ........................................................................ 20 REGISTER 0X1C – CALIBRATION, DEFAULT 0X0F ....................................................................... 21 REGISTER 0X1D – CALIBRATION, DEFAULT 0X00 ....................................................................... 21 REGISTER 0X1E – CALIBRATION, DEFAULT 0X80 ....................................................................... 21 REGISTER 0X1F – CALIBRATION, DEFAULT 0X80 ....................................................................... 21 REGISTER 0X20 – CALIBRATION, DEFAULT 0X00 ....................................................................... 21 REGISTER 0X21 – CALIBRATION, DEFAULT 0X00 ....................................................................... 22 REGISTER 0X22 – ADC, DEFAULT 0XC0 ...................................................................................... 22 REGISTER 0X23 – ADC, DEFAULT 0X00 ...................................................................................... 22 REGISTER 0X24 – ADC, DEFAULT 0X01 ...................................................................................... 22 REGISTER 0X25 – ADC, DEFAULT 0X08 ...................................................................................... 22 REGISTER 0X26 – ADC, DEFAULT 0X10 ...................................................................................... 23 REGISTER 0X27 – ADC, DEFAULT 0XC0 ...................................................................................... 23 REGISTER 0X29 – ADC, DEFAULT 0X1C ...................................................................................... 23 REGISTER 0X2A – ADC, DEFAULT 0X00 ...................................................................................... 24 REGISTER 0X2B – ADC, DEFAULT 0XB0 ...................................................................................... 24 REGISTER 0X2C – ADC, DEFAULT 0X32 ...................................................................................... 25 REGISTER 0X2D – ADC, DEFAULT 0X03 ...................................................................................... 25 REGISTER 0X2E – ADC, DEFAULT 0X00 ...................................................................................... 25 REGISTER 0X2F – DAC, DEFAULT 0X11 ...................................................................................... 25 REGISTER 0X30 – DAC, DEFAULT 0X10 ...................................................................................... 26 REGISTER 0X31 – DAC, DEFAULT 0X00 ...................................................................................... 26 REGISTER 0X32– DAC, DEFAULT 0X00 ....................................................................................... 26 REGISTER 0X33 – DAC, DEFAULT 0XC0 ...................................................................................... 27 REGISTER 0X34 – DAC, DEFAULT 0XC0 ...................................................................................... 27 Revision 3.0 3 February 2021 Everest Semiconductor Confidential ES8336 REGISTER 0X4D – GPIO, DEFAULT 0X00 .................................................................................... 27 REGISTER 0X4E – GPIO, DEFAULT 0X00 ..................................................................................... 27 REGISTER 0X4F – FLAG, DEFAULT 0X00 ..................................................................................... 28 9. PACKAGE (UNIT: MM) .......................................................................................................... 29 10. CORPORATE INFORMATION .......................................................................................... 30 Revision 3.0 4 February 2021 Everest Semiconductor Confidential ES8336 1. BLOCK DIAGRAM RIN1 RIN2 I S/PCM ADC ALC DAC PEQ DAC SE 2 Stereo DAC LOUT HP Driver ROUT Analog Reference Power Supply DVDD PVDD DGND AVDD AGND CPVDD CPGND CPTOP CPBOT CPVSSP CPGNDREF MICBIAS Revision 3.0 Charge Pump GPIO ADCVREF DACVREF VMID Mic Bias Mono ADC DSDIN ASDOUT SCLK DLRCK PGA 2 IC GPIO1 GPIO2 GPIO3 LIN2 LIN1 CDATA CCLK CE MCLK Clock Mgr 5 February 2021 Everest Semiconductor Confidential ES8336 2. PIN OUT AND DESCRIPTION VMID MICBIAS RIN2 LIN2 RIN1 LIN1 CE CDATA 25 26 27 28 29 30 31 32 CCLK MCLK DVDD PVDD DGND SCLK DSDIN DLRCK 1 2 3 4 5 6 7 8 ES8336 24 23 22 21 20 19 18 17 ADCVREF AGND AVDD DACVREF LOUT ROUT CPGNDREF CPGND 16 15 14 13 12 11 10 9 CPBOT CPTOP CPVDD CPVSSP GPIO3 GPIO2 GPIO1 ASDOUT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Revision 3.0 NAME CCLK MCLK DVDD PVDD DGND SCLK DSDIN DLRCK ASDOUT GPIO1 GPIO2 GPIO3 CPVSSP CPVDD CPTOP CPBOT CPGND CPGNDREF ROUT LOUT DACVREF AVDD AGND ADCVREF VMID MICBIAS RIN2 LIN2 RIN1 LIN1 CE CDATA I/O I I Supply Supply Supply I/O I I/O O I/O I/O I/O O O O Supply Supply O O O I I I I I I/O DESCRIPTION I2C clock input Master clock Digital core supply Digital IO supply Digital ground Audio data bit clock DAC audio data DAC audio data left and right clock ADC audio data General purpose IO General purpose IO General purpose IO Charge pump filtering Charge pump power supply Charge pump capacitor top Charge pump capacitor bottom Charge pump ground Charge pump filtering Right analog output Left analog output Decoupling capacitor Analog supply Analog ground Decoupling capacitor Decoupling capacitor Mic bias Right analog input Left analog input Right analog input Left analog input I2C device address selection I2C data input or output 6 February 2021 Everest Semiconductor Confidential ES8336 3. TYPICAL APPLICATION CIRCUIT MICBIAS C68 1uF R67 2K C66 1uF Differential signal with ground shield HeadSetMICP HeadSetMICN MK4 MICROPHONE 1 2 C88 100pF C67 1uF Pulled up, I2C chip address = 0x22 Pulled down, I2C chip address is 0x20 These capacitors must be located as close as possible to ES8336 package C89 100pF C90 100pF MainMicP MainMicN R48 2K AU_GND +3.3V_VP +3.3V_VP R65 10K DACVREF ADCVREF C77 1uF C83 1uF R44 100R AU_GND I2C_SDA R59 10K MICBIAS R49 2K I2C_SCL R45 100R C54 20pF C81 1uF AU_GND AU_GND AU_GND C55 20pF C78 1uF VMID AU_GND AU_GND R76 2K +3.3V_VP AU_GND 33 32 31 30 29 28 27 26 25 MICBIAS AU_GND I2S_MCLK 1 2 3 4 5 6 7 8 C72 20pF R61 33R I2S_SCLK I2S_DSDIN I2S_LRCK AU_GND R63 33R +3.3V_VP C95 100nF AU_GND AU_GND I2S_ASDOUT U2 ES8336 ADCVREF AGND AVDD DACVREF LOUT ROUT CPGNDREF CPGND ADCVREF C86 100nF R74 10K R77 330R GPIO2_HEADSET_MIC_DET C98 1uF DACVREF AU_GND R72 33R AU_GND 1 2 L 3 R 4 MIC 5 GND DET R73 33R AU_GND GPIO1_HP_INSERT_DET R64 33R HEADSET AU_GND GPIO1_HP_INSERT_DET GPIO2_HEADSET_MIC_DET HP_IRQ 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 R62 33R CCLK MCLK DVDD PVDD DGND SCLK DSDIN DLRCK AU_VCC33 PAD_GND CDATA CE LIN1 RIN1 LIN2 RIN2 MICBIAS VMID C70 100nF R60 33R ASDOUT GPIO1 GPIO2 GPIO3 CPVSSP CPVDD CPTOP CPBOT +1.8V_VD C91 1uF C76 2.2uF C99 10nF GPIO3_HEADSET_INTERRUPT_SIG_TO_CPU HeadSetMICP HeadSetMICN C92 1uF +1.8V_VCP C71 100nF AU_GND C73 1uF CPVDD must be 1.8V AU_GND GND AU_GND PVDD, The IO buffer Power supply DVDD, Digital Core power supply, 1.8V recommended AU_GND The capacitor must be located as close as possible to ES8336 package CPVDD, Charge pump Power supply, must be 1.8V AVDD, Analog Power supply, 3.3V Revision 3.0 7 February 2021 Everest Semiconductor Confidential ES8336 4. CLOCK MODES AND SAMPLING FREQUENCIES The device supports two types of clocking: standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz), and non standard audio clocks like 19.2 MHz. According to the serial audio data sampling frequency (Fs), the device can work in two speed modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz. The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the system clock with specific rates. In master mode, LRCK and SCLK are derived internally from device master clock. 5. MICRO-CONTROLLER CONFIGURATION INTERFACE The device supports standard I2C micro-controller configuration interface. External microcontroller can completely configure the device through writing to internal configuration registers. I2C interface is a bi-directional serial bus that uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. The timing diagram for data transfer of this interface is given in Figure 1. Data are transmitted synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each bit in a byte is sampled during SCL high with MSB bit being transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull the SDA low. The transfer rate of this interface can be up to 400 kbps. Figure 1 Data Transfer for I2C Interface A master controller initiates the transmission by sending a “start” signal, which is defined as a high-to-low transition at SDA while SCL is high. The first byte transferred is the slave address. It is a seven-bit chip address followed by a RW bit. The chip address must be 001000x, where x equals AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction specified by the RW bit. The master can terminate the communication by generating a “stop” signal, which is defined as a low-to-high transition at SDA while SCL is high. Revision 3.0 8 February 2021 Everest Semiconductor Confidential ES8336 In I2C interface mode, the registers can be written and read. The formats of “write” and “read” instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the register. Table 1 Write Data to Register in I2C Interface Mode Chip Address 001000 AD0 R/W 0 Register Address RAM ACK ACK Data to be written DATA Table 2 Read Data from Register in I2C Interface Mode Chip Address 001000 Chip Address 001000 AD0 AD0 R/W 0 R/W 1 Register Address RAM Data to be read Data ACK ACK 6. DIGITAL AUDIO INTERFACE The device provides many formats of serial audio data interface to the input of the DAC or output from the ADC through LRCK, BCLK (SCLK) and DACDAT/ADCDAT pins. These formats are I2S, left justified, DSP/PCM and TDM mode. DAC input DACDAT is sampled by the device on the rising edge of SCLK. ADC data is out at ADCDAT on the falling edge of SCLK. The relationship of SDATA (DACDAT/ADCDAT), SCLK and LRCK with these formats are shown through Figure 2 to Figure 6. 1 SCLK 1 SCLK SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LEFT CHANNEL LRCK RIGHT CHANNEL Figure 2 I2S Serial Audio Data Format Up To 24-bit SDATA 1 2 3 n-2 n-1 MSB n 1 LSB MSB 2 3 n-2 n-1 n LSB SCLK LRCK RIGHT CHANNEL LEFT CHANNEL Figure 3 Left Justified Serial Audio Data Format Up To 24-bit Revision 3.0 9 February 2021 Everest Semiconductor Confidential ES8336 Figure 5 DSP/PCM Mode A Figure 6 DSP/PCM Mode B 7. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Continuous operation at or beyond these conditions may permanently damage the device. PARAMETER Analog Supply Voltage Level Digital Supply Voltage Level Analog Input Voltage Range Digital Input Voltage Range Operating Temperature Range Storage Temperature MIN -0.3V -0.3V AGND-0.3V DGND-0.3V -40°C -65°C MAX +3.6V +3.6V AVDD+0.3V PVDD+0.3V +85°C +150°C RECOMMENDED OPERATING CONDITIONS PARAMETER AVDD CPVDD DVDD PVDD Revision 3.0 MIN 2.0 1.6 1.6 1.6 10 TYP 3.3 1.8 1.8/3.3 1.8/3.3 MAX 3.6 2.0 3.6 3.6 UNIT V V V V February 2021 Everest Semiconductor Confidential ES8336 ADC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER ADC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Gain Error Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Stopband Attenuation Analog Input Full Scale Input Level Input Impedance MIN TYP MAX UNIT 85 -88 80 92 -85 85 0.1 95 -75 90 dB dB dB dB % 0 0.5465 ±5 0.4535 Fs Fs dB dB ±0.05 50 0 0.4535 0.2268 Fs Fs dB dB ±0.005 50 ±AVDD/3.3 20 ±Vrms KΩ DAC ANALOG AND FILTER CHARACTERISTICS AND SPECIFICATIONS Test conditions are as the following unless otherwise specify: AVDD=3.3V, DCVDD=1.8V, AGND=0V, DGND=0V, Ambient temperature=25°C, Fs=48 KHz, 96 KHz or 192 KHz, MCLK/LRCK=256. PARAMETER DAC Performance Signal to Noise ratio (A-weigh) THD+N Channel Separation (1KHz) Interchannel Gain Mismatch Filter Frequency Response – Single Speed Passband Stopband Passband Ripple Stopband Attenuation Filter Frequency Response – Double Speed Passband Stopband Passband Ripple Revision 3.0 MIN TYP MAX UNIT 83 -85 80 93 -83 85 0.05 95 -75 90 dB dB dB dB 0.4535 Fs Fs dB dB 0 0.5465 40 0 0.4535 11 ±0.05 0.2268 ±0.005 Fs Fs dB February 2021 Everest Semiconductor Confidential Stopband Attenuation 40 De-emphasis Error at 1 KHz (Single Speed Mode Only) Fs = 32KHz Fs = 44.1KHz Fs = 48KHz Analog Output Full Scale Output Level ES8336 dB 0.002 0.013 0.0009 dB AVDD/3.3 Vrms POWER CONSUMPTION CHARACTERISTICS PARAMETER Normal Operation Mode DVDD=1.8V, PVDD=1.8V, AVDD=1.8V: Play back Play back and record DVDD=3.3V, PVDD=3.3V, AVDD=3.3V: Play back Play back and record Power Down Mode DVDD=1.8V, PVDD=1.8V, AVDD=1.8V DVDD=3.3V, PVDD=3.3V, AVDD=3.3V MIN TYP MAX UNIT mW 7 16 31 59 TBD TBD mW SERIAL AUDIO PORT SWITCHING SPECIFICATIONS PARAMETER MCLK frequency MCLK duty cycle LRCK frequency LRCK duty cycle SCLK frequency SCLK pulse width low SCLK Pulse width high SCLK falling to LRCK edge SCLK falling to SDOUT valid SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time Revision 3.0 Symbol MIN 40 40 TSCLKL TSCLKH TSLR TSDO TSDIS TSDIH 12 15 15 –10 0 10 10 MAX 51.2 60 200 60 26 10 UNIT MHz % KHz % MHz ns ns ns ns ns ns February 2021 Everest Semiconductor Confidential ES8336 Figure 8 Serial Audio Port Timing I2C SWITCHING SPECIFICATIONS (SLOW SPEED MODE/HIGH SPEED MODE) PARAMETER CCLK Clock Frequency Bus Free Time Between Transmissions Start Condition Hold Time Clock Low time Clock High Time Setup Time for Repeated Start Condition CDATA Hold Time from CCLK Falling CDATA Setup time to CCLK Rising Rise Time of CCLK Fall Time CCLK Symbol FCCLK TTWID TTWSTH TTWCL TTWCH TTWSTS TTWDH TTWDS TTWR TTWF MIN 4.7/1.3 4.0/0.6 4.7/1.3 4.0/0.6 4.7/0.6 0.25/0.1 MAX 100/400 UNIT KHz us us us us us us us us us 3.45/0.9 1.0/0.3 1.0/0.3 SDA TTWSTS TTWSTH TTWCL SCL TTWDH TTWID TTWDS TTWCH S TTWF TTWR P S Figure 10 I2C Timing Revision 3.0 13 February 2021 Everest Semiconductor Confidential ES8336 8. CONFIGURATION REGISTER DEFINITION REGISTER 0X00 – RESET, DEFAULT 0X03 Bit Name csm_on Bit 7 seq_en 6 rst_dig 5 rst_regs 4 rst_clkmgr 3 rst_master 2 rst_adc_dig 1 rst_dac_dig 0 Description Chip current state machine control 0 – csm power down(default) 1 – csm power on Power up sequence control 0 – power up sequence disable (default) 1 – power up sequence enable Digital reset 0 – normal(default) 1 – reset digital except control port block registers reset 0 – normal(default) 1 – reset all registers to default value except “rst_regs” clock manager block reset 0 – normal(default) 1 – reset clock manager block master block reset 0 – normal(default) 1 – reset master block ADC digital block reset 0 – normal 1 – reset ADC digital block (default) DAC digital block reset 0 – normal 1 – reset DAC digital block (default) REGISTER 0X01 – CLOCK MANAGER, DEFAULT 0X03 Bit Name mclk_div2 Bit 7 mclk_on 6 bclk_on 5 clk_cp_on 4 clk_adc_on 3 clk_dac_on 2 anaclk_adc_on 1 Revision 3.0 Description MCLK divide by 2 control 0 – normal (default) 1 – MCLK divide by 2 MCLK in control 0 – MCLK off(default) 1 – MCLK on SDP bit clock control 0 – BCLK off(default) 1 – BCLK on Charge pump clock control 0 – CLK_CP off(default) 1 – CLK_CP on ADC digital clock control 0 – adc_mclk off(default) 1 – adc_mclk on DAC digital clock control 0 – dac_mclk off(default) 1 – dac_mclk on ADC analog clock control 14 February 2021 Everest Semiconductor anaclk_dac_on Confidential ES8336 0 – anaclk_adc off 1 – anaclk_adc on(default) DAC analog clock control 0 – anaclk dac off 1 – anaclk_dac on(default) 0 REGISTER 0X02 – CLOCK MANAGER, DEFAULT 0X00 Bit Name clk_adc_double Bit 5 clk_dac_double 4 tm_sel 3 adclrck_sel 2 clk_adc_sel 1 syncMode 0 Description clk_adc divide by 2 control 0 – normal(default) 1 – clk_adc divide by 2 clk_dac divide by 2 control 0 – normal(default) 1 – clk_dac divide by 2 timer select 0 – use adclrck_out(default) 1 – use daclrck_out adclrck select 0 – use DACLRC (default) 1 – use ADCLRC adc_mclk select 0 – use clk_adc(default) 1 – use clk_dac sync mode 0 – normal(default) 1 – sync mode REGISTER 0X03 – CLOCK MANAGER, DEFAULT 0X20 Bit Name adc_osr[5:0] Bit 5 Description ADC delta sigma over sample rate adc_osr=f(adc_mclk) / fs / 8 f(adc_mclk) refer to clk_adc_div and clk_adc_double REGISTER 0X04 – CLOCK MANAGER, DEFAULT 0X11 Bit Name clk_adc_div[3:0] adclrck_div[11:8] Bit 7 3 Description adc_mclk clock divider Internal adclrck divider bit 11 to bit 8 REGISTER 0X05 – CLOCK MANAGER, DEFAULT 0X00 Bit Name adclrck_div[7:0] Bit 7 Description Internal adclrck divider bit 7 to bit 0 REGISTER 0X06 – CLOCK MANAGER, DEFAULT 0X11 Bit Name clk_dac_div[3:0] daclrck_div[11:8] Bit 7 3 Description dac_mclk clock divider Internal daclrck divider bit 11 to bit 8 REGISTER 0X07 – CLOCK MANAGER, DEFAULT 0X00 Bit Name Bit Revision 3.0 Description 15 February 2021 Everest Semiconductor daclrck_div[7:0] 7 Confidential ES8336 Internal daclrck divider bit 7 to bit 0 REGISTER 0X08 – CLOCK MANAGER, DEFAULT 0X00 Bit Name div_cp Bit 5:0 Description charge pump clock divider 0 – divide by 32 (default) 1 to 60 – divide by 1 to 60 61 – divide by 64 62 – divide by 96 63 – divide by 127 REGISTER 0X09 – SERIAL DATA PORT, DEFAULT 0X01 Bit Name MSC Bit 7 TRI 6 BCLK_INV 5 BCLKDIV 4:0 Description 0 – slave serial port mode 1 – master serial port mode (default) 0 – normal (default) 1 – Hi-Z output 0 – normal (default) 1 – BCLK inverted 0 – no BCLK (default) 1 to 18 – MCLK/BCLKDIV 19 – MCLK/20 20 – MCLK/22 21 – MCLK/24 22 – MCLK/25 23 – MCLK/30 24 – MCLK/32 25 – MCLK/33 26 – MCLK/34 27 – MCLK/36 28 – MCLK/44 29 – MCLK/48 30 – MCLK/66 31 – MCLK/72 REGISTER 0X0A – SERIAL DATA PORT, DEFAULT 0X00 Bit Name adc_sdp_mute Bit 6 ADCLRP 5 ADCWL 4:2 Revision 3.0 Description ADC SDP mute control 0 – ADC SDP unmute(default) 1 – ADC SDP mute I2S, left justified or right justified mode: 0 – left and right normal polarity 1 – left and right inverted polarity DSP/PCM mode: 0 – MSB is available on 2nd BCLK rising edge after ALRCK rising edge 1 – MSB is available on 1st BCLK rising edge after ALRCK rising edge 000 – 24-bit serial audio data word length(default) 001 – 20-bit serial audio data word length 010 – 18-bit serial audio data word length 011 – 16-bit serial audio data word length 100 – 32-bit serial audio data word length 16 February 2021 Everest Semiconductor ADCFORMAT 1:0 Confidential ES8336 00 – I2S serial audio data format(default) 01 – left justify serial audio data format 10 – right justify serial audio data format 11 – DSP/PCM mode serial audio data format REGISTER 0X0B – SERIAL DATA PORT, DEFAULT 0X00 Bit Name dac_sdp_mute Bit 6 DACLRP 5 DACWL 4:2 DACFORMAT 1:0 Description DAC SDP mute control 0 – DAC SDP unmute(default) 1 – DAC SDP mute I2S, left justified or right justified mode: 0 – left and right normal polarity 1 – left and right inverted polarity DSP/PCM mode: 0 – MSB is available on 2nd BCLK rising edge after DLRCK rising edge 1 – MSB is available on 1st BCLK rising edge after DLRCK rising edge 000 – 24-bit serial audio data word length(default) 001 – 20-bit serial audio data word length 010 – 18-bit serial audio data word length 011 – 16-bit serial audio data word length 100 – 32-bit serial audio data word length 00 – I2S serial audio data format(default) 01 – left justify serial audio data format 10 – right justify serial audio data format 11 – DSP/PCM mode serial audio data format REGISTER 0X0C – SYSTEM, DEFAULT 0XF8 Bit Name vmid_seq1 Bit 7:6 vmid_seq2 5:4 vmidSel_reg vmidSel 3:2 1:0 Description vmidSel at Pseq1 MCLK*adcSampleRate*512 from 0.042ms min to 170ms max vmidSel at Pseq2 MCLK*dacSampleRate*512 from 0.042ms min to 170ms max vmidSel sequence result vmidSel user configure sequence: vmidSel(00,default) -> vmid_seq1(11) -> vmid_seq2(10) -> vmidSel_reg(10) -> write vmidSel REGISTER 0X0D – SYSTEM, DEFAULT 0X3F Bit Name pdnMic pdn_ana ibiasgen_pdn pdn_adcBiasgen pdn_adcVrefgen pdn_dacVrefgen Bit 5 4 3 2 1 0 Description Power down internal micBias circuits Power down overall analog circuits Power down bias circuits Power down ADC bias circuits Power down ADC reference circuits Power down ADC reference circuits REGISTER 0X0E – SYSTEM, DEFAULT 0X00 Bit Name Bit Description Revision 3.0 17 February 2021 Everest Semiconductor LPCPNLDO LPVcmMod LPADCVrp LPadcVrp flashLP int1LP 5 4 3 2 1 0 Confidential ES8336 Low power mode negative supply Low power mode ADC modulator referrence Low power mode ADC reference Low power mode ADC reference Low power mode ADC flash Low power mode ADC modulator REGISTER 0X0F – SYSTEM, DEFAULT 0X00 Bit Name LPPGA LPDacL LPDacR LPHP LPHPMix Bit 4 3 2 1 0 Description Low power PGA Low power LDAC Low power RDAC Low power HP output driver Low power HP mixer REGISTER 0X10 – SYSTEM, DEFAULT 0X01 Bit Name dac_ibias_sw vmidLow Bit 4 3:2 vx2off vx1Sel 1 0 Description DAC bias selection Vmid selection 00 – vdda/2 01 – vdda/2-50mv 10 – vdda/2-100mv 11 – vdda/2-150mv disable vx2 Vx1 selection REGISTER 0X11 – SYSTEM, DEFAULT 0XFC Bit Name vsel Bit 7:0 Description 11111100 – normal (default) REGISTER 0X12 – SYSTEM, DEFAULT 0X28 Bit Name hp_ref2 Bit 5 hp_ref1 4 HPmix_ref2 HPmix_ref1 mref2 3 2 1 mref1 0 Description HP output driver ref 0 light load 1 heavy load; this bit work together with hp_ref1 HP output driver ref 0 light load 1 heavy load; this bit work together with hp_ref2 HPmixer ref2 HPmixer ref1 ADC ref control 0 default ADC ref control 0 default REGISTER 0X14 – HEADPHONE MIXER, DEFAULT 0X00 Bit Name LD2LHPMIX Bit 7 Description LDAC signal to LHPmixer Revision 3.0 18 February 2021 Everest Semiconductor RD2RHPMIX 3 Confidential ES8336 RDAC signal to RHPmixer REGISTER 0X15 – HEADPHONE MIXER, DEFAULT 0X33 Bit Name LHPMIX_HI LHPMIX_LO LHPMIX_MUTE pdnLHPMix RHPMIX_HI RHPMIX_LO RHPMIX_MUTE pdnRHPMix Bit 7 6 5 4 3 2 1 0 Description LHPmixer gain high LHPmixer gain low LHPmixer mute Power down LHPmixer RHPmixer gain high RHPmixer gain low RHPmixer mute Power down RHPmixer REGISTER 0X16 – HEADPHONE MIXER, DEFAULT 0X00 Bit Name LHPMIXVol[3:0] Bit 7:4 RHPMIXVol[3:0] 3:0 Description 0000 – -12dB 0001 – -10.5dB 0010 – -9dB 0011 – -7.5dB 0100 – -6dB 1000 – -4.5dB 1001 – -3dB 1010 – -1.5dB 1011 – 0dB 0000 – -12dB 0001 – -10.5dB 0010 – -9dB 0011 – -7.5dB 0100 – -6dB 1000 – -4.5dB 1001 – -3dB 1010 – -1.5dB 1011 – 0dB REGISTER 0X17 – HEADPHONE, DEFAULT 0X00 Bit Name HPL_zcen EnHPL HPL_outen HPLcal HPR_zcen EnHPR HPR_outen HPRcal Bit 7 6 5 4 3 2 1 0 Description Enable LHP output driver zero cross Enable LHP output driver Enable LHP output Enable LHP output driver calibration Enable RHP output driver zero cross Enable RHP output driver Enable RHP output Enable RHP output driver calibration REGISTER 0X18 – HEADPHON , DEFAULT 0X88 Bit Name pdn_Lical Bit 7 Description Reserved Revision 3.0 19 February 2021 Everest Semiconductor HPL_iCal_sw HPLVol[1:0] 6 5:4 pdn_Rical HPR_iCal_sw HPRVol[1:0] 3 2 1:0 Confidential ES8336 Reserved 00 – 0dB 01 – -12dB 10 – -24dB 11 – -48dB Reserved Reserved 00 – 0dB 01 – -12dB 10 – -24dB 11 – -48dB REGISTER 0X19 – HEADPHONE, DEFAULT 0X06 Bit Name pdn_CPHP EnRefr_HP VROI_HP Bit 2 1 0 Description Power down HP output driver Enable HP referrence Reserved REGISTER 0X1A – HEADPHONE, DEFAULT 0X22 Bit Name pdn_cp cp_HIPWR Bit 5 4 cpn_swcomp_en cp_swdly_auto cp_swdly_reg cp_clkdly_en 3 2 1 0 Description Power down charge pump circuits CP power level 0 – normal 1 - high power Reserved Reserved, automatic CP power up sequence Reserved, user register controlled CP power up sequence Default 0 REGISTER 0X1B – HEADPHONE, DEFAULT 0X03 Bit Name vhp_ldolvl[1:0] Bit 7:6 cpn_ldolvl[1:0] 5:4 cpn_swlvl[1:0] 3:2 pdn_CPNLDO pdn_cpvncomp 1 0 Revision 3.0 Description HP output driver supply voltage select 00 – 1.5v 01 – 1.4v 10 – 1.3v 11 – 1.2v HP output driver supply voltage select 00 – -1.15v 01 – -1.25v 10 – -1.35v 11 – -1.45v Reserved, CP power automatic switching level 00 – -1.5v 01 – -1.4v 10 – -1.3v 11 – -1.2v Power down CP negative supply regulator Reserved, power down level switching 20 February 2021 Everest Semiconductor Confidential ES8336 REGISTER 0X1C – CALIBRATION, DEFAULT 0X0F Bit Name HPL_iCal_on Bit 3 HPL_mCal_on 2 HPR_iCal_on 1 HPR_mCal_on 0 Description ical: analog calibration, mV level 0 – iCal off 1 – iCal on(default), auto clear to "0" after iCal mCal: digital calibration, uV level 0 – mCal off 1 – mCal on(default), auto clear after mCal ical: analog calibration, mV level 0 – iCal off 1 – iCal on(default), auto clear to "0" after iCal mCal: digital calibration, uV level 0 – mCal off 1 – mCal on(default), auto clear after mCal REGISTER 0X1D – CALIBRATION, DEFAULT 0X00 Bit Name mcal_fast Bit 7 ical_raw 6 mCal_step 5:4 cal_stl 3:2 HPL_iCal_8 HPR_iCal_8 1 0 Description mcal fast mode 0 – normal mode 1 – fast mode ical raw 0 – use mcal to find a better ical data 1 – ical raw mCal resolution 00 – vpp/8192 01 – vpp/4096 10 – vpp/2048 11 – vpp/1024 Calibration settling time, per calculate 00 – 4 (default) 01 – 8 10 – 16 11 – 32 HPL_iCal MSB HPR_iCal MSB REGISTER 0X1E – CALIBRATION, DEFAULT 0X80 Bit Name HPL_iCal[7:0] Bit 7:0 Description Reserved REGISTER 0X1F – CALIBRATION, DEFAULT 0X80 Bit Name HPF_iCal[7:0] Bit 7:0 Description Reserved REGISTER 0X20 – CALIBRATION, DEFAULT 0X00 Bit Name HPL_mCal[7:0] Bit 7:0 Revision 3.0 Description Reserved 21 February 2021 Everest Semiconductor Confidential ES8336 REGISTER 0X21 – CALIBRATION, DEFAULT 0X00 Bit Name HPR_mCal[7:0] Bit 7:0 Description REGISTER 0X22 – ADC, DEFAULT 0XC0 Bit Name PdnAInL PdnModL LInSel[1:0] Bit 7 6 5:4 Description Power down PGA Power down ADC modulator PGA input select 00 – Lin1-Rin1 (MIC DF) 01 – Lin2-Rin2 (Board DF) 10 – Lin1 DF2SE (MIC) 11 – Lin2 DF2SE (Board) REGISTER 0X23 – ADC, DEFAULT 0X00 Bit Name LPGAgain[3:0] Bit 7:4 Description Left PGA gain 0000 – -3.5dB (default) 0001 – 0dB 0010 – 2.5dB 0011 – 4.5dB 0100 – 7dB 0101 – 10dB 0110 – 13dB 0111 – 16dB 1000 – 18dB 1001 – 21dB 1010 –24dB others – 0dB REGISTER 0X24 – ADC, DEFAULT 0X01 Bit Name DCM Bit 1 DF2SE_15dB 0 Description DC measure 0 – disable 1 – enable DF2SE intensive: 0 – 0dB 1 – 15dB REGISTER 0X25 – ADC, DEFAULT 0X08 Bit Name adcFsMode Bit 4 adc_HPF_L 3 dmic_src[1:0] 1:0 Description adc fs mode 0 – single speed 1 – double speed 0 – disable ADC left channel high pass filter 1 – enable ADC left channel high pass filter (default) digital mic control 0x – dmic disable 10 – DMIC high 11 – DMIC low Revision 3.0 22 February 2021 Everest Semiconductor Confidential ES8336 REGISTER 0X26 – ADC, DEFAULT 0X10 Bit Name adcMute Bit 5 adcSoftRamp 4 adcInvL 1 Description ADC mute 0 – normal 1 – mute ADC volume to -96dB adc soft ramp 0 – disable 1 – adc soft ramp enable 0 – normal (default) 1 – left channel polarity inverted REGISTER 0X27 – ADC, DEFAULT 0XC0 Bit Name adcVolumeL Bit 7:0 Description 00000000 － 0dB 00000001 － -0.5dB 00000010 － -1dB … 11000000 － -96dB(default) REGISTER 0X29 – ADC, DEFAULT 0X1C Bit Name ALCSEL Bit 7:6 ALCMODE 5 MAXGAIN[4:0] 4:0 Revision 3.0 Description 00 － alc off other － alc on Determines the ALC mode of operation: 0 – ALC mode (Normal Operation) 1 – Limiter mode. ALC MAXGAIN[1:0] for PGA max gain 00000 – -6.5dB 00001 – -5 dB 00010 – -3.5dB 00011 – -2dB 00100 – -0.5dB 00101 – +1dB 00100 – +2.5dB 00111 – +4dB 01000 – +5.5dB 01001 – +7dB 01010 – +8.5dB 01011 – +10dB 01100 – +11.5dB 01101 – +13dB 01110 – +14.5dB 01111– +16dB 10000 – +17.5dB 10001 – +19dB 10010 – +20.5dB 10011 – +22dB 10100 – +23.5dB 10101 – +25dB 10110 – +26.5dB 10111 – +28dB 23 February 2021 Everest Semiconductor Confidential ES8336 11000 – +29.5dB 11001 – +31dB 11010 – +32.5dB 11011 – +34dB others – +35.5dB REGISTER 0X2A – ADC, DEFAULT 0X00 Bit Name MINGAIN[4:0] Bit 4:0 Description ALC MINGAIN[1:0] for PGA min gain 00000 – -12dB 00001 – -10.5 dB 00010 – -9dB 00011 – -7.5dB 00100 – -6dB 00101 – -4.5dB 00100 – -3dB 00111 – -1.5dB 01000 – 0dB 01001 – +1.5dB 01010 – +3dB 01011 – +4.5dB 01100 – +6dB 01101 – +7.5dB 01110 – +9dB 01111– +10.5dB 10000 – +12dB 10001 – +13.5dB 10010 – +15dB 10011 – +16.5dB 10100 – +18dB 10101 – +19.5dB 10110 – +21dB 10111 – +22.5dB 11000 – +24dB 11001 – +25.5dB 11010 – +27dB 11011 – +28.5dB others – +30dB REGISTER 0X2B – ADC, DEFAULT 0XB0 Bit Name ALCLVL Bit 7:4 ALCHLD 3:0 Description ALC target 0000 – -16.5 dB 0001 – -15 dB 0010 – -13.5 dB …… 0111 – -6 dB 1000 – -4.5 dB 1001 – -3 dB 1010-1111 – -1.5 dB ALC hold time before gain is increased Revision 3.0 24 February 2021 Everest Semiconductor Confidential ES8336 0000 – 0ms 0001 – 2.67ms 0010 – 5.33ms …… (time doubles with every step) 1001 – 0.68s 1010 or higher – 1.36s REGISTER 0X2C – ADC, DEFAULT 0X32 Bit Name ALCDCY Bit 7:4 ALCATK 3:0 Description ALC decay (gain ramp up) time at ALC mode/limiter mode: 0000 – 410 us/90.8 us 0001 – 820 us/182us 0010 – 1.64 ms/363us …… (time doubles with every step) 1001 – 210 ms/46.5 ms 1010 or higher – 420 ms/93 ms ALC attack (gain ramp down) time at ALC mode/limiter mode: 0000 – 104 us/22.7 us 0001 – 208 us/45.4 us 0010 – 416 us/90.8 us …… (time doubles with very step) 1001 – 53.2 ms/11.6 ms 1010 or higher – 106 ms/23.2 ms REGISTER 0X2D – ADC, DEFAULT 0X03 Bit Name WIN_SIZE Bit 4:0 Description Windows size for peak detector，set the window size to N*16 samples 00110 – 96 samples (default) 00111 – 102 samples ….. 11111 – 496 samples REGISTER 0X2E – ADC, DEFAULT 0X00 Bit Name ALC_NGG Bit 6 ALC_NGAT 5 ALC_NGTH 4:0 Description noise gate type 0 – original gain(default) 1 – mute noise gate enable 0 – disable(default) 1 – enable Noise gate threshold 00000 – -76.5 dBFS 00001 – -75 dBFS …… 11110 – -31.5 dBFS 11111 – -30 dBFS REGISTER 0X2F – DAC, DEFAULT 0X11 Bit Name PdnDacL Bit 4 Description Pdn Left DAC Revision 3.0 25 February 2021 Everest Semiconductor PdnDacR Confidential ES8336 0 – normal 1 – power down Power down right DAC 0 – normal 1 – power down 0 REGISTER 0X30 – DAC, DEFAULT 0X10 Bit Name dacDATSEL Bit 7:6 dacMute 5 dacSoftRamp 4 dacRampRate 3:2 dacInvL 1 dacInvR 0 Description for dacDATSEL 00 – Lin->Lout, Rin->Rout 01 – Lin->Lout, Lin->Rout 10 – Rin->Lout, Rin->Rout 11 – Rin->Lout, Lin->Rout dac mute 0 – normal 1 – mute dac volume to -96dB dac soft ramp 0 – normal 1 – dac soft ramp enable 00 – 0.5 dB per 4 LRCKs (default) 01 – 0.5 dB per 32 LRCKs 10 – 0.5 dB per 64 LRCKs 11 – 0.5 dB per 128 LRCKs 0 – normal DAC left channel analog output no phase inversion (default) 1 – normal DAC left channel analog output 180 degree phase inversion 0 – normal DAC right channel analog output no phase inversion (default) 1 – normal DAC right channel analog output 180 degree phase inversion REGISTER 0X31 – DAC, DEFAULT 0X00 Bit Name dacFsMode Bit 7 dacNotchMode 6 dacAutoMute 5 automute_type 4 dacLeR 2 Description fs mode 0 – single speed 1 – double speed 0 – normal 1 – DAC at DS, FS*2, to cancel DAC harmonic noise auto mute control 0 – auto mute dis (default) 1 – auto mute en 0 – mute L when L=0, mute R when R=0 1 – mute L/R when L and R=0 0 – normal (default) 1 – both channel gain control is set by DAC left gain control register REGISTER 0X32– DAC, DEFAULT 0X00 Bit Name Vpp_scale Bit 7:6 dacZeroL 5 Description 00 – Vpp set at 3.5V (0.7 modulation index) (default) 01 – Vpp set at 4.0V 10 – Vpp set at 3.0V 11 – Vpp set at 2.5V 0 – normal (default) Revision 3.0 26 February 2021 Everest Semiconductor dacZeroR 4 dacMono 3 Se_strength 2:0 Confidential ES8336 1 – set Left Channel DAC output all zero 0 – normal (default) 1 – set Right Channel DAC output all zero 0 – stereo (default) 1– mono (L+R)/2 into DACL and DACR SE strength 000 – 0 (default) …… 111 – 7 REGISTER 0X33 – DAC, DEFAULT 0XC0 Bit Name dacVolumeL Bit 7:0 Description Digital volume control attenuates the signal in 0.5 dB incremental from 0 to –96 dB. 00000000 – 0 dB 00000001 – -0.5 dB 00000010 – -1 dB … 11000000 – -96 dB (default) REGISTER 0X34 – DAC, DEFAULT 0XC0 Bit Name dacVolumeR Bit 7:0 Description Digital volume control attenuates the signal in 0.5 dB incremental from 0 to –96 dB. 00000000 – 0 dB 00000001 – -0.5 dB 00000010 – -1 dB … 11000000 – -96 dB (default) REGISTER 0X4D – GPIO, DEFAULT 0X00 Bit Name gpio3_sel Bit 3:2 gpio2_sel 1 gpio1_sel 0 Description 00 – Interrupt out 01 – clk_cp out 10 – adc_mclk out 11 – dac_mclk out 0 – GMShorted in 1 – DMIC_SCL out 0 – HPInserted in 1 – ADCLRCK inout REGISTER 0X4E – GPIO, DEFAULT 0X00 Bit Name button_debounce[1:0] Bit 7:6 insert_debounce[1:0] 5:4 Revision 3.0 Description Headset Button debounce: 00 – 256fs - 5.3ms 01 – 512fs - 10.6ms 10 – 1024fs - 21ms 11 – 2048fs - 42ms Headset Detection debounce 00 – 512fs - 10.6ms 01 – 1024fs - 21ms 10 – 4096fs - 84ms 27 February 2021 Everest Semiconductor int_en 1 int_pol 0 Confidential ES8336 11 – 16384fs - 341ms interrupt control 0 – disable (default) 1 – enable interrupt polarity 0 – high active 1 – low active REGISTER 0X4F – FLAG, DEFAULT 0X00 Bit Name csm_chip Bit 5:4 Master_err FlagHPInserted 3 2 FlagGMShorted 1 Revision 3.0 Description chip csm 00 – PwDown 01 – Pseq1 11 – Pseq2 10 – Normal Reserved HP inserted read only flag 0 – HP not inserted 1 – HP inserted GM shorted read only flag 0 – GM not shorted 1 – GM shorted 28 February 2021 Everest Semiconductor Confidential ES8336 9. PACKAGE (UNIT: MM) Revision 3.0 29 February 2021 Everest Semiconductor Confidential ES8336 10.CORPORATE INFORMATION Everest Semiconductor Co., Ltd. 苏州工业园区金鸡湖大道 1355 号国际科技园, 邮编 215021 Email: info@everest-semi.com 11.IMPORTANT NOTICE AND DISCLAIMER Everest Semiconductor publishes reliable technical information about its products. Information contained herein is subject to change without notice. It may be used by a party at their own discretion and risk. Everest Semiconductor disclaims responsibility for any claims, damages, costs, losses, and liabilities arising out of your use of the information. This publication is not to be taken as a license to operate under any existing patents and intellectual properties. Revision 3.0 30 February 2021