HEF4052BT-Q100,118

HEF4052B-Q100 Dual 4-channel analog multiplexer/demultiplexer Rev. 2 — 11 September 2014 Product data sheet 1. General description The HEF4052B-Q100 is a dual 4-channel analog multiplexer/demultiplexer with common channel select logic. Each multiplexer/demultiplexer has four independent inputs/outputs (nY0 to nY3) and a common input/output (nZ). The common channel select logic includes two select inputs (S1 and S2) and an active LOW enable input (E). Both multiplexers/demultiplexers contain four bidirectional analog switches, each with one side connected to an independent input/output (nY0 to nY3) and the other side connected to a common input/output (nZ). With E LOW, one of the four switches is selected (low-impedance ON-state) by S1 and S2. With E HIGH, all switches are in the high-impedance OFF-state, independent of S1 and S2. If break before make is needed, then it is necessary to use the enable input. VDD and VSS are the supply voltage connections for the digital control inputs (S1 and S2, and E). The VDD to VSS range is 3 V to 15 V. The analog inputs/outputs (nY0 to nY3, and nZ) can swing between VDD as a positive limit and VEE as a negative limit. VDD  VEE may not exceed 15 V. Unused inputs must be connected to VDD, VSS, or another input. For operation as a digital multiplexer/demultiplexer, VEE is connected to VSS (typically ground). VEE and VSS are the supply voltage connections for the switches. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits  Automotive product qualification in accordance with AEC-Q100 (Grade 1)  Specified from 40 C to +85 C and from 40 C to +125 C  Fully static operation  5 V, 10 V, and 15 V parametric ratings  Standardized symmetrical output characteristics  ESD protection:  MIL-STD-833, method 3015 exceeds 2000 V  HBM JESD22-A114F exceeds 2000 V  MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 )  Complies with JEDEC standard JESD 13-B 3. Applications  Analog multiplexing and demultiplexing  Digital multiplexing and demultiplexing  Signal gating HEF4052B-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4052BT-Q100 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4052BTT-Q100 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 5. Functional diagram VDD 16 13 12 14 15 S1 10 11 S2 9 LOGIC LEVEL CONVERSION 1 - OF - 4 DECODER 1 5 E 1Z 1Y0 1Y1 1Y2 1Y3 2Y0 2Y1 6 2 4 3 8 7 VSS VEE 2Y2 2Y3 2Z mnb042 Fig 1. Functional diagram nYn VDD VDD nZ VEE 001aak604 Fig 2. Schematic diagram (one switch) HEF4052B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 September 2014 © Nexperia B.V. 2017. All rights reserved 2 of 21 HEF4052B-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 10 9 13 6 0 1 4× 0 3 G4 1Z 1Y0 12 MDX 10 S1 1Y1 14 9 S2 1Y2 15 1Y3 11 2 2Y0 1 3 2Y1 5 2Y2 2 2Y3 4 6 E 3 Fig 3. Logic symbol HEF4052B_Q100 Product data sheet 5 1 2 4 12 14 13 15 2Z 3 1 0 11 001aak605 mnb041 Fig 4. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 September 2014 © Nexperia B.V. 2017. All rights reserved 3 of 21 HEF4052B-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 1Z 1Y0 S1 LEVEL CONVERTER 1Y1 S2 LEVEL CONVERTER 1Y2 E LEVEL CONVERTER 1Y3 2Y0 2Y1 2Y2 2Y3 2Z 001aak634 Fig 5. Logic diagram HEF4052B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2 — 11 September 2014 © Nexperia B.V. 2017. All rights reserved 4 of 21 HEF4052B-Q100 Nexperia Dual 4-channel analog multiplexer/demultiplexer 6. Pinning information 6.1 Pinning +()%4