DA7219-02VB6

DA7219 Audio Codec with Advanced Accessory Detect General Description The DA7219 is an ultra low-power audio codec with Advanced Accessory Detection (AAD), which supports sample rates up to 96 kHz at 24-bit resolution. It contains a mono microphone to analog to digital converter (ADC) path, and a stereo digital to analog converter (DAC) to headphone (HP) path. AAD supports the detection and identification of 3-pole (headphone) and 4-pole (headset) jacks, and allows the automatic pin order switching of MIC/GND on CTIA or OMTP headsets. It also supports automatic multiple button detection. Key Features ■ Android Wired Headset v1.1 compliant ■ Microphone input with automatic level control ■ High performance mono microphone to ADC ■ Digital sidetone path with gain record path with 90 dB SNR ■ Digital tone generator □ ADC digital filters with Audio and Voice ■ System controller for simplified pop-free startmode high-pass characteristics up and shut-down □ Low-noise microphone bias regulator with ■ Mixed sample rates of 24 kHz ADC, 48 kHz programmable output DAC supported from a single digital interface ■ High performance stereo DAC to headphone ■ Sample rates of up to 96 kHz at 24-bit playback path with 100 dB SNR □ DAC digital filters with Audio and Voice mode high-pass cutoff and 5-band equalizer ■ Advanced Accessory Detect supports □ 3-pole and 4-pole jack detection □ MIC/GND polarity switching □ Multiple button detection □ Headphone impedance testing resolution ■ Shut-down mode for very low current consumption during standby ■ Phase locked loop with WCLK tracking to generate system clock ■ 4-wire digital audio interface with support for I2S, TDM and other audio formats ■ 2-wire I2C compatible interface with support for High Speed mode up to 3.4 MHz ■ 4.5 mm x 1.6 mm WLCSP RouteEasy™ package for low cost PCB manufacture Applications ■ ■ ■ ■ Chromebooks Portable audio applications Tablets and eBooks ■ Headphone accessories ■ Remote controllers ■ Gaming controllers All digital distributed systems Datasheet CFR0011-120-00 Revision 3.4 1 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect System Diagram DA7219 Codec Analog Audio Switch Analog HP Amp Audio Jack Headset Digital Digital SoC Digital Class D Digital Class D DMIC Stereo Speaker Figure 1: DA7219 in a Digital Distributed System Datasheet CFR0011-120-00 Revision 3.4 2 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Contents General Description ............................................................................................................................ 1 Key Features ........................................................................................................................................ 1 Applications ......................................................................................................................................... 1 System Diagram .................................................................................................................................. 2 Contents ............................................................................................................................................... 3 Figures .................................................................................................................................................. 6 Tables ................................................................................................................................................... 7 1 Terms and Definitions................................................................................................................. 11 1.1 Terminology ........................................................................................................................ 12 2 References ................................................................................................................................... 12 3 Block Diagram ............................................................................................................................. 13 4 Ballout .......................................................................................................................................... 14 5 Pin Descriptions .......................................................................................................................... 16 5.1 Microphone Pins ................................................................................................................. 16 5.1.1 MIC_P .................................................................................................................. 16 5.1.2 MIC_N .................................................................................................................. 16 5.1.3 MICBIAS .............................................................................................................. 16 5.2 Accessory Detect Pins ........................................................................................................ 16 5.2.1 JACKDET ............................................................................................................ 16 5.2.2 SLEEVE ............................................................................................................... 16 5.2.3 RING2 .................................................................................................................. 16 5.2.4 SLEEVE_SENSE................................................................................................. 16 5.2.5 RING2_SENSE.................................................................................................... 16 5.2.6 MIC ...................................................................................................................... 16 5.3 Interface Input Pins ............................................................................................................. 16 5.3.1 MCLK ................................................................................................................... 16 5.3.2 SCL ...................................................................................................................... 17 5.3.3 DATIN .................................................................................................................. 17 5.4 Interface Output Pins .......................................................................................................... 17 5.4.1 nIRQ..................................................................................................................... 17 5.4.2 DATOUT .............................................................................................................. 17 5.5 Interface Bidirectional Pins ................................................................................................. 17 5.5.1 SDA...................................................................................................................... 17 5.5.2 BCLK.................................................................................................................... 17 5.5.3 WCLK .................................................................................................................. 17 5.6 Headphone Output Pins ...................................................................................................... 17 5.6.1 HP_L .................................................................................................................... 17 5.6.2 HP_R ................................................................................................................... 17 5.7 Charge Pump Pins .............................................................................................................. 17 5.7.1 HPCSP ................................................................................................................ 17 5.7.2 HPCSN ................................................................................................................ 18 5.7.3 HPCFP ................................................................................................................. 18 5.7.4 HPCFN ................................................................................................................ 18 Datasheet CFR0011-120-00 Revision 3.4 3 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 5.8 References .......................................................................................................................... 18 5.8.1 VMID .................................................................................................................... 18 5.8.2 DACREF .............................................................................................................. 18 5.8.3 VREF ................................................................................................................... 18 5.9 Supply Pins ......................................................................................................................... 18 5.9.1 VDD ..................................................................................................................... 18 5.9.2 VDD_IO ............................................................................................................... 18 5.9.3 VDD_MIC ............................................................................................................. 18 5.10 Ground Pins ........................................................................................................................ 18 5.10.1 GND ..................................................................................................................... 18 5.10.2 GND_CP .............................................................................................................. 18 5.10.3 GND_HP .............................................................................................................. 19 6 Absolute Maximum Ratings ....................................................................................................... 20 7 Recommended Operating Conditions ....................................................................................... 20 8 Electrical Characteristics ........................................................................................................... 21 9 Digital Interfaces ......................................................................................................................... 26 10 Timing Characteristics................................................................................................................ 27 11 Functional Description ............................................................................................................... 29 11.1 Device Operating Modes..................................................................................................... 29 11.1.1 DEEP SLEEP ...................................................................................................... 29 11.1.2 SLEEP ................................................................................................................. 29 11.1.3 ON........................................................................................................................ 29 11.2 Input Paths .......................................................................................................................... 31 11.2.1 Microphone Input ................................................................................................. 31 11.2.2 Analog to Digital Converter .................................................................................. 33 11.3 Digital Engine ...................................................................................................................... 33 11.3.1 Input Processing .................................................................................................. 35 11.3.2 Sidetone Processing ............................................................................................ 37 11.3.3 Tone Generator ................................................................................................... 37 11.3.4 Digital Router ....................................................................................................... 39 11.3.5 System Control .................................................................................................... 39 11.3.6 Output Processing ............................................................................................... 40 11.4 Output Paths ....................................................................................................................... 43 11.4.1 Digital to Analog Converter .................................................................................. 43 11.4.2 Headphone Outputs............................................................................................. 44 11.4.3 Charge Pump Control .......................................................................................... 45 11.4.4 Tracking the Demands on the Charge Pump Output .......................................... 46 11.5 Advanced Accessory Detection .......................................................................................... 47 11.5.1 Configuring Advanced Accessory Detection ....................................................... 48 11.5.2 Detection of Jack Insertion or Removal ............................................................... 50 11.5.3 Three-Pole or Four-Pole Jack Insertion............................................................... 51 11.5.4 Jack Pin Order Detection with Four-Pole Jacks .................................................. 52 11.5.5 Headphone Output and Line Output.................................................................... 52 11.5.6 Detection of Buttons ............................................................................................ 53 11.6 Clocking ............................................................................................................................. 55 11.6.1 MCLK Input .......................................................................................................... 55 Datasheet CFR0011-120-00 Revision 3.4 4 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 11.6.2 Audio Reference Oscillator .................................................................................. 55 11.6.3 PLL Bypass Mode................................................................................................ 55 11.6.4 PLL Normal Mode (DAI Master) .......................................................................... 56 11.6.5 Example Calculation of the Feedback Divider Setting ........................................ 57 11.6.6 PLL SRM Mode (DAI Slave) ................................................................................ 57 11.7 Reference Generation ......................................................................................................... 58 11.7.1 Voltage References ............................................................................................. 58 11.7.2 Bias Currents ....................................................................................................... 58 11.7.3 Voltage Levels ..................................................................................................... 58 11.8 I2C Control Interface ............................................................................................................ 58 11.9 Digital Audio Interface ......................................................................................................... 62 11.9.1 DAI Channels....................................................................................................... 63 11.9.2 I2S Mode .............................................................................................................. 63 11.9.3 Left Justified Mode............................................................................................... 63 11.9.4 Right Justified Mode ............................................................................................ 63 11.9.5 DSP Mode ........................................................................................................... 64 12 Register Definitions .................................................................................................................... 65 13 Package Information ................................................................................................................. 117 14 Ordering Information ................................................................................................................ 118 Appendix A Applications Information ........................................................................................... 119 A.1 Codec Initialization ............................................................................................................ 119 A.2 Automatic ALC Calibration ................................................................................................ 119 Appendix B Components................................................................................................................ 120 B.1 Audio Inputs ...................................................................................................................... 120 B.2 Microphone Bias ............................................................................................................... 121 B.3 Audio Outputs ................................................................................................................... 121 B.4 Headphone Charge Pump ................................................................................................ 122 B.5 Digital Interfaces ............................................................................................................... 123 B.6 References ........................................................................................................................ 123 B.7 Supplies ............................................................................................................................ 124 B.8 Ground .............................................................................................................................. 124 Appendix C PCB Layout Guidelines.............................................................................................. 125 C.1 Layout and Schematic Support ......................................................................................... 125 C.2 General Recommendations .............................................................................................. 125 C.3 Capacitor Selection ........................................................................................................... 126 Revision History .............................................................................................................................. 127 Datasheet CFR0011-120-00 Revision 3.4 5 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Figures Figure 1: DA7219 in a Digital Distributed System ................................................................................. 1 Figure 2: DA7219 Block Diagram ........................................................................................................ 13 Figure 3: DA7219 Ballout Diagram...................................................................................................... 14 Figure 4: I2C Bus Timing ..................................................................................................................... 27 Figure 5: Digital Audio Interface Timing Diagram ............................................................................... 28 Figure 6: Analog Inputs Block Diagram ............................................................................................... 31 Figure 7: ECM Microphone Configurations ......................................................................................... 32 Figure 8: Digital Engine Block Diagram............................................................................................... 34 Figure 9: Digital Filters Block Diagram ................................................................................................ 34 Figure 10: ALC Principle of Operation................................................................................................. 36 Figure 11: Attack, Delay and Hold Parameters ................................................................................... 37 Figure 12: DA7219 Digital Router ....................................................................................................... 39 Figure 13: Equalizer Filter Band 1 Frequency Response at FS = 48 kHz .......................................... 41 Figure 14: Equalizer Filter Band 2 Frequency Response at FS = 48 kHz .......................................... 42 Figure 15: Equalizer Filter Band 3 Frequency Response at FS = 48 kHz .......................................... 42 Figure 16: Equalizer Filter Band 4 Frequency Response at FS = 48 kHz .......................................... 42 Figure 17: Equalizer Filter Band 5 Frequency Response at FS = 48 kHz .......................................... 43 Figure 18: Headphone Output Paths Showing the Two Amplifiers ..................................................... 44 Figure 19: Jack Socket Variants .......................................................................................................... 47 Figure 20: Signal Timing Diagram for the AAD Function .................................................................... 50 Figure 21: Measuring the Impedance of a Button Press ..................................................................... 53 Figure 22: Schematic of the I2C Control Interface Bus........................................................................ 59 Figure 23: I2C START and STOP Conditions...................................................................................... 59 Figure 24: I2C Byte Write (SDA line) ................................................................................................... 60 Figure 25: Examples of the I2C Byte Read (SDA line) ........................................................................ 60 Figure 26: Examples of I2C Page Read (SDA line) ............................................................................. 60 Figure 27: I2C Page Write (SDA line) .................................................................................................. 61 Figure 28: I2C Repeated Write (SDA line) ........................................................................................... 61 Figure 29: Master Mode (dai_clk_en = 1) ........................................................................................... 62 Figure 30: Slave Mode (dai_clk_en = 0) ............................................................................................. 62 Figure 31: I2S Mode ............................................................................................................................. 63 Figure 32: Left Justified Mode ............................................................................................................. 63 Figure 33: Right Justified Mode ........................................................................................................... 63 Figure 34 DSP Mode ........................................................................................................................... 64 Figure 35: DA7219 Package Outline Drawing................................................................................... 117 Figure 36: MICBIAS Decoupling ....................................................................................................... 121 Figure 37: Recommended Headphone Layout ................................................................................. 122 Figure 38: Charge Pump Decoupling ................................................................................................ 122 Figure 39: Charge Pump Flying Capacitor ........................................................................................ 122 Figure 40: I2C Pull Ups ...................................................................................................................... 123 Figure 41: Reference Capacitors ...................................................................................................... 124 Figure 42: Power Supply Decoupling ................................................................................................ 124 Figure 43: DA7219 Example Layout ................................................................................................. 125 Datasheet CFR0011-120-00 Revision 3.4 6 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Tables Table 1: Ball Description...................................................................................................................... 14 Table 2: Ball/Pin Type Definition ......................................................................................................... 15 Table 3: Absolute Maximum Ratings................................................................................................... 20 Table 4: Recommended Operating Conditions ................................................................................... 20 Table 5: Power Consumption .............................................................................................................. 21 Table 6: Microphone Bias .................................................................................................................... 21 Table 7: Microphone Amplifier ............................................................................................................. 21 Table 8: Input Mix Amplifier (mixinamp) .............................................................................................. 22 Table 9: Mono Analog to Digital Converter (adc_mono) ..................................................................... 22 Table 10: Stereo Digital to Analog Converter (dac_stereo) ................................................................ 22 Table 11: Stereo Headphone Amplifier (audio_hpamp_stereo) .......................................................... 22 Table 12: Input Filters .......................................................................................................................... 23 Table 13: DAC Filter ............................................................................................................................ 23 Table 14: Automatic Level Control (ALC) ............................................................................................ 24 Table 15: Advanced Accessory Detect (AAD)..................................................................................... 24 Table 16: Reference Voltages ............................................................................................................. 24 Table 17: PLL Mode ............................................................................................................................ 25 Table 18: Bypass Mode ....................................................................................................................... 25 Table 19: Tone Generator ................................................................................................................... 25 Table 20: Digital I/O Characteristics .................................................................................................... 26 Table 21: I2C Control Bus (VDD_IO = 1.8 V) .......................................................................................... 27 Table 22: Digital Audio Interface Timing (I2S/DSP in Master/Slave Mode) ......................................... 28 Table 23: System States, Configuration, and Current Consumption .................................................. 30 Table 24: Microphone Bias Settings .................................................................................................... 31 Table 25: First Microphone Amplifier Gain Settings ............................................................................ 32 Table 26: Input Mixer Gain Settings .................................................................................................... 33 Table 27: Input HPF Settings .............................................................................................................. 35 Table 28: DTMF Tones Corresponding to the dtmf_reg Value ........................................................... 38 Table 29: Output HPF Settings ........................................................................................................... 40 Table 30: Output 5-Band Equalizer Center/Cutoff Frequencies.......................................................... 41 Table 31: Charge Pump Output Voltage Control ................................................................................ 45 Table 32: cp_thresh_vdd2 Settings in DAC Volume Mode (cp_mchange = 10)................................. 45 Table 33: cp_thresh_vdd2 Settings in Signal Size Mode (cp_mchange = 11) ................................... 46 Table 34: DA7219 Advanced Accessory Detection Feature Summary .............................................. 49 Table 35: Jack Detection Latency Timings Controlled by jack_detect_rate........................................ 51 Table 36: Debounce Settings for Jack Insertion Events ..................................................................... 51 Table 37: Debounce Settings for Jack Removal Events ..................................................................... 51 Table 38: Resistance Threshold Settings for Three-Pole and Four-Pole Jack Determination ........... 52 Table 39: Resistance Threshold Settings for Headphone and Lineout Determination ....................... 53 Table 40: Button Names and Functions in Android Devices ............................................................... 54 Table 41: Setting the Number of Measurements Used in Averaging .................................................. 54 Table 42: Sample Rate Control Register and Corresponding System Clock Frequency ................... 55 Table 43: PLL Input Divider ................................................................................................................. 56 Table 44: Example PLL Configurations ............................................................................................... 57 Table 45: IO Voltage Level Setting ...................................................................................................... 58 Table 46: Device I2C Slave Addresses................................................................................................ 59 Table 47: Register map accdet_cad_00 page 0 ................................................................................. 65 Table 48: ACCDET_STATUS_A (Page 0: 0x000000C0).................................................................... 66 Table 49: ACCDET_STATUS_B (Page 0: 0x000000C1).................................................................... 66 Table 50: ACCDET_IRQ_EVENT_A (Page 0: 0x000000C2) ............................................................. 66 Table 51: ACCDET_IRQ_EVENT_B (Page 0: 0x000000C3) ............................................................. 67 Table 52: ACCDET_IRQ_MASK_A (Page 0: 0x000000C4) ............................................................... 67 Table 53: ACCDET_IRQ_MASK_B (Page 0: 0x000000C5) ............................................................... 68 Table 54: ACCDET_CONFIG_1 (Page 0: 0x000000C6) .................................................................... 68 Table 55: ACCDET_CONFIG_2 (Page 0: 0x000000C7) .................................................................... 69 Table 56: ACCDET_CONFIG_3 (Page 0: 0x000000C8) .................................................................... 71 Table 57: ACCDET_CONFIG_4 (Page 0: 0x000000C9) .................................................................... 71 Table 58: ACCDET_CONFIG_5 (Page 0: 0x000000CA) .................................................................... 72 Datasheet CFR0011-120-00 Revision 3.4 7 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Table 59: ACCDET_CONFIG_6 (Page 0: 0x000000CB) .................................................................... 72 Table 60: ACCDET_CONFIG_7 (Page 0: 0x000000CC).................................................................... 72 Table 61: ACCDET_CONFIG_8 (Page 0: 0x000000CD).................................................................... 73 Table 62: Register map adc_filters_cad_00 page 0............................................................................ 74 Table 63: ADC_FILTERS1 (Page 0: 0x00000038) ............................................................................. 74 Table 64: Register map alc_cad_00 page 0........................................................................................ 74 Table 65: ALC_CTRL1 (Page 0: 0x0000002F) ................................................................................... 75 Table 66: ALC_CTRL2 (Page 0: 0x0000009A) ................................................................................... 76 Table 67: ALC_CTRL3 (Page 0: 0x0000009B) ................................................................................... 76 Table 68: ALC_NOISE (Page 0: 0x0000009C) ................................................................................... 77 Table 69: ALC_TARGET_MIN (Page 0: 0x0000009D) ....................................................................... 77 Table 70: ALC_TARGET_MAX (Page 0: 0x0000009E) ...................................................................... 78 Table 71: ALC_GAIN_LIMITS (Page 0: 0x0000009F) ........................................................................ 78 Table 72: ALC_ANA_GAIN_LIMITS (Page 0: 0x000000A0) .............................................................. 79 Table 73: ALC_ANTICLIP_CTRL (Page 0: 0x000000A1)................................................................... 79 Table 74: ALC_ANTICLIP_LEVEL (Page 0: 0x000000A2) ................................................................. 80 Table 75: ALC_OFFSET_AUTO_M_L (Page 0: 0x000000A3) ........................................................... 80 Table 76: ALC_OFFSET_AUTO_U_L (Page 0: 0x000000A4) ........................................................... 80 Table 77: Register map analogue_cad_00 page 0 ............................................................................. 80 Table 78: MIC_1_GAIN_STATUS (Page 0: 0x00000006) .................................................................. 82 Table 79: MIXIN_L_GAIN_STATUS (Page 0: 0x00000008)............................................................... 83 Table 80: ADC_L_GAIN_STATUS (Page 0: 0x0000000A)................................................................. 83 Table 81: DAC_L_GAIN_STATUS (Page 0: 0x0000000C) ................................................................ 83 Table 82: DAC_R_GAIN_STATUS (Page 0: 0x0000000D) ................................................................ 84 Table 83: HP_L_GAIN_STATUS (Page 0: 0x0000000E) ................................................................... 84 Table 84: HP_R_GAIN_STATUS (Page 0: 0x0000000F) ................................................................... 84 Table 85: MIC_1_SELECT (Page 0: 0x00000010) ............................................................................. 85 Table 86: REFERENCES (Page 0: 0x00000032) ............................................................................... 85 Table 87: MIXIN_L_SELECT (Page 0: 0x00000033).......................................................................... 85 Table 88: MIXIN_L_GAIN (Page 0: 0x00000034) ............................................................................... 85 Table 89: ADC_L_GAIN (Page 0: 0x00000036) ................................................................................. 86 Table 90: MIC_1_GAIN (Page 0: 0x00000039) .................................................................................. 86 Table 91: DAC_L_GAIN (Page 0: 0x00000045) ................................................................................. 86 Table 92: DAC_R_GAIN (Page 0: 0x00000046) ................................................................................. 87 Table 93: HP_L_GAIN (Page 0: 0x00000048) .................................................................................... 87 Table 94: HP_R_GAIN (Page 0: 0x00000049) ................................................................................... 87 Table 95: MIXOUT_L_SELECT (Page 0: 0x0000004B) ..................................................................... 88 Table 96: MIXOUT_R_SELECT (Page 0: 0x0000004C) .................................................................... 88 Table 97: MICBIAS_CTRL (Page 0: 0x00000062) ............................................................................. 88 Table 98: MIC_1_CTRL (Page 0: 0x00000063) .................................................................................. 88 Table 99: MIXIN_L_CTRL (Page 0: 0x00000065) .............................................................................. 89 Table 100: ADC_L_CTRL (Page 0: 0x00000067) ............................................................................... 89 Table 101: DAC_L_CTRL (Page 0: 0x00000069) ............................................................................... 90 Table 102: DAC_R_CTRL (Page 0: 0x0000006A) .............................................................................. 90 Table 103: HP_L_CTRL (Page 0: 0x0000006B) ................................................................................. 90 Table 104: HP_R_CTRL (Page 0: 0x0000006C) ................................................................................ 91 Table 105: MIXOUT_L_CTRL (Page 0: 0x0000006E) ........................................................................ 92 Table 106: MIXOUT_R_CTRL (Page 0: 0x0000006F) ....................................................................... 92 Table 107: IO_CTRL (Page 0: 0x00000091)....................................................................................... 92 Table 108: Register map charge_pump_cad_00 page 0 .................................................................... 93 Table 109: CP_CTRL (Page 0: 0x00000047) ..................................................................................... 93 Table 110: CP_VOL_THRESHOLD1 (Page 0: 0x00000095) ............................................................. 93 Table 111: Register map cif_i2c_addr_cad_00 page 0....................................................................... 93 Table 112: CIF_I2C_ADDR_CFG (Page 0: 0x0000001B) .................................................................. 94 Table 113: Register map common1_cad_00 page 0 .......................................................................... 94 Table 114: CIF_TIMEOUT_CTRL (Page 0: 0x00000012) .................................................................. 94 Table 115: CIF_CTRL (Page 0: 0x00000013)..................................................................................... 95 Table 116: SR_24_48 (Page 0: 0x00000016) ..................................................................................... 95 Table 117: SR (Page 0: 0x00000017) ................................................................................................. 95 Datasheet CFR0011-120-00 Revision 3.4 8 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Table 118: GAIN_RAMP_CTRL (Page 0: 0x00000092) ..................................................................... 96 Table 119: PC_COUNT (Page 0: 0x00000094) .................................................................................. 96 Table 120: Register map common2_cad_00 page 0 .......................................................................... 96 Table 121: CHIP_ID1 (Page 0: 0x00000081)...................................................................................... 97 Table 122: CHIP_ID2 (Page 0: 0x00000082)...................................................................................... 97 Table 123: CHIP_REVISION (Page 0: 0x00000083) .......................................................................... 97 Table 124: Register map dac_filters_cad_00 page 0.......................................................................... 97 Table 125: DAC_FILTERS5 (Page 0: 0x00000040) ........................................................................... 98 Table 126: DAC_FILTERS2 (Page 0: 0x00000041) ........................................................................... 98 Table 127: DAC_FILTERS3 (Page 0: 0x00000042) ........................................................................... 99 Table 128: DAC_FILTERS4 (Page 0: 0x00000043) ........................................................................... 99 Table 129: DAC_FILTERS1 (Page 0: 0x00000044) ......................................................................... 100 Table 130: Register map dac_ng_cad_00 page 0 ............................................................................ 100 Table 131: DAC_NG_SETUP_TIME (Page 0: 0x000000AF) ........................................................... 101 Table 132: DAC_NG_OFF_THRESH (Page 0: 0x000000B0) .......................................................... 101 Table 133: DAC_NG_ON_THRESH (Page 0: 0x000000B1) ............................................................ 102 Table 134: DAC_NG_CTRL (Page 0: 0x000000B2) ......................................................................... 102 Table 135: Register map dai_cad_00 page 0 ................................................................................... 102 Table 136: DAI_CLK_MODE (Page 0: 0x0000002B) ....................................................................... 103 Table 137: DAI_CTRL (Page 0: 0x0000002C) .................................................................................. 103 Table 138: DAI_TDM_CTRL (Page 0: 0x0000002D) ........................................................................ 104 Table 139: DAI_OFFSET_LOWER (Page 0: 0x00000030) .............................................................. 104 Table 140: DAI_OFFSET_UPPER (Page 0: 0x00000031) ............................................................... 105 Table 141: Register map pll_cad_00 page 0..................................................................................... 105 Table 142: PLL_CTRL (Page 0: 0x00000020) .................................................................................. 106 Table 143: PLL_FRAC_TOP (Page 0: 0x00000022) ........................................................................ 106 Table 144: PLL_FRAC_BOT (Page 0: 0x00000023) ........................................................................ 106 Table 145: PLL_INTEGER (Page 0: 0x00000024) ........................................................................... 107 Table 146: PLL_SRM_STS (Page 0: 0x00000025) .......................................................................... 107 Table 147: Register map router_cad_00 page 0 ............................................................................... 107 Table 148: DIG_ROUTING_DAI (Page 0: 0x0000002A) .................................................................. 107 Table 149: DIG_ROUTING_DAC (Page 0: 0x0000002E)................................................................. 108 Table 150: DIG_CTRL (Page 0: 0x00000099) .................................................................................. 108 Table 151: Register map sidetone_cad_00 page 0 .......................................................................... 109 Table 152: SIDETONE_CTRL (Page 0: 0x0000003A) ..................................................................... 109 Table 153: SIDETONE_GAIN (Page 0: 0x0000003B) ...................................................................... 109 Table 154: DROUTING_ST_OUTFILT_1L (Page 0: 0x0000003C) .................................................. 110 Table 155: DROUTING_ST_OUTFILT_1R (Page 0: 0x0000003D) ................................................. 110 Table 156: Register map system_active_cad_00 page 0 ................................................................. 110 Table 157: SYSTEM_ACTIVE (Page 0: 0x000000FD) ..................................................................... 110 Table 158: Register map system_controller_cad_00 page 0 ............................................................ 111 Table 159: SYSTEM_MODES_INPUT (Page 0: 0x00000050) ......................................................... 111 Table 160: SYSTEM_MODES_OUTPUT (Page 0: 0x00000051) ..................................................... 111 Table 161: SYSTEM_STATUS (Page 0: 0x000000E0) .................................................................... 112 Table 162: Register map tone_gen_cad_00 page 0 ......................................................................... 112 Table 163: TONE_GEN_CFG1 (Page 0: 0x000000B4) .................................................................... 112 Table 164: TONE_GEN_CFG2 (Page 0: 0x000000B5) .................................................................... 113 Table 165: TONE_GEN_CYCLES (Page 0: 0x000000B6) ............................................................... 114 Table 166: TONE_GEN_FREQ1_L (Page 0: 0x000000B7) ............................................................. 114 Table 167: TONE_GEN_FREQ1_U (Page 0: 0x000000B8) ............................................................. 114 Table 168: TONE_GEN_FREQ2_L (Page 0: 0x000000B9) ............................................................. 115 Table 169: TONE_GEN_FREQ2_U (Page 0: 0x000000BA) ............................................................ 115 Table 170: TONE_GEN_ON_PER (Page 0: 0x000000BB) .............................................................. 115 Table 171: TONE_GEN_OFF_PER (Page 0: 0x000000BC) ............................................................ 116 Table 172: Ordering Information ....................................................................................................... 118 Table 173: Audio Inputs..................................................................................................................... 120 Table 174: Microphone Bias .............................................................................................................. 121 Table 175: Headset ........................................................................................................................... 121 Table 176: Headphone Charge Pump............................................................................................... 122 Datasheet CFR0011-120-00 Revision 3.4 9 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Table 177: Digital Interfaces – I2C ..................................................................................................... 123 Table 178: Digital Interfaces - I2S ...................................................................................................... 123 Table 179: References ...................................................................................................................... 123 Table 180: Power Supplies................................................................................................................ 124 Table 181: Ground............................................................................................................................. 124 Table 182: Recommended Capacitor Values.................................................................................... 126 Datasheet CFR0011-120-00 Revision 3.4 10 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 1 Terms and Definitions AAD ADC ALC CMRR CTIA DAC DAI DMIC DTMF EQ FS HP HPF I2C I2S LDO MCLK OMTP PC PGA PLL PSRR SC SDM SNR SRM SWG TDM THD+N VCO WCLK Datasheet CFR0011-120-00 Advanced Accessory Detect Analog to Digital Converter Automatic Level Control Common Mode Rejection Ratio Cellular Telecommunications Industry Association, (now known as ‘The Wireless Association’) Digital to Analog Converter Digital Audio Interface Digital Microphone Dual Tone Multi Frequency Equalizer Sample Rate Headphones High-Pass Filter Inter-Integrated Circuit Interface Inter-Integrated Circuit Sound Low Dropout Regulator Master Clock Open Mobile Terminals Platform Program Counter Programmable Gain Amplifier Phase Locked Loop Power Supply Rejection Ratio System Controller Sigma Delta Modulator Signal to Noise Ratio Sample Rate Matching Sine Wave Generator Time Division Multiplexing Total Harmonic Distortion plus Noise Voltage-Controlled Oscillator Word Clock Revision 3.4 11 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 1.1 Terminology Crosstalk (dB) The level difference between the active path output and the idle path measured signal level, at the test signal frequency. The active path is configured and supplied with an input signal capable of driving a full scale output, with the signal measured at the output of the specified idle path. Mute Attenuation The difference in level between the full scale output signal and the output with mute applied. Channel Separation (dB) [left-to-right and right-to-left] The difference in level between the active channel (driven to maximum full scale output) and the signal level measured in the idle channel at the test signal frequency. The active channel is configured and supplied with an input signal capable of driving a full scale output, with the signal measured at the output of the associated idle channel. PSRR The ratio of a given power supply change relative to the output signal that results from it. PSRR is measured under quiescent signal path conditions. SNR The difference in level between the maximum full scale output signal and the output with no input signal applied. THD+N The level of the rms value of the sum of harmonic distortion products plus noise in the specified bandwidth relative to the amplitude of the measured output signal. All performance measurements carried out with 20 kHz low pass filter, and where noted an Aweighted filter. Failure to use such a filter will result in higher THD and lower SNR readings than are found in the Electrical Characteristics. The low-pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. 2 [1] References Android Wired Audio Headset Specification (v1.1) (https://source.android.com/accessories/headset/specification.html ) Datasheet CFR0011-120-00 Revision 3.4 12 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 3 Block Diagram DIGITAL ENGINE Impedance Detection Sidetone Path System Controller ADC DACL HP_L DACR HP_R MICBIAS MIC Accessory Detect MIC_N MCLK Input Filters (High-Pass, ALC) MIC_P Tone Generator Output Filters (High-Pass, 5-BandEQ) DA7219 PLL RING2 SLEEVE AAD JACKDET SLEEVE_SENSE RING2_SENSE HPCFP HPCFN HPCSN HPCSP GND_CP VDD GND GND_HP CHARGE PUMP VDD_MIC DATIN DATOUT BCLK VDD_IO SCL SDA WCLK DIGITAL AUDIO INTERFACE I2C CONTROL INTERFACE nIRQ VMID VREF DACREF VOLTAGE REFS Figure 2: DA7219 Block Diagram Datasheet CFR0011-120-00 Revision 3.4 13 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 4 Ballout 1 A HPCSP B C 2 3 4 5 HP_L HPCSN D 1 2 VDD 4 5 9 DACREF DATIN 6 10 11 DATOUT 7 9 MICBIAS 12 13 16 MIC_P MIC JACKDET SDA SCL 11 15 MIC_N RING2 SCL MCLK 10 14 VDD_MIC nIRQ 8 13 GND_HP RING2 GND WCLK 12 SLEEVE VMID BCLK VDD_IO VDD_IO 3 8 SLEEVE_ SENSE HPCFN HPCFP 7 VREF HP_R RING2_ SENSE GND_CP 6 14 15 16 View from above “Live Bug” Analogue Digital Power Ground Figure 3: DA7219 Ballout Diagram Table 1: Ball Description Ball No. Ball/Pin Name Type (Table 2) Description Microphone Inputs B16 MIC_P AI Differential analog microphone 1 input (Pos) A15 MIC_N AI Differential analog microphone 1 input (Neg) B14 MICBIAS AO Microphone bias output Accessory Detect D16 JACKDET DI Jack Detect Input from socket A11 SLEEVE AIO Socket Sleeve (configured as MIC or GND) C13 RING2 AIO Socket Ring 2 (configured as GND or MIC) B6 SLEEVE_SENSE AIO Socket Sleeve (Sense) B4 RING2_SENSE AIO Socket Ring 2 (Sense) C15 MIC AIO Microphone DC input Headphone Outputs A3 HP_L AO Single-ended headphone output (Left) A5 HP_R AO Single-ended headphone output (Right) Charge Pump A1 HPCSP AIO Charge pump reservoir capacitor (Positive) C1 HPCSN AIO Charge pump reservoir capacitor (Negative) D2 HPCFP AIO Charge pump flying capacitor (Positive) C3 HPCFN AIO Charge pump flying capacitor (Negative) Digital Interface D14 SDA DIOD I2C bidirectional data D12 SCL DI I2C clock Datasheet CFR0011-120-00 Revision 3.4 14 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Ball No. Ball/Pin Name Type (Table 2) Description D10 nIRQ DIOD Interrupt output (open drain active low) C7 DATIN DIO DAI data input to DA7219 C9 DATOUT DIO DAI data output from DA7219 D6 BCLK DIO DAI bit clock D8 WCLK DIO DAI word clock C11 MCLK DI Master clock input References B8 DACREF AIO DAC reference decoupling capacitor A9 VMID AIO Mid-rail reference decoupling capacitor A7 VREF AIO Bandgap reference decoupling capacitor C5 VDD AI Main analog and digital supply A13 VDD_MIC AI Supply for MICBIAS LDO D4 VDD_IO AI Supply for digital interfaces B2 GND_CP AI Ground B10 GND AI Ground B12 GND_HP AI Ground Supplies Grounds Table 2: Ball/Pin Type Definition Ball/Pin Type Description Ball/Pin Type Description DI Digital Input AI Analog Input DIO Digital Input/Output AO Analog Output DIOD Digital Input/Output open Drain AIO Analog Input/Output Datasheet CFR0011-120-00 Revision 3.4 15 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 5 5.1 Pin Descriptions Microphone Pins 5.1.1 MIC_P MIC_P is the positive differential input for the analog microphone channel. It can be used as a singleended input if MIC_N is grounded (see Figure 7). 5.1.2 MIC_N MIC_N is the negative differential input for the analog microphone channel. It should be grounded when using a single-ended analog microphone configuration. 5.1.3 MICBIAS MICBIAS is the internally generated microphone supply. This must be decoupled with a 1 µF capacitor. 5.2 5.2.1 Accessory Detect Pins JACKDET JACKDET is used to signal to the device when the Jack is fully inserted into the 3.5 mm jack (or alternative) socket. The JACKDET pin is designed to be pulled either HIGH or LOW on the insertion of the jack. If using an HPLDET type headset socket additional external circuitry is required. If not required it should be left unconnected. 5.2.2 SLEEVE Sleeve is tested during the sense stage and then configured as either the headset microphone input or the headset ground connection. 5.2.3 RING2 RING2 is tested during the sense stage and then configured as either the headset microphone input or the headset ground connection. 5.2.4 SLEEVE_SENSE SLEEVE sense line to guarantee accuracy over distance, cables and connectors. 5.2.5 RING2_SENSE RING2 sense line to guarantee accuracy over distance, cables and connectors. 5.2.6 MIC MIC is the DC input for the analog accessory detect. 5.3 5.3.1 Interface Input Pins MCLK MCLK is the master clock input pin. It is used as the main system clock either directly or via the PLL. Datasheet CFR0011-120-00 Revision 3.4 16 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 5.3.2 SCL SCL is the Control Interface (I2C) clock input and is used in conjunction with SDA to control the device. 5.3.3 DATIN DATIN is the data input pin which forms part of the Digital Audio Interface (DAI). It is used to present audio playback data to the device. 5.4 5.4.1 Interface Output Pins nIRQ nIRQ is the open drain active-low interrupt output to alert the host to either an accessory or a level detect event. 5.4.2 DATOUT DATOUT is the data output pin which forms part of the DAI. It is used to present audio record data to the host. 5.5 5.5.1 Interface Bidirectional Pins SDA SDA is the Control Interface (I2C) data input/output and is used in conjunction with SCL to control the device. 5.5.2 BCLK BCLK is the bit clock input/output pin which forms part of the DAI. It is used to clock audio data bits into or out from the device or both. 5.5.3 WCLK WCLK is the word clock input/output pin which forms part of the DAI. It is used to indicate whether the data bits belong to the left or right audio channel. 5.6 5.6.1 Headphone Output Pins HP_L HP_L is the left-channel single-ended headphone output. It is ground-centered so the headphone speaker can be connected directly between HP_L and ground. 5.6.2 HP_R HP_R is the right-channel single-ended headphone output. It is ground-centered so the headphone speaker can be connected directly between HP_R and ground. 5.7 5.7.1 Charge Pump Pins HPCSP HPCSP is the positive output from the headphone charge pump. It should be connected to GND_CP via a reservoir capacitor. Datasheet CFR0011-120-00 Revision 3.4 17 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 5.7.2 HPCSN HPCSN is the negative output from the headphone charge pump. It must be connected to GND_CP via a reservoir capacitor. 5.7.3 HPCFP HPCFP is one of the flying capacitor connections required by the headphone charge pump. It must be connected to HPCFN via a capacitor. 5.7.4 HPCFN HPCFN is one of the flying capacitor connections required by the headphone charge pump. It must be connected to HPCFP via a capacitor. 5.8 5.8.1 References VMID VMID is the mid-rail reference decoupling capacitor connection. 5.8.2 DACREF DACREF is the DAC reference decoupling capacitor connection. 5.8.3 VREF VREF is the bandgap reference decoupling capacitor connection. 5.9 5.9.1 Supply Pins VDD VDD is main analog supply pin. It supplies all the analog circuits except the MICBIAS output and the HPAMP outputs. 5.9.2 VDD_IO VDD_IO is the supply pin for the digital input/output signals. VDD_IO must be greater than or equal to VDD during device operation. 5.9.3 VDD_MIC VDD_MIC is the supply pin for the MICBIAS. VDD_MIC must be greater than or equal to VDD during device operation. 5.10 Ground Pins 5.10.1 GND GND is the main analog ground pin. It is the ground connection for all analog circuits with the exception of the charge pump. 5.10.2 GND_CP GND_CP is the ground pin for the charge pump and the digital engine. Datasheet CFR0011-120-00 Revision 3.4 18 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 5.10.3 GND_HP GND_HP is the ground point for the headset. When a headset is connected this pin is automatically connected internally to either RING2 or SLEEVE. Datasheet CFR0011-120-00 Revision 3.4 19 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 6 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings Parameter Description TSTG Conditions (Note 1) Min Max Unit Storage temperature –65 +165 °C Ta Operating temperature –40 +85 °C VDD_LIM Main supply voltage –0.3 +2.75 V VVDD_IO Digital IO supply voltage –0.3 +5.5 V VDD_MIC Microphone bias supply voltage –0.3 +5.5 V VDDIO Digital IO pins: SDA, SCL, BCLK, WCLK, DATIN, DATOUT, MCLK –0.3 VDD_IO + 0.3 V VJACKDET Accessory detect pins: JACKDET –0.3 VDD + 0.3 V VACCDET Accessory detect pins: RING2, SLEEVE, MIC, RING2_SENSE, SLEEVE_SENSE –0.3 VDD_MIC + 0.3 V VMIC_P, VMIC_N Analog input pins MIC_P and MIC_N –0.3 VDD + 0.3 V VESD_HBM ESD susceptibility Human body model (HBM) 2000 V VESD_CDM ESD susceptibility Charged device model (CDM) 500 V Note 1 7 Stresses beyond those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the device. These are stress ratings only, so functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Table 4: Recommended Operating Conditions Parameter Description Ta Operating temperature VDD Main supply voltage VDD_IO Digital IO supply voltage VDD_MIC Microphone bias supply voltage Note 1 Conditions Min Typ Max Unit –25 85 °C 1.7 2.5 V (Note 1) VDD 3.6 V (Note 1) VDD 3.6 V VDD_IO and VDD_MIC must be greater than or equal to VDD. Datasheet CFR0011-120-00 Revision 3.4 20 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 8 Electrical Characteristics Unless otherwise stated, test conditions are as follows: VDD = VDD_IO = 1.8 V, VDD_MIC = 3.3 V, MCLK = 12.288 MHz, SR = 48 kHz, PLL = Bypass mode, Ta = 25 ºC. Table 5: Power Consumption Description Conditions Min Typ Max Unit 4 10 µA DEEP SLEEP mode SLEEP mode AAD on without button detection 185 µA Digital playback to headphone, no load DAC to HP_L/R, quiescent 3.4 mW Digital playback to headphone, with load DAC to HP_L/R, 16 Ω load, 0.1 mW at 0 dBFS 7.5 mW Microphone stereo record MIC P/N to ADCL/R 2.75 mW Microphone stereo record and digital playback to headphone, no load MIC P/N to ADCL/R and DACL/R to HP_L/R, quiescent 4.8 mW Microphone stereo record and digital playback to headphone, with load MIC P/N to ADCL/R and DACL/R to HP_L/R, 16 Ω load, 0.1 mW at 0 dBFS 8.9 mW Table 6: Microphone Bias Parameter Description Conditions Min VMICBIAS Output voltage No load, VDD_MIC > VMICBIAS + 200 mV Level programmable using micbias1_level 1.6 IBIAS Output current Output voltage droop < 50 mV PSRR Power supply rejection ratio 20 Hz to 2 kHz 2 kHz to 20 kHz VNO Output voltage noise VMICBIAS ≤ 2.2 V Typ Max Unit 2.9 V 2 mA 70 50 dB 5 µVRMS Table 7: Microphone Amplifier Parameter Description Conditions Full-scale input signal 0 dB, singled-ended 0 dB gain, differential Min PSRR Max 0.8*VDD 1.6*VDD Input resistance 12 Programmable gain −6 Gain step size VNI Typ 15 Unit VPP 18 kΩ 36 dB 6 dB Absolute gain accuracy 0 dB @ 1 kHz -1.0 1.0 dB Gain step error 20 Hz to 20 kHz -0.1 0.1 dB Input noise level Inputs connected to GND, 24 dB gain, input-referred, A-weighted Amplitude ripple 20 Hz to 20 kHz -0.5 Power supply rejection ratio 20 Hz to 2 kHz 2 kHz to 20 kHz 90 70 Datasheet CFR0011-120-00 Revision 3.4 21 of 128 5 µVRMS 0.5 dB dB 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Parameter Description CMRR Common mode rejection ratio Conditions Min Typ Max 70 Unit dB Table 8: Input Mix Amplifier (mixinamp) Parameter Description Conditions Min Typ −4.5 Programmable gain Gain step size Max Unit +18 dB 1.5 dB Absolute gain accuracy 0 dB @ 1 kHz -1.0 +1.0 dB Gain step error 20 Hz to 20 kHz -0.1 +0.1 dB Amplitude ripple 20 Hz to 20 kHz -0.5 +0.5 dB Max Unit Table 9: Mono Analog to Digital Converter (adc_mono) Parameter Description Conditions VMAX Full-scale input signal 0 dBFS digital output level SNR Signal to noise ratio THD+N PSRR Min Typ 1.6*VDD VPP A-weighted 90 dB Total harmonic distortion plus noise -1 dBFS analog input level -85 dB Power supply rejection ratio 20 Hz to 2 kHz 2 kHz to 20 kHz 70 50 dB Table 10: Stereo Digital to Analog Converter (dac_stereo) Parameter Description Conditions VMAX Full-scale output signal 0 dBFS digital input level SNR Signal to Noise Ratio THD+N PSRR Min Typ Max Unit 1.6*VDD VPP A-weighted 100 dB Total harmonic distortion plus noise -1 dBFS digital input level -90 dB Power supply rejection ratio 20 Hz to 2 kHz 2 kHz to 20 kHz 70 50 dB Table 11: Stereo Headphone Amplifier (audio_hpamp_stereo) Parameter Description Conditions VMAX Full-scale output signal No load DC output offset Min Typ Max Unit 1.6*VDD VPP −30 dB gain 250 µV Maximum output power per channel VDD = 1.8 V, THD < 0.1%, RLOAD = 16 Ω, 1 kHz 30 mWRMS Maximum output power per channel VDD = 2.5 V, THD < 0.1%, RLOAD = 16 Ω, 1 kHz 70 mWRMS 16 Ω Load resistance 13 Load capacitance 500 pF Load inductance 400 µH +0.5 dB Frequency Response 20 Hz to 20 kHz SNR Signal to Noise Ratio Datasheet CFR0011-120-00 -0.5 VDD = 1.8 V, 0 dB gain Revision 3.4 22 of 128 98 dB 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Parameter Description Conditions Min Typ VDD = 2.5 V, 0 dB gain Max 100 Unit dB VNO Output noise level 20 Hz to 20 kHz, 10 MΩ 300 1.0 Typ Max Unit 2.5 Ω pF T BCLK period tr BCLK rise time 8 ns tf BLCK fall time 8 ns thC BCLK high period 40 % 60 % T tlC BCLK low period 40 % 60 % T tdCW BCLK to WCLK delay -30 % +30 % T tdCD BCLK to DATOUT delay -30 % +30 % T thW 75 DSP mode WCLK high time Non-DSP mode tlW 100 % T Word length (Note 1) T 100 % T Word length (Note 2) T DSP mode WCLK low time Non-DSP mode ns tsW WCLK setup time Slave mode 7 ns thW WCLK hold time Slave mode 2 ns tsD DATIN setup time 7 ns thD DATIN hold time 2 ns tdWD DATOUT to WCLK delay DATOUT is synchronized to BCLK Note 1 WCLK must be high for at least the word length number of BCLK periods Note 2 WCLK must be low for at least the word length number of BCLK periods Datasheet CFR0011-120-00 Revision 3.4 28 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect 11 Functional Description DA7219 is a high-performance, low-power audio codec with in-built Advanced Accessory Detection (AAD). The AAD supports the detection of 3-pole (headphone or lineout) or 4-pole (headset) jacks, with automatic pin order switching of MIC/GND on CTIA and OMTP headsets. The DA7219 contains a mono analog microphone-to-ADC path and a DAI for input and output. The DAC to headphone path has a ground-centered, single-ended stereo headphone output. The digital core has an input filter with a high-pass filter (HPF), and automatic level control (ALC), while the output filter has an HPF, and a 5-band equalizer (EQ). There is also a sidetone path with gain and a tone generator that supports Dual Tone MultiFrequency (DTMF). 11.1 Device Operating Modes The DA7219 codec has three operating modes: 11.1.1 DEEP SLEEP There is no clocking in DEEP SLEEP mode and consequently no functionality available and no accessory detection is performed. The system will awake when system_active = 1. 11.1.2 SLEEP In SLEEP mode and with micbias off, AAD performs jack detection and jack configuration detection. Any button press is detected, but identification of the button cannot be performed until micbias is on. No clocking is performed in SLEEP mode, and playback and record are not supported. 11.1.3 ON AAD performs full-function accessory detection. Playback and record are supported. All modes, their maximum current consumption, and functionality are listed in Table 23. Datasheet CFR0011-120-00 Revision 3.4 29 of 128 24-Dec-2021 © 2021 Renesas Electronics DA7219 Audio Codec with Advanced Accessory Detect Table 23: System States, Configuration, and Current Consumption Configuration Typical current consumption CODEC Comments Mode VDD + VDD_IO VDD_MIC system_active MCLK PLL mode AAD config OFF OFF OFF N/A N/A N/A N/A N/A DEEP SLEEP ON ON 0 N/A N/A N/A OFF Audio path AAD VDD + VDD_IO VDD_MIC N/A N/A N/A None None N/A OFF OFF OFF