W78L32/W78L032A/W78M032A
8-BIT MICROCONTROLLER
Table of Content1.
GENERAL DESCRIPTION ......................................................................................................... 2
2.
FEATURES ................................................................................................................................. 2
3.
PIN CONFIGURATIONS ............................................................................................................ 3
4.
PIN DESCRIPTION..................................................................................................................... 4
5.
BLOCK DIAGRAM ...................................................................................................................... 6
6.
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 8
8.
DC CHARACTERISTICS............................................................................................................ 8
9.
AC CHARACTERISTICS .......................................................................................................... 10
10.
TIMING WAVEFORMS ............................................................................................................. 12
11.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 14
12.
PACKAGE DIMENSIONS ......................................................................................................... 16
13.
REVISION HISTORY ................................................................................................................ 18
-1-
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
1. GENERAL DESCRIPTION
The W78L32 microcontroller supplies a wider frequency range and supply voltages than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C32 microcontroller
series.
The W78L32 contains four 8-bit bidirectional parallel ports, three 16-bit timer/counters and a serial
port. These peripherals are supported by a six-source, two-level interrupt capability. There are 256
bytes of RAM, and the device supports ROMless operation for application programs.
The W78L32 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
Fully static design
y
Supply voltage of 1.8V to 5.5V
y
Low power consumption at full supply voltage
y
DC-24 MHz operation
y
256 bytes of on-chip scratchpad RAM
y
64K bytes program memory address space
y
64K bytes data memory address space
y
Four 8-bit bidirectional ports
y
Three 16-bit timer/counters
y
One full duplex serial port
y
Boolean processor
y
Six-source, two-level interrupt capability
y
y
Built-in power management
Packages:
− DIP 40:
W78L32-24
− PLCC 44: W78L32P-24
− QFP 44: W78L32F-24
− Lead Free (RoHS) DIP 40:
W78L032A24DL, W78M032A24DL
− Lead Free (RoHS) PLCC 44: W78L032A24PL, W78M032A24PL
− Lead Free (RoHS) PQFP 44: W78L032A24FL, W78M032A24FL
-2-
W78L32/W78L032A/W78M032A
3. PIN CONFIGURATIONS
40-Pin DIP (W78L32)
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
44-Pin PLCC (W78L32P)
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
P1.5
P1.6
P1.7
RST
RXD, P3.0
NC
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
3
.
7
,
/
R
D
X
T
A
L
2
A
T
D
2
0
,
,
P
P
1
V 0
. N D .
0 C D 0
X V N P
T S C 2
A S
.
L
0
1
,
A
8
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
P2.0, A8
44-Pin QFP (W78L32F)
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
T
2
E
X
,
P P P P
1 1 1 1
. . . .
4 3 2 1
A
D
3
,
P
0
.
3
6 5 4 3 2 1 44 43 42 41 40
7
39
8
38
9
37
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 19 20 21 22 23 24 25 26 27 28
P
3
.
6
,
/
W
R
VDD
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P1.5
P1.6
P1.7
RST
RXD, P3.0
NC
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
2
.
4
,
A
1
2
A
D
0
,
P
0
.
0
A
D
1
,
P
0
.
1
A
D
2
,
P
0
.
2
A
D
3
,
P
0
.
3
44 43 42 41 40 39 38 37 36 35 34
33
32
31
3
30
4
29
5
28
6
27
7
26
8
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
1
2
P
3
.
6
,
/
W
R
-3-
T
2
,
P
1
V
. N D
0 C D
P
3
.
7
,
/
R
D
X
T
A
L
2
X V N P
T S C 2
A S
.
L
0
1
,
A
8
P
2
.
1
,
A
9
P
2
.
2
,
A
1
0
P
2
.
3
,
A
1
1
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
EA
NC
ALE
PSEN
P2.7, A15
P2.6, A14
P2.5, A13
P
2
.
4
,
A
1
2
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
4. PIN DESCRIPTION
P0.0−P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0−P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups. Pins P1.0 and P1.1
also serve as T2 (Timer 2 external input) and T2EX (Timer 2 capture/reload trigger), respectively.
P2.0−P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0−P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
ALTERNATE FUNCTION
P3.0
RXD Serial Receive Data
P3.1
TXD Serial Transmit Data
P3.2
INT0 External Interrupt 0
P3.3
INT1 External Interrupt 1
P3.4
T0 Timer 0 Input
P3.5
T1 Timer 1 Input
P3.6
WR Data Write Strobe
P3.7
RD Data Read Strobe
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM. This
pin should be kept low for all W78L32 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
ALE
Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high state during reset with a weak
pull-up.
-4-
W78L32/W78L032A/W78M032A
PSEN
Program Store Enable Output, active low. PSEN enables the external ROM onto the Port 0
address/data bus during fetch and MOVC operations. PSEN goes to a high state during reset with a
weak pull-up.
XTAL1
Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.
XTAL2
Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.
VSS, VDD
Power Supplies. These are the chip ground and positive supplies.
-5-
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
5. BLOCK DIAGRAM
RAM
SFR
256
Bytes
Port 0
Port 1
Alternate
Tim er 2
Port 2
CPU
Port 3
Data Bus
Alternate
CORE
Serial
Port
Timer 0
Interrupt
Tim er 1
INT 0
INT 1
-6-
W78L32/W78L032A/W78M032A
6. FUNCTIONAL DESCRIPTION
The W78L32 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different instruction and references both a 64K program address space and a 64K data storage
space.
Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C31. Timer 2 is a special feature
of the W78L32: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, autoreload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
Clock
The W78L32 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78L32 relatively insensitive to duty cycle
variations in the clock.
Crystal Oscillator
The W78L32 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.
External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input one level of greater than 3.5 volts when VDD = 5V.
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.
-7-
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78L32 is used with an external RC network. The reset logic also has
a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
VCC−VSS
-0.3
+7.0
V
Input Voltage
VIN
VSS -0.3
VCC +0.3
V
Operating Temperature
TA
0
70
°C
Storage Temperature
TST
-55
+150
°C
DC Power Supply
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. DC CHARACTERISTICS
(VDD−VSS = 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER
SYM.
PECIFICATION
MIN.
MAX.
UNIT
TEST CONDITIONS
Operating Voltage
VDD
1.8
5.5
V
Operating Current
IDD
-
20
mA
No load, VDD = 5.5V, 20 MHz
-
3
mA
No load, VDD = 2.0V, 16 MHz
-
6
mA
VDD = 5.5V, Fosc = 20 MHz
-
1.5
mA
VDD = 2.0V, Fosc =16 MHz
-
50
µA
VDD = 5.5V, Fosc = 20 MHz
-
20
µA
VDD = 2.0V, Fosc = 16 MHz
Idle Current
Power Down Current
IIDLE
IPWDN
Input Current
P1, P2, P3
IIN1
-50
+10
µA
VDD = 5.5V
VIN = 0V or VDD
Input Current
RST
IIN2
-10
+300
µA
VDD = 5.5V
0 < VIN < VDD
ILK
-10
+10
µA
VDD = 5.5V
0V < VIN < VDD
ITL [*4]
-500
-
µA
VDD = 5.5V
VIN = 2.0V
Input Leakage Current
P0, EA
Logic 1 to 0 Transition
Current
P1, P2, P3
-8-
W78L32/W78L032A/W78M032A
DC Characteristics, continued
PARAMETER
Input Low Voltage
SYM.
UNIT
TEST CONDITIONS
0.8
V
VDD = 4.5V
0
0.5
V
VDD = 2.0V
0
0.8
V
VDD = 4.5V
0
0.3
V
VDD = 2.0V
0
0.8
V
VDD = 4.5V
0
0.6
V
VDD = 2.0V
2.4
VDD +0.2
V
VDD = 5.5V
1.4
VDD +0.2
V
VDD = 2.0V
3.5
VDD +0.2
V
VDD = 5.5V
1.7
VDD +0.2
V
VDD = 2.0V
3.5
VDD +0.2
V
VDD = 5.5V
1.6
VDD +0.2
V
VDD = 2.0V
VOL1
-
0.45
V
VDD = 4.5V, IOL = +2 mA
-
0.25
V
VDD = 2.0V, IOL = +1 mA
VOL2
-
0.45
V
VDD = 4.5V, IOL = +4 mA
-
0.25
V
VDD = 2.0V, IOL = +2 mA
4
9
mA
VDD = 4.5V, Vin = 0.45V
1.8
5.4
mA
VDD = 2.0V, Vin = 0.45V
8
16
mA
VDD = 4.5V, Vin = 0.45V
4.5
9
mA
VDD = 2.0V, Vin = 0.45V
2.4
-
V
VDD = 4.5V, IOH = -100 µA
1.4
-
V
VDD = 2.0V, IOH = -8 µA
2.4
-
V
VDD = 4.5V, IOH = -400 µA
1.4
-
V
VDD = 2.0V, IOH = -200 µA
-100
-250
µA
VDD = 4.5V,Vin = 2.4V
-12
-30
µA
VDD = 2.0V,Vin = 1.4V
-8
-16
mA
VDD = 4.5V,Vin = 2.4V
-1.4
-2.4
mA
VDD = 2.0V,Vin = 1.4V
VIL1
P0, P1, P2, P3, EA
Input Low Voltage
VIL2
RST
Input Low Voltage
VIL3
XTAL1 [*4]
Input High Voltage
VIH1
P0, P1, P2, P3, EA
Input High Voltage
VIH2
RST
Input High Voltage
VIH3
XTAL1 [*4]
Output Low Voltage
P1, P2, P3
Output Low Voltage
P0, ALE, PSEN [*3]
Sink Current
ISK1
P1, P2, P3
Sink Current
ISK2
P0, ALE, PSEN
Output High Voltage
VOH1
P1, P2, P3
Output High Voltage
VOH2
P0, ALE, PSEN [*3]
Source Current
ISR1
P1, P2, P3
Source Current
P0, ALE, PSEN
PECIFICATION
ISR2
MIN.
MAX.
0
Notes:
*1. RST pin is a Schmitt trigger input.
*3. P0, ALE and /PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input.
*5. Pins of P1, P2, P3 can source a transition current when they are being externally driven from 1 to 0.
-9-
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
9. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.5 micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
T CH
T CL
F OP,
PARAMETER
Operating Speed
Clock Period
Clock High
Clock Low
TCP
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
FOP
TCP
TCH
TCL
0
41.7
20
20
-
24
-
MHz
nS
nS
nS
1
2
3
3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
Program Fetch Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
Address Valid to ALE Low
TAAS
1 TCP-∆
-
-
nS
4
Address Hold after ALE Low
TAAH
1 TCP-∆
-
-
nS
1, 4
ALE Low to PSEN Low
TAPL
1 TCP-∆
-
-
nS
4
PSEN Low to Data Valid
TPDA
-
-
2 TCP
nS
2
Data Hold after PSEN High
TPDH
0
-
1 TCP
nS
3
Data Float after PSEN High
TPDZ
0
-
1 TCP
nS
ALE Pulse Width
TALW
2 TCP-∆
2 TCP
-
nS
4
PSEN Pulse Width
TPSW
3 TCP-∆
3 TCP
-
nS
4
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "∆" (due to buffer driving delay and wire loading) is 20 nS.
- 10 -
W78L32/W78L032A/W78M032A
Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTES
ALE Low to RD Low
TDAR
3 TCP-∆
-
3 TCP+∆
nS
1, 2
RD Low to Data Valid
TDDA
-
-
4 TCP
nS
1
Data Hold after RD High
TDDH
0
-
2 TCP
nS
Data Float after RD High
TDDZ
0
-
2 TCP
nS
RD Pulse Width
TDRD
6 TCP-∆
6 TCP
-
nS
2
Notes:
1. Data memory access time is 8 TCP.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
ALE Low to WR Low
TDAW
3 TCP-∆
-
3 TCP+∆
nS
Data Valid to WR Low
TDAD
1 TCP-∆
-
-
nS
Data Hold from WR High
TDWD
1 TCP-∆
-
-
nS
WR Pulse Width
TDWR
6 TCP-∆
6 TCP
-
nS
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
Port Access Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Port Input Setup to ALE Low
TPDS
1 TCP
-
-
nS
Port Input Hold from ALE Low
TPDH
0
-
-
nS
Port Output to ALE
TPDA
1 TCP
-
-
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
- 11 -
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
10. TIMING WAVEFORMS
Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
TALW
ALE
TAPL
PSEN
TPSW
TAAS
PORT 2
TPDA
TAAH
TPDH, TPDZ
PORT 0
Code
A0-A7
Data
A0-A7
Code
A0-A7
Data
A0-A7
Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
PSEN
PORT 2
A8-A15
A0-A7
DATA
PORT 0
TDAR
TDDA
T DDH, T DDZ
RD
TDRD
- 12 -
S1
S2
S3
W78L32/W78L032A/W78M032A
Timing Waveforms, continued
Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
PORT 0
A8-A15
A0-A7
DATA OUT
TDWD
TDAD
WR
TDAW
T DWR
Port Access Cycle
S5
S6
S1
XTAL1
ALE
TPDS
TPDA
TPDH
PORT
DATA OUT
INPUT
SAMPLE
- 13 -
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
11. TYPICAL APPLICATION CIRCUITS
Using External Program Memory and Crystal
VDD
31
19 XTAL1
10 u
CRYSTAL
R 18
XTAL2
8.2 K
9
C1
EA
C2
RST
12
13
14
15
INT0
INT1
T0
T1
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39 AD0
38 AD1
37 AD2
36 AD3
35 AD4
34 AD5
33 AD6
32 AD7
AD0 3
AD1 4
AD2 7
AD3 8
AD413
AD514
AD617
AD718
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
GND 1 OC
11 G
A8
A9
A10
A11
A12
A13
A14
A15
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2 A0
5 A1
6 A2
9 A3
12 A4
15 A5
16 A6
19 A7
74LS373
A0 10
A1 9
A2 8
A3 7
A4 6
A5 5
A6 4
A7 3
A8 25
A9 24
A10 21
A11 23
A12 2
A13 26
A14 27
A15 1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
O0
O1
O2
O3
O4
O5
O6
O7
11
12
13
15
16
17
18
19
GND20 CE
22
OE
RD 17
WR 16
29
PSEN
30
ALE 11
TXD
10
RXD
27512
W78L32
Figure A
CRYSTAL
C1
C2
R
16 MHz
30P
30P
-
24 MHz
15P
15P
-
Above table shows the reference values for crystal applications.
Note: C1, C2, R components refer to Figure A.
- 14 -
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
W78L32/W78L032A/W78M032A
Typical Application Circuits, continued
Expanded External Data Memory and Oscillator
VDD
31
19
10 u
8.2 K
OSCILLATOR
EA
XTAL1
18
XTAL2
9
RST
12
13
14
15
1
2
3
4
5
6
7
8
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
39
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
21
22
23
24
25
26
27
28
A8
A9
A10
A11
A12
A13
A14
RD
17
16
29
30
11
10
WR
PSEN
ALE
TXD
RXD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND 1 OC
11 G
74LS373
2
5
6
9
12
15
16
19
A0
A1
A2
A3
A4
A5
A6
A7
10
9
8
7
6
5
4
3
25
24
21
23
2
26
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND 20
22
27
CE
OE
WR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
D0
D1
D2
D3
D4
D5
D6
D7
11
12
13
15
16
17
18
19
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
20256
W78L32
Figure B
- 15 -
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
12. PACKAGE DIMENSIONS
40-pin DIP
Dimension in inchDimension in mm
Min. Nom. Max. Min. Nom. Max.
Symbol
A
A1
A2
B
B1
c
D
E
E1
e1
L
D
40
21
E1
A A2
A1
Base Plane
Seating Plane
B
e1
eA
a
B1
0.406 0.457 0.559
0.048 0.050 0.054
1.219 1.27
0.008 0.010 0.014
0.203 0.254 0.356
2.055 2.070
52.20 52.58
3.937 4.064
0.090 0.100 0.110 2.286
2.54
0.120 0.130 0.140 3.048
3.302 3.556
0
0
15
15
0.090
2.286
HD
D
1
44
40
7
Symbol
39
E
17
HE
GE
29
18
28
c
L
e
b
b1
0.185
4.699
0.508
0.020
0.145
0.150
0.155
3.683
3.81
3.937
0.026
0.028
0.032
0.66
0.711
0.813
0.016
0.018
0.022
0.406
0.457
0.559
0.008
0.010
0.014
0.203
0.254
0.356
0.648
0.653
0.658
16.46
16.59
16.71
0.648
0.653
0.658
16.46
16.59
16.71
0.050
BSC
1.27
A1
y
GD
- 16 -
BSC
0.590
0.610
0.630
14.99
15.49
0.590
0.610
0.630
14.99
15.49
16.00
0.680
0.690
0.700
17.27
17.53
17.78
16.00
0.680
0.690
0.700
17.27
17.53
17.78
0.090
0.100
0.110
2.296
2.54
2.794
0.004
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
θ
Seating Plane
A
A1
A2
b1
b
c
D
E
e
GD
GE
HD
HE
L
y
Dimension in inch Dimension in mm
Min. Nom. Max. Min. Nom. Max.
Notes:
A2 A
2.794
0.630 0.650 0.670 16.00 16.51 17.01
44-pin PLCC
6
1.372
1. Dimension D Max. & S include mold flash or
tie bar burrs.
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the.mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
c
L
3.81
0.016 0.018 0.022
Notes:
E
S
0.150 0.155 0.160
0.540 0.545 0.550 13.72 13.84 13.97
eA
S
20
0.254
0.590 0.600 0.610 14.986 15.24 15.494
a
1
5.334
0.210
0.010
0.10
W78L32/W78L032A/W78M032A
Package Dimensions, continued
44-pin QFP
HD
Dimension in inch
D
A
A1
A2
b
c
D
E
e
HD
HE
L
L1
y
θ
33
1
E HE
11
12
e
b
Dimension in mm
Symbol Min. Nom. Max. Min. Nom. Max.
34
44
22
---
---
---
---
0.002 0.01
0.02
0.05
0.25
0.5
0.075 0.081 0.087
1.90
2.05
2.20
0.01
0.25
0.35
0.45
---
0.014 0.018
---
0.004 0.006 0.010
0.101 0.152 0.254
0.390 0.394 0.398
9.9
10.00
10.1
0.390 0.394 0.398
9.9
10.00
10.1
0.025 0.031 0.036
0.635
0.80
0.952
0.510 0.520 0.530 12.95
13.2
13.45
0.510 0.520 0.530 12.95 13.2
13.45
0.65
0.8
0.95
0.051 0.063 0.075 1.295
1.6
1.905
0.025 0.031 0.037
0.08
0.003
0
7
0
7
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
c
A2 A
Seating Plane
See Detail F
A1
y
θ
L
L1
Detail F
- 17 -
Publication Release Date: March 7, 2006
Revision A5
W78L32/W78L032A/W78M032A
13. REVISION HISTORY
VERSION
DATE
PAGE
REASONS FOR CHANGE
A2
October 2000
A3
April 20, 2005
16
Add Important Notice
A4
December 21, 2005
2
Add lead-free(RoHS) parts
A5
March 7, 2006
2
Add 2nd lead-free(RoHS) parts
-
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
Winbond Electronics Corporation America
Winbond Electronics (Shanghai) Ltd.
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
- 18 -
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