NuMicro NUC200/220 Series
Datasheet
NuMicro™ NUC200/220 Series
Datasheet
Nuvoton is providing this document only for reference purposes of NuMicroTM microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com
June 06, 2014
Page 1 of 98
Revision 1.00
NUMICRO™ NUC200/220 DATASHEET
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
NuMicro NUC200/220 Series
Datasheet
Table of Contents
LIST OF FIGURES .................................................................................................................................. 5
LIST OF TABLES .................................................................................................................................... 6
1
GENERAL DESCRIPTION ......................................................................................................... 7
2
FEATURES ................................................................................................................................. 8
NUMICRO™ NUC200/220 DATASHEET
3
2.1
NuMicro NUC200 Features – Advanced Line.............................................................. 8
2.2
NuMicro NUC220 Features – USB Line .................................................................... 12
PARTS INFORMATION LIST AND PIN CONFIGURATION .................................................... 16
3.1
3.2
3.3
4
5
NuMicro NUC200/220xxxAN Selection Guide ........................................................... 16
3.1.1
NuMicro NUC200 Advanced Line Selection Guide ...................................................... 16
3.1.2
NuMicro NUC220 USB Line Selection Guide .............................................................. 16
Pin Configuration .......................................................................................................... 18
3.2.1
NuMicro NUC200 Pin Diagram .................................................................................... 18
3.2.2
NuMicro NUC220 Pin Diagram .................................................................................... 21
Pin Description .............................................................................................................. 24
3.3.1
NuMicro NUC200 Pin Description ............................................................................... 24
3.3.2
NuMicro NUC220 Pin Description ............................................................................... 31
BLOCK DIAGRAM .................................................................................................................... 38
4.1
NuMicro NUC200 Block Diagram .............................................................................. 38
4.2
NuMicro NUC220 Block Diagram .............................................................................. 39
FUNCTIONAL DESCRIPTION.................................................................................................. 40
®
5.1
ARM Cortex™-M0 Core .............................................................................................. 40
5.2
System Manager ........................................................................................................... 42
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.3
Clock Controller ............................................................................................................ 54
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.4
Overview ........................................................................................................................ 60
Features ......................................................................................................................... 60
General Purpose I/O (GPIO) ........................................................................................ 61
5.5.1
June 06, 2012
Overview ........................................................................................................................ 54
Clock Generator ............................................................................................................. 56
System Clock and SysTick Clock ................................................................................... 57
Peripherals Clock ........................................................................................................... 58
Power-down Mode Clock................................................................................................ 58
Frequency Divider Output............................................................................................... 59
USB Device Controller (USB) ....................................................................................... 60
5.4.1
5.4.2
5.5
Overview ........................................................................................................................ 42
System Reset ................................................................................................................. 42
System Power Distribution ............................................................................................. 43
System Memory Map...................................................................................................... 45
System Timer (SysTick) ................................................................................................. 47
Nested Vectored Interrupt Controller (NVIC) .................................................................. 48
System Control (SCS) .................................................................................................... 54
Overview ........................................................................................................................ 61
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Datasheet
5.5.2
5.6
5.6.1
5.6.2
5.7
June 06, 2014
Overview ...................................................................................................................... 75
Features ....................................................................................................................... 75
Overview ...................................................................................................................... 76
Features ....................................................................................................................... 76
PDMA Controller (PDMA) ............................................................................................. 77
Overview ...................................................................................................................... 77
Features ....................................................................................................................... 77
Smart Card Host Interface (SC).................................................................................... 78
5.19.1
5.19.2
5.20
Overview ...................................................................................................................... 74
Features ....................................................................................................................... 74
Analog Comparator (ACMP) ......................................................................................... 76
5.18.1
5.18.2
5.19
2
Analog-to-Digital Converter (ADC) ............................................................................... 75
5.17.1
5.17.2
5.18
Overview ...................................................................................................................... 73
Features ....................................................................................................................... 73
Overview ...................................................................................................................... 78
Features ....................................................................................................................... 78
FLASH MEMORY CONTROLLER (FMC) .................................................................... 79
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NUMICRO™ NUC200/220 DATASHEET
2
5.16.1
5.16.2
5.17
Overview ...................................................................................................................... 70
Features ....................................................................................................................... 72
I S Controller (I S) ........................................................................................................ 74
5.15.1
5.15.2
5.16
Overview ...................................................................................................................... 69
Features ....................................................................................................................... 69
PS/2 Device Controller (PS2D)..................................................................................... 73
5.14.1
5.14.2
5.15
Overview ...................................................................................................................... 69
Features ....................................................................................................................... 69
UART Interface Controller (UART) ............................................................................... 70
5.13.1
5.13.2
5.14
Overview ...................................................................................................................... 68
Features ....................................................................................................................... 68
Window Watchdog Timer (WWDT)............................................................................... 69
5.12.1
5.12.2
5.13
Overview ........................................................................................................................ 67
Features ......................................................................................................................... 67
Watchdog Timer (WDT) ................................................................................................ 69
5.11.1
5.11.2
5.12
Overview ........................................................................................................................ 66
Features ......................................................................................................................... 66
Timer Controller (TMR) ................................................................................................. 68
5.10.1
5.10.2
5.11
Overview ........................................................................................................................ 64
Features ......................................................................................................................... 65
Serial Peripheral Interface (SPI) ................................................................................... 67
5.9.1
5.9.2
5.10
Overview ........................................................................................................................ 62
Features ......................................................................................................................... 63
Real Time Clock (RTC) ................................................................................................. 66
5.8.1
5.8.2
5.9
2
PWM Generator and Capture Timer (PWM) ................................................................ 64
5.7.1
5.7.2
5.8
Features ......................................................................................................................... 61
2
I C Serial Interface Controller (I C) ............................................................................... 62
NuMicro NUC200/220 Series
Datasheet
5.20.1
5.20.2
6
ELECTRICAL CHARACTERISTICS ......................................................................................... 80
6.1
Absolute Maximum Ratings .......................................................................................... 80
6.2
DC Electrical Characteristics ........................................................................................ 81
6.3
AC Electrical Characteristics ........................................................................................ 87
NUMICRO™ NUC200/220 DATASHEET
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.4
6.5
8
External 4~24 MHz High Speed Oscillator ..................................................................... 87
External 4~24 MHz High Speed Crystal ......................................................................... 87
External 32.768 kHz Low Speed Crystal Oscillator ........................................................ 88
Internal 22.1184 MHz High Speed Oscillator.................................................................. 88
Internal 10 kHz Low Speed Oscillator............................................................................. 88
Analog Characteristics .................................................................................................. 89
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
7
Overview ...................................................................................................................... 79
Features ....................................................................................................................... 79
12-bit SARADC Specification ......................................................................................... 89
LDO and Power Management Specification ................................................................... 89
Low Voltage Reset Specification .................................................................................... 90
Brown-out Detector Specification ................................................................................... 90
Power-on Reset Specification ........................................................................................ 90
Temperature Sensor Specification ................................................................................. 91
Comparator Specification ............................................................................................... 91
USB PHY Specification .................................................................................................. 92
Flash DC Electrical Characteristics .............................................................................. 94
PACKAGE DIMENSIONS ......................................................................................................... 95
7.1
100-pin LQFP (14x14x1.4 mm footprint 2.0 mm) ......................................................... 95
7.2
64-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................................... 96
7.3
48-pin LQFP (7x7x1.4 mm footprint 2.0 mm) ............................................................... 97
REVISION HISTORY ................................................................................................................ 98
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Datasheet
List of Figures
Figure 3-1 NuMicro NUC200 Series Selection Code .................................................................. 17
Figure 3-2 NuMicro NUC200VxxAN LQFP 100-pin Diagram ..................................................... 18
Figure 3-3 NuMicro NUC200SxxAN LQFP 64-pin Diagram ....................................................... 19
Figure 3-4 NuMicro NUC200LxxAN LQFP 48-pin Diagram ........................................................ 20
Figure 3-5 NuMicro NUC220VxxAN LQFP 100-pin Diagram ..................................................... 21
Figure 3-6 NuMicro NUC220SxxAN LQFP 64-pin Diagram ....................................................... 22
Figure 3-7 NuMicro NUC220LxxAN LQFP 48-pin Diagram ........................................................ 23
Figure 4-1 NuMicro NUC200 Block Diagram .............................................................................. 38
Figure 4-2 NuMicro NUC220 Block Diagram .............................................................................. 39
Figure 5-1 Functional Controller Diagram ...................................................................................... 40
Figure 5-2 NuMicro NUC200 Power Distribution Diagram .......................................................... 43
Figure 5-3 NuMicro NUC220 Power Distribution Diagram .......................................................... 44
Figure 5-4 Clock Generator Global View Diagram......................................................................... 55
Figure 5-5 Clock Generator Block Diagram ................................................................................... 56
Figure 5-6 System Clock Block Diagram ....................................................................................... 57
Figure 5-7 SysTick Clock Control Block Diagram .......................................................................... 57
Figure 5-8 Clock Source of Frequency Divider .............................................................................. 59
2
Figure 5-18 I C Bus Timing ............................................................................................................ 62
Figure 6-1 Typical Crystal Application Circuit ................................................................................ 88
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NUMICRO™ NUC200/220 DATASHEET
Figure 5-9 Frequency Divider Block Diagram ................................................................................ 59
NuMicro NUC200/220 Series
Datasheet
List of Tables
Table 1-1 Connectivity Support Table .............................................................................................. 7
Table 5-1 Address Space Assignments for On-Chip Controllers ................................................... 46
Table 5-2 Exception Model ............................................................................................................ 49
Table 5-3 System Interrupt Map..................................................................................................... 50
NUMICRO™ NUC200/220 DATASHEET
Table 5-4 Vector Table Format ...................................................................................................... 51
Table 5-9 UART Baud Rate Equation ............................................................................................ 70
Table 5-10 UART Baud Rate Setting Table ................................................................................... 71
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NuMicro NUC200/220 Series
Datasheet
1
GENERAL DESCRIPTION
®
The NuMicro NUC200 Series 32-bit microcontrollers is embedded with the newest ARM
Cortex™-M0 core with a cost equivalent to traditional 8-bit MCU for industrial control and
applications requiring rich communication interfaces. The NuMicro NUC200 Series includes
NUC200 and NUC220 product lines.
The NuMicro NUC200 Advanced Line is embedded with the Cortex™-M0 core running up to 50
MHz and features 32K/64K/128K bytes flash, 8K/16K bytes embedded SRAM, and 4 Kbytes
loader ROM for the ISP. It is also equipped with plenty of peripheral devices, such as Timers,
Watchdog Timer, Window Watchdog Timer, RTC, PDMA with CRC calculation unit, UART, SPI,
2
2
I C, I S, PWM Timer, GPIO, PS/2, Smart Card Host, 12-bit ADC, Analog Comparator, Low
Voltage Reset Controller and Brown-out Detector.
The NuMicro NUC220 USB Line with USB 2.0 full-speed function is embedded with the
Cortex™-M0 core running up to 50 MHz and features 32K/64K/128K bytes flash, 8K/16K bytes
embedded SRAM, and 4 Kbytes loader ROM for the ISP. It is also equipped with plenty of
peripheral devices, such as Timers, Watchdog Timer, Window Watchdog Timer, RTC, PDMA with
2
2
CRC calculation unit, UART, SPI, I C, I S, PWM Timer, GPIO, PS/2, USB 2.0 FS Device, Smart
Card Host, 12-bit ADC, Analog Comparator, Low Voltage Reset Controller and Brown-out
Detector.
2
Product Line
UART
SPI
IC
NUC200
●
●
●
NUC220
●
●
●
USB
LIN
CAN
●
PS/2
IS
2
SC
●
●
●
●
●
●
Table 1-1 Connectivity Support Table
NUMICRO™ NUC200/220 DATASHEET
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NuMicro NUC200/220 Series
Datasheet
2
FEATURES
The equipped features are dependent on the product line and their sub products.
2.1
NuMicro NUC200 Features – Advanced Line
•
®
ARM Cortex™-M0 core
NUMICRO™ NUC200/220 DATASHEET
– Runs up to 50 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
• Built-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
•
Flash Memory
–
–
–
32K/64K/128K bytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for flash
– Configurable data flash address and size for 128 KB system, fixed 4 KB data flash for
the 32 KB and 64 KB system
– Supports 2-wired ICP update through SWD/ICE interface
– Supports fast parallel programming mode by external programmer
• SRAM Memory
– 8K/16K bytes embedded SRAM
– Supports PDMA mode
• PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
– Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC16 and CRC-32
• Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to
1 % at +25 ℃ and VDD = 5 V
Trimmed to
3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL, up to 50 MHz, for high performance system operation
– External 4~24 MHz high speed crystal input for precise timing operation
– External 32.768 kHz low speed crystal input for RTC function and low power system
operation
• GPIO
–
–
–
June 06, 2012
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin configured as interrupt source with edge/level setting
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NuMicro NUC200/220 Series
Datasheet
•
Timer
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
• Watchdog Timer
– Multiple clock sources
– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
• Window Watchdog Timer
•
– 6-bit down counter with 11-bit prescale for wide range window selected
RTC
–
–
–
–
–
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
– Supports battery power pin (VBAT)
– Supports wake-up function
• PWM/Capture
–
–
–
–
–
–
–
–
–
• SPI
–
–
–
–
–
–
–
–
June 06, 2014
Up to three UART controllers
UART ports with flow control (TXD, RXD, nCTS and nRTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
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NUMICRO™ NUC200/220 DATASHEET
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
– Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
– Supports Capture interrupt
• UART
NuMicro NUC200/220 Series
Datasheet
–
–
–
–
•
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
2
IC
NUMICRO™ NUC200/220 DATASHEET
–
–
–
–
–
–
–
–
–
–
2
• IS
2
Up to two sets of I C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
– Interface with external audio CODEC
– Operate as either Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports mono and stereo audio data
2
– Supports I S and MSB justified data format
– Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports two DMA requests, one for transmitting and the other for receiving
• PS/2 Device
– Host communication inhibit and request to send detection
– Reception frame error detection
– Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
– Double buffer for data reception
– Software override bus
• ADC
– 12-bit SAR ADC with 760 kSPS
– Up to 8-ch single-end input or 4-ch differential input
– Single scan/single cycle scan/continuous scan
– Each channel with individual result register
– Scan on enabled channels
– Threshold voltage detection
– Conversion started by software programming or external input
– Supports PDMA mode
• Analog Comparator
– Up to two analog comparators
– External input or internal Band-gap voltage selectable at negative node
– Interrupt when compare result change
– Supports Power-down wake-up
• Smart Card Host (SC)
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NuMicro NUC200/220 Series
Datasheet
–
–
–
–
–
–
–
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
– Supports auto inverse convention function
– Supports transmitter and receiver error retry and error limit function
– Supports hardware activation sequence process
– Supports hardware warm reset sequence process
– Supports hardware deactivation sequence process
– Supports hardware auto deactivation sequence when detecting the card removal
• 96-bit unique ID (UID)
•
One built-in temperature sensor with 1℃ resolution
•
Brown-out Detector
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
• Low Voltage Reset
– Threshold voltage level: 2.0 V
• Operating Temperature: -40℃ ~ 85℃
•
Packages:
–
–
All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin
NUMICRO™ NUC200/220 DATASHEET
June 06, 2014
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NuMicro NUC200/220 Series
Datasheet
2.2
NuMicro NUC220 Features – USB Line
•
®
ARM Cortex™-M0 core
NUMICRO™ NUC200/220 DATASHEET
– Runs up to 50 MHz
– One 24-bit system timer
– Supports low power sleep mode
– Single-cycle 32-bit hardware multiplier
– NVIC for the 32 interrupt inputs, each with 4-levels of priority
– Serial Wire Debug supports with 2 watchpoints/4 breakpoints
• Built-in LDO for wide operating voltage ranges from 2.5 V to 5.5 V
•
Flash Memory
–
–
–
32K/64K/128K bytes Flash for program code
4 KB flash for ISP loader
Supports In-System-Program (ISP) and In-Application-Program (IAP) application code
update
– 512 byte page erase for flash
– Configurable data flash address and size for 128 KB system, fixed 4 KB data flash for
the 32 KB and 64 KB system
– Supports 2-wired ICP update through SWD/ICE interface
– Supports fast parallel programming mode by external programmer
• SRAM Memory
– 8K/16K bytes embedded SRAM
– Supports PDMA mode
• PDMA (Peripheral DMA)
–
Supports 9 channels PDMA for automatic data transfer between SRAM and
peripherals
– Supports CRC calculation with four common polynomials, CRC-CCITT, CRC-8, CRC16 and CRC-32
• Clock Control
–
–
Flexible selection for different applications
Built-in 22.1184 MHz high speed oscillator for system operation
Trimmed to
1 % at +25 ℃ and VDD = 5 V
Trimmed to
3 % at -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V
– Built-in 10 kHz low speed oscillator for Watchdog Timer and Wake-up operation
– Supports one PLL, up to 50 MHz, for high performance system operation
– External 4~24 MHz high speed crystal input for USB and precise timing operation
– External 32.768 kHz low speed crystal input for RTC function and low power system
operation
• GPIO
–
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-drain output
Input only with high impendence
– TTL/Schmitt trigger input selectable
– I/O pin configured as interrupt source with edge/level setting
• Timer
June 06, 2012
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NuMicro NUC200/220 Series
Datasheet
– Supports 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit prescale counter
– Independent clock source for each timer
– Provides one-shot, periodic, toggle and continuous counting operation modes
– Supports event counting function
– Supports input capture function
• Watchdog Timer
– Multiple clock sources
– 8 selectable time-out period from 1.6 ms ~ 26.0 sec (depending on clock source)
– Wake-up from Power-down or Idle mode
– Interrupt or reset selectable on watchdog time-out
• Window Watchdog Timer
– 6-bit down counter with 11-bit prescale for wide range window selected
• RTC
–
–
–
–
–
–
Supports software compensation by setting frequency compensate register (FCR)
Supports RTC counter (second, minute, hour) and calendar counter (day, month, year)
Supports Alarm registers (second, minute, hour, day, month, year)
Selectable 12-hour or 24-hour mode
Automatic leap year recognition
Supports periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8,
1/4, 1/2 and 1 second
– Supports battery power pin (VBAT)
– Supports wake-up function
• PWM/Capture
–
–
–
–
–
–
–
–
–
• SPI
–
–
–
–
–
–
–
–
–
June 06, 2014
Up to three UART controllers
UART ports with flow control (TXD, RXD, nCTS and nRTS)
UART0 with 64-byte FIFO is for high speed
UART1/2(optional) with 16-byte FIFO for standard device
Supports IrDA (SIR) and LIN function
Supports RS-485 9-bit mode and direction control
Programmable baud-rate generator up to 1/16 system clock
Supports PDMA mode
Up to four sets of SPI controllers
The maximum SPI clock rate of Master can up to 36 MHz (chip working at 5V)
The maximum SPI clock rate of Slave can up to 18 MHz (chip working at 5V)
Supports SPI Master/Slave mode
Full duplex synchronous serial data transfer
Variable length of transfer data from 8 to 32 bits
MSB or LSB first data transfer
Rx and Tx on both rising or falling edge of serial clock independently
Two slave/device select lines in Master mode, and one slave/device select line in
Slave mode
Page 13 of 98
Revision 1.00
NUMICRO™ NUC200/220 DATASHEET
Up to four built-in 16-bit PWM generators providing eight PWM outputs or four
complementary paired PWM outputs
– Each PWM generator equipped with one clock source selector, one clock divider, one
8-bit prescaler and one Dead-Zone generator for complementary paired PWM
– Up to eight 16-bit digital capture timers (shared with PWM timers) providing eight
rising/falling capture inputs
– Supports Capture interrupt
• UART
NuMicro NUC200/220 Series
Datasheet
–
–
–
•
Supports Byte Suspend mode in 32-bit transmission
Supports PDMA mode
Supports three wire, no slave select signal, bi-direction interface
2
IC
NUMICRO™ NUC200/220 DATASHEET
–
–
–
–
–
–
–
–
–
–
2
• IS
2
Up to two sets of I C device
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and resume
serial transfer
Programmable clocks allowing for versatile rate control
Supports multiple address recognition (four slave address with mask option)
Supports wake-up function
– Interface with external audio CODEC
– Operate as either Master or Slave mode
– Capable of handling 8-, 16-, 24- and 32-bit word sizes
– Supports mono and stereo audio data
2
– Supports I S and MSB justified data format
– Provides two 8 word FIFO data buffers, one for transmitting and the other for receiving
– Generates interrupt requests when buffer levels cross a programmable boundary
– Supports two DMA requests, one for transmitting and the other for receiving
• PS/2 Device
– Host communication inhibit and request to send detection
– Reception frame error detection
– Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
– Double buffer for data reception
– Software override bus
• USB 2.0 Full-Speed Device
– One set of USB 2.0 FS Device 12 Mbps
– On-chip USB Transceiver
– Provides 1 interrupt source with 4 interrupt events
– Supports Control, Bulk In/Out, Interrupt and Isochronous transfers
– Auto suspend function when no bus signaling for 3 ms
– Provides 6 programmable endpoints
– Includes 512 Bytes internal SRAM as USB buffer
– Provides remote wake-up capability
• ADC
–
–
–
–
–
–
–
June 06, 2012
12-bit SAR ADC with 760 kSPS
Up to 8-ch single-end input or 4-ch differential input
Single scan/single cycle scan/continuous scan
Each channel with individual result register
Scan on enabled channels
Threshold voltage detection
Conversion started by software programming or external input
Page 14 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
– Supports PDMA mode
• Analog Comparator
– Up to two analog comparators
– External input or internal Band-gap voltage selectable at negative node
– Interrupt when compare result change
– Supports Power-down wake-up
• Smart Card Host (SC)
–
–
–
–
–
–
–
Compliant to ISO-7816-3 T=0, T=1
Supports up to three ISO-7816-3 ports
Separate receive / transmit 4 bytes entry FIFO for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
– Supports auto inverse convention function
– Supports transmitter and receiver error retry and error limit function
– Supports hardware activation sequence process
– Supports hardware warm reset sequence process
– Supports hardware deactivation sequence process
– Supports hardware auto deactivation sequence when detecting the card removal
• 96-bit unique ID (UID)
•
One built-in temperature sensor with 1℃ resolution
•
Brown-out Detector
NUMICRO™ NUC200/220 DATASHEET
– With 4 levels: 4.4 V/3.7 V/2.7 V/2.2 V
– Supports Brown-out Interrupt and Reset option
• Low Voltage Reset
– Threshold voltage level: 2.0 V
• Operating Temperature: -40℃ ~ 85℃
•
Packages:
–
–
June 06, 2014
All Green package (RoHS)
LQFP 100-pin / 64-pin / 48-pin
Page 15 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
3
PARTS INFORMATION LIST AND PIN CONFIGURATION
3.1
3.1.1
NuMicro NUC200/220xxxAN Selection Guide
NuMicro NUC200 Advanced Line Selection Guide
NUMICRO™ NUC200/220 DATASHEET
Part number
APROM RAM
Data
Flash
ISP
Loader
ROM
Connectivity
I/O
I2S
Timer
UART SPI
I2C
SC Comp. PWM
ADC
USB LIN CAN
RTC ISP Package
ICP
IAP
NUC200LC2AN
32 KB
8 KB
4 KB
4 KB
up to 35 4x32-bit
2
1
2
-
-
-
1
2
1
6
7x12-bit
v
v
LQFP48
NUC200LD2AN
64 KB
8 KB
4KB
4 KB
up to 35 4x32-bit
2
1
2
-
-
-
1
2
1
6
7x12-bit
v
v
LQFP48
NUC200LE3AN 128 KB 16 KB Definable
4 KB
up to 35 4x32-bit
2
1
2
-
-
-
1
2
1
6
7x12-bit
v
v
LQFP48
NUC200SC2AN
32 KB
8 KB
4 KB
4 KB
up to 49 4x32-bit
3
2
2
-
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC200SD2AN
64 KB
8 KB
4KB
4 KB
up to 49 4x32-bit
3
2
2
-
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC200SE3AN 128 KB 16 KB Definable
4 KB
up to 49 4x32-bit
3
2
2
-
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC200VE3AN 128 KB 16 KB Definable
4 KB
up to 83 4x32-bit
3
4
2
-
-
-
1
3
2
8
8x12-bit
v
v
LQFP100
3.1.2
NuMicro NUC220 USB Line Selection Guide
Part number
APROM RAM
Data
Flash
ISP
Loader
ROM
Connectivity
I/O
I2S
Timer
UART SPI
2
IC
SC Comp. PWM
ADC
USB LIN CAN
ISP
RTC ICP Package
IAP
NUC220LC2AN
32 KB
8 KB
4 KB
4 KB
up to 31 4x32-bit
2
1
2
1
-
-
1
2
1
4
7x12-bit
v
v
LQFP48
NUC220LD2AN
64 KB
8 KB
4 KB
4 KB
up to 31 4x32-bit
2
1
2
1
-
-
1
2
1
4
7x12-bit
v
v
LQFP48
NUC220LE3AN 128 KB 16 KB Definable
4 KB
up to 31 4x32-bit
2
1
2
1
-
-
1
2
1
4
7x12-bit
v
v
LQFP48
NUC220SC2AN
32 KB
8 KB
4 KB
4 KB
up to 45 4x32-bit
2
2
2
1
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC220SD2AN
64 KB
8 KB
8 KB
4 KB
up to 45 4x32-bit
2
2
2
1
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC220SE3AN 128 KB 16 KB Definable
4 KB
up to 45 4x32-bit
2
2
2
1
-
-
1
2
2
6
7x12-bit
v
v
LQFP64
NUC220VE3AN 128 KB 16 KB Definable
4 KB
up to 79 4x32-bit
3
4
2
1
-
-
1
3
2
8
8x12-bit
v
v
LQFP100
June 06, 2012
Page 16 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
NUC 2 0 0 - X X X X X
ARM-Based
32-bit Microcontroller
Temperature
CPU core
N: -40℃ ~ +85℃
E: -40℃ ~ +105℃
C: -40℃ ~ +125℃
1/2: Cortex-M0
5/7: ARM7
9: ARM9
Reserved
Function
RAM Size
1: 4KB
2: 8KB
3: 16KB
0: Advanced Line
2: USB Line
3: Automotive Line
4: Connectivity Line
APROM Size
C: 32KB
D: 64KB
E: 128KB
Package Type
L: LQFP 48
S: LQFP 64
V: LQFP 100
Figure 3-1 NuMicro NUC200 Series Selection Code
NUMICRO™ NUC200/220 DATASHEET
June 06, 2014
Page 17 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin Configuration
ICE_DAT
PA.12/PWM0/SC2_DAT
PA.13/PWM1/SC2_CLK
PA.14/PWM2/SC2_RST
PA.15/PWM3/I2S_MCLK/SC2_PWR
PC.8/SPI1_SS0
PC.9/SPI1_CLK
PC.10/SPI1_MISO0
PC.11/SPI1_MOSI0
PC.12/SPI1_MISO1
PC.13/SPI1_MOSI1
PE.0/PWM6
PE.1/PWM7
PE.2
PE.3
PE.4
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
66
AVSS
69
VDD
PA.0/ADC0/SC0_PWR
70
ICE_CLK
PA.1/ADC1/SC0_RST
71
67
PA.2/ADC2/SC0_CLK
72
68
PA.3/ADC3/SC0_DAT
73
SC1_RST/ADC5/PA.5
76
50
PB.9/TM1/SPI1_SS1
SC1_CLK/ADC6/PA.6
77
49
PB.10/TM2/SPI0_SS1
SC1_DAT/ADC7/SPI2_SS1/PA.7
78
48
PB.11/TM3/PWM4
VREF
79
47
PE.5/TM1_EXT/PWM5
AVDD
80
46
PE.6
SPI2_SS0/PD.0
81
45
PC.0/SPI0_SS0/I2S_LRCK
SPI2_CLK/PD.1
82
44
PC.1/SPI0_CLK/I2S_BCLK
SPI2_MISO0/PD.2
83
43
PC.2/SPI0_MISO0/I2S_DI
SPI2_MOSI0/PD.3
84
42
PC.3/SPI0_MOSI0/I2S_DO
SPI2_MISO1/PD.4
85
41
PC.4/SPI0_MISO1
SPI2_MOSI1/PD.5
86
40
PC.5/SPI0_MOSI1
SC1_CD/CMP0_N/PC.7
87
39
PD.15/UART2_TXD
SC0_CD/CMP0_P/PC.6
88
38
PD.14/UART2_RXD
CMP1_N/PC.15
89
37
PD.7
CMP1_P/PC.14
90
36
PD.6
TM0_EXT/INT1/PB.15
91
35
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
XT1_OUT/PF.0
92
34
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
XT1_IN/PF.1
93
33
PB.1/UART0_TXD
nRESET
94
32
PB.0/UART0_RXD
VSS
95
31
PE.7
VDD
96
30
PE.8
PS2_DAT/PF.2
97
29
PE.9
PS2_CLK/PF.3
98
28
PE.10
PVSS
99
27
PE.11
100
26
PE.12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PE.13
SPI3_SS1/INT0/PB.14
CMP1_O/PB.13
VBAT
X32_OUT
X32_IN
I2C1_SCL/PA.11
I2C1_SDA/PA.10
I2C0_SCL/PA.9
I2C0_SDA/PA.8
SPI3_SS0/PD.8
SPI3_CLK/PD.9
SPI3_MISO0/PD.10
SPI3_MOSI0/PD.11
SPI3_MISO1/PD.12
SPI3_MOSI1/PD.13
UART1_RXD/PB.4
UART1_TXD/PB.5
UART1_nRTS/PB.6
UART1_nCTS/PB.7
LDO_CAP
VDD
VSS
CLKO/TM0/STADC/PB.8
NUC200VxxAN
LQFP 100-pin
PE.14
NUMICRO™ NUC200/220 DATASHEET
PA.4/ADC4/SC1_PWR
NuMicro NUC200 Pin Diagram
NuMicro NUC200VxxAN LQFP 100-pin
74
3.2.1.1
75
3.2.1
PE.15
3.2
Figure 3-2 NuMicro NUC200VxxAN LQFP 100-pin Diagram
June 06, 2012
Page 18 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
ICE_CLK
ICE_DAT
PA.12/PWM0/SC2_DAT
PA.13/PWM1/SC2_CLK
PA.14/PWM2/SC2_RST
PA.15/PWM3/I2S_MCLK/SC2_PWR
PC.8/SPI1_SS0
41
40
39
38
37
36
PC.11/SPI1_MOSI0
AVSS
42
33
PA.0/ADC0/SC0_PWR
43
PC.9/SPI1_CLK
PA.1/ADC1/SC0_RST
44
PC.10/SPI1_MISO0
PA.2/ADC2/SC0_CLK
45
34
PA.3/ADC3/SC0_DAT
46
35
PA.4/ADC4
47
NuMicro NUC200RxxAN LQFP 64-pin
48
3.2.1.2
ADC5/PA.5
49
32
PB.9/TM1
ADC6/PA.6
50
31
PB.10/TM2
VREF
51
30
PB.11/TM3/PWM4
AVDD
52
29
PE.5/TM1_EXT/PWM5
CMP0_N/PC.7
53
28
PC.0/SPI0_SS0/I2S_LRCK
SC0_CD/CMP0_P/PC.6
54
27
PC.1/SPI0_CLK/I2S_BCLK
CMP1_N/PC.15
55
26
PC.2/SPI0_MISO0/I2S_DI
CMP1_P/PC.14
56
25
PC.3/SPI0_MOSI0/I2S_DO
TM0_EXT/INT1/PB.15
57
24
PD.15/UART2_TXD
XT1_OUT/PF.0
58
23
PD.14/UART2_RXD
XT1_IN/PF.1
59
22
PD.7
nRESET
60
21
PD.6
VSS
61
20
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
VDD
62
19
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
PVSS
63
18
PB.1/UART0_TXD
CLKO/TM0/STADC/PB.8
64
17
PB.0/UART0_RXD
10
11
12
13
14
15
16
UART1_RXD/PB.4
UART1_TXD/PB.5
UART1_nRTS/PB.6
UART1_nCTS/PB.7
LDO_CAP
VDD
VSS
9
6
I2C1_SCL/PA.11
I2C0_SDA/PA.8
5
X32_IN
8
4
X32_OUT
I2C0_SCL/PA.9
3
VBAT
7
2
I2C1_SDA/PA.10
1
INT0/PB.14
NUMICRO™ NUC200/220 DATASHEET
CMP1_O/PB.13
NUC200SxxAN
LQFP 64-pin
Figure 3-3 NuMicro NUC200SxxAN LQFP 64-pin Diagram
June 06, 2014
Page 19 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
ICE_DAT
PA.12/PWM0/SC2_DAT
PA.13/PWM1/SC2_CLK
PA.14/PWM2/SC2_RST
PA.15/PWM3/I2S_MCLK/SC2_PWR
29
28
27
26
25
PA.0/ADC0/SC0_PWR
32
AVSS
PA.1/ADC1/SC0_RST
33
ICE_CLK
PA.2/ADC2/SC0_CLK
34
30
PA.3/ADC3/SC0_DAT
31
PA.4/ADC4
ADC5/PA.5
37
24
PB.9/TM1
ADC6/PA.6
38
23
PB.10/TM2
VREF
39
22
PB.11/TM3/PWM4
AVDD
40
21
PE.5/TM1_EXT/PWM5
CMP0_N/PC.7
41
20
PC.0/SPI0_SS0/I2S_LRCK
SC0_CD/CMP0_P/PC.6
42
19
PC.1/SPI0_CLK/I2S_BCLK
TM0_EXT/INT1/PB.15
43
18
PC.2/SPI0_MISO0/I2S_DI
XT1_OUT/PF.0
44
XT1_IN/PF.1
NUC200LxxAN
LQFP 48-pin
10
11
12
VSS
9
UART1_TXD/PB.5
VDD
8
UART1_RXD/PB.4
LDO_CAP
7
PB.0/UART0_RXD
I2C0_SDA/PA.8
13
6
48
I2C0_SCL/PA.9
CLKO/TM0/STADC/PB.8
5
PB.1/UART0_TXD
I2C1_SDA/PA.10
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
14
4
15
47
3
46
PVSS
X32_IN
nRESET
I2C1_SCL/PA.11
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
2
16
1
PC.3/SPI0_MOSI0/I2S_DO
45
VBAT
17
X32_OUT
NUMICRO™ NUC200/220 DATASHEET
35
NuMicro NUC200LxxAN LQFP 48-pin
36
3.2.1.3
Figure 3-4 NuMicro NUC200LxxAN LQFP 48-pin Diagram
June 06, 2012
Page 20 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
PC.11/SPI1_MOSI0
PC.12/SPI1_MISO1
PC.13/SPI1_MOSI1
PE.0/PWM6
PE.1/PWM7
PE.2
PE.3
PE.4
57
56
55
54
53
52
51
PC.8/SPI1_SS0
58
PA.15/PWM3/I2S_MCLK/SC2_PWR
61
PC.9/SPI1_CLK
PA.14/PWM2/SC2_RST
62
PC.10/SPI1_MISO0
PA.13/PWM1/SC2_CLK
63
59
PA.12/PWM0/SC2_DAT
64
60
ICE_DAT
VSS
65
AVSS
69
66
PA.0/ADC0/SC0_PWR
70
VDD
PA.1/ADC1/SC0_RST
71
ICE_CLK
PA.2/ADC2/SC0_CLK
72
67
PA.3/ADC3/SC0_DAT
73
68
PA.4/ADC4/SC1_PWR
74
NuMicro NUC220 Pin Diagram
3.2.2.1 NuMicro NUC220VxxAN LQFP 100-pin
75
3.2.2
SC1_RST/ADC5/PA.5
76
50
PB.9/TM1/SPI1_SS1
SC1_CLK/ADC6/PA.6
77
49
PB.10/TM2/SPI0_SS1
SC1_DAT/ADC7/SPI2_SS1/PA.7
78
48
PB.11/TM3/PWM4
VREF
79
47
PE.5/TM1_EXT/PWM5
AVDD
80
46
PE.6
SPI2_SS0/PD.0
81
45
PC.0/SPI0_SS0/I2S_LRCK
82
44
PC.1/SPI0_CLK/I2S_BCLK
83
43
PC.2/SPI0_MISO0/I2S_DI
SPI2_MOSI0/PD.3
84
42
PC.3/SPI0_MOSI0/I2S_DO
SPI2_MISO1/PD.4
85
41
PC.4/SPI0_MISO1
SPI2_MOSI1/PD.5
86
40
PC.5/SPI0_MOSI1
SC1_CD/CMP0_N/PC.7
87
39
PD.15/UART2_TXD
SC0_CD/CMP0_P/PC.6
88
38
PD.14/UART2_RXD
CMP1_N/PC.15
89
37
PD.7
CMP1_P/PC.14
90
36
PD.6
TM0_EXT/INT1/PB.15
91
35
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
XT1_OUT/PF.0
92
34
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
XT1_IN/PF.1
93
33
PB.1/UART0_TXD
nRESET
94
32
PB.0/UART0_RXD
VSS
95
31
USB_D+
VDD
96
30
USB_D-
PS2_DAT/PF.2
97
29
USB_VDD33_CAP
PS2_CLK/PF.3
98
28
USB_VBUS
PVSS
99
27
PE.7
100
26
PE.8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PE.15
PE.14
PE.13
SPI3_SS1/INT0/PB.14
CMP1_O/PB.13
VBAT
X32_OUT
X32_IN
I2C1_SCL/PA.11
I2C1_SDA/PA.10
I2C0_SCL/PA.9
I2C0_SDA/PA.8
SPI3_SS0/PD.8
SPI3_CLK/PD.9
SPI3_MISO0/PD.10
SPI3_MOSI0/PD.11
SPI3_MISO1/PD.12
SPI3_MOSI1/PD.13
UART1_RXD/PB.4
UART1_TXD/PB.5
UART1_nRTS/PB.6
UART1_nCTS/PB.7
LDO_CAP
VDD
VSS
CLKO/TM0/STADC/PB.8
NUC220VxxAN
LQFP 100-pin
NUMICRO™ NUC200/220 DATASHEET
SPI2_CLK/PD.1
SPI2_MISO0/PD.2
Figure 3-5 NuMicro NUC220VxxAN LQFP 100-pin Diagram
June 06, 2014
Page 21 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
PA.4/ADC4
PA.3/ADC3/SC0_DAT
PA.2/ADC2/SC0_CLK
PA.1/ADC1/SC0_RST
PA.0/ADC0/SC0_PWR
AVSS
ICE_CLK
ICE_DAT
PA.12/PWM0/SC2_DAT
PA.13/PWM1/SC2_CLK
PA.14/PWM2/SC2_RST
PA.15/PWM3/I2S_MCLK/SC2_PWR
PC.8/SPI1_SS0
PC.9/SPI1_CLK
PC.10/SPI1_MISO0
PC.11/SPI1_MOSI0
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADC5/PA.5
49
32
PB.9/TM1
ADC6/PA.6
50
31
PB.10/TM2
VREF
51
30
PB.11/TM3/PWM4
AVDD
52
29
PE.5/TM1_EXT/PWM5
CMP0_N/PC.7
53
28
PC.0/SPI0_SS0/I2S_LRCK
SC0_CD/CMP0_P/PC.6
54
27
PC.1/SPI0_CLK/I2S_BCLK
CMP1_N/PC.15
55
26
PC.2/SPI0_MISO0/I2S_DI
CMP1_P/PC.14
56
25
PC.3/SPI0_MOSI0/I2S_DO
TM0_EXT/INT1/PB.15
57
24
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
XT1_OUT/PF.0
58
23
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
XT1_IN/PF.1
59
22
PB.1/UART0_TXD
nRESET
60
21
PB.0/UART0_RXD
VSS
61
20
USB_D+
NUC220SxxAN
LQFP 64-pin
11
12
13
14
15
16
UART1_TXD/PB.5
UART1_nRTS/PB.6
UART1_nCTS/PB.7
LDO_CAP
VDD
VSS
9
I2C0_SDA/PA.8
10
8
I2C0_SCL/PA.9
UART1_RXD/PB.4
7
6
I2C1_SCL/PA.11
I2C1_SDA/PA.10
5
X32_IN
USB_VBUS
4
17
X32_OUT
64
3
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
VBAT
USB_D-
18
2
19
63
1
62
INT0/PB.14
VDD
PVSS
CMP1_O/PB.13
NUMICRO™ NUC200/220 DATASHEET
47
NuMicro NUC220RxxAN LQFP 64-pin
48
3.2.2.2
Figure 3-6 NuMicro NUC220SxxAN LQFP 64-pin Diagram
June 06, 2012
Page 22 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
ICE_DAT
PA.12/PWM0/SC2_DAT
PA.13/PWM1/SC2_CLK
PA.14/PWM2/SC2_RST
PA.15/PWM3/I2S_MCLK/SC2_PWR
29
28
27
26
25
PA.0/ADC0/SC0_PWR
AVSS
PA.1/ADC1/SC0_RST
32
ICE_CLK
PA.2/ADC2/SC0_CLK
33
30
PA.3/ADC3/SC0_DAT
34
31
PA.4/ADC4
35
NuMicro NUC220LxxAN LQFP 48-pin
36
3.2.2.3
ADC5/PA.5
37
24
PC.0/SPI0_SS0/I2S_LRCK
ADC6/PA.6
38
23
PC.1/SPI0_CLK/I2S_BCLK
VREF
39
22
PC.2/SPI0_MISO0/I2S_DI
AVDD
40
21
PC.3/SPI0_MOSI0/I2S_DO
CMP0_N/PC.7
41
20
PB.3/UART0_nCTS/TM3_EXT/SC2_CD
SC0_CD/CMP0_P/PC.6
42
19
PB.2/UART0_nRTS/TM2_EXT/CMP0_O
TM0_EXT/INT1/PB.15
43
18
PB.1/UART0_TXD
XT1_OUT/PF.0
44
17
PB.0/UART0_RXD
XT1_IN/PF.1
45
16
USB_D+
nRESET
46
15
USB_D-
PVSS
47
14
USB_VDD33_CAP
CLKO/TM0/STADC/PB.8
48
13
USB_VBUS
10
11
12
VDD
VSS
9
UART1_TXD/PB.5
LDO_CAP
8
UART1_RXD/PB.4
5
I2C1_SDA/PA.10
7
4
I2C1_SCL/PA.11
I2C0_SDA/PA.8
3
X32_IN
6
2
I2C0_SCL/PA.9
1
VBAT
NUMICRO™ NUC200/220 DATASHEET
X32_OUT
NUC220LxxAN
LQFP 48-pin
Figure 3-7 NuMicro NUC220LxxAN LQFP 48-pin Diagram
June 06, 2014
Page 23 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
3.3
Pin Description
3.3.1
NuMicro NUC200 Pin Description
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
NUMICRO™ NUC200/220 DATASHEET
1
PE.15
I/O
General purpose digital I/O pin.
2
PE.14
I/O
General purpose digital I/O pin.
3
PE.13
I/O
General purpose digital I/O pin.
PB.14
I/O
General purpose digital I/O pin.
INT0
I
1
4
5
External interrupt0 input pin.
nd
SPI3_SS1
I/O
2
PB.13
I/O
General purpose digital I/O pin.
CMP1_O
O
Comparator1 output pin.
SPI3 slave select pin.
2
6
3
1
VBAT
P
Power supply by batteries for RTC.
7
4
2
X32_OUT
O
External 32.768 kHz (low speed) crystal output pin.
8
5
3
X32_IN
I
External 32.768 kHz (low speed) crystal input pin.
9
6
4
10
11
12
7
8
9
PA.11
I/O
General purpose digital I/O pin.
I2C1_SCL
I/O
I C1 clock pin.
PA.10
I/O
General purpose digital I/O pin.
I2C1_SDA
I/O
I C1 data input/output pin.
PA.9
I/O
General purpose digital I/O pin.
I2C0_SCL
I/O
I C0 clock pin.
PA.8
I/O
General purpose digital I/O pin.
I2C0_SDA
I/O
I C0 data input/output pin.
PD.8
I/O
General purpose digital I/O pin.
SPI3_SS0
I/O
1 SPI3 slave select pin.
PD.9
I/O
General purpose digital I/O pin.
SPI3_CLK
I/O
SPI3 serial clock pin.
PD.10
I/O
General purpose digital I/O pin.
SPI3_MISO0
I/O
1 SPI3 MISO (Master In, Slave Out) pin.
PD.11
I/O
General purpose digital I/O pin.
5
6
7
13
2
2
2
2
st
14
15
16
June 06, 2012
st
Page 24 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
st
SPI3_MOSI0
I/O
1 SPI3 MOSI (Master Out, Slave In) pin.
PD.12
I/O
General purpose digital I/O pin.
SPI3_MISO1
I/O
2
PD.13
I/O
General purpose digital I/O pin.
SPI3_MOSI1
I/O
2
PB.4
I/O
General purpose digital I/O pin.
17
18
19
10
21
22
11
nd
SPI3 MISO (Master In, Slave Out) pin.
SPI3 MOSI (Master Out, Slave In) pin.
8
UART1_RXD
20
nd
I
Data receiver input pin for UART1.
PB.5
I/O
General purpose digital I/O pin.
UART1_TXD
O
Data transmitter output pin for UART1.
PB.6
I/O
General purpose digital I/O pin.
UART1_nRTS
O
Request to Send output pin for UART1.
PB.7
I/O
General purpose digital I/O pin.
9
12
13
UART1_nCTS
I
Clear to Send input pin for UART1.
14
10
LDO_CAP
P
LDO output pin.
24
15
11
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
25
16
12
VSS
P
Ground pin for digital circuit.
26
PE.12
I/O
General purpose digital I/O pin.
27
PE.11
I/O
General purpose digital I/O pin.
28
PE.10
I/O
General purpose digital I/O pin.
29
PE.9
I/O
General purpose digital I/O pin.
30
PE.8
I/O
General purpose digital I/O pin.
31
PE.7
I/O
General purpose digital I/O pin.
PB.0
I/O
General purpose digital I/O pin.
32
17
13
UART0_RXD
33
34
June 06, 2014
18
19
NUMICRO™ NUC200/220 DATASHEET
23
I
Data receiver input pin for UART0.
PB.1
I/O
General purpose digital I/O pin.
UART0_TXD
O
Data transmitter output pin for UART0.
PB.2
I/O
General purpose digital I/O pin.
UART0_nRTS
O
Request to Send output pin for UART0.
TM2_EXT
I
Timer2 external capture input pin.
CMP0_O
O
Comparator0 output pin.
14
15
Page 25 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
PB.3
35
20
Pin
Description
Type
I/O
General purpose digital I/O pin.
NUMICRO™ NUC200/220 DATASHEET
UART0_nCTS
I
Clear to Send input pin for UART0.
TM3_EXT
I
Timer3 external capture input pin.
SC2_CD
I
SmartCard2 card detect pin.
16
36
21
PD.6
I/O
General purpose digital I/O pin.
37
22
PD.7
I/O
General purpose digital I/O pin.
PD.14
I/O
General purpose digital I/O pin.
38
23
UART2_RXD
39
I
Data receiver input pin for UART2.
PD.15
I/O
General purpose digital I/O pin.
UART2_TXD
O
Data transmitter output pin for UART2.
PC.5
I/O
General purpose digital I/O pin.
SPI0_MOSI1
I/O
2
PC.4
I/O
General purpose digital I/O pin.
SPI0_MISO1
I/O
2
PC.3
I/O
General purpose digital I/O pin.
SPI0_MOSI0
I/O
1 SPI0 MOSI (Master Out, Slave In) pin.
I2S_DO
O
I S data output.
PC.2
I/O
General purpose digital I/O pin.
SPI0_MISO0
I/O
1 SPI0 MISO (Master In, Slave Out) pin.
24
40
41
42
43
25
26
17
18
I2S_DI
44
45
27
28
19
20
46
47
29
21
nd
SPI0 MOSI (Master Out, Slave In) pin.
SPI0 MISO (Master In, Slave Out) pin.
st
2
st
2
I S data input.
PC.1
I/O
General purpose digital I/O pin.
SPI0_CLK
I/O
SPI0 serial clock pin.
I2S_BCLK
I/O
I S bit clock pin.
PC.0
I/O
General purpose digital I/O pin.
SPI0_SS0
I/O
1 SPI0 slave select pin.
I2S_LRCK
I/O
I S left right channel clock.
PE.6
I/O
General purpose digital I/O pin.
PE.5
I/O
General purpose digital I/O pin.
PWM5
I/O
PWM5 output/Capture input.
TM1_EXT
June 06, 2012
I
nd
I
2
st
2
Timer1 external capture input pin.
Page 26 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
PB.11
I/O
General purpose digital I/O pin.
TM3
I/O
Timer3 event counter input / toggle output.
PWM4
I/O
PWM4 output/Capture input.
PB.10
I/O
General purpose digital I/O pin.
TM2
I/O
Timer2 event counter input / toggle output.
SPI0_SS1
I/O
2
PB.9
I/O
General purpose digital I/O pin.
TM1
I/O
Timer1 event counter input / toggle output.
SPI1_SS1
I/O
2
51
PE.4
I/O
General purpose digital I/O pin.
52
PE.3
I/O
General purpose digital I/O pin.
53
PE.2
I/O
General purpose digital I/O pin.
PE.1
I/O
General purpose digital I/O pin.
PWM7
I/O
PWM7 output/Capture input.
PE.0
I/O
General purpose digital I/O pin.
PWM6
I/O
PWM6 output/Capture input.
PC.13
I/O
General purpose digital I/O pin.
SPI1_MOSI1
I/O
2
PC.12
I/O
General purpose digital I/O pin.
SPI1_MISO1
I/O
2
PC.11
I/O
General purpose digital I/O pin.
SPI1_MOSI0
I/O
1 SPI1 MOSI (Master Out, Slave In) pin.
PC.10
I/O
General purpose digital I/O pin.
SPI1_MISO0
I/O
1 SPI1 MISO (Master In, Slave Out) pin.
PC.9
I/O
General purpose digital I/O pin.
SPI1_CLK
I/O
SPI1 serial clock pin.
PC.8
I/O
General purpose digital I/O pin.
SPI1_SS0
I/O
1 SPI1 slave select pin.
PA.15
I/O
General purpose digital I/O pin.
PWM3
I/O
PWM output/Capture input.
48
30
31
22
23
49
32
nd
SPI0 slave select pin.
24
50
nd
SPI1 slave select pin.
54
55
57
58
59
60
61
62
June 06, 2014
33
34
nd
nd
NUMICRO™ NUC200/220 DATASHEET
56
SPI1 MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
st
st
35
36
37
st
25
Page 27 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
NUMICRO™ NUC200/220 DATASHEET
63
64
65
38
39
40
26
27
28
Pin
Description
Type
2
I2S_MCLK
O
I S master clock output pin.
SC2_PWR
O
SmartCard2 power pin.
PA.14
I/O
General purpose digital I/O pin.
PWM2
I/O
PWM2 output/Capture input.
SC2_RST
O
SmartCard2 reset pin.
PA.13
I/O
General purpose digital I/O pin.
PWM1
I/O
PWM1 output/Capture input.
SC2_CLK
O
SmartCard2 clock pin.
PA.12
I/O
General purpose digital I/O pin.
PWM0
I/O
PWM0 output/Capture input.
SC2_DAT
O
SmartCard2 data pin.
66
41
29
ICE_DAT
I/O
Serial wire debugger data pin.
67
42
30
ICE_CLK
I
Serial wire debugger clock pin.
68
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
69
VSS
P
Ground pin for digital circuit.
AVSS
AP
Ground pin for analog circuit.
PA.0
I/O
General purpose digital I/O pin.
ADC0
AI
ADC0 analog input.
SC0_PWR
O
SmartCard0 power pin.
PA.1
I/O
General purpose digital I/O pin.
ADC1
AI
ADC1 analog input.
SC0_RST
O
SmartCard0 reset pin.
PA.2
I/O
General purpose digital I/O pin.
ADC2
AI
ADC2 analog input.
SC0_CLK
O
SmartCard0 clock pin.
PA.3
I/O
General purpose digital I/O pin.
ADC3
AI
ADC3 analog input.
SC0_DAT
O
SmartCard0 data pin.
PA.4
I/O
General purpose digital I/O pin.
ADC4
AI
ADC4 analog input.
70
71
72
73
74
75
June 06, 2012
43
44
45
46
47
48
31
32
33
34
35
36
Page 28 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
49
SC1_PWR
O
SmartCard1 power pin.
PA.5
I/O
General purpose digital I/O pin.
ADC5
AI
ADC5 analog input.
SC1_RST
O
SmartCard1 reset pin.
PA.6
I/O
General purpose digital I/O pin.
ADC6
AI
ADC6 analog input.
SC1_CLK
I/O
SmartCard1 clock pin.
PA.7
I/O
General purpose digital I/O pin.
ADC7
AI
ADC7 analog input.
SC1_DAT
O
SmartCard1 data pin.
SPI2_SS1
I/O
2
37
76
50
Pin
Description
Type
38
77
78
nd
SPI2 slave select pin.
79
51
39
VREF
AP
Voltage reference input for ADC.
80
52
40
AVDD
AP
Power supply for internal analog circuit.
PD.0
I/O
General purpose digital I/O pin.
SPI2_SS0
I/O
1 SPI2 slave select pin.
PD.1
I/O
General purpose digital I/O pin.
SPI2_CLK
I/O
SPI2 serial clock pin.
PD.2
I/O
General purpose digital I/O pin.
SPI2_MISO0
I/O
1 SPI2 MISO (Master In, Slave Out) pin.
PD.3
I/O
General purpose digital I/O pin.
SPI2_MOSI0
I/O
1 SPI2 MOSI (Master Out, Slave In) pin.
PD.4
I/O
General purpose digital I/O pin.
SPI2_MISO1
I/O
2
PD.5
I/O
General purpose digital I/O pin.
SPI2_MOSI1
I/O
2
PC.7
I/O
General purpose digital I/O pin.
CMP0_N
AI
Comparator0 negative input pin.
SC1_CD
I
81
st
NUMICRO™ NUC200/220 DATASHEET
82
83
st
84
st
85
86
53
June 06, 2014
54
nd
SPI2 MISO (Master In, Slave Out) pin.
SPI2 MOSI (Master Out, Slave In) pin.
41
87
88
nd
SmartCard1 card detect pin.
PC.6
I/O
General purpose digital I/O pin.
CMP0_P
AI
Comparator0 positive input pin.
42
Page 29 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
SC0_CD
89
NUMICRO™ NUC200/220 DATASHEET
90
91
92
93
Pin
Description
Type
I
SmartCard0 card detect pin.
PC.15
I/O
General purpose digital I/O pin.
CMP1_N
AI
Comparator1 negative input pin.
PC.14
I/O
General purpose digital I/O pin.
CMP1_P
AI
Comparator1 positive input pin.
PB.15
I/O
General purpose digital I/O pin.
INT1
I
External interrupt1 input pin.
TM0_EXT
I
Timer0 external capture input pin.
55
56
57
58
59
43
PF.0
I/O
General purpose digital I/O pin.
XT1_OUT
O
External 4~24 MHz (high speed) crystal output pin.
PF.1
I/O
General purpose digital I/O pin.
44
45
46
XT1_IN
I
External 4~24 MHz (high speed) crystal input pin.
nRESET
I
External reset input: active LOW, with an internal pull-up.
Set this pin low reset chip to initial state.
94
60
95
61
VSS
P
Ground pin for digital circuit.
96
62
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
PF.2
I/O
General purpose digital I/O pin.
PS2_DAT
I/O
PS2 data pin.
PF.3
I/O
General purpose digital I/O pin.
PS2_CLK
I/O
PS2 clock pin.
97
98
99
63
47
PVSS
P
PB.8
I/O
STADC
100
64
I
PLL ground.
General purpose digital I/O pin.
ADC external trigger input.
48
TM0
I/O
Timer0 event counter input / toggle output.
CLKO
O
Frequency divider clock output pin.
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power.
June 06, 2012
Page 30 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
3.3.2
NuMicro NUC220 Pin Description
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
1
PE.15
I/O
General purpose digital I/O pin.
2
PE.14
I/O
General purpose digital I/O pin.
3
PE.13
I/O
General purpose digital I/O pin.
PB.14
I/O
General purpose digital I/O pin.
INT0
I
1
4
5
External interrupt0 input pin.
nd
SPI3_SS1
I/O
2
PB.13
I/O
General purpose digital I/O pin.
CMP1_O
O
Comparator1 output pin.
SPI3 slave select pin.
2
6
3
1
VBAT
P
Power supply by batteries for RTC.
7
4
2
X32_OUT
O
External 32.768 kHz (low speed) crystal output pin.
8
5
3
X32_IN
I
External 32.768 kHz (low speed) crystal input pin.
9
6
4
10
12
8
9
I/O
General purpose digital I/O pin.
I2C1_SCL
I/O
I C1 clock pin.
PA.10
I/O
General purpose digital I/O pin.
I2C1_SDA
I/O
I C1 data input/output pin.
PA.9
I/O
General purpose digital I/O pin.
I2C0_SCL
I/O
I C0 clock pin.
PA.8
I/O
General purpose digital I/O pin.
I2C0_SDA
I/O
I C0 data input/output pin.
PD.8
I/O
General purpose digital I/O pin.
SPI3_SS0
I/O
1 SPI3 slave select pin.
PD.9
I/O
General purpose digital I/O pin.
SPI3_CLK
I/O
SPI3 serial clock pin.
PD.10
I/O
General purpose digital I/O pin.
SPI3_MISO0
I/O
1 SPI3 MISO (Master In, Slave Out) pin.
PD.11
I/O
General purpose digital I/O pin.
SPI3_MOSI0
I/O
1 SPI3 MOSI (Master Out, Slave In) pin.
PD.12
I/O
General purpose digital I/O pin.
SPI3_MISO1
I/O
2
5
6
7
2
2
NUMICRO™ NUC200/220 DATASHEET
11
7
PA.11
2
2
13
st
14
15
st
16
st
17
June 06, 2014
nd
SPI3 MISO (Master In, Slave Out) pin.
Page 31 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
PD.13
I/O
General purpose digital I/O pin.
SPI3_MOSI1
I/O
2
PB.4
I/O
General purpose digital I/O pin.
18
19
10
NUMICRO™ NUC200/220 DATASHEET
21
22
11
SPI3 MOSI (Master Out, Slave In) pin.
8
UART1_RXD
20
nd
I
Data receiver input pin for UART1.
PB.5
I/O
General purpose digital I/O pin.
UART1_TXD
O
Data transmitter output pin for UART1.
PB.6
I/O
General purpose digital I/O pin.
UART1_nRTS
O
Request to Send output pin for UART1.
PB.7
I/O
General purpose digital I/O pin.
9
12
13
UART1_nCTS
I
Clear to Send input pin for UART1.
23
14
10
LDO_CAP
P
LDO output pin.
24
15
11
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
25
16
12
VSS
P
Ground pin for digital circuit.
26
PE.8
I/O
General purpose digital I/O pin.
27
PE.7
I/O
General purpose digital I/O pin.
28
17
13
USB_VBUS
USB Power supply from USB host or HUB.
29
18
14
USB_VDD33_
CAP
USB Internal power regulator output 3.3V decoupling pin.
30
19
15
USB_D-
USB USB differential signal D-.
31
20
16
USB_D+
USB USB differential signal D+.
32
21
17
PB.0
UART0_RXD
33
34
35
22
23
24
I
General purpose digital I/O pin.
Data receiver input pin for UART0.
PB.1
I/O
General purpose digital I/O pin.
UART0_TXD
O
Data transmitter output pin for UART0.
PB.2
I/O
General purpose digital I/O pin.
UART0_nRTS
O
Request to Send output pin for UART0.
TM2_EXT
I
Timer2 external capture input pin.
CMP0_O
O
Comparator0 output pin.
PB.3
I/O
General purpose digital I/O pin.
18
19
20
UART0_nCTS
June 06, 2012
I/O
I
Clear to Send input pin for UART0.
Page 32 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
TM3_EXT
I
Timer3 external capture input pin.
SC2_CD
I
SmartCard2 card detect pin.
36
PD.6
I/O
General purpose digital I/O pin.
37
PD.7
I/O
General purpose digital I/O pin.
PD.14
I/O
General purpose digital I/O pin.
38
UART2_RXD
I
Data receiver input pin for UART2.
PD.15
I/O
General purpose digital I/O pin.
UART2_TXD
O
Data transmitter output pin for UART2.
PC.5
I/O
General purpose digital I/O pin.
SPI0_MOSI1
I/O
2
PC.4
I/O
General purpose digital I/O pin.
SPI0_MISO1
I/O
2
PC.3
I/O
General purpose digital I/O pin.
SPI0_MOSI0
I/O
1 SPI0 MOSI (Master Out, Slave In) pin.
I2S_DO
O
I S data output.
PC.2
I/O
General purpose digital I/O pin.
SPI0_MISO0
I/O
1 SPI0 MISO (Master In, Slave Out) pin.
39
40
41
42
26
21
22
I2S_DI
44
45
27
28
46
47
29
23
24
June 06, 2014
30
SPI0 MISO (Master In, Slave Out) pin.
st
2
st
2
I S data input.
PC.1
I/O
General purpose digital I/O pin.
SPI0_CLK
I/O
SPI0 serial clock pin.
I2S_BCLK
I/O
I S bit clock pin.
PC.0
I/O
General purpose digital I/O pin.
SPI0_SS0
I/O
1 SPI0 slave select pin.
I2S_LRCK
I/O
I S left right channel clock.
PE.6
I/O
General purpose digital I/O pin.
PE.5
I/O
General purpose digital I/O pin.
PWM5
I/O
PWM5 output/Capture input.
TM1_EXT
48
I
nd
SPI0 MOSI (Master Out, Slave In) pin.
PB.11
I
I/O
NUMICRO™ NUC200/220 DATASHEET
43
25
nd
2
st
2
Timer1 external capture input pin.
General purpose digital I/O pin.
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NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
Pin
Description
Type
TM3
I/O
Timer3 event counter input / toggle output.
PWM4
I/O
PWM4 output/Capture input.
PB.10
I/O
General purpose digital I/O pin.
TM2
I/O
Timer2 event counter input / toggle output.
SPI0_SS1
I/O
2
PB.9
I/O
General purpose digital I/O pin.
TM1
I/O
Timer1 event counter input / toggle output.
SPI1_SS1
I/O
2
51
PE.4
I/O
General purpose digital I/O pin.
52
PE.3
I/O
General purpose digital I/O pin.
53
PE.2
I/O
General purpose digital I/O pin.
PE.1
I/O
General purpose digital I/O pin.
PWM7
I/O
PWM7 output/Capture input.
PE.0
I/O
General purpose digital I/O pin.
PWM6
I/O
PWM6 output/Capture input.
PC.13
I/O
General purpose digital I/O pin.
SPI1_MOSI1
I/O
2
PC.12
I/O
General purpose digital I/O pin.
SPI1_MISO1
I/O
2
PC.11
I/O
General purpose digital I/O pin.
SPI1_MOSI0
I/O
1 SPI1 MOSI (Master Out, Slave In) pin.
PC.10
I/O
General purpose digital I/O pin.
SPI1_MISO0
I/O
1 SPI1 MISO (Master In, Slave Out) pin.
PC.9
I/O
General purpose digital I/O pin.
SPI1_CLK
I/O
SPI1 serial clock pin.
PC.8
I/O
General purpose digital I/O pin.
SPI1_SS0
I/O
1 SPI1 slave select pin.
PA.15
I/O
General purpose digital I/O pin.
PWM3
I/O
PWM3 output/Capture input.
I2S_MCLK
O
I S master clock output pin.
31
NUMICRO™ NUC200/220 DATASHEET
49
nd
SPI0 slave select pin.
32
50
nd
SPI1 slave select pin.
54
55
56
57
58
59
60
61
62
June 06, 2012
33
34
nd
nd
SPI1MOSI (Master Out, Slave In) pin.
SPI1 MISO (Master In, Slave Out) pin.
st
st
35
36
37
25
st
2
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NuMicro NUC200/220 Series
Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
63
64
65
38
39
40
26
27
28
Pin
Description
Type
SC2_PWR
O
SmartCard2 power pin.
PA.14
I/O
General purpose digital I/O pin.
PWM2
I/O
PWM2 output/Capture input.
SC2_RST
O
SmartCard2 reset pin.
PA.13
I/O
General purpose digital I/O pin.
PWM1
I/O
PWM1 output/Capture input.
SC2_CLK
O
SmartCard2 clock pin.
PA.12
I/O
General purpose digital I/O pin.
PWM0
I/O
PWM0 output/Capture input.
SC2_DAT
O
SmartCard2 data pin.
41
29
ICE_DAT
I/O
Serial wire debugger data pin.
67
42
30
ICE_CLK
I
Serial wire debugger clock pin.
68
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
69
VSS
P
Ground pin for digital circuit.
AVSS
AP
Ground pin for analog circuit.
PA.0
I/O
General purpose digital I/O pin.
ADC0
AI
ADC0 analog input.
SC0_PWR
O
SmartCard0 power pin.
PA.1
I/O
General purpose digital I/O pin.
ADC1
AI
ADC1 analog input.
SC0_RST
O
SmartCard0 reset pin.
PA.2
I/O
General purpose digital I/O pin.
ADC2
AI
ADC2 analog input.
SC0_CLK
O
SmartCard0 clock pin.
PA.3
I/O
General purpose digital I/O pin.
ADC3
AI
ADC3 analog input.
SC0_DAT
O
SmartCard0 data pin.
PA.4
I/O
General purpose digital I/O pin.
ADC4
AI
ADC4 analog input.
SC1_PWR
O
SmartCard1 power pin.
70
71
72
73
74
43
44
45
46
47
48
75
June 06, 2014
31
32
33
34
35
NUMICRO™ NUC200/220 DATASHEET
66
36
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Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
49
NUMICRO™ NUC200/220 DATASHEET
PA.5
I/O
General purpose digital I/O pin.
ADC5
AI
ADC5 analog input.
SC1_RST
O
SmartCard1 reset pin.
PA.6
I/O
General purpose digital I/O pin.
ADC6
AI
ADC6 analog input.
SC1_CLK
I/O
SmartCard1 clock pin.
PA.7
I/O
General purpose digital I/O pin.
ADC7
AI
ADC7 analog input.
SC1_CLK
O
SmartCard1 clock pin.
SPI2_SS1
I/O
2
37
76
50
Pin
Description
Type
38
77
78
nd
SPI2 slave select pin.
79
51
39
VREF
AP
Voltage reference input for ADC.
80
52
40
AVDD
AP
Power supply for internal analog circuit.
PD.0
I/O
General purpose digital I/O pin.
SPI2_SS0
I/O
1 SPI2 slave select pin.
PD.1
I/O
General purpose digital I/O pin.
SPI2_CLK
I/O
SPI2 serial clock pin.
PD.2
I/O
General purpose digital I/O pin.
SPI2_MISO0
I/O
1 SPI2 MISO (Master In, Slave Out) pin.
PD.3
I/O
General purpose digital I/O pin.
SPI2_MOSI0
I/O
1 SPI2 MOSI (Master Out, Slave In) pin.
PD.4
I/O
General purpose digital I/O pin.
SPI2_MISO1
I/O
2
PD.5
I/O
General purpose digital I/O pin.
SPI2_MOSI1
I/O
2
PC.7
I/O
General purpose digital I/O pin.
CMP0_N
AI
Comparator0 negative input pin.
SC1_CD
I
81
st
82
83
st
84
st
85
86
53
June 06, 2012
54
nd
SPI2 MISO (Master In, Slave Out) pin.
SPI2 MOSI (Master Out, Slave In) pin.
41
87
88
nd
42
SmartCard1 card detect pin.
PC.6
I/O
General purpose digital I/O pin.
CMP0_P
AI
Comparator0 positive input pin.
SC0_CD
I
SmartCard0 card detect pin.
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Datasheet
Pin No.
LQFP LQFP LQFP Pin Name
100-pin 64-pin 48-pin
89
90
91
92
93
Pin
Description
Type
PC.15
I/O
General purpose digital I/O pin.
CMP1_N
AI
Comparator1 negative input pin.
PC.14
I/O
General purpose digital I/O pin.
CMP1_P
AI
Comparator1 positive input pin.
PB.15
I/O
General purpose digital I/O pin.
INT1
I
External interrupt1 input pin.
TM0_EXT
I
Timer 0 external capture input pin.
55
56
57
58
59
43
PF.0
I/O
General purpose digital I/O pin.
XT1_OUT
O
External 4~24 MHz (high speed) crystal output pin.
PF.1
I/O
General purpose digital I/O pin.
44
45
46
XT1_IN
I
External 4~24 MHz (high speed) crystal input pin.
nRESET
I
External reset input: active LOW, with an internal pull-up.
Set this pin low reset chip to initial state.
60
95
61
VSS
P
Ground pin for digital circuit.
96
62
VDD
P
Power supply for I/O ports and LDO source for internal
PLL and digital circuit.
PF.2
I/O
General purpose digital I/O pin.
PS2_DAT
I/O
PS2 data pin.
PF.3
I/O
General purpose digital I/O pin.
PS2_CLK
I/O
PS2 clock pin.
97
98
99
63
47
PVSS
P
PB.8
I/O
STADC
100
64
I
PLL ground.
General purpose digital I/O pin.
ADC external trigger input.
48
TM0
I/O
Timer0 event counter input / toggle output.
CLKO
O
Frequency divider clock output pin.
Note: Pin Type I = Digital Input, O = Digital Output; AI = Analog Input; P = Power Pin; AP = Analog Power.
June 06, 2014
Page 37 of 98
Revision 1.00
NUMICRO™ NUC200/220 DATASHEET
94
NuMicro NUC200/220 Series
Datasheet
4
4.1
BLOCK DIAGRAM
NuMicro NUC200 Block Diagram
NUMICRO™ NUC200/220 DATASHEET
Figure 4-1 NuMicro NUC200 Block Diagram
June 06, 2012
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NuMicro NUC200/220 Series
Datasheet
4.2
NuMicro NUC220 Block Diagram
NUMICRO™ NUC200/220 DATASHEET
Figure 4-2 NuMicro NUC220 Block Diagram
June 06, 2014
Page 39 of 98
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NuMicro NUC200/220 Series
Datasheet
5
5.1
FUNCTIONAL DESCRIPTION
ARM® Cortex™-M0 Core
NUMICRO™ NUC200/220 DATASHEET
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor, which has an
AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug
functionality. The processor can execute Thumb code and is compatible with other Cortex™-M
profile processor. The profile supports two modes -Thread mode and Handler mode. Handler
mode is entered as a result of an exception. An exception return can only be issued in Handler
mode. Thread mode is entered on Reset, and can be entered as a result of an exception return.
Figure 5-1 shows the functional controller of processor.
CortexTM-M0 Components
CortexTM-M0 Processor
Nested
Vectored
Interrupt
Controller
(NVIC)
Interrupts
Debug
CortexTM-M0
Processor
Core
Wake-up
Interrupt
Controller
(WIC)
Bus Matrix
Breakpoint
and
Watchpoint
Unit
Debug
Access
Port
(DAP)
Debugger
Interface
AHB-Lite
Interface
Serial Wire or
JTAG Debug Port
Figure 5-1 Functional Controller Diagram
The implemented device provides the following components and features:
June 06, 2012
A low gate count processor:
®
ARMv6-M Thumb instruction set
Thumb-2 technology
ARMv6-M compliant 24-bit SysTick timer
A 32-bit hardware multiplier
System interface supported with little-endian data accesses
Ability to have deterministic, fixed-latency, interrupt handling
Load/store-multiples and multicycle-multiplies that can be abandoned and
restarted to facilitate rapid interrupt handling
C Application Binary Interface compliant exception model. This is the ARMv6-M,
C Application Binary Interface (C-ABI) compliant exception model that enables
the use of pure C functions as interrupt handlers
Low Power Sleep mode entry using Wait For Interrupt (WFI), Wait For Event
(WFE) instructions, or the return from interrupt sleep-on-exit feature
Page 40 of 98
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NuMicro NUC200/220 Series
Datasheet
NVIC:
32 external interrupt inputs, each with four levels of priority
Dedicated Non-maskable Interrupt (NMI) input
Supports for both level-sensitive and pulse-sensitive interrupt lines
Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power
Sleep mode
Debug support:
Four hardware breakpoints
Two watchpoints
Program Counter Sampling Register (PCSR) for non-intrusive code profiling
Single step and vector catch capabilities
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration
to all system peripherals and memory
Single 32-bit slave port that supports the DAP (Debug Access Port).
NUMICRO™ NUC200/220 DATASHEET
June 06, 2014
Page 41 of 98
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NuMicro NUC200/220 Series
Datasheet
5.2
System Manager
5.2.1
Overview
System management includes the following sections:
NUMICRO™ NUC200/220 DATASHEET
5.2.2
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip controllers
reset , multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
Power-on Reset
Low level on the nRESET pin
Watchdog Time-out Reset
Low Voltage Reset
Brown-out Detector Reset
CPU Reset
System Reset
System Reset and Power-on Reset all reset the whole chip including all peripherals. The
difference between System Reset and Power-on Reset is external crystal circuit and ISPCON.BS
bit. System Reset does not reset external crystal circuit and ISPCON.BS bit, but Power-on Reset
does.
June 06, 2012
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Datasheet
5.2.3
System Power Distribution
In this chip, the power distribution is divided into four segments.
Analog power from AVDD and AVSS provides the power for analog components
operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 1.8 V power for digital operation and I/O pins.
USB transceiver power from USB_VBUS offers the power for operating the USB
transceiver.
Battery power from VBAT supplies the RTC and external 32.768 kHz crystal.
The outputs of internal voltage regulators, LDO_CAP and USB_VDD33_CAP, require an external
capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be
the same voltage level of the digital power (VDD). Figure 5-2 shows the power distribution of
NuMicro NUC200; Figure 5-3 shows the power distribution of NuMicro NUC220.
NUC200 Power Distribution
AVDD
12-bit
SAR-ADC
AVSS
Digital Logic
FLASH
Brownout
Detector
Low
Voltage
Reset
Internal
22.1184 MHz & 10 kHz
Oscillator
LDO_CAP
1.8V
1.8V
RTC
LDO
PLL
IO cell
GPIO
VSS
VDD
POR50
PVSS
X32_IN
External
32.768 kHz
Crystal
X32_UTO
VBAT
ULDO
1uF
POR18
Figure 5-2 NuMicro NUC200 Power Distribution Diagram
June 06, 2014
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NUMICRO™ NUC200/220 DATASHEET
Temperature
Seneor
Analog
Comparator
NuMicro NUC200/220 Series
Datasheet
AVDD
12-bit
SAR-ADC
AVSS
NUC220
Power
Distribution
Analog Comparator
Low
Voltage
Reset
USB_DUSB_VDD33_CAP
3.3V
Brownout
Detector
NUMICRO™ NUC200/220 DATASHEET
Temperature
Seneor
USB_D+
USB 1.1
Tranceiver
1uF
5V to 3.3V LDO
FLASH
USB_VBUS
Internal
22.1184 MHz & 10 kHz
Oscillator
Digital Logic
LDO_CAP
1.8V
1.8V
LDO
PLL
IO cell
GPIO
VSS
POR50
VDD
RTC
PVSS
X32_IN
External
32.768 kHz
Crystal
X32_OUT
VBAT
ULDO
1uF
POR18
Figure 5-3 NuMicro NUC220 Power Distribution Diagram
June 06, 2012
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NuMicro NUC200/220 Series
Datasheet
5.2.4
System Memory Map
The NuMicro NUC200 Series provides 4G-byte addressing space. The memory locations
assigned to each on-chip controllers are shown in the following table. The detailed register
definition, memory space, and programming detailed will be described in the following sections for
each on-chip peripheral. The NuMicro NUC200 Series only supports little-endian data format.
Address Space
Token
Controllers
Flash and SRAM Memory Space
0x0000_0000 – 0x0001_FFFF FLASH_BA
FLASH Memory Space (128 KB)
0x2000_0000 – 0x2000_3FFF
SRAM Memory Space (16 KB)
SRAM_BA
AHB Controllers Space (0x5000_0000 – 0x501F_FFFF)
0x5000_0000 – 0x5000_01FF
GCR_BA
System Global Control Registers
0x5000_0200 – 0x5000_02FF
CLK_BA
Clock Control Registers
0x5000_0300 – 0x5000_03FF
INT_BA
Interrupt Multiplexer Control Registers
0x5000_4000 – 0x5000_7FFF
GPIO_BA
GPIO Control Registers
0x5000_8000 – 0x5000_BFFF PDMA_BA
Peripheral DMA Control Registers
0x5000_C000 – 0x5000_FFFF FMC_BA
Flash Memory Control Registers
0x4000_4000 – 0x4000_7FFF
WDT_BA
Watchdog Timer Control Registers
0x4000_8000 – 0x4000_BFFF RTC_BA
Real Time Clock (RTC) Control Register
0x4001_0000 – 0x4001_3FFF
TMR01_BA
Timer0/Timer1 Control Registers
0x4002_0000 – 0x4002_3FFF
I2C0_BA
I C0 Interface Control Registers
0x4003_0000 – 0x4003_3FFF
SPI0_BA
SPI0 with master/slave function Control Registers
0x4003_4000 – 0x4003_7FFF
SPI1_BA
SPI1 with master/slave function Control Registers
0x4004_0000 – 0x4004_3FFF
PWMA_BA
PWM0/1/2/3 Control Registers
0x4005_0000 – 0x4005_3FFF
UART0_BA
UART0 Control Registers
0x4006_0000 – 0x4006_3FFF
USBD_BA
USB 2.0 FS device Controller Registers
2
0x400D_0000 – 0x400D_3FFF ACMP_BA
Analog Comparator Control Registers
0x400E_0000 – 0x400E_FFFF ADC_BA
Analog-Digital-Converter (ADC) Control Registers
APB2 Controllers Space (0x4010_0000 ~ 0x401F_FFFF)
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NUMICRO™ NUC200/220 DATASHEET
APB1 Controllers Space (0x4000_0000 ~ 0x400F_FFFF)
NuMicro NUC200/220 Series
Datasheet
NUMICRO™ NUC200/220 DATASHEET
0x4010_0000 – 0x4010_3FFF
PS2_BA
PS/2 Interface Control Registers
0x4011_0000 – 0x4011_3FFF
TMR23_BA
Timer2/Timer3 Control Registers
0x4012_0000 – 0x4012_3FFF
I2C1_BA
I C1 Interface Control Registers
0x4013_0000 – 0x4013_3FFF
SPI2_BA
SPI2 with master/slave function Control Registers
0x4013_4000 – 0x4013_7FFF
SPI3_BA
SPI3 with master/slave function Control Registers
0x4014_0000 – 0x4014_3FFF
PWMB_BA
PWM4/5/6/7 Control Registers
0x4015_0000 – 0x4015_3FFF
UART1_BA
UART1 Control Registers
0x4015_4000 – 0x4015_7FFF
UART2_BA
UART2 Control Registers
0x4019_0000 – 0x4019_3FFF
SC0_BA
SC0 Control Registers
0x4019_4000 – 0x4019_7FFF
SC1_BA
SC1 Control Registers
0x4019_8000 – 0x4019_BFFF SC2_BA
SC2 Control Registers
0x401A_0000 – 0x401A_3FFF I2S_BA
I S Interface Control Registers
2
2
System Controllers Space (0xE000_E000 ~ 0xE000_EFFF)
0xE000_E010 – 0xE000_E0FF SYST_BA
System Timer Control Registers
0xE000_E100 – 0xE000_ECFF NVIC_BA
External Interrupt Controller Control Registers
0xE000_ED00 – 0xE000_ED8F SCS_BA
System Control Registers
Table 5-1 Address Space Assignments for On-Chip Controllers
June 06, 2012
Page 46 of 98
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NuMicro NUC200/220 Series
Datasheet
5.2.5
System Timer (SysTick)
The Cortex™-M0 includes an integrated system timer, SysTick, which provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to 0, and reload (wrap) to the value in the SysTick Reload Value Register
(SYST_RVR) on the next clock cycle, then decrement on subsequent clocks. When the counter
transitions to 0, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to 0
before enabling the feature. This ensures the timer will count from the SYST_RVR value rather
than an arbitrary value when it is enabled.
If the SYST_RVR is 0, the timer will be maintained with a current value of 0 after it is reloaded
with this value. This mechanism can be used to disable the feature independently from the timer
enable bit.
For more detailed information, please refer to the “ARM
®
Manual” and “ARM v6-M Architecture Reference Manual”.
®
Cortex™-M0 Technical Reference
NUMICRO™ NUC200/220 DATASHEET
June 06, 2014
Page 47 of 98
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NuMicro NUC200/220 Series
Datasheet
5.2.6
Nested Vectored Interrupt Controller (NVIC)
The Cortex™-M0 provides an interrupt controller as an integral part of the exception mode,
named as “Nested Vectored Interrupt Controller (NVIC)”, which is closely coupled to the
processor kernel and provides following features:
Nested and Vectored interrupt support
Automatic processor state saving and restoration
Reduced and deterministic interrupt latency
NUMICRO™ NUC200/220 DATASHEET
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When an interrupt is accepted, the starting address of the interrupt service routine (ISR) is fetched
from a vector table in memory. There is no need to determine which interrupt is accepted and
branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the “ARM
®
Manual” and “ARM v6-M Architecture Reference Manual”.
June 06, 2012
Page 48 of 98
®
Cortex™-M0 Technical Reference
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
5.2.6.1
Exception Model and System Interrupt Map
The following table lists the exception model supported by NuMicro NUC200 Series. Software
can set four levels of priority on some of these exceptions as well as on all interrupts. The highest
user-configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default
priority of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth
priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception Name
Vector Number
Priority
Reset
1
-3
NMI
2
-2
Hard Fault
3
-1
Reserved
4 ~ 10
Reserved
SVCall
11
Configurable
Reserved
12 ~ 13
Reserved
PendSV
14
Configurable
SysTick
15
Configurable
Interrupt (IRQ0 ~ IRQ31)
16 ~ 47
Configurable
Table 5-2 Exception Model
Interrupt
Name
Source IP Interrupt Description
0 ~ 15
-
-
16
0
BOD_INT
17
1
WDT_INT
WDT
Watchdog Timer interrupt
18
2
EINT0
GPIO
External signal interrupt from PB.14 pin
19
3
EINT1
GPIO
External signal interrupt from PB.15 pin
20
4
GPAB_INT
GPIO
External signal interrupt from PA[15:0]/PB[13:0]
21
5
GPCDEF_INT
GPIO
External interrupt from
PC[15:0]/PD[15:0]/PE[15:0]/ PF[3:0]
22
6
PWMA_INT
PWM0~3 PWM0, PWM1, PWM2 and PWM3 interrupt
23
7
PWMB_INT
PWM4~7 PWM4, PWM5, PWM6 and PWM7 interrupt
24
8
TMR0_INT
TMR0
Timer 0 interrupt
25
9
TMR1_INT
TMR1
Timer 1 interrupt
26
10
TMR2_INT
TMR2
Timer 2 interrupt
June 06, 2014
-
System exceptions
Brown-out Brown-out low voltage detected interrupt
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NUMICRO™ NUC200/220 DATASHEET
Interrupt
Number
Vector
Number (Bit in Interrupt
Registers)
NuMicro NUC200/220 Series
Datasheet
NUMICRO™ NUC200/220 DATASHEET
27
11
TMR3_INT
TMR3
28
12
UART02_INT
UART0/2
29
13
UART1_INT
UART1
30
14
SPI0_INT
SPI0
SPI0 interrupt
31
15
SPI1_INT
SPI1
SPI1 interrupt
32
16
SPI2_INT
SPI2
SPI2 interrupt
33
17
SPI3_INT
SPI3
SPI3 interrupt
Timer 3 interrupt
UART0 and UART2 interrupt
UART1 interrupt
2
I C0 interrupt
2
2
I C1 interrupt
34
18
I2C0_INT
I C0
35
19
I2C1_INT
I C1
36
20
Reserved
-
-
37
21
Reserved
-
-
38
22
SC012_INT
SC0/1/2
SC0, SC1 and SC2 interrupt
39
23
USB_INT
USBD
USB 2.0 FS Device interrupt
40
24
PS2_INT
PS/2
41
25
ACMP_INT
ACMP
Analog Comparator-0 or Comaprator-1 interrupt
42
26
PDMA_INT
PDMA
PDMA interrupt
43
27
I2S_INT
IS
44
28
PWRWU_INT
CLKC
Clock controller interrupt for chip wake-up from
power-down state
45
29
ADC_INT
ADC
ADC interrupt
46
30
IRCT_INT
IRC
IRC TRIM interrupt
47
31
RTC_INT
RTC
Real time clock interrupt
2
2
PS/2 interrupt
2
I S interrupt
Table 5-3 System Interrupt Map
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Datasheet
5.2.6.2
Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset Description
0
Vector Number
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 5-4 Vector Table Format
5.2.6.3
Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt SetEnable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
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NUMICRO™ NUC200/220 DATASHEET
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NuMicro NUC200/220 Series
Datasheet
5.2.6.4
Interrupt Source Register Map
Besides the interrupt control registers associated with the NVIC, the NuMicro NUC200 Series
also implements some specific control registers to facilitate the interrupt functions, including
“interrupt source identification”, ”NMI source selection” and “interrupt test mode”, which are
described below.
R: read only, W: write only, R/W: both read and write
NUMICRO™ NUC200/220 DATASHEET
Register
Offset
R/W
Description
Reset Value
INT Base Address:
INT_BA = 0x5000_0300
IRQ0_SRC
INT_BA+0x00
R
IRQ0 (BOD) interrupt source identity
0xXXXX_XXXX
IRQ1_SRC
INT_BA+0x04
R
IRQ1 (WDT) interrupt source identity
0xXXXX_XXXX
IRQ2_SRC
INT_BA+0x08
R
IRQ2 (EINT0) interrupt source identity
0xXXXX_XXXX
IRQ3_SRC
INT_BA+0x0C
R
IRQ3 (EINT1) interrupt source identity
0xXXXX_XXXX
IRQ4_SRC
INT_BA+0x10
R
IRQ4 (GPA/GPB) interrupt source identity
0xXXXX_XXXX
IRQ5_SRC
INT_BA+0x14
R
IRQ5 (GPC/GPD/GPE/GPF) interrupt source identity
0xXXXX_XXXX
IRQ6_SRC
INT_BA+0x18
R
IRQ6 (PWMA) interrupt source identity
0xXXXX_XXXX
IRQ7_SRC
INT_BA+0x1C
R
IRQ7 (PWMB) interrupt source identity
0xXXXX_XXXX
IRQ8_SRC
INT_BA+0x20
R
IRQ8 (TMR0) interrupt source identity
0xXXXX_XXXX
IRQ9_SRC
INT_BA+0x24
R
IRQ9 (TMR1) interrupt source identity
0xXXXX_XXXX
IRQ10_SRC INT_BA+0x28
R
IRQ10 (TMR2) interrupt source identity
0xXXXX_XXXX
IRQ11_SRC INT_BA+0x2C
R
IRQ11 (TMR3) interrupt source identity
0xXXXX_XXXX
IRQ12_SRC INT_BA+0x30
R
IRQ12 (UART0/UART2) interrupt source identity
0xXXXX_XXXX
IRQ13_SRC INT_BA+0x34
R
IRQ13 (UART1) interrupt source identity
0xXXXX_XXXX
IRQ14_SRC INT_BA+0x38
R
IRQ14 (SPI0) interrupt source identity
0xXXXX_XXXX
IRQ15_SRC INT_BA+0x3C
R
IRQ15 (SPI1) interrupt source identity
0xXXXX_XXXX
IRQ16_SRC INT_BA+0x40
R
IRQ16 (SPI2) interrupt source identity
0xXXXX_XXXX
IRQ17_SRC INT_BA+0x44
R
IRQ17 (SPI3) interrupt source identity
0xXXXX_XXXX
IRQ18_SRC INT_BA+0x48
R
IRQ18 (I2C0) interrupt source identity
0xXXXX_XXXX
IRQ19_SRC INT_BA+0x4C
R
IRQ19 (I2C1) interrupt source identity
0xXXXX_XXXX
IRQ20_SRC INT_BA+0x50
R
Reserved
0xXXXX_XXXX
IRQ21_SRC INT_BA+0x54
R
Reserved
0xXXXX_XXXX
IRQ22_SRC INT_BA+0x58
R
IRQ22 (SC0/SC1/SC2) interrupt source identity
0xXXXX_XXXX
June 06, 2012
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Datasheet
IRQ23_SRC INT_BA+0x5C
R
IRQ23 (USB) interrupt source identity
0xXXXX_XXXX
IRQ24_SRC INT_BA+0x60
R
IRQ24 (PS/2) interrupt source identity
0xXXXX_XXXX
IRQ25_SRC INT_BA+0x64
R
IRQ25 (ACMP) interrupt source identity
0xXXXX_XXXX
IRQ26_SRC INT_BA+0x68
R
IRQ26 (PDMA) interrupt source identity
0xXXXX_XXXX
IRQ27_SRC INT_BA+0x6C
R
IRQ27 (I2S) interrupt source identity
0xXXXX_XXXX
IRQ28_SRC INT_BA+0x70
R
IRQ28 (PWRWU) interrupt source identity
0xXXXX_XXXX
IRQ29_SRC INT_BA+0x74
R
IRQ29 (ADC) interrupt source identity
0xXXXX_XXXX
IRQ30_SRC INT_BA+0x78
R
IRQ30 (IRCT) interrupt source identity
0xXXXX_XXXX
IRQ31_SRC INT_BA+0x7C
R
IRQ31 (RTC) interrupt source identity
0xXXXX_XXXX
NMI_SEL
INT_BA+0x80
R/W
NMI source interrupt select control register
0x0000_0000
MCU_IRQ
INT_BA+0x84
R/W
MCU interrupt request source register
0x0000_0000
NUMICRO™ NUC200/220 DATASHEET
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Datasheet
5.2.7
System Control (SCS)
The Cortex™-M0 status and operating mode control are managed by System Control Registers.
Including CPUID, Cortex™-M0 interrupt priority and Cortex™-M0 power management can be
controlled through these system control registers
For more detailed information, please refer to the “ARM
®
Manual” and “ARM v6-M Architecture Reference Manual”.
®
Cortex™-M0 Technical Reference
NUMICRO™ NUC200/220 DATASHEET
5.3 Clock Controller
5.3.1
Overview
The clock controller generates clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and clock divider. The chip enters
Power-down mode when Cortex™-M0 core executes the WFI instruction only if the
PWR_DOWN_EN (PWRCON[7]) bit and PD_WAIT_CPU (PWRCON[8]) bit are both set to 1.
After that, chip enters Power-down mode and waits for wake-up interrupt source triggered to exit
Power-down mode. In Power-down mode, the clock controller turns off the external 4~24 MHz
high speed crystal and internal 22.1184 MHz high speed oscillator to reduce the overall system
power consumption.
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Datasheet
22.1184
MHz
22.1184 MHz
111
10 kHz
4~24
MHz
PLLFOUT
000
22.1184 MHz
4~24 MHz
HCLK
PLLFOUT
0
HCLK
4~24 MHz
1/2
111
1/2
011
1/2
010
32.768 kHz
001
4~24 MHz
000
CLKSEL0[5:3]
22.1184 MHz
HCLK
PLLFOUT
4~24 MHz
01
00
4~24 MHz
HCLK
PLLFOUT
4~24 MHz
01
HCLK
PLLFOUT
4~24 MHz
CLKSEL3[5:4]
CLKSEL3[3:2]
CLKSEL3[1:0]
22.1184 MHz
CPUCLK
1
0
10 kHz
22.1184 MHz
HCLK
32.768 kHz
4~24 MHz
011
SysTick
PWM 6-7
PWM 4-5
PWM 2-3
PWM 0-1
010
001
000
CLKSEL2[17:16]
CLKSEL2[11:4]
CLKSEL1[31:28]
HCLK
FMC
SYST_CSR[2]
111
10 kHz
11
10
10 kHz
1/2048
32.768 kHz
WWDT
11
10
01
WDT
22.1184 MHz
PS2
CLKSEL1[1:0]
I2S
CPUCLK
00
1
SPI0-3
0
SYST_CSR[2]
1/(UART_N+1)
UART 0-2
1/(ADC_N+1)
ADC
11
10
01
22.1184 MHz
00
HCLK
32.768 kHz
CLKSEL1[3:2]
22.1184 MHz
000
11
CLKSEL1[25:24]
22.1184 MHz
001
4~24 MHz
11
10
10 kHz
11
10
BOD
FDIV
01
32.768 kHz
00
RTC
CLKSEL2[3:2]
01
00
PLLFOUT
1/(SC2_N+1)
SC 2
1/(SC1_N+1)
SC 1
1/(SC0_N+1)
SC 0
1/(USB_N+1)
USB
Figure 5-4 Clock Generator Global View Diagram
June 06, 2014
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NUMICRO™ NUC200/220 DATASHEET
PLLFOUT
TMR 3
TMR 2
TMR 1
TMR 0
CLKSEL1[22:20]
CLKSEL1[18:16]
CLKSEL1[14:12]
CLKSEL1[10:8]
CLKSEL2[1:0]
22.1184 MHz
ACMP
I2C 0~1
011
11
10
PCLK
010
32.768 kHz
4~24 MHz
PLLCON[19]
22.1184 MHz
PDMA
101
External trigger
1
HCLK
111
10 kHz
CLKSEL0[2:0]
22.1184 MHz
CPU
001
4~24 MHz
10 kHz
1/(HCLK_N+1)
010
32.768 kHz
32.768
kHz
CPUCLK
011
NuMicro NUC200/220 Series
Datasheet
5.3.2
Clock Generator
The clock generator consists of 5 clock sources as listed below:
NUMICRO™ NUC200/220 DATASHEET
One external 32.768 kHz low speed crystal
One external 4~24 MHz high speed crystal
One programmable PLL FOUT (PLL source consists of external 4~24 MHz high
speed crystal and internal 22.1184 MHz high speed oscillator)
One internal 22.1184 MHz high speed oscillator
One internal 10 kHz low speed oscillator
XTL32K_EN (PWRCON[1])
X32_IN
External
32.768 kHz
Crystal
32.768 kHz
X32_OUT
XTL12M_EN (PWRCON[0])
4~24 MHz
XT1_IN
External
4~24 MHz
Crystal
XT1_OUT
PLL_SRC (PLLCON[19])
0
OSC22M_EN (PWRCON[2])
PLL FOUT
PLL
1
Internal
22.1184 MHz
Oscillator
22.1184 MHz
OSC10K_EN(PWRCON[3])
Internal
10 kHz
Oscillator
10 kHz
Figure 5-5 Clock Generator Block Diagram
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Datasheet
5.3.3
System Clock and SysTick Clock
The system clock has 5 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown in Figure 5-6.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
10 kHz
PLLFOUT
32.768 kHz
4~24 MHz
111
011
CPUCLK
010
HCLK
CPU
AHB
1/(HCLK_N+1)
001
HCLK_N (CLKDIV[3:0])
PCLK
APB
000
CPU in Power Down Mode
Figure 5-6 System Clock Block Diagram
The clock source of SysTick in Cortex™-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 5 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]). The block
diagram is shown in Figure 5-7.
STCLK_S (CLKSEL0[5:3])
HCLK
4~24 MHz
32.768 kHz
4~24 MHz
1/2
111
1/2
011
1/2
010
NUMICRO™ NUC200/220 DATASHEET
22.1184 MHz
STCLK
001
000
Figure 5-7 SysTick Clock Control Block Diagram
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Datasheet
5.3.4
Peripherals Clock
The peripherals clock can be selected as different clock source depends on the clock source
select control registers (CLKSEL1, CLKSEL2 and CLKSEL3).
5.3.5
Power-down Mode Clock
NUMICRO™ NUC200/220 DATASHEET
When chip enters Power-down mode, system clocks, some clock sources, and some peripheral
clocks will be disabled. Some clock sources and peripherals clocks are still active in Power-down
mode.
The clocks still kept active are listed below:
June 06, 2012
Clock Generator
Internal 10 kHz low speed oscillator clock
External 32.768 kHz low speed crystal clock
Peripherals Clock (when IP adopt external 32.768 kHz low speed crystal oscillator or
10 kHz low speed oscillator as clock source)
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Datasheet
5.3.6
Frequency Divider Output
This device is equipped with a power-of-2 frequency divider which is composed by16 chained
divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one
multiplexer is reflected to CLKO function pin. Therefore there are 16 options of power-of-2 divided
1
16
clocks with the frequency from Fin/2 to Fin/2 where Fin is input clock frequency to the clock
divider.
(N+1)
, where Fin is the input clock frequency, Fout is the clock
The output formula is Fout = Fin/2
divider output frequency and N is the 4-bit value in FSEL (FRQDIV[3:0]).
When writing 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When writing 0
to DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
If DIVIDER1(FRQDIV[5]) is set to 1, the frequency divider clock (FRQDIV_CLK) will bypass
power-of-2 frequency divider. The frequency divider clock will be output to CLKO pin directly.
FRQDIV_S (CLKSEL2[3:2])
FDIV_EN(APBCLK[6])
10 kHz
11
FRQDIV_CLK
HCLK
10
32.768 kHz
01
4~24 MHz
00
DIVIDER_EN
(FRQDIV[4])
Enable
divide-by-2 counter
FRQDIV_CLK
1/2
16 chained
divide-by-2 counter
1/22
1/23
…...
1/215
1/216
0000
0001
16 to 1
MUX
:
:
1110
1111
CLKO
FSEL
(FRQDIV[3:0])
Figure 5-9 Frequency Divider Block Diagram
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NUMICRO™ NUC200/220 DATASHEET
Figure 5-8 Clock Source of Frequency Divider
NuMicro NUC200/220 Series
Datasheet
5.4 USB Device Controller (USB)
5.4.1
Overview
There is one set of USB 2.0 full-speed device controller and transceiver in this device, which is
compliant with USB 2.0 full-speed device specification and supports control/bulk/interrupt/
isochronous transfer types.
NUMICRO™ NUC200/220 DATASHEET
In this device controller, there are two main interfaces: the APB bus and USB bus which comes
from the USB PHY transceiver. For the APB bus, the CPU can program control registers through
it. There are 512 bytes internal SRAM as data buffer in this controller. For IN or OUT transfer, it is
necessary to write data to SRAM or read data from SRAM through the APB interface or SIE. User
needs to set the effective starting address of SRAM for each endpoint buffer through “buffer
segmentation register (USB_BUFSEGx)”.
There are 6 endpoints in this controller. Each of the endpoint can be configured as IN or OUT
endpoint. All the operations including Control, Bulk, Interrupt and Isochronous transfer are
implemented in this block. The block of ENDPOINT CONTROL is also used to manage the data
sequential synchronization, endpoint states, current start address, transaction status, and data
buffer status for each endpoint.
There are four different interrupt events in this controller. They are the wake-up function, device
plug-in or plug-out event, USB events, e.g. IN ACK, OUT ACK, and BUS events, e.g. suspend
and resume. Any event will cause an interrupt, and users just need to check the related event
flags in interrupt event status register (USB_INTSTS) to acknowledge what kind of interrupt
occurring, and then check the related USB Endpoint Status Register (USB_EPSTS) to
acknowledge what kind of event occurring in this endpoint.
A software-disable function is also supported for this USB controller. It is used to simulate the
disconnection of this device from the host. If user enables DRVSE0 bit (USB_DRVSE0), the USB
controller will force the output of USB_DP and USB_DM to level low and its function is disabled.
After disable the DRVSE0 bit, host will enumerate the USB device again.
Please refer to Universal Serial Bus Specification Revision 1.1.
5.4.2
Features
This Universal Serial Bus (USB) performs a serial interface with a single connector type for
attaching all USB peripherals to the host system. Following is the feature list of this USB.
Compliant with USB 2.0 Full-Speed specification
Provides 1 interrupt vector with 4 different interrupt events (WAKE-UP, FLDET,
USB and BUS)
Supports Control/Bulk/Interrupt/Isochronous transfer type
Supports suspend function when no bus activity existing for 3 ms
Provides 6 endpoints for configurable Control/Bulk/Interrupt/Isochronous transfer
types and maximum 512 bytes buffer size
Provides remote wake-up capability
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Datasheet
5.5 General Purpose I/O (GPIO)
5.5.1
Overview
The NuMicro NUC200 series has up to 80 General Purpose I/O pins to be shared with other
function pins depending on the chip configuration. These 80 pins are arranged in 6 ports named
as GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and GPIOF. The GPIOA/B/C/D/E port has the
maximum of 16 pins and GPIOF port has the maximum of 4 pins. Each of the 80 pins is
independent and has the corresponding register bits to control the pin mode function and data.
The I/O type of each of I/O pins can be configured by software individually as input, output, opendrain or Quasi-bidirectional mode. After reset, the I/O mode of all pins are depending on
Config0[10] setting. In Quasi-bidirectional mode, I/O pin has a very weak individual pull-up
resistor which is about 110~300 KΩ for VDD is from 5.0 V to 2.5 V.
5.5.2
Features
Four I/O modes:
Quasi-bidirectional
Push-pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable by GPx_TYPE[15:0] in GPx_MFP[31:16]
I/O pin configured as interrupt source with edge/level setting
Configurable default I/O mode of all pins after reset by Config0[10] setting
If Config[10] is 0, all GPIO pins in input tri-state mode after chip reset
If Config[10] is 1, all GPIO pins in Quasi-bidirectional mode after chip reset
I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode
Enabling the pin interrupt function will also enable the pin wake-up function.
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NUMICRO™ NUC200/220 DATASHEET
NuMicro NUC200/220 Series
Datasheet
5.6 I2C Serial Interface Controller (I2C)
5.6.1
Overview
2
I C is a two-wire, bidirectional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
NUMICRO™ NUC200/220 DATASHEET
Data is transferred between a Master and a Slave. Data bits transfer on the SCL and SDA lines
are synchronously on a byte-by-byte basis. Each data byte is 8-bit long. There is one SCL clock
pulse for each data bit with the MSB being transmitted first, and an acknowledge bit follows each
transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA line may
be changed only during the low period of SCL and must be held stable during the high period of
SCL. A transition on the SDA line while SCL is high is interpreted as a command (START or
STOP). Please refer to Figure 5-10 for more detailed I2C BUS Timing.
STOP
Repeated
START
START
STOP
SDA
tBUF
tLOW
SCL
tr
tHIGH
tHD;STA
tHD;DAT
tf
tSU;DAT
tSU;STA
tSU;STO
Figure 5-10 I2C Bus Timing
The device’s on-chip I2C logic provides a serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1
in I2CON should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA and SCL.
Pull-up resistor is needed for I2C operation as the SDA and SCL are open drain pins. When I/O
pins are used as I2C ports, user must set the pins function to I2C in advance.
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Datasheet
5.6.2
Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus include:
Master/Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allowing devices with different bit rates to communicate
via one serial bus
Serial clock synchronization used as a handshake mechanism to suspend and
resume serial transfer
A built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
External pull-up resistors needed for high output
Programmable clocks allowing for versatile rate control
Supports 7-bit addressing mode
Supports multiple address recognition (four slave addresses with mask option)
NUMICRO™ NUC200/220 DATASHEET
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NuMicro NUC200/220 Series
Datasheet
5.7 PWM Generator and Capture Timer (PWM)
5.7.1
Overview
The NuMicro NUC200 series has 2 sets of PWM group supporting a total of 4 sets of PWM
generators that can be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4
complementary PWM pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6,
PWM7) with 4 programmable Dead-zone generators.
NUMICRO™ NUC200/220 DATASHEET
Each PWM generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, 1/2,
1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM counters for PWM
period control, two 16-bit comparators for PWM duty control and one Dead-zone generator. The 4
sets of PWM generators provide eight independent PWM interrupt flags set by hardware when the
corresponding PWM period down counter reaches 0. Each PWM interrupt source with its
corresponding enable bit can cause CPU to request PWM interrupt. The PWM generators can be
configured as one-shot mode to produce only one PWM cycle signal or auto-reload mode to
output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM period, duty and Dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to 錯誤! 找不到參照來源。 and 錯誤! 找不到參照來源。 for the
architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching 0. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches 0, the interrupt request is generated. If PWM-timer
is set as auto-reload mode, when the down counter reaches 0, it is reloaded with PWM Counter
Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set as oneshot mode, the down counter will stop and generate one interrupt request when it reaches 0.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM0 and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 2 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR2. For each group, whenever Capture issues Interrupt 0/1/2/3,
the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, including: Read
PIIR to get interrupt source and Read CRLRx/CFLRx(x=0~3) to get capture value and finally write
1 to clear PIIR to 0. If interrupt latency will take time T0 to finish, the capture signal mustn’t
transition during this interval (T0). In this case, the maximum capture frequency will be 1/T0. For
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example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will be 1/900ns ≈ 1000 kHz
5.7.2
5.7.2.1
5.7.2.2
Features
PWM function:
Up to 2 PWM groups (PWMA/PWMB) to support 8 PWM channels or 4
complementary PWM paired channels
Each PWM group has two PWM generators with each PWM generator supporting
one 8-bit prescaler, two clock divider, two PWM-timers, one Dead-zone generator
and two PWM outputs.
Up to 16-bit resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Edge-aligned type or Center-aligned type option
Capture Function:
Timing control logic shared with PWM generators
Supports 8 Capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register
(CFLR) and Capture interrupt flag (CAPIFx)
NUMICRO™ NUC200/220 DATASHEET
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5.8
Real Time Clock (RTC)
5.8.1
Overview
NUMICRO™ NUC200/220 DATASHEET
The Real Time Clock (RTC) controller provides user with the real time and calendar message.
The clock source of RTC controller is from an external 32.768 kHz low speed crystal which
connected at pins X32_IN and X32_OUT (refer to pin Description) or from an external 32.768 kHz
low speed oscillator output fed at pin X32_IN. The RTC controller provides the real time message
(hour, minute, second) in TLR (RTC Time Loading Register) as well as calendar message (year,
month, day) in CLR (RTC Calendar Loading Register). It also offers RTC alarm function that user
can preset the alarm time in TAR (RTC Time Alarm Register) and alarm calendar in CAR (RTC
Calendar Alarm Register). The data format of RTC time and calendar message are all expressed
in BCD format.
The RTC controller supports periodic RTC Time Tick and Alarm Match interrupts. The periodic
RTC Time Tick interrupt has 8 period interval options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1
second which are selected by TTR (TTR[2:0] Time Tick Register). When real time and calendar
message in TLR and CLR are equal to alarm time and calendar settings in TAR and CAR, the AIF
(RIIR [0] RTC Alarm Interrupt Flag) is set to 1 and the RTC alarm interrupt signal is generated if
the AIER (RIER [0] Alarm Interrupt Enable) is enabled.
Both RTC Time Tick and Alarm Match interrupt signal can cause chip to wake-up from Idle or
Power-down mode if the correlate interrupt enable bit (AIER or TIER) is set to 1 before chip
enters Idle or Power-down mode.
5.8.2
Features
Supports real time counter in TLR (hour, minute, second) and calendar counter in CLR (year,
month, day) for RTC time and calendar check
Supports alarm time (hour, minute, second) and calendar (year, month, day) settings in TAR
and CAR
Selectable 12-hour or 24-hour time scale in TSSR register
Supports Leap Year indication in LIR register
Supports Day of the Week counter in DWR register
Frequency of RTC clock source compensate by FCR register
All time and calendar message expressed in BCD format
Supports periodic RTC Time Tick interrupt with 8 period interval options 1/128, 1/64, 1/32,
1/16, 1/8, 1/4, 1/2 and 1 second
Supports RTC Time Tick and Alarm Match interrupt
Supports chip wake-up from Idle or Power-down mode while a RTC interrupt signal is
generated
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5.9
Serial Peripheral Interface (SPI)
5.9.1
Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol that
operates in full duplex mode. Devices communicate in Master/Slave mode with the 4-wire bidirection interface. The NuMicro NUC200 series contains up to four sets of SPI controllers
performing a serial-to-parallel conversion on data received from a peripheral device, and a
parallel-to-serial conversion on data transmitted to a peripheral device. Each set of SPI controller
can be configured as a master or a slave device.
The SPI controller supports the variable serial clock function for special applications and 2-bit
Transfer mode to connect 2 off-chip slave devices at the same time. This controller also supports
the PDMA function to access the data buffer and also supports Dual I/O Transfer mode.
5.9.2
Features
Up to four sets of SPI controllers
Supports Master or Slave mode operation
Supports 2-bit Transfer mode
Supports Dual I/O Transfer mode
Configurable bit length of a transfer word from 8 to 32-bit
Provides separate 8-layer depth transmit and receive FIFO buffers
Supports MSB first or LSB first transfer sequence
Two slave select lines in Master mode
Supports the byte reorder function
Supports Byte or Word Suspend mode
Variable output serial clock frequency in Master mode
Supports PDMA transfer
Supports 3-wire, no slave select signal, bi-direction interface
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5.10 Timer Controller (TMR)
5.10.1 Overview
NUMICRO™ NUC200/220 DATASHEET
The timer controller includes four 32-bit timers, TIMER0~TIMER3, allowing user to easily
implement a timer control for applications. The timer can perform functions, such as frequency
measurement, event counting, interval measurement, clock generation, and delay timing. The
timer can generate an interrupt signal upon time-out, or provide the current value during
operation.
5.10.2 Features
Four sets of 32-bit timers with 24-bit up counter and one 8-bit prescale counter
Independent clock source for each timer
Provides one-shot, periodic, toggle and continuous counting operation modes
Time-out period = (Period of timer clock input) * (8-bit prescale counter + 1) * (24-bit TCMP)
Maximum counting cycle time = (1 / T MHz) * (2 ) * (2 ), T is the period of timer clock
24-bit up counter value is readable through TDR (Timer Data Register)
Supports event counting function to count the event from external pin
Supports external pin capture function for interval measurement
Supports external pin capture function for reset timer counter
Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated
(TIF set to 1)
8
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5.11 Watchdog Timer (WDT)
5.11.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports the function to wake-up system from Idle/Power-down mode.
5.11.2 Features
18-bit free running up counter for Watchdog Timer time-out interval.
Selectable time-out interval (2 ~ 2 ) and the time-out interval is 104 ms ~ 26.3168 s if
WDT_CLK = 10 kHz.
System kept in reset state for a period of (1 / WDT_CLK) * 63
Supports selectable Watchdog Timer reset delay period, it includes (1024+2)、(128+2) 、
(16+2) or (1+2) WDT_CLK reset delay period.
Supports force Watchdog Timer enabled after chip powered on or reset while CWDTEN
(Config0[31] watchdog enable) bit is set to 0.
Supports Watchdog Timer time-out wake-up function when WDT clock source is selected to
10 kHz low speed oscillator.
4
18
5.12 Window Watchdog Timer (WWDT)
The purpose of Window Watchdog Timer is to perform a system reset within a specified window
period to prevent software run to uncontrollable status by any unpredictable condition.
5.12.2 Features
6-bit down counter (WWDTVAL[5:0]) and 6-bit compare value (WWDTCR[21:16] – WINCMP
value) to make the window period flexible
Selectable maximum 11-bit WWDT clock prescale (WWDTCR[11:8] – PERIODSEL value) to
make WWDT time-out interval variable
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5.12.1 Overview
NuMicro NUC200/220 Series
Datasheet
5.13 UART Interface Controller (UART)
The NuMicro NUC200 series provides up to three channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform
Normal Speed UART. Besides, only UART0 and UART1 support the flow control function.
5.13.1 Overview
NUMICRO™ NUC200/220 DATASHEET
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR, LIN master/slave mode
and RS-485 mode functions. Each UART channel supports seven types of interrupts including:
Transmitter FIFO empty interrupt (INT_THRE);
Receiver threshold level reached interrupt (INT_RDA);
Line status interrupt (parity error or frame error or break interrupt) (INT_RLS);
Receiver buffer time-out interrupt (INT_TOUT);
MODEM/Wake-up status interrupt (INT_MODEM);
Buffer error interrupt (INT_BUF_ERR);
LIN interrupt (INT_LIN).
Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt
number 13 (vector number is 29) only supports UART1 interrupt. Refer to the Nested Vectored
Interrupt Controller chapter for System Interrupt Map.
The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO
(RX_FIFO) that reduces the number of interrupts presented to the CPU. The UART1~2 are
equipped with 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The
CPU can read the status of the UART at any time during the operation. The reported status
information includes the type and condition of the transfer operations being performed by the
UART, as well as 4 error conditions (parity error, frame error, break interrupt and buffer error)
probably occur while receiving data. The UART includes a programmable baud rate generator
that is capable of dividing clock input by divisors to produce the serial clock that transmitter and
receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and
BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 5-5 lists the equations in the
various conditions and Table 5-6 lists the UART baud rate setting table.
Mode
DIV_X_EN
DIV_X_ONE
Divider X
BRD Baud Rate Equation
0
0
0
Don’t care
A
UART_CLK / [16 * (A+2)]
1
1
0
B
A
UART_CLK / [(B+1) * (A+2)] , B must >= 8
2
1
1
Don’t care
A
UART_CLK / (A+2), A must >=3
Table 5-5 UART Baud Rate Equation
System clock = internal 22.1184 MHz high speed oscillator
Baud Rate
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Parameter
Register
Parameter
Register
Parameter
Register
921600
x
x
A=0,B=11
0x2B00_0000
A=22
0x3000_0016
460800
A=1
0x0000_0001
A=1,B=15
A=2,B=11
0x2F00_0001
0x2B00_0002
A=46
0x3000_002E
230400
A=4
0x0000_0004
A=4,B=15
A=6,B=11
0x2F00_0004
0x2B00_0006
A=94
0x3000_005E
115200
A=10
0x0000_000A
A=10,B=15
A=14,B=11
0x2F00_000A
0x2B00_000E
A=190
0x3000_00BE
57600
A=22
0x0000_0016
A=22,B=15
A=30,B=11
0x2F00_0016
0x2B00_001E
A=382
0x3000_017E
38400
A=34
0x0000_0022
A=62,B=8
A=46,B=11
A=34,B=15
0x2800_003E
0x2B00_002E
0x2F00_0022
A=574
0x3000_023E
19200
A=70
0x0000_0046
A=126,B=8
A=94,B=11
A=70,B=15
0x2800_007E
0x2B00_005E
0x2F00_0046
A=1150
0x3000_047E
9600
A=142
A=254,B=8
0x0000_008E A=190,B=11
A=142,B=15
0x2800_00FE
0x2B00_00BE
0x2F00_008E
A=2302
0x3000_08FE
4800
A=286
A=510,B=8
0x0000_011E A=382,B=11
A=286,B=15
0x2800_01FE
0x2B00_017E
0x2F00_011E
A=4606
0x3000_11FE
Table 5-6 UART Baud Rate Setting Table
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UA_FUN_SEL [1]) to enable IrDA function). The SIR specification defines a short-range
infrared asynchronous serial transmission mode with 1 start bit, 8 data bits, and 1 stop bit. The
maximum data rate supports up to 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA
SIR Protocol encoder/decoder. The IrDA SIR Protocol encoder/decoder is half-duplex only. So it
cannot transmit and receive data at the same time. The IrDA SIR physical layer specifies a
minimum 10ms transfer delay between transmission and reception, and this delay feature must
be implemented by software.
The alternate function of UART controllers is LIN (Local Interconnect Network) function. The LIN
mode is selected by setting the UA_FUN_SEL[1:0] to ’01’. In LIN mode, 1 start bit and 8 data bits
format with 1 stop bit are required in accordance with the LIN standard.
For NuMicro NUC200 Series, another alternate function of UART controllers is RS-485 9-bit
mode, and direction control provided by nRTS pin or can program GPIO (PB.2 for UART0_nRTS
and PB.6 for UART1_nRTS) to implement the function by software. The RS-485 mode is selected
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The UART0 and UART1 controllers support the auto-flow control function that uses two low-level
signals, nCTS (clear-to-send) and nRTS (request-to-send), to control the flow of data transfer
between the chip and external devices (e.g. Modem). When auto-flow is enabled, the UART is not
allowed to receive data until the UART asserts nRTS to external device. When the number of
bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the nRTS is deasserted. The UART sends data out when UART controller detects nCTS is asserted from
external device. If a valid asserted nCTS is not detected the UART controller will not send data
out.
NuMicro NUC200/220 Series
Datasheet
by setting the UA_FUN_SEL register to select RS-485 function. The RS-485 transceiver control is
implemented using the nRTS control signal from an asynchronous serial port to enable the RS485 transceiver. In RS-485 mode, many characteristics of the receiving and transmitting are same
as UART.
5.13.2 Features
NUMICRO™ NUC200/220 DATASHEET
Full duplex, asynchronous communications
Separates receive / transmit 64/16/16 bytes (UART0/UART1/UART2) entry FIFO for data
payloads
Supports hardware auto flow control/flow control function (nCTS, nRTS) and programmable
nRTS flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Supports programmable baud-rate generator for each channel individually
Supports nCTS wake-up function (UART0 and UART1 support)
Supports 7-bit receiver buffer time-out detection function
UART0/UART1 can through DMA channels to receive/transmit data
Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
Supports break error, frame error, parity error and receive / transmit buffer overflow detect
function
Fully programmable serial-interface characteristics
Programmable data bit length, 5-, 6-, 7-, 8-bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and
detection
Programmable stop bit length, 1, 1.5, or 2 stop bit generation
IrDA SIR function mode
Supports 3-/16-bit duration for normal mode
LIN function mode
Supports LIN master/slave mode
Supports programmable break generation function for transmitter
Supports break detect function for receiver
RS-485 function mode.
Supports RS-485 9-bit mode
Supports hardware or software direct enable control provided by nRTS pin
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5.14 PS/2 Device Controller (PS2D)
5.14.1 Overview
PS/2 device controller provides a basic timing control for PS/2 communication. All communication
between the device and the host is managed through the PS2_CLK and PS2_DAT pins. Unlike
PS/2 keyboard or mouse device controller, the receive/transmit code needs to be translated as
meaningful code by firmware. The device controller generates the PS2_CLK signal after receiving
a “Request to Send” state, but host has ultimate control over communication. Data of PS2_DAT
line sent from the host to the device is read on the rising edge and sent from the device to the
host is change after rising edge. A 16 bytes FIFO is used to reduce CPU intervention. Software
can select 1 to 16 bytes for a continuous transmission.
5.14.2 Features
Host communication inhibit and Request to Send state detection
Reception frame error detection
Programmable 1 to 16 bytes transmit buffer to reduce CPU intervention
Double buffer for data reception
Software override bus
NUMICRO™ NUC200/220 DATASHEET
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5.15 I2S Controller (I2S)
5.15.1 Overview
2
The I2S controller consists of I S protocol to interface with external audio CODEC. Two 8-word
deep FIFO for read path and write path respectively and is capable of handling 8-, 16-, 24- and
32-bit word sizes. PDMA controller handles the data movement between FIFO and memory.
5.15.2 Features
NUMICRO™ NUC200/220 DATASHEET
Operated as either Master or Slave
Capable of handling 8-, 16-, 24- and 32-bit word sizes
Supports Mono and stereo audio data
Supports I2S and MSB justified data format
Provides two 8-word FIFO data buffers, one for transmitting and the other for receiving
Generates interrupt requests when buffer levels cross a programmable boundary
Two PDMA requests, one for transmitting and the other for receiving
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5.16 Analog-to-Digital Converter (ADC)
5.16.1 Overview
The NuMicro NUC200 Series contains one 12-bit successive approximation analog-to-digital
converters (SAR A/D converter) with 8 input channels. The A/D converter supports three
operation modes: single, single-cycle scan and continuous scan mode. The A/D converter can be
started by software, PWM Center-aligned trigger and external STADC pin.
5.16.2 Features
Analog input voltage range: 0~VREF
12-bit resolution and 10-bit accuracy is guaranteed
Up to 8 single-end analog input channels or 4 differential analog input channels
Up to 760 kSPS conversion rate as ADC clock frequency is 16 MHz (chip working at 5V)
Three operating modes
Single mode: A/D conversion is performed one time on a specified channel
Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the smallest numbered channel to the largest
numbered channel
Continuous scan mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion
An A/D conversion can be started by:
Writing 1 to ADST bit through software
PWM Center-aligned trigger
Conversion results are held in data registers for each channel with valid and overrun
indicators
Conversion result can be compared with specify value and user can select whether to
generate an interrupt when conversion result matches the compare register setting
Channel 7 supports 3 input sources: external analog voltage, internal Band-gap voltage,
and internal temperature sensor output
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External pin STADC
NuMicro NUC200/220 Series
Datasheet
5.17 Analog Comparator (ACMP)
5.17.1 Overview
The NuMicro NUC200 Series contains two comparators which can be used in a number of
different configurations. The comparator output is logic 1 when positive input voltage is greater
than negative input voltage; otherwise the output is logic 0. Each comparator can be configured to
cause an interrupt when the comparator output value changes. The block diagram is shown in 錯
誤! 找不到參照來源。.
NUMICRO™ NUC200/220 DATASHEET
5.17.2 Features
Analog input voltage range: 0~ VDDA
Supports Hysteresis function
Supports optional internal reference voltage input at negative end for each comparator
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5.18 PDMA Controller (PDMA)
5.18.1 Overview
The NuMicro NUC200 series DMA contains nine-channel peripheral direct memory access
(PDMA) controller and a cyclic redundancy check (CRC) generator.
The PDMA that transfers data to and from memory or transfer data to and from APB devices. For
PDMA channel (PDMA CH0~CH8), there is one-word buffer as transfer buffer between the
Peripherals APB devices and Memory. Software can stop the PDMA operation by disable PDMA
PDMA_CSRx[PDMACEN]. The CPU can recognize the completion of a PDMA operation by
software polling or when it receives an internal PDMA interrupt. The PDMA controller can
increase source or destination address or fixed them as well.
The DMA controller contains a cyclic redundancy check (CRC) generator that can perform CRC
calculation with programmable polynomial settings. The CRC engine supports CPU PIO mode
and DMA transfer mode.
5.18.2 Features
Supports nine PDMA channels and one CRC channel. Each PDMA channel can support
a unidirectional transfer
AMBA AHB master/slave interface compatible, for data transfer and register read/write
Hardware round robin priority scheme. DMA channel 0 has the highest priority and
channel 8 has the lowest priority
PDMA operation
□ Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer
□ Supports word/half-word/byte transfer data width from/to peripheral
Cyclic Redundancy Check (CRC)
□ Supports four common polynomials CRC-CCITT, CRC-8, CRC-16, and CRC-32
- CRC-CCITT: X
8
16
+X
12
5
+X +1
2
- CRC-8: X + X + X + 1
- CRC-16: X
16
+X
15
+X +1
2
- CRC-32: X
32
+X
26
+X
23
+X
22
+X
16
+X
12
+X
11
+X
10
8
7
5
4
2
+X +X +X +X +X +X+1
□ Supports programmable CRC seed value.
□ Supports programmable order reverse setting for input data and CRC checksum.
□ Supports programmable 1’s complement setting for input data and CRC checksum.
□ Supports CPU PIO mode or DMA transfer mode.
□ Supports the follows write data length in CPU PIO mode
- 8-bit write mode (byte): 1-AHB clock cycle operation.
- 16-bit write mode (half-word): 2-AHB clock cycle operation.
□ - 32-bit write mode (word): 4-AHB clock cycle operation.
□ Supports byte alignment transfer data length and word alignment transfer source
address in CRC DMA mode.
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□ Supports address direction: increment, fixed.
NuMicro NUC200/220 Series
Datasheet
5.19 Smart Card Host Interface (SC)
5.19.1 Overview
The Smart Card Interface controller (SC controller) is based on ISO/IEC 7816-3 standard and fully
compliant with PC/SC Specifications. It also provides status of card insertion/removal.
5.19.2 Features
NUMICRO™ NUC200/220 DATASHEET
ISO7816-3 T=0, T=1 compliant
EMV2000 compliant
Supports up to three ISO7816-3 ports
Separates receive/ transmit 4 byte entry buffer for data payloads
Programmable transmission clock frequency
Programmable receiver buffer trigger level
Programmable guard time selection (11 ETU ~ 266 ETU)
One 24-bit and two 8-bit time-out counters for Answer to Request (ATR) and waiting
times processing
Supports auto inverse convention function
Supports transmitter and receiver error retry and error retry number limitation function
Supports hardware activation sequence process
Supports hardware warm reset sequence process
Supports hardware deactivation sequence process
Supports hardware auto deactivation sequence when detecting the card removal
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5.20 FLASH MEMORY CONTROLLER (FMC)
5.20.1 Overview
The NuMicro NUC200 Series has 128/64/32K bytes on-chip embedded Flash for application
program memory (APROM) that can be updated through ISP procedure. The In-SystemProgramming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip is powered on, Cortex™-M0 CPU fetches code from APROM or LDROM decided
by boot select (CBS) in Config0. By the way, the NuMicro NUC200 Series also provides
additional DATA Flash for user to store some application dependent data. For 128K bytes
APROM device, the data flash is shared with original 128K program memory and its start address
is configurable in Config1. For 64K/32K bytes APROM device, the data flash is fixed at 4K.
5.20.2 Features
Runs up to 50 MHz with zero wait state for continuous address read access
All embedded flash memory supports 512 bytes page erase
128/64/32 KB application program memory (APROM)
4 KB In-System-Programming (ISP) loader program memory (LDROM)
4KB data flash for 64/32 KB APROM device
Configurable data flash size for 128KB APROM device
Configurable or fixed 4 KB data flash with 512 bytes page erase unit
Supports In-Application-Programming (IAP) to switch code between APROM and
LDROM without reset
In-System-Programming (ISP) to update on-chip Flash
NUMICRO™ NUC200/220 DATASHEET
June 06, 2014
Page 79 of 98
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
6
6.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
SYMBOL
PARAMETER
MIN.
MAX
UNIT
VDD−VSS
-0.3
+7.0
V
VIN
VSS-0.3
VDD+0.3
V
1/tCLCL
4
24
MHz
TA
-40
+85
°C
TST
-55
+150
°C
-
120
mA
Maximum Current out of VSS
120
mA
Maximum Current sunk by a I/O pin
35
mA
Maximum Current sourced by a I/O pin
35
mA
Maximum Current sunk by total I/O pins
100
mA
Maximum Current sourced by total I/O pins
100
mA
DC Power Supply
Input Voltage
NUMICRO™ NUC200/220 DATASHEET
Oscillator Frequency
Operating Temperature
Storage Temperature
Maximum Current into VDD
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability
of the device.
June 06, 2012
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Revision 1.00
NuMicro NUC200/220 Series
Datasheet
6.2
DC Electrical Characteristics
(VDD-VSS=5.5 V, TA = 25°C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Operation Voltage
Power Ground
LDO Output Voltage
Analog Operating Voltage
VDD
VSS
AVSS
VLDO
AVDD
TYP.
MAX.
UNIT
5.5
V
2.5
-0.3
1.62
VDD = 2.5V ~ 5.5V up to 50 MHz
V
1.8
1.98
VDD
V
VDD > 2.5V
V
When system used analog
function, please refer to chapter 6.4
for corresponding analog operating
voltage
VDD = 5.5V,
IDD1
34
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
IDD2
15
Operating Current
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
Normal Run Mode
IDD3
32
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V,
IDD4
14
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
IDD5
8.5
mA All IP enabled and PLL disabled,
XTAL = 12 MHz
Operating Current
Normal Run Mode
VDD = 5.5V,
IDD6
3.6
at 12 MHz
mA All IP and PLL disabled,
XTAL = 12 MHz
VDD = 3.3V,
IDD7
7.5
mA All IP enabled and PLL disabled,
XTAL = 12 MHz
June 06, 2014
Page 81 of 98
Revision 1.00
NUMICRO™ NUC200/220 DATASHEET
VDD = 3.3V,
at 50 MHz
NuMicro NUC200/220 Series
Datasheet
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 3.3V,
IDD8
2.6
mA All IP and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
NUMICRO™ NUC200/220 DATASHEET
IDD9
3.6
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
IDD10
2
Operating Current
mA All IP and PLL disabled,
XTAL = 4 MHz
Normal Run Mode
VDD = 3.3V,
at 4 MHz
IDD11
2.8
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
VDD = 3.3V,
IDD12
1.2
mA All IP and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
IDD13
141
µA All IP enabled and PLL disabled,
XTAL = 32.768 kHz
VDD = 5.5V,
IDD14
129
Operating Current
µA All IP and PLL disabled,
XTAL = 32.768 kHz
Normal Run Mode
VDD = 3.3V,
at 32.768 kHz
IDD15
138
µA All IP enabled and PLL disabled,
XTAL = 32.768 kHz
VDD = 3.3V,
IDD16
125
µA All IP and PLL disabled,
XTAL = 32.768 kHz
VDD = 5.5V,
IDD17
125
Operating Current
µA All IP enabled and PLL disabled,
LIRC10 kHz enabled
Normal Run Mode
VDD = 5.5V,
at 10 kHz
IDD18
120
µA All IP and PLL disabled,
LIRC10 kHz enabled
June 06, 2012
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Revision 1.00
NuMicro NUC200/220 Series
Datasheet
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 3.3V,
IDD19
125
µA All IP enabled and PLL disabled,
LIRC10 kHz enabled
VDD = 3.3V,
IDD20
120
µA All IP and PLL disabled,
LIRC10kHz enabled
VDD = 5.5V,
IIDLE1
28
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 5.5V,
IIDLE2
10
Operating Current
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
Idle Mode
VDD = 3.3V,
at 50 MHz
IIDLE3
27
mA All IP and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V
IIDLE4
9
mA All IP disabled and PLL enabled,
XTAL = 12 MHz
7.5
VDD = 5.5V,
mA All IP enabled and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
IIDLE6
2.4
Operating Current
mA All IP and PLL disabled,
XTAL = 12 MHz
Idle Mode
at 12 MHz
IIDLE7
6.5
VDD = 3.3V,
mA All IP enabled and PLL enabled,
XTAL = 12 MHz
VDD = 3.3V,
IIDLE8
1.5
mA All IP and PLL disabled,
XTAL = 12 MHz
VDD = 5.5V,
Operating Current
Idle Mode
IIDLE9
3.3
at 4 MHz
June 06, 2014
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
Page 83 of 98
Revision 1.00
NUMICRO™ NUC200/220 DATASHEET
IIDLE5
NuMicro NUC200/220 Series
Datasheet
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD = 5.5V
IIDLE10
1.7
mA All IP and PLL disabled,
XTAL = 4 MHz
VDD = 3.3V,
NUMICRO™ NUC200/220 DATASHEET
IIDLE11
2.4
mA All IP enabled and PLL disabled,
XTAL = 4 MHz
VDD = 3.3V,
IIDLE12
0.8
mA All IP and PLL disabled,
XTAL = 4 MHz
VDD = 5.5V,
IIDLE13
133
µA All IP enabled and PLL disabled,
XTAL = 32.768 kHz
VDD = 5.5V,
IIDLE14
120
µA All IP and PLL disabled,
Operating Current
XTAL = 32.768 kHz
Idle Mode
at 32.768 kHz
VDD = 3.3V,
IIDLE15
133
µA All IP enabled and PLL disabled,
XTAL = 32.768 kHz
VDD = 3.3V,
IIDLE16
120
µA All IP and PLL disabled,
XTAL = 32.768 kHz
VDD = 5.5V,
IIDLE13
122
µA All IP enabled and PLL disabled,
LIRC10 kHz enabled
VDD = 5.5V,
IIDLE14
118
µA All IP and PLL disabled,
Operating Current
LIRC10 kHz enabled
Idle Mode
at 10 kHz
VDD = 3.3V,
IIDLE15
122
µA All IP enabled and PLL disabled,
LIRC10 kHz enabled
VDD = 3.3V
IIDLE16
118
µA All IP and PLL disabled,
LIRC10 kHz enabled
Standby Current
June 06, 2012
IPWD1
15
Page 84 of 98
µA
VDD = 5.5V, RTC disabled,
When BOD function disabled
Revision 1.00
NuMicro NUC200/220 Series
Datasheet
SPECIFICATION
PARAMETER
SYM.
TEST CONDITIONS
MIN.
Power-down Mode
TYP.
MAX.
UNIT
IPWD2
15
µA
VDD = 3.3V, RTC disabled,
When BOD function disabled
IPWD3
17
µA
VDD = 5.5V, RTC enabled ,
When BOD function disabled
IPWD4
17
µA
VDD = 3.3V, RTC enabled ,
When BOD function disabled
IIN1
-50
-60
µA
VDD = 5.5V, VIN = 0V or VIN=VDD
(Deep Sleep Mode)
Input Current PA, PB, PC,
PD, PE, PF (Quasibidirectional mode)
[1]
Input Current at nRESET
IIN2
-55
-45
-30
µA VDD = 3.3V, VIN = 0.45V
Input Leakage Current PA,
PB, PC, PD, PE, PF
ILK
-2
-
+2
µA
VDD = 5.5V, 0
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